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rev. 4669b?rke?10/03 features programmable driver current regulation antenna driver stage for 1 a peak current lf baudrates between 1 kbaud to 8 kbaud integrated oscillator for ceramic resonators two inputs for push-button switches bi-directional single-wire interface diagnosis function and overtemperature protection quick start control (qsc) for fast oscillation build-up and decay timing operation temperature -40 c to +85 c carrier frequency range from 100 khz to 150 khz amplitude shift keying (ask) modulation phase shift keying (psk) modulation power supply range 7 v to 16 v direct battery input (6 v and 28 v with limited function range) emi and esd according to automotive requirements highly integrated ? less external components required applications car access benefits dedicated for decentralized systems constant magnetic field strength electrostatic sensitive device. observe precautions for handling. description the circuit is an integrated bcdmos antenna driver ic dedicated as a transmitter for passive entry/go (peg) car applications and for other handsfree access control applications. it includes the full functionality to generate a magnetic lf field in conjunction with an antenna coil to transmit data to a receiver in a key fob, card or transponder. the trans- mission can be controlled via an one wire i/o interface (dio) by an external control unit. stand-alone antenna driver ATA5277 preliminary
2 ATA5277 [preliminary] 4669b?rke?10/03 figure 1. block diagram pin configuration figure 2. pinning qfn 28 5 v regulator oscillator serial interface (single wire ) ATA5277 switch debounce and wake-up boost converter control hs driver driver control logic control and status register current and zero crossing sensing test dgnd scane scani agnd vshunt qsc drv1 cboost pgnd1 pgnd2 vds vl1 vl2 vl3 vbatt vdd osci osco vsw sw1 sw2 clko vdio dio pgnd3 cint ls driver pgnd1 pgnd2 pgnd3 vds drv1 cboost nc sw1 vdd osci osco clko test scani vl3 vl2 vl1 scane vbatt sw2 vsw qsc vshunt agnd dgnd cint vdio dio 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 ATA5277
3 ATA5277 [preliminary] 4669b?rke?10/03 pin description pin symbol function 1 pgnd1 power supply ground 2 pgnd2 power supply ground 3 pgnd3 power supply ground 4 vds driver voltage supply input 5 drv1 antenna driver stage output 6 cboost external bootstrap capacitor connection 7 nc not connected 8 qsc qsc transistor driver stage output 9 vshunt antenna current sensing 10 agnd analog ground (sensoric and antenna driver) 11 dgnd digital ground (logic) 12 cint external integrator capacitor connection 13 vdio dio line interface supply voltage 14 dio one-wire serial interface line 15 scani for test purposes only 16 test for test purposes only 17 clko clock output 18 osco oscillator output (for resonator/crystal connection) 19 osci oscillator input (for external source or resonator/crystal) 20 vdd 5 v supply output (for filter capacitor only) 21 sw1 door switch input 1 22 vsw door switch interface supply voltage 23 sw2 door switch input 2 24 vbatt battery supply voltage 7 v to 16 v (28 v jump start) 25 scane for test purposes only 26 vl1 coil input of the switch mode power supply 27 vl2 coil input of the switch mode power supply 28 vl3 coil input of the switch mode power supply
4 ATA5277 [preliminary] 4669b?rke?10/03 functional description general description the ic contains a half-bridge coil driver stage with a special driver voltage regulator and control logic with diagnosis circuitry. further it contains a one-wire bi-directional micro- controller interface for the carrier modulation and the mode selection. an integrated oscillator for ceramic resonators generates the clock signal for the control logic. addi- tionally, the ic contains two connectors for switches to wake-up the ic. the ic generates an electromagnetic lf field in combination with an lc antenna cir- cuitry. the carrier frequency for the antenna is generated by the oscillator and prescaler logic. the lf field can be modulated to transmit data to a suitable receiver. there are two modulation modes available, amplitude shift keying (ask) and 180 phase shift keying (psk). a microcontroller or another control unit must be used to control the transmitter via the bi-directional single-wire interface. a boost converter power supply is used to supply the driver half-bridge and the antenna with a high voltage and a regulated current even if the battery voltage is low. the antenna current is programmable in 16 steps to support a transmission with various field strengths. the driver circuitry is short circuit (sc) protected and the driver logic contains diagnosis functions for short circuit and open wire detection at the antenna outputs. operation modes three different operation modes are defined: standby command mode modulation mode after power-on reset, the ATA5277 is in standby mode. to achieve minimum power con- sumption, only the internal 5-v supply, the dio-line interface and the door switch inputs are active. the ic can be activated either by the external control unit via the serial inter- face or by one of the switch inputs. a low signal at the dio-line or at the switch inputs (sw1, sw2) powers up the ic. if this is done at a switch input, a low signal is generated on the dio-line which can be used as a wake-up signal for the connected microcontroller. in command mode, the ic can be configured and diagnostics can be run. this mode is always activated after wake-up from standby mode and after leaving modulation mode. the communication is based on a one-wire serial interface (dio-line) with the con- nected microcontroller being the master and ATA5277 being the slave. in this mode, the antenna driver stage is disabled, except if the automatic field generation after wake-up is selected. in modulation mode, the antenna driver stage is activated (if enabled) and the data applied to the dio-line modulates the lf field (in ask or psk). this mode is activated after the command mode and remains active as long as data is applied to the dio-line (i.e., until a timeout has occured). after that, the ic falls back to command mode. standby and wake-up there are two different wake-up modes. in the default mode the antenna driver stage remains off after wake-up. the second mode can be programmed by a control com- mand. here, also the driver output stage is enabled. the ic generates the carrier signal for the antenna immediately.
5 ATA5277 [preliminary] 4669b?rke?10/03 figure 3. wake-up by external switch in figure 3, the ic is woken up by an external switch (pulled to ground). after a debouncing time t deb , the ic leaves sleep mode and sends a wake-up impulse to a con- nected microcontroller via the dio line. note that this impulse is already the start bit of the first command. after that, the ATA5277 waits for a control or status command from the microcontroller. the carrier remains off as the configuration bit m_wake (see control command 2) is '0'. figure 4. wake-up by external switch, automatic field generation the wake-up event as shown in figure 4 is the same as in figure 3, except for the con- figuration bit m_wake which is '1'. the driver stage will start operation after the wake-up command has been confirmed. this behaviour can be used to build up an lf field inde- pendently of the connected microcontroller. figure 5. wake-up by connected microcontroller, automatic field generation figure 5 shows a wake-up event triggered by the connected microcontroller, which now pulls the dio line to ground. to prevent the ATA5277 from waking up due to noise on the dio line, there is also a debouncing time before it will start operation. in this exam- ple, m_wake is again '1', so the driver stage starts operation after the wake-up event has been confirmed. ext. switch dio line carrier state t deb t wake ext. switch dio line carrier state t deb t wake ext. switch dio line carrier state t deb t wake
6 ATA5277 [preliminary] 4669b?rke?10/03 there are two ways to enter standby mode. one is to keep the dio-line at a high level for more than 32 ms while the ic is in command mode. a low signal at the dio line keeps the ic active and resets the standby timer. as the clock output clko remains active, this configuration can be used to supply a clock signal to a connected microcontroller. the second way to shut down the ATA5277 is to set the stby bit to control command 0. note that the ic will switch off operation immediately after receiving the last data bit (bit 3) of the control command. the rest of the telegram (i.e., acknowledge and stop bit) is then omitted. command mode protocol as described above, the communication between a controlling unit and the ATA5277 is done via a one-wire serial interface. figure 6 shows the structure of one communication bit. figure 6. structure of one communication bit all bits start with a falling edge. this pull-down has to be done by the microcontroller and maintained for at least t sync,minimum . after that, the setup for the data bit itself has to be performed. if the ATA5277 is the receiver, the microcontroller has to change the state of the dio-line according to the bit it wants to transmit. the maximum time for this setup is t setup,maximum . this state should then be applied for a time of at least t data,minimum . indepen- dent of the former state of the dio-line, it has to return to '1' and keep this state for a minimum time of t recover,minimum . if the ATA5277 is the transmitter of the data, the ic will apply the bit to the dio-line after t sync,minimum (i.e., activate the internal pull-down when a '0' needs to be transmitted). this signal on the dio-line is then valid for t data,maximum . generally, the following conditions have to be met in all cases: t sync,minimum t sync < t setup,maximum t setup t setup,maximum t data t data,maximum t recover t recover,minimum t bit t bit,minimum the timing values can be found in the electrical characteristics section for the dio interface. a command consists of a start bit followed by four command bits and four control or sta- tus bits respectively. it ends with an acknowledge bit and, if no further commands are to be transmitted, a stop bit. t sync valid data t setup t data t bit t recover
7 ATA5277 [preliminary] 4669b?rke?10/03 any command is preceded by a start bit. note again that, if the ATA5277 is woken up by one of the external switches, the wake-up signal from the ATA5277 (slave) to the micro- controller (master) on the dio-line is already the start bit of the first command. it is followed by the command bits cmd0...cmd3. bits cmd0 to cmd2 are used to select one of the eight registers of control and status bits. these registers have a depth of four bits and are used to configure the ATA5277 and to check its status. the cmd3 bit is used to select the operation mode of the ATA5277 after the current command has been processed (i.e., switch to modulation mode or stay in command mode). the next four bits of the protocol (bit0 to bit3) are the data bits. depending on the selected register, these bits are to be transmitted by the microcontroller (for control com- mands) or by ATA5277 (for status commands). note that even if data is transmitted by ATA5277, the initial falling edge for any bit has to be transmitted by the microcontroller, as it is the master of the transmission. furthermore, the ic has a built-in bit error check for input bits. if no errors are detected during a command transfer, the ic acknowledges the command with n_ackn = 0. if a bit error is detected, the transfer is not acknowledged (n_ackn =1), the received data is dismissed and the command has to be sent again immediately. figure 7. data consistency check as can be seen in figure 7, the state of the dio line is sampled twice during the data- valid time. during this time, the state must not change, both samples must result in the same value. if they differ, the n_ackn bit is set to '1' and thus a fault is reported at the end of the sequence. the bit is reset after each control/status command (i.e., after it is transmitted to the microcontroller). if the controller receives a ?1? acknowledge bit, it has to repeat the command immedi- ately (i.e., without transmitting the stop bit), starting again with the start bit. the stop bit is used to end the command mode. after receiving the stop bit, the ic switches to modulation mode. note that this bit is omitted if the cmd3 bit has been sent as a '1' (i.e., another command is to be transmitted). figure 8. control/status command structure sample point 1 sample point 2 bit 0 in wake-up in n_ackn dio start out in in bit 1 standby or command mode cmd0 cmd1 bit 2 bit 3 in/out cmd2 stop modulation mode in/out in/out in/out command bits control and status bits cmd3
8 ATA5277 [preliminary] 4669b?rke?10/03 figure 8 shows a typical sequence for data communication with the ATA5277. any sta- tus/command sequence is started with a st art bit. the shown sequence requires the cmd3 bit to be '0', as the protocol ends with the stop bit and after that, modulation mode is activated. if another command should be transmitted, the cmd3 bit of the preceding command must be '1' and the new command, which starts again with a start bit, is applied right after the acknowledge bit of the preceding command. usually, the driver output stage is disabled during command mode. but as described above, by setting the m_wake bit to '1', the driver stage will be enabled together with the command mode after wake-up. note that this is only happening after a wake-up from standby mode. the driver stage will be disabled when switching back from modulation mode to command mode, even with the m_wake bit set to '1'. if the dio-line is kept in a passive state (i.e., '1') for more than 32 ms, the ic will fall into sleep mode. command tables the following tables contain the description of the eight ATA5277 commands. note: 1. default values after power-on reset note: 1. see coil current adjustment, default all bits ' 1 ' table 1. control command 0 bit name/value type function 1 function 2 cmd0 0 cmd bit command selection ? cmd1 0 cmd bit command selection ? cmd2 0 cmd bit command selection ? cmd3 x cmd bit ' 0 ' return to modulation mode ' 1 ' keep command mode bit0 c_on ctrl bit ' 0 ' carrier/driver off (1) ' 1 ' carrier/driver on bit1 stby ctrl bit ' 0 ' no effect (1) ' 1 ' invokes standby mode bit2 nask_psk ctrl bit ' 0 ' ask modulation mode (1) ' 1 ' psk modulation mode bit3 tmod_sel ctrl bit ' 0 ' modulation timeout 2 ms (1) ' 1 ' modulation timeout 500 s table 2. control command 1 bit name/value type function 1 function 2 cmd0 1 cmd bit command selection ? cmd1 0 cmd bit command selection ? cmd2 0 cmd bit command selection ? cmd3 x cmd bit ' 0 ' return to modulation mode ' 1 ' keep command mode bit0 i_coil0 ctrl bit bit0 of the current control stage (1) ? bit1 i_coil1 ctrl bit bit1 of the current control stage (1) ? bit2 i_coil2 ctrl bit bit2 of the current control stage (1) ? bit3 i_coil3 ctrl bit bit3 of the current control stage (1) ?
9 ATA5277 [preliminary] 4669b?rke?10/03 note: 1. default values after power on reset table 3. control command 2 bit name/value type function 1 function 2 cmd0 0 cmd bit command selection ? cmd1 1 cmd bit command selection ? cmd2 0 cmd bit command selection ? cmd3 x cmd bit ' 0 ' return to modulation mode ' 1 ' keep command mode bit0 ps_clk ctrl bit ' 0 ' disable prescaler for clko-pin ' 1 ' enable prescaler (/2) for clko-pin (1) bit1 m_wake ctrl bit ' 0 ' carrier off after wake-up (1) ' 1 ' carrier on after wake-up bit2 dis_sw1 ctrl bit ' 0 ' sw1 input pull-up on (1) ' 1 ' sw1 input pull-up off bit3 dis_sw2 ctrl bit ' 0 ' sw2 input pull-up on (1) ' 1 ' sw2 input pull-up off table 4. status command 3 bit name/value type function 1 function 2 cmd0 1 cmd bit command selection ? cmd1 1 cmd bit command selection ? cmd2 0 cmd bit command selection ? cmd3 x cmd bit ' 0 ' return to modulation mode ' 1 ' keep command mode bit0 sw1 status bit logical level at sw1 input (low: 0; high: 1) ? bit1 sw2 status bit logical level at sw2 input (low: 0; high: 1) ? bit2 ? ? not used ? bit3 ? ? not used ? table 5. status command 4 bit name/value type function 1 function 2 cmd0 0 cmd bit command selection ? cmd1 0 cmd bit command selection ? cmd2 1 cmd bit command selection ? cmd3 x cmd bit ' 0 ' return to modulation mode ' 1 ' keep command mode bit0 diag0 status bit diagnosis bit0 ? bit1 diag1 status bit diagnosis bit0 ? bit2 diag2 status bit diagnosis bit0 ? bit3 ? ? not used ?
10 ATA5277 [preliminary] 4669b?rke?10/03 table 6. status command 5 bit name/value type function 1 function 2 cmd0 1 cmd bit command selection ? cmd1 0 cmd bit command selection ? cmd2 1 cmd bit command selection ? cmd3 x cmd bit ' 0 ' return to modulation mode ' 1 ' keep command mode bit0 c_on status bit ' 0 ' carrier/driver off ' 1 ' carrier/driver on bit1 stby status bit ' 0 ' ? bit2 nask_psk status bit ' 0 ' ask modulation selected ' 1 ' psk modulation selected bit3 tmod_sel status bit ' 0 ' modulation timeout is 2 ms ' 1 ' modulation timeout is 500 s table 7. status command 6 bit name/value type function 1 function 2 cmd0 0 cmd bit command selection ? cmd1 1 cmd bit command selection ? cmd2 1 cmd bit command selection ? cmd3 x cmd bit ' 0 ' return to modulation mode ' 1 ' keep command mode bit0 i_coil0 status bit bit0 of the current control stage ? bit1 i_coil1 status bit bit1 of the current control stage ? bit2 i_coil2 status bit bit2 of the current control stage ? bit3 i_coil3 status bit bit3 of the current control stage ? table 8. status command 7 bit name/value type function 1 function 2 cmd0 1 cmd bit command selection ? cmd1 1 cmd bit command selection ? cmd2 1 cmd bit command selection ? cmd3 x cmd bit ' 0 ' return to modulation mode ' 1 ' keep command mode bit0 ps_clk status bit ' 0 ' prescaler for clko-pin disabled ' 1 ' prescaler (/2) for clko pin enabled bit1 m_wake status bit ' 0 ' carrier off after wake-up ' 1 ' carrier onafter wake-up bit2 dis_sw1 status bit ' 0 ' sw1 input pull-up on ' 1 ' sw1 input pull-up off bit3 dis_sw2 status bit ' 0 ' sw2 input pull-up on ' 1 ' sw2 input pull-up off
11 ATA5277 [preliminary] 4669b?rke?10/03 modulation after the ic has woken up and a command has been received, the dio line is used for lf modulation. the ic has two modulation modes, ask and psk. the mode can be selected with the control command '0', bit 2. if ask modulation mode is selected (nask_psk = 0), the ic switches the carrier on and off, depending on the state of the dio line ('1' is on, '0' is off). note that, depending on the quality of the connected lf antenna and on the desired lf data rate, the usage of the qsc transistor t1 (see typi- cal applications section) is neccessary. if psk mode is selected (nask_psk = 1), the phase of the carrier is shifted by 180 on any change of the dio line. here, the qsc transistor must be used. figure 9. modulation modes the ic switches from modulation mode to command mode if the dio-line has not been changed for a time peraiod longer than t modsel . qsc feature the quick start control (qsc) feature suppor ts a short oscillation build up and decay timing during lf data modulation. an external high-voltage mos transistor is used as a switch to close and open the current loop of the antenna. by synchronizing this switch to the zero-crossing events of the antenna current, very short build-up and decay times for the lf-field and hence high data baud rates can be achieved. figure 10. qsc operation the external transistor (t1 in the typical applications section) is driven by the qsc pin. it provides a fast and synchronized gate-driver signal. d_io coil voltage (ask mode) coil voltage (psk mode) modulation after setup standby switch off cycle with qsc transistor coil qsc dio ask modulation psk modulation
12 ATA5277 [preliminary] 4669b?rke?10/03 coil driver the coil driver is composed of a power mos stage in half-bridge configuration, which is supplied by a current regulated boost converter. the driver generates a square-wave output signal to supply the antenna circuit with the carrier frequency. the antenna coil current is regulated by the voltage of the switch mode power supply. the current is therefore sensed by a shunt resistor connected between the vshunt and the gnd pins of the ic. to avoid damages in case of short circuits and high currents, the driver is switched off by the integrated fault detection unit. current adjustment to provide an adjustable coil current, the ic is equipped with a voltage regulator com- posed of a switch mode power supply (smps), which is used if the supply voltage is too low to reach the desired antenna coil current. in this case, the driver stage voltage is brought up to the required level (maximum 40 v). the ic contains the control logic and the switching transistor for the boost converter. all other components like the choke coil and the capacitor have to be applied externally. the antenna coil current can be adjusted in 16 steps by modifying the i_coil0 to i_coil3 bits in the control register. according to the selected current, the pulse width of the antenna coil driver signal is adjusted in order to enlarge the control range for the voltage regulator. the 16 steps are scaled logarithmically and have the follwing current ratings: note: 1. default table 9. current settings step current [ma] i_coil0 i_coil1 i_coil2 i_coil3 p/p ratio 1i maximum /3.158 0 0 0 0 1/7 2i maximum /2.927 1 0 0 0 1/7 3i maximum /2.727 0 1 0 0 1/7 4i maximum /2.5 1 1 0 0 1/7 5i maximum /2.353 0 0 1 0 2/6 6i maximum /2.143 1 0 1 0 2/6 7i maximum /2 0 1 1 0 2/6 8i maximum /1.846 1 1 1 0 2/6 9i maximum /1.714 0 0 0 1 3/5 10 i maximum /1.579 1 0 0 1 3/5 11 i maximum /1.463 0 1 0 1 3/5 12 i maximum /1.367 1 1 0 1 3/5 13 i maximum /1.263 0 0 1 1 4/4 14 i maximum /1.165 1 0 1 1 4/4 15 i maximum /1.081 0 1 1 1 4/4 16 (1) i maximum 11114/4
13 ATA5277 [preliminary] 4669b?rke?10/03 the maximum output current can be selected with the external shunt resistor. its resis- tance can be calculated with the formula: where the minimum and maximum ratings for i maximum,peak quoted in the dc characteris- tics have to be considered. see figure 11 to determine the antennas parameters. the maximum reachable output current can be calculated as follows: here, v drv is the maximum reachable driver voltage (40 v) and z the antennas imped- ance (inculding the r dson of the qsc mosfet, the shunt resistor and the driver output resistance). fault diagnotics the ic contains several fault diagnotic stages to protect itself from destruction and to provide diagnostic information. once there is a fault detected, both the switch mode power supply and the antenna driver stage are switched off and the corresponding fault information is written into the status register. note that besides shutting down the driver stages, the ATA5277 will not change its behaviour (i.e., it will remain in modulation mode until the dio line timeout has occured). the fault information can be read out from status command 4, which will also reset the status register. following protection and diagnostic mechanisms are defined: general ? the ic is equipped with temperature measurement obilities in order to detect a critical junction temperature drv output ? short-circuit protection of the driver stage output is realized by means of voltage monitoring. thus, the output voltage is compared to a corresponding threshold (depeding on the active transistor in the power mos half-bridge). if this threshold is surpassed for several oscillations, a short circuit (sc) fault is detected; ? open load or qsc transistor sc to gnd is detected with the external current sensing resistor r shunt . if there is no signal at this point even if the output is active, there is at least one of those two faults present. there is no possibility to determine the exact fault source. the diagnostic bits contain the information as given in table 10 on page 14. r shunt 1 i max,peak ---------------------- = i ant,peak v drv 2 z ----------------------- - a =
14 ATA5277 [preliminary] 4669b?rke?10/03 switch inputs the switch inputs sw1 and sw2 can be used to connect switches, e.g., the door handle contactors. these inputs are equipped with pull-ups, capable of driving currents up to 20 ma per pin. the pull-up voltage can be selected with the vsw input pin, which has to be connected either to v dd (5 v) for 5 v operation or to v batt for 12 v operation. the state of the switches is determined by the voltage level at the corresponding pin. this information can be read out via the dio-line during the status command 3. if the ic is in the standby mode, it wakes up if an input is pulled to ground. after a debounce time the ic generates a low signal at the dio-line (wake-up). this signal can be used to wake up and request a microcontroller to read the switches with a setup cycle. once the ic has woken up or during normal operation mode, a low state at a switch input (i.e., the switch is triggered) is stored until the status command 3 has been read out or alya enters standby mode. this enables the microcontroller to determine which of the two switch inputs was triggered, independant of the time it needs for processing status com- mand 3. to prevent high standby currents caused by a hanging door switch or a short-circuited line, the pull-ups can be disabled individually by setting the dis_sw1 and the dis_sw2 bits in the command register 2. clko output pin the clock output pin clko on the ATA5277 can be used to supply an onboard micro- controller with a clock signal (either 8 or 4 mhz). due to this frequency and the 5-v output stage, this signal is not suited to supply any device beyond the pcb boundaries. this clock signal is directly derived from the clock source connected to the osci/osco pins of the ATA5277 and is available as long as ATA5277 is not in standby mode. the frequency can be selected with the ps_clk bit of control command 2, which is '0' for full clock rate (typical 8 mhz) or '1' for the half clock rate (4 mhz). table 10. diagnostic bits diag0 diag1 diag2 fault type 0 0 0 no fault detected 1 0 0 open load or qsc transistor sc to gnd 0 1 0 overtemperature 1 1 0 antenna driver sc to gnd 0 0 1 antenna driver sc to v batt 1 0 1 qsc transistor sc to v batt 011not defined 111not defined
15 ATA5277 [preliminary] 4669b?rke?10/03 application hints figure 11. antenna coil inductance versus quality figure 11 shows the maximum usable antenna coil inductance in order to meet the requirements (maximum output voltage of 40 v square wave, output peak current of 1 a, maximum frequency deviation of antenna is 2.5%). 0.0001 0.00015 0.0002 0.00025 0.0003 0.00035 0.0004 0.00045 0.0005 4 6 8 10121416182022 quality q inductnce l[h] antenna ind. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol value unit supply voltage v batt -0.3 to +44 v input voltage v in v ss -0.3 v in 44 v power dissipation (ic, qfn) p tot 2w emission emi 250 v/m minimum esd protection (100 pf through 1.5 k) esd 2 (onboard pins) 4 (offboard pins) kv junction temperature t j 150 c storage temperature range t stg -55 to +150 c note: 1. voltages are given relative to v ss . thermal resistance parameters symbol value unit thermal resistance junction-case r thjc 5k/w thermal resistance junction-ambient (qfn28) r thja 32 k/w operating range parameters symbol value unit power supply range v batt 7 to 16.5 v operating temperature range t amb -40 to +85 c
16 ATA5277 [preliminary] 4669b?rke?10/03 electrical characteristics (1) no. parameters test conditions pin symbol min. typ. max. unit type* 1 power supply 1.1 operating voltage 24 v batt 7 (2) 16.5 (2) vd 1.2 smps voltage range 4 v vds 16.5 40 v d 1.3 switching frequency 26, 27, 28 f smps 2 f cf khz c 1.4 current regulation set up time t reg 11,5msd 1.5 supply current v s = 7 v i sup 3.5 a eff d 1.6 standby current ic in standby, v batt = 12 v 24 i stb tbd a a 1.7 power on reset v batt 24 v por 4.2 4.7 v a 1.8 ov discharger ic in standby, v batt > 23 v 24 i dis 9.5 ma a 1.9 internal 5 v supply 20 v vdd 4.7 5.3 v a 1.10 integrator current after fusing = 2 i ref 12 i cint 18 22 a a 1.11 dv cp for high side clamping v boost 6dv cp 7.7 8.9 v a 1.12 thermal shutdown temperature temperature reference = v scani 15 t jsd 155 c b 2 serial interface 2.1 data output current 14 i dio 10 20 ma a 2.2 output low level i dio = 20 ma 14 v lout 1.2 1.5 v a 2.3 input impedance 14 r in 0.6 3.5 m a 2.4 input low level 5 v v dio v batt 14 v lin 0.4 v dio va 2.5 input high level 5 v v dio v batt 14 v hin 0.7 v dio va 2.6 serial interface baud rate 14 bd if 5 kbit/s d 2.7 signal rise-time (l to h) 14 t rise 01sa 2.8 signal fall-time (h to l) 14 t fall 01sa 2.9 wake-up debounce time 14 t deb 550 s d 2.10 wake-up impulse length 14 t wake 20 50 s d 2.11 minimum synchronize time 14 t sync 20 s d 2.12 maximum set-up time 14 t setup 50 s d 2.13 data valid time for input 14 t data,in 140 s d 2.14 data valid time for output 14 t data,out 140 160 s d 2.15 recovery time 14 t recover 20 s d 2.16 bit length 14 t bit 200 s d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. 7 v < v batt < 16.5 v; t amb = 25c unless otherwise specified; all values refer to gnd pins 2. 6 v possible with approximately 30% decrease of maximum output power; 28 v operation possible (jump start), but output current stability is not guranteed
17 ATA5277 [preliminary] 4669b?rke?10/03 3 driver stage 3.1 coil driver output voltage square wave 4 v vds v batt 40 v a 3.2 coil driver output current depends on antenna inductance 5i drv,peak 1a peak d 3.3 coil driver resistance 5 r drv 0.4 a 3.4 qsc driver output voltage 8v qsc 10 20 v a 3.5 qsc driver output current short-term loads 8 i qsc 50 ma a 3.6 qsc driver output highside-impedance 8r qsch 3 a 3.7 qsc driver output lowside-impedance 8r qscl 3 a 3.8 carrier frequency range 5 f cf 100 150 khz d 3.9 lf data baud rate bi-phase/ manchester 5bd rf 1 8 kbit/s d 3.10 output rise/fall time between 10% and 90% of driver supply 26, 27, 28 t rf tbd s a 3.11 output duty cycle 5 d cf 12.5 50 % a 4 door switch inputs 4.1 trigger voltage level 5 v v sw v batt 21, 23 v swtrig 0.4 v sw va 4.2 output current (pull-up) 21, 23 i sw 82040maa 4.3 input debounce time 17 t deb 2msa 4.4 oscillator set-up time dependent on ceramic resonator 17 t oscon 500 s d 5 oscillator 5.1 input frequency range ceramic resonator, crystal or external clko source 17 f osc 6.4 10 mhz b 5.2 clko-output frequency scani change 17 f out f osc /2 4 f osc mhz a 5.3 clko high level 17 v hclko 4.4 7.1 v a 5.4 clko low level 17 v lclko 2.2 v a electrical characteristics (1) (continued) no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. 7 v < v batt < 16.5 v; t amb = 25c unless otherwise specified; all values refer to gnd pins 2. 6 v possible with approximately 30% decrease of maximum output power; 28 v operation possible (jump start), but output current stability is not guranteed soldering recommendations parameters symbol value unit maximum heating rate t d 1 to 3 c/s peak temperature in preheat zone z ph 100 to 140 c duration of time above melting point of solder t mp 10 min/75 max s peak reflow temperature t peak 220 to 225 c maximum cooling rate t rpeak 2 to 4 c/s
18 ATA5277 [preliminary] 4669b?rke?10/03 figure 12. application circuit vbatt sw1 sw2 dio vdd clko drv1 vshunt vds agnd vbatt min. 7 v 5 v supply osc serial interface and status/control register ATA5277 switch debounce and wake-up boost converter control driver driver control logic sensing microcontroller lf receiver data magnetic lf link l a dgnd test pgnd vl vsw vdio
19 ATA5277 [preliminary] 4669b?rke?10/03 package information ordering information extended type number package remarks ATA5277-pcq qfn28 7 mm 7 mm
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