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DUAL subscriber line interface circuit (slic) fxs daughtercard bd-slic-1 user? guide april 2002
ii copyright 2001, 2002 by lsi logic corporation. all rights reserved. this document is preliminary. as such, it contains data derived from functional simulations and performance estimates. lsi logic has not veri?d either the functional descriptions, or the electrical and mechanical speci?ations using production parts. this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?er of lsi logic corporation. document db15-000227-00, first edition (april 2002) this document describes the lsi logic corporation subscriber line interface circuit (slic) fxs daughtercard and will remain the of?ial reference source for all revisions/releases of this product until rescinded by an update. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright 2001, 2002 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, zopen, and zsp are trademarks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. gl to receive product literature, visit us at http://www.lsilogic.com. for a current list of our distributors, sales of?es, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/na_salesof?es.html
DUAL subscriber line interface circuit (slic) fxs daughtercard iii copyright 2001, 2002 by lsi logic corporation. all rights reserved. preface this document is the primary reference and users guide for the DUAL subscriber line interface circuit (DUAL-slic) daughtercard. this DUAL- slic daughtercard provides two standard telephone interfaces which interoperate with the lsi logic zsp processor families. this daughtercard is designed to mate directly with the lsi logic zsp evaluation boards, both eb402 and eb403 series. the DUAL-slic daughtercard interfaces to the standard zsp processor serial tdm interface and provides all the normal programmable telephony borscht (battery, overvoltage, ringing, supervision, coding, hybrid, and test) features. a programmable 5 ren ringing generator is provided directly on the daughtercard. the daughtercard is fully programmable to meet global telephony standards, allowing designs to be implemented worldwide for a variety short-loop (<2000ft) applications. audience this document assumes that you are familiar with telephony subscriber line interface circuits and digital signal processing devices. the people who bene? from this book are: ? engineers and managers who are evaluating the lsi logic zsp digital signal processor (dsp) for possible use in a system. ? engineers who are designing the lsi logic zsp dsp into a system. ? engineers developing voice telephony subsystems.
iv preface copyright 2001, 2002 by lsi logic corporation. all rights reserved. organization this document has the following chapters and appendixes: ? chapter 1, introduction ? chapter 2, installation ? chapter 3, programmers model related publications ? lsi402zx digital signal processor users guide , lsi logic corporation ? eb402 users guide , lsi logic corporation ? proslic si3210 data sheet , silicon laboratories conventions used in this manual the ?st time a word or phrase is de?ed in this manual, it is italicized. the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. signals that are active low end in an ?. hexadecimal numbers are indicated by the pre? ?x ?or example, 0x32cf. binary numbers are indicated by the pre? ?b ?or example, 0b0011.0010.1100.1111.
contents v copyright 2001, 2002 by lsi logic corporation. all rights reserved. contents chapter 1 introduction 1.1 product features 1-1 chapter 2 installation 2.1 hardware equipment required 2-1 2.2 software requirements 2-1 2.3 hardware set-up for the slic daughtercard 2-2 2.4 firmware installation 2-3 2.5 connection to external equipment and operation overview 2-6 2.5.1 external equipment setup 2-6 2.5.2 operation overview 2-8 2.5.3 block diagram 2-9 chapter 3 programmers model 3.1 interface timing diagram 3-1 3.1.1 tdm data stream organization 3-1 3.2 tdm interface timing 3-6
vi contents copyright 2001, 2002 by lsi logic corporation. all rights reserved.
contents vii copyright 2001, 2002 by lsi logic corporation. all rights reserved. figures 2.1 slic daughtercard 2-4 2.2 eb402 development board 2-5 2.3 slic daughtercard setup 2-7 2.4 board stacking 2-7 2.5 DUAL-slic block diagram 2-10 3.1 pcm frame 3-6 3.2 pcm serial port transmit 3-6 3.3 pcm serial portreceive 3-7
viii contents copyright 2001, 2002 by lsi logic corporation. all rights reserved.
contents ix copyright 2001, 2002 by lsi logic corporation. all rights reserved. tables 2.1 power selection 2-2 2.2 switch swi settings 2-9 2.3 power requirements 2-12 3.1 time slot 53 proslic comand byte 3-2 3.2 time slot 55 proslic address/register 3-3 3.3 time slot 57 proslic data register 3-3 3.4 time slot 53 proslic comand byte 3-4 3.5 time slot 55 proslic address register 3-5 3.6 time slot 61 read data resister 3-5
x contents copyright 2001, 2002 by lsi logic corporation. all rights reserved.
DUAL subscriber line interface circuit (slic) fxs daughtercard 1-1 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 1 introduction this users guide describes all the steps necessary to interface the DUAL- slic daughtercard (bd-slic-1) to the lsi logic zsp evaluation boards (either eb402 or eb403). the daughtercard provides two (2) separate voice interfaces thereby allowing connection to two subscriber telephony equipment (plain telephone, fax or modem). the slic daughtercard plugs into one of the two sport connectors on the eb402 or eb403 evaluation board. the con?uration of the serial port is described in chapter 3, ?rogrammers model. this users guide describes all hardware details for installation and operation of the slic daughtercard. section 3.2, ?dm interface timing, page 3-6 , covers the programming aspects of the serial zsp tdm interface port to allow proper interfacing and programming to the slic daughtercard. 1.1 product features the DUAL-slic daughtercard (bd-slic-1) provides the following features: ? two completely separate subscriber line interface circuits. ? board stackable (total two DUAL-slic cards) for a total of four subscriber interface capability. ? direct interface to lsi logic eb402/eb403 evaluation card serial tdm interface connectors. ? fully programmable from lsi logic zsp processor via in-band tdm time slots used for control/monitor functions (reference driver code available).
1-2 introduction copyright 2001, 2002 by lsi logic corporation. all rights reserved. ? dc power supplied directly from evaluation board supply (9 vdc). ? performs all battery, overvoltage, ringing, supervision, coding, hybrid, and test (borscht) functions. ? battery voltage generated dynamically with on-chip dc-to-dc converter controller. ? 5 ren ringing generator with programmable waveshape, amplitude frequency, and cadence. ? programmable ac impedance. ? programmable ring trip and loop closure detect thresholds. ? on-hook transmission, pulse metering, and polarity reversal. ? programmable constant loop current feed (20?1 ma).
DUAL subscriber line interface circuit (slic) fxs daughtercard 2-1 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 2 installation the DUAL-slic daughtercard may be installed onto either the lsi logic zsp eb402 or eb403 evaluation boards. this daughtercard provides two subscriber telephony ports (maximum of four ports if two cards stacked together) to aid in the development of telephony applications on the lsi logic zsp processors. this section describes the required software and hardware to con?ure and use the slic daughtercard interfaces. 2.1 hardware equipment required the following is the minimum recommended list of hardware required to evaluate and use the DUAL-slic daughtercard. ? lsi logic eb402 or eb403 zsp evaluation board. (eb402 shown in figure 2.2 on page 2-5 .) ? DUAL-slic daughtercard (bd-slic-1) (shown in figure 2.3 on page 2-7 .) ? external telephones, fax, modem or telephony test equipment supporting 2-wire subscriber loop interface. 2.2 software requirements the following is the minimum recommended list of development software and drivers to fully evaluate and use the DUAL-slic daughtercard. ? lsi logic sdk tools version 3.1 or later. ? lsi logic zopen DUAL-slic driver peripheral support package (psp).
2-2 installation copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.3 hardware set-up for the slic daughtercard the DUAL-slic daughtercard may be used with either the lsi logic eb402 or the eb403 zsp evaluation boards. the daughtercard is installed onto either the sport0 or sport1 tdm interface connectors provided on the zsp evaluation boards. the daughtercards can also be stacked together to provide additional telephony ports for each sport interface. the zsp evaluation boards support a maximum of two (2) DUAL-slic daughtercards simultaneously. the DUAL-slic daughtercard installation procedure is as follows: 1. set jumper ?p1 for desired power supply in accordance with table 2.1 . this jumper selects the 9vdc power source to be supplied from the zsp evaluation board (normal setting) or from an external source connected to connector j4. see figure 2.1 for daughtercard component locations. 2. keeping alignment of pin 1s plug the fxs interface board into one of the sport tdm interface connectors on the desired motherboard. see figure 2.2 for location of sport0 and sport1 connectors. 3. set sw1 to desired stacked board number in binary (0?) in accordance with table 2.2 . the zsp evaluation boards can support a total of two (2) daughtercards maximum. there must always be a board con?ured as card #0 and installed closest to the zsp evaluation board. 4. turn the zsp evaluation board power on (switch s3 on eb402). 5. using the zsp jtag debugger connected to the evaluation board, load and run the zopen peripheral support slic driver software as per the instructions provided with the software package. table 2.1 power selection 9 vdc location mother board external supply connected to j4 j4-1 (+9 vdc) j4-2 (gnd) jp1 1? (normal setting) 2? (test only)
firmware installation 2-3 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.4 firmware installation example zopen slic driver ?mware is available from lsi logic. this example software demonstrates the features supported by the bd-slic-1 daughtercard. the ?mware provides capability to detect a phone on/off hook status and also ability to ring a telephone. it also provides the necessary apis to enable access to all proslic registers available on the daughtercard. it is beyond the scope of this DUAL-slic daughtercard users guide to detail speci? registers available on the proslic device. therefore, it is recommended that the user obtain both the silicon laboratories proslic data sheet as well as the lsi logic zopen slic driver support package. the lsi logic zopen slic driver support package executes on the zsp 402zx dsp processor available on the eb402 evaluation board. this driver support package may also be easily ported to the zsp403lp device available on the eb403 evaluation board. please reference the lsi logic slic driver support package for detailed instructions on installing and executing the slic demonstration ?mware on the eb402 platform. this driver support package supports the necessary apis to control a maximum of two (2) DUAL-slic daughtercards for a total of four (4) telephony 2-wire subscriber ports.
2-4 installation copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.1 slic daughtercard 119 220 jp1 1 jr2 jr1 u3 u4 sw1 j4 j3 j1 j2
firmware installation 2-5 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.2 eb402 development board bd-slic-1 j1 pll out j4 pll ref in jp1 clkin j6 hpi jp22 a17 1 1 1 19 20 20 j3 2 1 a t e k r 51015 16 a18 tp7 tp6 1.8v tp5 1 3 s2 1 byp open jp12 j8 1 ext a/d j11 pllsel sport0 ext cntl 1 3 jp21 a16 jp20 fpv jp15 iognd tp8 3.3v cgnd 1 3 0 1 1 2 3 3 3 2 4 5 6 jp18 xboot 1 3 f a jp19 d3-xen jp17 d2-f jp16 d1-a jp14 d0-sb jp13 ic1-a lsb msb ld1 led1 ld3 ld4 ld5 ld6 ld7 ld8 ld9 ld10 ld11 ld12 ld13 ld14 ld15 ld16 ld2 lsi402z 1 1 2 2 13 14 15 16 3.3v led2 led3 1.8v selftest pio pin1-2(0) pin2-3(1) 2 sport1 off j9 r11 vr1 vr1 s3 on jtag j7 j5 jp5 jp6 jp7 jp8 jp9 jp10 jp11 u5 4 1 s1 reset 3 2 jp2 jp3 jp4 4 1 1 1 s4 int 0 r12 j10 1 0 c4 8 1 19 j2 eb402 s/n 134-30 rev 2/2.1 sn:
2-6 installation copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.5 connection to external equipment and operation overview this section provides a general overview of a DUAL-slic daughtercard used in a typical lsi logic zsp development system. this development platform provides a multi-channel telephony system for the zsp processor families. 2.5.1 external equipment setup the slic daughtercard is connected as shown in figure 2.3 . a total of two (2) DUAL-slic daughtercards are supported on either the eb402 or eb403 evaluation boards. the daughtercard con?uration can be either of the following: ? single daughtercard installed on either sport0 or sport1 interface connectors, or ? one card installed on the evaluation board sport0 interface and the second on the sport1 interface, or ? two cards stacked together on the same sport interface (either sport0 or sport1). refer to figure 2.4 for board stacking option. the daughercard switch sw1 selects the card number in the stackup (refer to table 2.2 ). the bottom card must be con?ured as card #0, the top card con?ured as any other number besides card #0. this con?uration can provide a total of four telephony interfaces for the zsp evaluation board. the external 9 vdc power supply shown in figure 2.3 is not required and is used for factory testing purposes only.
connection to external equipment and operation overview 2-7 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.3 slic daughtercard setup figure 2.4 board stacking slic card 0 j4 rj-11 x 2 sport0 sport1 eb40x slic card 1 up to 8 cards may be stacked for a total of 16 ports per sport connector note: slic card 1 is an optional con?uration j4 rj-11 x 2 card 1 j2 card 0 j2 card 1 j1 card 0 j1
2-8 installation copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.5.2 operation overview the DUAL-slic daughtercard consists of two silicon laboratories si3210 proslic devices. these proslic devices, along with their associated external components, provide the following functions; line voltage generation, ring voltage generation, onhook and offhook detection, and the 2-wire to 4-wire line hybrid. the DUAL-slic daughtercard connects directly to the lsi logic zsp serial tdm sport interface available on the zsp evaluation boards. this serial tdm interface provides support for both the normal digital pcm data transmission as well as the proslic register read/write access by the zsp processor. timeslots in the tdm stream are reserved for this speci? proslic monitor and control functions and are further described in chapter 3, ?rogrammers model. an 8.192 mhz clock on the daughtercard sources the clock for this tdm interface between the daughtercard and zsp processor. this clock frequency con?ures the tdm interface for a total of 128 available tdm timeslots. four of these timeslots are used for the normal transfer of pcm data between the daughtercard telephony ports and the zsp processor. these pcm timeslots are normally con?ured to begin at timeslots 0?, however these may be reprogrammed to different timeslots via the proslic con?uration registers. timeslots 53?1 are reserved and dedicated for the zsp processor read/write access to the proslic registers (refer to chapter 3, ?rogrammers model. ) a ?omplex programmable logic device (cpld) on the daughtercard converts these dedicated control tdm timeslots into the necessary proslic spi interface standard. the cpld translates these proslic register access between this serial spi control interface and the serial tdm interface. the DUAL-slic daughtercard supports stacking of up to 2 cards on an indiviDUAL sport connector. each card in the stack-up must be set with a unique card address set by sw1 on the daughtercard. the ?st card in the stack-up must always be con?ured as card #0 address. table 2.2 provides the sw1 switch con?uration settings to allow board stacking.
connection to external equipment and operation overview 2-9 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.5.3 block diagram figure 2.5 provides a block diagram overview of the DUAL-slic daughtercard. as is shown, the two major components of the daughtercard consist of the silicon laboratories proslic devices (with external components) and a cpld device. a brief description of the daughtercard circuitry is provided below. table 2.2 switch swi settings sw1 (pos3, pos2, pos1) board number note on, on, on 0 first board in stack (closest to eb403 board). on, on, off 1 highest number possible on the eb402 evaluation board. on, off, on 2 currently not supported on, off, off 3 currently not supported off, on, on 4 currently not supported off, on, off 5 currently not supported off, off, on 6 currently not supported off, off, off 7 currently not supported
2-10 installation copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.5 DUAL-slic block diagram the external 2-wire subscriber telephony equipment is connected to either or both of the standard rj-11 connectors on the daughtercard. line protection circuitry is provided to protect against excessive line voltages in support of normal short subscriber loop applications (less than 4kft line). the proslic device contains the 2-to-4 wire hybrid circuitry to convert the external 2-wire subscriber signals into a 4-wire serial tdm digital interface. each proslic on the daughtercard provides fully programmable combination slic and codec devices with integrated line battery feed and ringing voltage generation. the proslic control/monitor features are provided over a standard serial spi control interface. the digital pcm data is provided over a standard tdm serial interface. the cpld device converts both these proslic interfaces into a compatible tdm sport interface which interconnects to the lsi logic zsp evaluation boards sport interfaces. pclk es dra dxa mb reset programmable logic int_no reset_n0 cs_0 clk fsync drx dtx sdi sdo proslic ringing/ bat circuit rj-11 tip ring crystal osc. sensing circuit protection circuits clk fsync drx dtx sdi sdo int_n1 cs_1 reset_n1 proslic ringing/ bat circuit rj-11 tip ring sensing circuit protection circuits
connection to external equipment and operation overview 2-11 copyright 2001, 2002 by lsi logic corporation. all rights reserved. the proslic contains internal dc-to-dc converters to generate both the telecom battery voltage feed as well as the high voltage ring generator. these voltages are all derived from the 9 vdc supply provided directly from the lsi logic zsp evaluation boards. no external dc supplies are necessary besides the normal evaluation board supply. the ring generator supply supports capability for 5 ringer equivalency number (ren) at a loop length of 2kft. the ringer may also support 3 ren at a reduced loop length of 4kft (maximum loop length supported). the proslic provides both on/off hook loop current detection as well as ring trip detection. this status is available to the zsp processor via the internal proslic status register access. the cpld device translates the proslic data and control interfaces to the lsi logic zsp compatible tdm sport interface. the cpld provides the master tdm clock source which is derived from an on-board 8.192 mhz oscillator. the available 128 tdm timeslots are divided between pcm data and proslic control timeslots. the pcm data timeslots are normally the ?st four timeslots in the tdm frame period, however these may be re-programmed via proslic registers to reside in any of the 128 available timeslots. the proslic control timeslots are ?ed and dedicated at timeslot locations 53 through 63. the cpld translates these tdm timeslots to/from the required serial spi control format on the proslic control interface. the cpld located on card address #0 in the daughtercard stack-up also provides timing to all other slave card addresses in this stackup. this provides a synchronous tdm serial bus between the zsp processor on the evaluation board to all DUAL-slic daughtercards attached to the evaluation board.
2-12 installation copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.5.3.1 power requirements all dc power on the DUAL-slic daughtercard is derived directly from the 9 vdc and 3.3 vdc sources provided by the zsp evaluation boards. these dc supply sources are provided on the tdm sport interface connectors. the power requirements for the DUAL-slic daughtercard are listed in table 2.3 . table 2.3 power requirements card condition amps drawn from 3.3 vdc amps drawn from 9 vdc idle 0.2 0.1 one channel ringing other channel offhook 0.22 0.1 both channels offhook 0.24 0.122
DUAL subscriber line interface circuit (slic) fxs daughtercard 3-1 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 3 programmers model this chapter describes the proslic control and monitoring interface that is supported via the zsp tdm sport interface. the user is recommended to review the silicon laboratories proslic (p/n si3210) data sheet for full description of register functions and values. this chapter merely describes the method for the zsp process to access these available proslic registers, not necessarily the detailed contents of each register. lsi logic also provides reference zopen reference driver ?mware which provides the user with standardized apis to initialize and control the proslic for default operation. 3.1 interface timing diagram this section describes the serial tdm data and dedicated proslic control timeslot interface de?ition. 3.1.1 tdm data stream organization all pcm data and proslic monitor and control register access is provided over the standard 128 time-slot serial tdm interface. the cpld located on the daughtercard multiplexes the tdm interface from the zsp sport connector between this data and control proslic ports. the pcm data timeslots are programmable via proslic registers, however these are normally initialized to reside in the ?st four (0-3) timeslots on the tdm interface. timeslots 53 through 63 are reserved and dedicated for the proslic register read/write access by the zsp processor on the evaluation board. the cpld translates these speci? control time-slots into the required
3-2 programmers model copyright 2001, 2002 by lsi logic corporation. all rights reserved. proslic spi interface. the following subsections detail these indiviDUAL control tdm timeslot de?itions. 3.1.1.1 tdm tx control (zsp to proslic direction) this section describes the dedicated control timeslots for the tdm bus tx (write) direction of zsp toward proslic. 3.1.1.1.1 proslic command (ts53) table 3.1 details the contents of the tdm timeslot 53 byte used for the proslic internal register access by the zsp processor. table 3.1 time slot 53 proslic comand byte u unused 7, 0 write as zero. ca slic card address [6:4] binary daughtercard address (0-7) to address boards in a stacked con?uration. ca2 = card address msb ca0 = card address lsb r/w reg. read/write bit 3 0 = read data from proslic 1= write data to proslic cs1 chip select control for proslic port 1 2 0 = proslic port 1 device not selected. 1 = proslic port 1 device selected. cs0 chip-select control for proslic port 0 1 0 = proslic port 0 device not selected. 1 = proslic port 0 device selected. 76543210 u ca2 ca1 ca0 r/w cs1 cs0 u
interface timing diagram 3-3 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.1.1.1.2 proslic address register (ts55) table 3.2 details the contents of the tdm timeslot 55 byte used for the proslic internal register access by the zsp processor. table 3.2 time slot 55 proslic address/register this time-slot contains the proslic address location for read/write access by the zsp processor. the proslic contains 108 direct addresses as detailed in the silicon laboratories si3210 data sheet. 7 proslic address msb 0 proslic address lsb 3.1.1.1.3 proslic data register (ts57) table 3.3 details the contents of the tdm timeslot 57 byte used for the proslic internal register access by the zsp processor. table 3.3 time slot 57 proslic data register this time-slot contains the proslic data value to be writ- ten to the proslic address as indicated in time-slot 55 above. refer to the silicon laboratories si3210 data sheet for more speci? information. 7 proslic data msb 0 proslic data lsb 76543210 a7 a6 a5 a4 a3 a2 a1 a0 76543210 d7 d6 d5 d4 d3 d2 d1 d0
3-4 programmers model copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.1.1.2 tdm rx control (proslic to zsp direction) this section describes the dedicated control timeslots for the tdm bus rx (read) direction of proslic toward zsp processor. the cpld loops back the contents of both timeslots 53 and 55 in the tx direction toward the rx direction. this register loop-back provides the necessary information to the zsp processor to associate read data with a particular proslic address location (i.e. the proslic address location is returned in time-slot 55). 3.1.1.2.1 proslic command (ts53) table 3.4 details the contents of the tdm timeslot 53 byte used for the proslic internal register access by the zsp processor. this register returns the same value as was written in the tdm tx direction (i.e. direct data byte loop-back). table 3.4 time slot 53 proslic comand byte u unused 7, 0 ca slic card address [6:4] binary daughtercard address (0-7) to address boards in a stacked con?uration. ca2 = card address msb ca0 = card address lsb r/w reg. read/write bit 3 0 = read data from proslic 1= write data to proslic cs1 chip select generation control for proslic 1 2 0 = proslic port 1 device not selected. 1 = proslic port 1 device selected. cs0 chip select generation control for proslic 0 1 0 = proslic port 0 device not selected. 1 = proslic port 0 device selected. 76543210 u ca2 ca1 ca0 r/w cs1 cs0 u
interface timing diagram 3-5 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.1.1.2.2 proslic address register (ts55) table 3.5 details the contents of the tdm timeslot 55 byte used for the proslic internal register access by the zsp processor. this register returns the same value as was written in the tdm tx direction (i.e. direct data byte loop-back). table 3.5 time slot 55 proslic address register returns the proslic internal address location used for the present tdm frame transaction. 7 proslic address msb 0 proslic address lsb 3.1.1.2.3 proslic read data register (ts61) table 3.6 details the contents of the tdm timeslot 61 byte used for the proslic internal register access by the zsp processor. table 3.6 time slot 61 read data resister data read from the internal proslic address as indicated by time-slot 55 above. 7 proslic data msb 0 proslic data lsb 76543210 a7 a6 a5 a4 a3 a2 a1 a0 76543210 d7 d6 d5 d4 d3 d2 d1 d0
3-6 programmers model copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.2 tdm interface timing this section provides the timing details for the serial tdm interface between the DUAL-slic daughtercard and zsp evaluation board. the pcm clock and frame are generated by the DUAL-slic daughtercard having a reference frequency of 8.192 mhz. as shown in figure 3.1 , this tdm clock frequency provides for a total of 128 tdm timeslots within a 8 khz frame period. figure 3.2 and figure 3.3 provide detailed timing information for the tdm transmit and receive interfaces respectfully. these ?ures show the timing relationships between the tdm clock, frame, and data for each direction. figure 3.1 pcm frame figure 3.2 pcm serial port transmit pcm clk frame data time slot 0 time slot 127 xclk xfs do valid valid valid valid t 3 t 4 t 5 t 6 serial port transmit timing for axfs = 0b10 (xfs/xfs/xclk as inputs
tdm interface timing 3-7 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 3.3 pcm serial portreceive xclk xfs do valid valid valid valid t 3 t 4 t 5 t 6 serial port transmit timing for axfs = 0b10 (xfs/xfs/xclk as inputs
3-8 programmers model copyright 2001, 2002 by lsi logic corporation. all rights reserved.

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