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c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 mixed-signal 32kb isp flash mcu family a analog peripherals - sar adc 12- bit ( c 8051f000/1/2, c8051f005/6/7) 10- bit ( c 8051f010/1/2, C8051F015/6/7) 1l sb i n l ; no m i ssing codes pr ogr am m a ble t h r oughput up to 100ksps up to 8 e x ter n al i nputs; pr ogr am m a ble as single- e nded or differ e ntial pr ogr am m a ble am plifier gain: 16, 8, 4, 2, 1, 0. 5 data dependent w i ndowed i n ter r upt gener a tor built-in tem p erature sensor ( 3 c) - tw o 12-bit dacs - tw o analog comparators program m a ble hysteresis values configur able to gener a te i n ter r upts or reset - voltage referen ce 2. 4v; 15 ppm / c available on e x ter n al pin - precision vdd monitor/brow n-out detector on-chip jtag debug & boundary scan - on-chip debug circuitry facilitates full speed, non- i n tr usive i n - s y s tem debug ( n o e m ulator requir e d! ) - pr ovides br eakpoints, single st epping, w a tchpoints, stack monitor - i n spect/m odify m e m o r y and register s - super i or per f or m a nce to e m ulation sy stem s using i c e - chips, target pods, and sockets - i e e e 1149. 1 com p liant boundar y scan - low cost developm ent kit high spe e d 8051 c core - pipelined instruction architecture; executes 70% of i n str u ction set in 1 or 2 sy stem clocks - up to 25m i ps t h r oughput with 25m hz clock - 21 vector ed i n ter r upt sour ces memory - 256 by tes i n ter n al data ram ( f 000/01/02/10/11/12) - 2304 by tes i n ter n al data ram ( f 005/06/07/15/16/17) - 32k by tes fl ash; i n - s y s tem pr ogr am m a ble in 512 by te sectors digital peripherals - 4 byte-wide port i/o; all are 5v tolerant - hardware smbus tm (i2 c tm com p atible), spi tm , and uart serial po rts av ailab l e co n c u rren tly - pr ogr am m a ble 16- bit counter /t im er ar r a y with five captur e/com p ar e m odules - four gener a l pur pose 16- bit counter /t im er s - dedicated w a tch- dog t i m e r - bi-directional reset clock sources - internal program m a ble oscillator: 2-to-16mhz - external oscillator: crystal, rc,c, or clock - can switch between clock sour ces on- the- fly ; useful in power saving m odes supply voltage ........................ 2.7v to 3.6v - t y pical oper ating cur r e nt: 12. 5m a @ 25m hz - multiple power saving sleep and shutdown modes 64-pin tqfp, 48-pin tqfp, 32-pin lqfp temperature range: ?40 c to +85 c jta g 32 kb isp flash 25 6/ 23 04 b sram sani t y co nt r o l + - sa r adc clo c k ci rc ui t pga vref 1 2 -b it d a c am ux te mp sensor vo lt a g e co mpa r ator s an alog per iphera ls port 0 po rt 1 uart sm bus sp i bus pca po rt 2 port 3 crossbar ti m e r 0 ti m e r 1 ti m e r 2 ti m e r 3 d i g i ta l i/o high-s peed controller core debug ci rc ui t r y 21 in t e rr upts 8 051 c p u (25mi ps) 1 2 -b it d a c + - rev. 1. 7 11/03 copyright ? 2003 by silicon laboratories
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table of contents 1. system overview ........................................................................................................ 8 table 1.1. product selection guide ............................................................................................ ....................... 8 figure 1.1. c8051f000/05/ 10/15 block diagram .................................................................................. ........... 9 figure 1.2. c8051f001/06/ 11/16 block diagram .................................................................................. ......... 10 figure 1.3. c8051f002/07/ 12/17 block diagram .................................................................................. ......... 11 1.1. cip-5 1 tm cpu ........................................................................................................................... ............ 12 figure 1.4. com p arison of peak mcu execution speeds ........................................................................... .... 12 figure 1.5. on-board clock and reset .......................................................................................... .................. 13 1.2. on-board mem o ry................................................................................................................ ................. 14 figure 1.6. on-board mem o ry map ............................................................................................... ................. 14 1.3. jtag debug and boundary scan................................................................................................... ....... 15 figure 1.7. debug environm ent diagram ......................................................................................... .............. 15 1.4. program m a ble digital i/o and crossbar .......................................................................................... ..... 16 figure 1.8. digital crossbar diagram .......................................................................................... .................... 16 1.5. program m a ble counter array ..................................................................................................... ........... 17 figure 1.9. pca block diagram ................................................................................................. .................... 17 1.6. serial ports ................................................................................................................... .......................... 17 1.7. analog to digital converter .................................................................................................... .............. 18 figure 1.10. adc diagram ...................................................................................................... ....................... 18 1.8. com p arators and dacs ........................................................................................................... .............. 19 figure 1.11. com p arator and dac diagram ....................................................................................... ............ 19 2. absolute maximum ratings*............................................................................. 20 3. global dc electrical characteristics ................................................... 20 4. pinout and package definitions .................................................................... 21 table 4.1. pin definitions .................................................................................................... ............................ 21 figure 4.1. tqfp-64 pinout diagram ............................................................................................ ................. 23 figure 4.2. tqfp-64 package drawing ........................................................................................... ............... 24 figure 4.3. tqfp-48 pinout diagram ............................................................................................ ................. 25 figure 4.4. tqfp-48 package drawing ........................................................................................... ............... 26 figure 4.5. lqfp-32 pinout diagram ............................................................................................ ................. 27 figure 4.6. lqfp-32 package drawing ........................................................................................... ............... 28 5. adc (12-bit, c8051f000/1/2/5/6/7 only) ......................................................................... 29 figure 5.1. 12-bit adc f unctional block diagram ............................................................................... ......... 29 5.1. analog multiplexer and pga ..................................................................................................... ........... 29 5.2. adc modes of operation ......................................................................................................... ............. 30 figure 5.2. 12-bit adc track a nd conversion exam ple tim i ng ................................................................... 3 0 figure 5.3. tem p erature sensor transfer function .............................................................................. ........... 31 figure 5.4. am x0cf: am ux conf iguration regist er (c8051f00x) ............................................................ 31 figure 5.5. am x0sl: am ux channe l select regist er (c8051f00x) ........................................................... 32 figure 5.6. adc0cf: adc configuration register (c8051f00x) ................................................................. 33 figure 5.7. adc0cn: adc control regist er (c8051f00x) .......................................................................... 34 figure 5.8. adc0h: adc data w o rd m s b register (c8051f00x) ............................................................. 35 figure 5.9. adc0l: adc data w o rd lsb register (c8051f00x) ............................................................... 35 5.3. adc program m a ble w i ndow detector ............................................................................................... .. 36 figure 5.10. adc0gth: adc greater-than data high by te re gister (c8051f00x) .................................. 36 figure 5.11. adc0gtl: adc greater-than data low by te register (c8051f00x) ................................... 36 figure 5.12. adc0lth: adc less-than data high by te re gister (c8051f00x) ....................................... 36 figure 5.13. adc0ltl: adc less-than data low byte re gister (c8051f00x) ......................................... 36 figure 5.14. 12-bit adc w i ndow interrupt exam ples, right justified data ................................................. 37 figure 5.15. 12-bit adc w i ndow interrupt exam ples, left justified data ................................................... 37 figure 5.15. 12-bit adc w i ndow interrupt exam ples, left justified data ................................................... 38 r e v. 1.7 2
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 5.1. 12-bit adc el ectrical char acteris tics .............................................................................. .............. 38 table 5.1. 12-bit adc el ectrical char acteris tics .............................................................................. .............. 39 6. adc (10-bit, c8051f010/1/2/5/6/7 only) ......................................................................... 40 figure 6.1. 10-bit adc f unctional block diagram ............................................................................... ......... 40 6.1. analog multiplexer and pga ..................................................................................................... ........... 40 6.2. adc modes of operation ......................................................................................................... ............. 41 figure 6.2. 10-bit adc track a nd conversion exam ple tim i ng ................................................................... 4 1 figure 6.3. tem p erature sensor transfer function .............................................................................. ........... 42 figure 6.4. am x0cf: am ux conf iguration regist er (c8051f01x) ............................................................ 42 figure 6.5. am x0sl: am ux channe l select regist er (c8051f01x) ........................................................... 43 figure 6.6. adc0cf: adc configuration register (c8051f01x) ................................................................. 44 figure 6.7. adc0cn: adc control regist er (c8051f01x) .......................................................................... 45 figure 6.8. adc0h: adc data w o rd m s b register (c8051f01x) ............................................................. 46 figure 6.9. adc0l: adc data w o rd lsb register (c8051f01x) ............................................................... 46 6.3. adc program m a ble w i ndow detector ............................................................................................... .. 47 figure 6.10. adc0gth: adc greater-than data high by te re gister (c8051f01x) .................................. 47 figure 6.11. adc0gtl: adc greater-than data low by te register (c8051f01x) ................................... 47 figure 6.12. adc0lth: adc less-than data high by te re gister (c8051f01x) ....................................... 47 figure 6.13. adc0ltl: adc less-than data low byte re gister (c8051f01x) ......................................... 47 figure 6.14. 10-bit adc w i ndow interrupt exam ples, right justified data ................................................. 48 figure 6.15. 10-bit adc w i ndow interrupt exam ples, left justified data ................................................... 48 figure 6.15. 10-bit adc w i ndow interrupt exam ples, left justified data ................................................... 49 table 6.1. 10-bit adc el ectrical char acteris tics .............................................................................. .............. 49 table 6.1. 10-bit adc el ectrical char acteris tics .............................................................................. .............. 50 7. dacs, 12 bit voltage mode.................................................................................... 51 figure 7.1. dac functi onal block diagram ....................................................................................... ............. 51 figure 7.2. dac0h: dac 0 high byte register .................................................................................... ......... 52 figure 7.3. dac0l: dac 0 low byte register ..................................................................................... ......... 52 figure 7.4. dac0cn: dac0 control register ..................................................................................... .......... 52 figure 7.5. dac1h: dac 1 high byte register .................................................................................... ......... 53 figure 7.6. dac1l: dac 1 low byte register ..................................................................................... ......... 53 figure 7.7. dac1cn: dac1 control register ..................................................................................... .......... 53 table 7.1. dac elect rical charact eristics ..................................................................................... .................. 54 8. comparators .............................................................................................................. 55 figure 8.1. com p arator functional block diagram ............................................................................... ......... 55 figure 8.2. com p arat or hysteresis plot ........................................................................................ ................... 56 figure 8.3. cpt0cn: com p ar ator 0 contro l regi ster ............................................................................. ....... 57 figure 8.4. cpt1cn: com p ar ator 1 contro l regi ster ............................................................................. ....... 58 table 8.1. com p arator electrical char acteris tics .............................................................................. .............. 59 9. voltage reference ................................................................................................ 60 figure 9.1. voltage referen ce functional bl ock diagram ........................................................................ ..... 60 figure 9.2. ref0cn: refe rence contro l regi ster ................................................................................ .......... 61 table 9.1. reference el ectrical char acteris tics ............................................................................... ................ 61 10. cip-51 cpu ..................................................................................................................... .... 62 figure 10.1. cip-51 block diagram ............................................................................................. ................... 62 10.1. instruction set................................................................................................................ ......... 63 table 10.1. cip-51 instruction set sum m a ry .................................................................................... .............. 65 10.2. memory organization .......................................................................................................... 68 figure 10.2. mem o ry map ....................................................................................................... ........................ 69 10.3. special function registers ................................................................................................ 70 table 10.2. special functi on register me m o ry map .............................................................................. ........ 70 table 10.3. special function registers ........................................................................................ ................... 70 figure 10.3. sp: stack pointer ................................................................................................ ......................... 74 figure 10.4. dpl: da ta pointer low byte ....................................................................................... ............... 74 3 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.5. dph: da ta pointer high byte ...................................................................................... ............... 74 figure 10.6. psw : program status w o rd ......................................................................................... ............... 75 figure 10.7. acc: accum u lator ................................................................................................. ..................... 76 figure 10.8. b: b register .................................................................................................... ........................... 76 10.4. interrupt handler .............................................................................................................. ... 77 table 10.4. interrupt sum m a ry ................................................................................................. ....................... 78 figure 10.9. ie: interrupt enable ............................................................................................. ........................ 79 figure 10.10. ip: interrupt priority .......................................................................................... ........................ 80 figure 10.11. eie1: extended interrupt enable 1 ............................................................................... ............ 81 figure 10.12. eie2: extended interrupt enable 2 ............................................................................... ............ 82 figure 10.13. eip1: extended interrupt priority 1 ............................................................................. ............. 83 figure 10.14. eip2: extended interrupt priority 2 ............................................................................. ............. 84 10.5. power managem e nt modes ......................................................................................................... ...... 85 figure 10.15. pcon: po wer control register .................................................................................... ............ 86 11. flash memory ............................................................................................................. 87 11.1. program m i ng the flash mem o ry ................................................................................................... ... 87 table 11.1. flash mem o ry electrical char acteris tics ........................................................................... ....... 87 11.2. non-volatile da ta storage ...................................................................................................... ........... 88 11.3. security options ............................................................................................................... ................. 88 figure 11.1. psctl: progr am store rw control .................................................................................. ......... 88 figure 11.2. flash program mem o ry secur ity by tes ............................................................................... ........ 89 figure 11.3. flacl: flash acce ss lim it (c8051f005/06/ 07/15/16/17 only ) ............................................... 90 figure 11.4. flscl: flas h mem o ry tim i ng prescaler ............................................................................. ...... 91 12. external ram (c8051f005/06/07/15/16/17) ............................................................. 92 figure 12.1. emi0cn: external mem o ry inte rface control ........................................................................ ... 92 13. reset so urces ............................................................................................................. 93 figure 13.1. reset sources diagram ............................................................................................ ................... 93 13.1. power-on reset ................................................................................................................. ................. 94 13.2. software forced reset .......................................................................................................... ............. 94 figure 13.2. vdd monitor tim i ng diagram ....................................................................................... ........... 94 13.3. power-fail reset............................................................................................................... .................. 94 13.4. external reset ................................................................................................................. ................... 95 13.5. missing clock det ector reset ................................................................................................... ........ 95 13.6. com p arator 0 reset ............................................................................................................. .............. 95 13.7. external cnvstr pin reset ...................................................................................................... ....... 95 13.8. w a tchdog tim e r reset ........................................................................................................... ........... 95 figure 13.3. w d tcn: w a tc hdog tim e r contro l regi ster ........................................................................... .. 96 figure 13.4. rstsrc: reset source register .................................................................................... ............. 97 table 13.1. reset elect rical charact eristics .................................................................................. .................. 98 14. oscillator ................................................................................................................... 99 figure 14.1. oscillator diagram ............................................................................................... ....................... 99 figure 14.2. oscicn: internal oscillator cont rol regi ster ..................................................................... .... 100 table 14.1. internal oscilla tor electrical ch aracteris tics .................................................................... .......... 100 figure 14.3. oscxcn: external oscillator cont rol regi ster ..................................................................... .. 101 14.1. external crys tal exam ple ....................................................................................................... ......... 102 14.2. external rc exam ple ............................................................................................................ .......... 102 14.3. external capac itor exam ple ..................................................................................................... ....... 102 15. port input/output .................................................................................................. 103 15.1. priority cross bar decoder ..................................................................................................... ......... 103 15.2. port i/o in itializa tion ........................................................................................................ ............... 103 figure 15.1. port i/o f unctional block diagram ................................................................................ .......... 104 figure 15.2. port i/ o cell block diagram ...................................................................................... ............... 104 table 15.1. crossbar priority decode .......................................................................................... ................. 105 figure 15.3. xbr0: port i/ o crossbar register 0 ............................................................................... ......... 106 r e v. 1.7 4
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 15.4. xbr1: port i/ o crossbar register 1 ............................................................................... ......... 107 figure 15.5. xbr2: port i/ o crossbar register 2 ............................................................................... ......... 108 15.3. general purpose port i/o ....................................................................................................... .......... 109 15.4. configuring ports w h ich are not pinned out .................................................................................. 109 figure 15.6. p0: port0 register ............................................................................................... ...................... 109 figure 15.7. prt0cf: port 0 configurati on register ............................................................................. ....... 109 figure 15.8. p1: port1 register ............................................................................................... ...................... 110 figure 15.9. prt1cf: port 1 configurati on register ............................................................................. ....... 110 figure 15.10. prt1if: port1 interrupt flag register ........................................................................... ......... 110 figure 15.11. p2: port2 register .............................................................................................. ..................... 111 figure 15.12. prt2cf: port 2 configurati on register ............................................................................ ...... 111 figure 15.13. p3: port3 register .............................................................................................. ..................... 112 figure 15.14. prt3cf: port 3 configurati on register ............................................................................ ...... 112 table 15.2. port i/o dc electrical char acteris tics ............................................................................ ............ 112 16. smbus / i2c bus ............................................................................................................... 1 13 figure 16.1. smbus block diagram .............................................................................................. ............... 113 figure 16.2. typical smbus configuration ...................................................................................... ............ 114 16.1. supporting docum e nts ........................................................................................................... ......... 114 16.2. operation ...................................................................................................................... ................... 115 figure 16.3. smbus transaction ................................................................................................ ................... 115 16.3. arbitration .................................................................................................................... ................... 116 16.4. clock low extension ............................................................................................................ .......... 116 16.5. tim e outs ....................................................................................................................... ................... 116 16.6. smbus special func tion registers ............................................................................................... ... 116 figure 16.4. smb0cn: sm bus control register .................................................................................... ...... 118 figure 16.5. smb0cr: smbu s clock rate register ................................................................................ .... 119 figure 16.6. smb0dat: smbus data register ..................................................................................... ...... 120 figure 16.7. smb0adr: sm bus address register .................................................................................. ... 120 figure 16.8. smb0sta: smbus status register ................................................................................... ....... 121 table 16.1. smbu s status codes ................................................................................................ .................. 122 17. serial peripheral interface bus ................................................................. 123 figure 17.1. spi block diagram ................................................................................................ ................... 123 figure 17.2. typical spi interconnection ...................................................................................... ................ 124 17.1. signal desc riptions ............................................................................................................ .............. 124 17.2. operation ...................................................................................................................... ................... 125 figure 17.3. full duplex operation ............................................................................................ ................... 125 17.3. serial cloc k tim i ng ............................................................................................................ ............. 126 figure 17.4. data/clo ck tim i ng diagram ........................................................................................ ............. 126 17.4. spi special func tion registers ................................................................................................. ....... 127 figure 17.5. spi0cfg: spi configurati on register .............................................................................. ........ 127 figure 17.6. spi0cn: spi control register ..................................................................................... ............. 128 figure 17.7. spi0ckr: spi clock rate register ................................................................................. ......... 129 figure 17.8. spi0dat: spi data register ....................................................................................... ............. 129 18. uart ........................................................................................................................... ...... 130 figure 18.1. uart block diagram ............................................................................................... ............... 130 18.1. uart operati onal modes ......................................................................................................... ...... 131 table 18.1. uart modes ........................................................................................................ ..................... 131 figure 18.2. uart mode 0 interconnect ......................................................................................... ............. 131 figure 18.3. uart mode 0 tim i ng diagram ....................................................................................... ........ 131 figure 18.4. uart mode 1 tim i ng diagram ....................................................................................... ........ 132 figure 18.5. uart modes 1, 2, and 3 interconnect diagram ...................................................................... 133 figure 18.6. uart modes 2 and 3 tim i ng diagram ................................................................................ .... 134 18.2. multiprocessor com m unications .................................................................................................. ... 135 figure 18.7. uart multi-processor mode interconnect diagram ............................................................... 135 5 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 18.2. oscillator frequenc ies for standard baud rates .................................................................... .... 136 figure 18.8. sbuf: serial ( uart) data bu ffer register ......................................................................... .... 136 figure 18.9. scon: serial port contro l regi ster ............................................................................... ........... 137 19. timers ......................................................................................................................... ... 138 19.1. tim e r 0 and tim e r 1 ............................................................................................................ ............ 138 figure 19.1. t0 mode 0 block diagram .......................................................................................... .............. 139 figure 19.2. t0 mode 2 block diagram .......................................................................................... .............. 140 figure 19.3. t0 mode 3 block diagram .......................................................................................... .............. 141 figure 19.4. tcon: ti m e r control register ..................................................................................... ............ 142 figure 19.5. tmod: ti m e r mode register ........................................................................................ ........... 143 figure 19.6. ckcon: cl ock control register .................................................................................... .......... 144 figure 19.7. tl0: tim e r 0 low byte ............................................................................................ ................ 145 figure 19.8. tl1: tim e r 1 low byte ............................................................................................ ................ 145 figure 19.9. th0: tim e r 0 high byte ........................................................................................... ................ 145 figure 19.10. th1: tim e r 1 high byte .......................................................................................... ............... 145 19.2. tim e r 2 ........................................................................................................................ .................... 146 figure 19.11. t2 mode 0 block diagram ......................................................................................... ............. 147 figure 19.12. t2 mode 1 block diagram ......................................................................................... ............. 148 figure 19.13. t2 mode 2 block diagram ......................................................................................... ............. 149 figure 19.14. t2con: ti m e r 2 control register ................................................................................. ......... 150 figure 19.15. rcap2l: tim e r 2 capture register low byte ...................................................................... 1 51 figure 19.16. rcap2h: tim e r 2 capture register high byte ..................................................................... 1 51 figure 19.17. tl2: tim e r 2 low byte ........................................................................................... ............... 151 figure 19.18. th2: tim e r 2 high byte .......................................................................................... ............... 151 19.3. tim e r 3 ........................................................................................................................ .................... 152 figure 19.19. tim e r 3 block diagram........................................................................................... ................ 152 figure 19.20. tmr3cn: ti m e r 3 control register ................................................................................ ...... 152 figure 19.21. tmr3rll: tim e r 3 reload register low byte .................................................................... 153 figure 19.22. tmr3rlh: tim e r 3 reload register high byte ................................................................... 153 figure 19.23. tmr3l: tim e r 3 low byte ......................................................................................... ........... 153 figure 19.24. tmr3h: tim e r 3 high byte ........................................................................................ ........... 153 20. programmable co unter array .................................................................... 154 figure 20.1. pca block diagram ................................................................................................ ................. 154 20.1. capture/com p are m odules ........................................................................................................ ...... 155 table 20.1. pca0cpm register settings for pca capture/com p are m odules ........................................... 155 figure 20.2. pca inte rrupt block diagram ...................................................................................... ............. 155 figure 20.3. pca capt ure mode diagram ......................................................................................... ........... 156 figure 20.4. pca software tim e r mode diagram .................................................................................. ...... 157 figure 20.5. pca high speed output mode diagram ............................................................................... ... 157 figure 20.6. pca pw m mode diagram ............................................................................................. .......... 158 20.2. pca counter /tim er .............................................................................................................. ........... 159 table 20.2. pca tim e base input options ........................................................................................ ............. 159 figure 20.7. pca counter /tim er block diagram .................................................................................. ....... 159 20.3. register descrip tions for pca .................................................................................................. ...... 160 figure 20.8. pca0cn: pc a control register ...................................................................................... ......... 160 figure 20.9. pca0md: pca mode register ........................................................................................ ........ 161 figure 20.10. pca0cpmn: pca ca pture/com p are registers ...................................................................... 162 figure 20.11. pca0l: pca counter/tim er low by te ............................................................................... .. 163 figure 20.12. pca0h: pca counter/tim er high by te .............................................................................. .. 163 figure 20.13. pca0cpln: pca capture m odule low by te ........................................................................ 163 figure 20.14. pca0cphn: pca capture m odule high by te ....................................................................... 163 21. jtag (ieee 1149.1) ........................................................................................................ 164 figure 21.1. ir: jtag instruction register .................................................................................... .............. 164 21.1. boundary scan .................................................................................................................. ............... 165 r e v. 1.7 6
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 21.1. boundary data register bit definitions ............................................................................ ......... 165 figure 21.2. deviceid: jtag device id register ................................................................................ .... 166 21.2. flash program m i ng com m a nds ..................................................................................................... .. 167 figure 21.3. flashcon: jt ag flash contro l regi ster ............................................................................ . 168 figure 21.4. flashadr: jtag flash addre ss regi ster ............................................................................ 168 figure 21.5. flashdat: jt ag flash data register ............................................................................... ... 169 figure 21.6. flashscl: jt ag flash scal e regi ster .............................................................................. ... 169 21.3. debug support .................................................................................................................. ............... 170 7 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1. system overview the c8051f000 fam ily are fully integrat ed m i xed-signal system on a chip mc us with a true 12-bit m u lti-channel adc (f000/01/02/05/ 06/07), or a true 10-bit m u lti-channel adc (f 010/11/12/15/16/17). see the product selection guide in table 1.1 for a quick reference of each mcus? feat ure set. each has a program m a ble gain pre-am plifier, t w o 12-bi t dac s, t w o vol t a ge com p arat ors (except for t h e f002/ 07/ 12/ 17, whi c h have one), a vol t a ge reference, and an 8051-com p at i b l e m i crocont rol l e r core wi t h 32kby t e s of flash m e m o ry . there are al so i2c / sm b u s, uart, and spi serial interfaces im plem ented in hardware (not ?bit-banged? in user software) as well as a program m a bl e c ount er/ t i m er array (pc a ) wi t h fi ve capt u re/ c om pare m odul es. there are al so 4 general - purpose 16-bi t t i m ers and 4 by t e -wi d e general - purpose di gi t a l po rt i/ o. the c 8051f000/ 01/ 02/ 10/ 11/ 12 have 256 by t e s of r a m and execut e up t o 20m ips, whi l e t h e c 8051f005/ 06/ 07/ 15/ 16/ 17 have 2304 by t e s of r a m and execut e up t o 25m ips. w ith an on-board vdd m onitor, w d t, and clock oscillato r, the mcus are truly sta nd-alone system -on-a-chip sol u t i ons. each m c u effect i v el y confi gures and m a nage s t h e anal og and di gi t a l peri pheral s . the flash m e m o ry can be reprogram m e d even in-circuit, providing non-volatile data st orage, and also allowing field upgrades of the 8051 fi rm ware. each m c u can al so i ndi vi dual l y shut down any or al l of t h e peri pheral s t o conserve power. on-board jtag debug support al l o ws non-i n t r usi v e (uses no on-chi p resources), ful l speed, i n -ci r cui t debug usi ng t h e product i on m c u i n st al l e d i n t h e fi nal appl i cat i on. thi s debug sy st em support s i n spect i on and m odi fi cat i on of m e m o ry and regi st ers, set t i ng breakpoi nt s, wat c hpoi nt s, si ngl e st eppi ng, and run and hal t com m a nds. al l anal og and di gi t a l peri pheral s are ful l y funct i onal when usi ng jtag debug. each m c u i s speci fi ed for 2.7v-t o-3.6v operat i on over t h e i ndust r i a l t e m p erat ure range (-45c t o +85c ). the port i/ os, / r st, and jtag pi ns are t o l e rant for i nput si gnal s up t o 5v. the c 8051f000/ 05/ 10/ 15 are avai l a bl e i n t h e 64-pi n tqfp (see bl ock di agram i n fi gure 1.1). the c 8051f001/ 06/ 11/ 16 are avai l a bl e i n t h e 48-pi n tqfp (see bl ock di agram i n fi gure 1.2). the c 8051f002/ 07/ 12/ 17 are avai l a bl e i n t h e 32-pi n lqfp (see bl ock di agram i n fi gure 1.3). table 1.1. product selection guide mips (peak ) flash memory ram smbus/i2c spi uart t i m e r s ( 16- bit) pr ogr am m a ble counter ar r a y digital port i/o?s adc resolution (bits) adc max sp eed (k sp s) adc i nputs vo ltag e referen ce temperature sensor dac resolution dac outputs voltage comparators package c 8 0 5 1 f 0 0 0 2 0 3 2 k 2 5 6 ? ? ? 4 ? 3 2 1 2 1 0 0 8 ? ? 1 2 2 2 64t q f p c 8 0 5 1 f 0 0 1 2 0 3 2 k 2 5 6 ? ? ? 4 ? 1 6 1 2 1 0 0 8 ? ? 1 2 2 2 48t q f p c 8 0 5 1 f 0 0 2 2 0 3 2 k 2 5 6 ? ? ? 4 ? 8 1 2 1 0 0 4 ? ? 1 2 2 1 32l q f p c 8 0 5 1 f 0 0 5 2 5 3 2 k 2 3 0 4 ? ? ? 4 ? 3 2 1 2 1 0 0 8 ? ? 1 2 2 2 64t q f p c 8 0 5 1 f 0 0 6 2 5 3 2 k 2 3 0 4 ? ? ? 4 ? 1 6 1 2 1 0 0 8 ? ? 1 2 2 2 48t q f p c 8 0 5 1 f 0 0 7 2 5 3 2 k 2 3 0 4 ? ? ? 4 ? 8 1 2 1 0 0 4 ? ? 1 2 2 1 32l q f p c 8 0 5 1 f 0 1 0 2 0 3 2 k 2 5 6 ? ? ? 4 ? 3 2 1 0 1 0 0 8 ? ? 1 2 2 2 64t q f p c 8 0 5 1 f 0 1 1 2 0 3 2 k 2 5 6 ? ? ? 4 ? 1 6 1 0 1 0 0 8 ? ? 1 2 2 2 48t q f p c 8 0 5 1 f 0 1 2 2 0 3 2 k 2 5 6 ? ? ? 4 ? 8 1 0 1 0 0 4 ? ? 1 2 2 1 32l q f p c 8 0 5 1 f 0 1 5 2 5 3 2 k 2 3 0 4 ? ? ? 4 ? 3 2 1 0 1 0 0 8 ? ? 1 2 2 2 64t q f p c 8 0 5 1 f 0 1 6 2 5 3 2 k 2 3 0 4 ? ? ? 4 ? 1 6 1 0 1 0 0 8 ? ? 1 2 2 2 48t q f p c 8 0 5 1 f 0 1 7 2 5 3 2 k 2 3 0 4 ? ? ? 4 ? 8 1 0 1 0 0 4 ? ? 1 2 2 1 32l q f p r e v. 1.7 8
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 1.1. c8051f000/05/10/15 block diagram por t 0 lat c h por t 1 lat c h jtag logic tck tms tdi tdo uart smb u s sp i b u s pc a 32k by t e fl a s h 2048 by t e xr a m (f005/ 15 on l y ) dac 0 da c0 (12 - b i t) sfr bus pr o g ga in por t 2 lat c h por t 3 lat c h 8 0 5 1 c o r e tim e rs 0, 1, 2 ti me r 3 da c1 (12 - b i t) ad c 100 ks ps a m u x ain 0 ain 1 ain 2 ain 3 ain 4 ain 5 ain 6 ain 7 p1 . 0 p1 . 1 p1 . 2 p1 . 3 p1 . 4 p1 . 5 p1 . 6 p1 . 7 p 1 d r v p0 . 0 p0 . 1 p0 . 2 p0 . 3 p0 . 4 p0 . 5 p0 . 6 p0 . 7 p 0 d r v p3 . 0 p3 . 1 p3 . 2 p3 . 3 p3 . 4 p3 . 5 p3 . 6 p3 . 7 p 3 d r v p2 . 0 p2 . 1 p2 . 2 p2 . 3 p2 . 4 p2 . 5 p2 . 6 p2 . 7 p 2 d r v dac 1 cp0 + cp0 - cp1 + cp1 - vre f c r o s s b a r s w i t c h av+ av+ vdd vdd vdd dgnd dgnd dgnd agnd agnd xtal1 xtal2 ex t e r nal o s cilla to r ci rc uit sy stem c l o c k in te r n a l o s cilla to r di g i tal pow e r a n al og pow e r debug hw te mp boun dary sc an 256 by t e ra m cp 0 cp 1 vr ef vdd m oni t o r re s e t /rst wd t 9 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 1.2. c8051f001/06/11/16 block diagram jt a g lo gic tc k tm s td i td o 32 k b yt e fla s h 20 48 by te xr a m (f 00 6/16 onl y ) s f r bus 8 0 5 1 c o r e p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p 1 d r v p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p 0 d r v p 3 d r v p 2 d r v av + av + vd d vd d dg nd dg nd dg nd dg nd ag nd ag nd xt al 1 xt al 2 ex t e r n a l o s cillator ci r c u i t syst e m cl oc k intern al o s cillator di gi t a l p o w e r an alo g po w e r d ebu g hw bo und ary s c an 2 56 by t e ram po r t 0 la t c h po r t 1 la t c h uart smbu s sp i bu s pca po r t 2 la t c h po r t 3 la t c h time rs 0,1,2 time r 3 c r o s s b a r s w i t c h d ac0 da c 0 ( 12- b i t) pr o g gain da c 1 ( 12- b i t) adc 1 00ksps a m u x a in0 a in1 a in2 a in3 a in4 a in5 a in6 a in7 d ac1 c p0+ c p0- c p1+ c p1- v ref te mp cp0 cp1 vr e f vdd mo ni t o r res e t /r st wd t r e v. 1.7 10
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 1.3. c8051f002/07/12/17 block diagram jt ag logic tck tms tdi tdo 32k by t e fla s h 2 048 by t e xr am (f 00 7/ 1 7 on l y ) sf r b u s 8 0 5 1 c o r e p 1 d r v p0. 0 p0. 1 p0. 2 p0. 3 p0. 4 p0. 5 p0. 6 p0. 7 p 0 d r v p 3 d r v p 2 d r v av+ av+ vdd vdd dgnd dgnd agnd agnd xtal1 xtal2 e x t e rnal o sci lla to r circ uit sy s t e m clo c k in te r n al o sci lla to r di g i t a l pow e r a n al og pow e r debug hw boundar y sc an 256 by t e ram por t 0 lat c h por t 1 lat c h uart smb u s sp i b u s pc a por t 2 lat c h por t 3 lat c h tim e rs 0, 1, 2 ti me r 3 c r o s s b a r s w i t c h d ac0 da c0 (12-bi t ) pr o g gain da c1 (12-bi t ) ad c 100 ks ps a m u x a in0 a in1 a in2 a in3 d ac1 c p0+ c p0- v ref te m p cp 0 cp 1 vr ef vd d monit o r r e set /rst wd t 11 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1.1. cip-51 tm cpu 1.1.1. fully 8051 com p atible the c8051f000 fam ily utilizes silicon laboratories? proprieta ry cip-51 m i crocontroller core. the cip-51 is fully co m p atib le with th e mcs-5 1 tm i n st ruct i on set . st andard 803x/ 805x asse m b l e rs and com p i l e rs can be used t o devel op soft ware. the core has al l t h e peri pheral s i n cl uded wi t h a st andard 8052, i n cl udi ng four 16-bi t counter/tim ers, a full-duplex uart, 256 bytes of internal ram space, 128 byte special function register (sfr) address space, and four byte-wide i/o ports. 1.1.2. improved throughput the c i p-51 em pl oy s a pi pel i n ed archi t ect ure t h at great l y i n creases i t s i n st ruct i on t h roughput over t h e st andard 8051 archi t ect ure. in a st andard 8051, al l i n st ruct i ons except for m u l and div t a ke 12 or 24 sy st em cl ock cy cl es t o execut e wi t h a m a xi m u m sy st em cl ock of 12-t o -24m hz. b y cont rast , t h e c i p-51 core execut e s 70% of i t s i n st ruct i ons i n one or t w o sy st em cl ock cy cl es, wi t h onl y four i n st ruct i ons t a ki ng m o re t h an four sy st em cl ock cycles. the c i p-51 has a t o t a l of 109 i n st ruct i ons. the num ber of i n st ruct i ons versus t h e sy st em cl ock cy cl es t o execut e th em is as fo llo ws: instructions 2 6 5 0 5 1 4 7 3 1 2 1 clocks to execute 1 2 2/ 3 3 3 / 4 4 4 / 5 5 8 w i t h t h e c i p-51?s m a xi m u m sy st em cl ock at 25m hz, i t has a peak t h roughput of 25m ips. fi gure 1.4 shows a com p ari s on of peak t h roughput s of vari ous 8-bi t m i crocont rol l e r cores wi t h t h ei r m a xi m u m sy st em cl ocks. figure 1.4. comparison of peak mcu execution speeds 5 10 15 20 ad uc 81 2 80 51 (1 6mhz clk) p h il ip s 8 0c51 ( 3 3mhz clk) m i c r oc hi p pic17 c 7 5x (33 m h z c l k) silicon la bs ci p - 5 1 ( 2 5mhz clk) mips 25 r e v. 1.7 12
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1.1.3. additional features the c 8051f000 m c u fam i l y has several key enhancem ent s bot h i n si de and out si de t h e c i p-51 core t o i m prove i t s overal l perform ance and ease of use i n t h e end appl i cat i ons. the ext e nded i n t e rrupt handl er provi des 21 i n t e rrupt sources i n t o t h e c i p-51 (as opposed t o 7 for t h e st andard 8051), al l o wi ng t h e num erous anal og and di gi t a l peri pheral s t o i n t e rrupt t h e cont rol l e r. an i n t e rrupt dri v en sy st em requi res l e ss i n t e rvent i on by t h e m c u, gi vi ng i t m o re effect i v e t h roughput . the ext r a i n t e rrupt sources are very u s efu l wh en b u ild in g m u lti-task in g , real-tim e system s. there are up t o seven reset sources for t h e m c u: an on-board vdd m oni t o r, a w a t c hdog ti m e r, a m i ssi ng cl ock det ect or, a vol t a ge l e vel det ect i on from c o m p arat or 0, a for ced soft ware reset , t h e c nvstr pi n, and t h e / r st pi n. the /rst pin is bi-directional, accom m oda ting an external reset, or allowing the internally generated por to be out put on t h e / r st pi n. each reset source except for t h e vdd m oni t o r and reset input pi n m a y be di sabl ed by t h e user in software. the w d t m a y be perm anently en abl e d i n soft ware aft e r a power-on reset duri ng m c u in itializatio n . the m c u has an i n t e rnal , st and al one cl ock generat o r whi c h i s used by default as the system clock after any reset. if d e sired , th e clo c k so u r ce m a y b e switch e d o n th e fly to th e ex tern al o s cillato r, wh ich can u s e a crystal, ceram ic resonat o r, capaci t o r, r c , or ext e rnal cl ock source t o generat e the system clock. this can be extrem ely useful in low power appl i cat i ons, al l o wi ng t h e m c u t o run from a sl ow ( power savi ng) ext e rnal cry s t a l source, whi l e peri odi cal l y switch i n g to th e fast (u p to 1 6 m hz) in tern al o s cillato r as n eed ed . figure 1.5. on-board clock and reset wd t xt al 1 xt al 2 os c in te rn a l cl oc k ge ner at or sy st em clock ci p- 51 m i c r oc ont r o lle r co re mi ss in g clock detector ( o ne- sho t ) wdt st r obe so f t w a r e r e s e t e x tend ed i n t e r r u pt h andl er cl o ck s e l e ct /r st + - vdd s uppl y res e t ti meout (w i r ed - o r ) syst e m r e se t su ppl y mo nit o r pre re s e t funn el + - cp 0+ co mparat or 0 cp 0- (p or t i/ o) cros sba r cn v s t r (cnvst r re s e t e nab le) (cp0 re se t en ab l e ) en wdt e nabl e en mc d e nabl e 13 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1.2. on-board memory the c i p-51 has a st andard 8051 program and dat a address conf i gurat i on. it i n cl udes 256 by t e s of dat a r a m , wi t h the upper 128 bytes dual-m a pped. indi rect addressing accesses the upper 128 by tes of general purpose ram, and direct addressing accesses the 128 byte sfr address space. the lower 128 byte s of ram are accessible via direct and i ndi rect addressi ng. the fi rst 32 by t e s are addressabl e as four banks of general - purpose regi st ers, and t h e next 16 by t e s can be by t e addressabl e or bi t addressabl e. the cip-51 in the c8051f005/06/ 07/15/16/17 mcus additi onally has a 2048 byte ram block in the external data m e m o ry address space. this 2048 byte block can be addressed over the entir e 64k external data m e m o ry address range (see fi gure 1.6). the m c u?s program m e m o ry consi s t s of 32k + 128 by t e s of flash. thi s m e m o ry m a y be reprogram m e d i n - sy st em i n 512 by t e sect ors, and requi res no speci al o ff-chi p program m i ng vol t a ge. the 512 by t e s from addresses 0x7e00 to 0x7fff are reserved for factory use. there is also a single 128-byte sect or at address 0x8000 to 0x807f, which m a y be useful as a sm all table for software consta nts or as additional program space. see figure 1.6 for the m c u s y s t e m me mo r y ma p . figure 1.6. on-board memory map f l ash (in-sy s t em p r og ram m a b le in 512 by te sectors) progr a m m e m o r y 0x 00 00 0x 7f f f (d irec t a nd indirec t a ddres si n g ) 0x 00 0x 7f u pper 128 r a m (indir e c t address i ng only ) 0x 80 0x f f special func tion reg i ste r 's (d irec t addres si n g only ) r eserved 0x 7 e 00 0x 7d f f 1 28 by te isp f l ash 0x 80 00 0x 807f da ta m e m o r y general p u r p os e re gist e r s 0x 1f 0x 20 0x 2f bit ad dr e s s a ble low er 128 r a m (d irec t a nd indirec t address i ng ) 0x 30 i n ter n al data addr ess space ex ter n al data addr ess space ram - 2 048 by t e s ( a cce ssa b l e u s i n g m o v x i n st ru ct io n ) 0x 0000 0x 07 f f (s am e 2 048 b y te ram bl o c k ) 0x 0800 0x 0ff f (s am e 2 048 b y te ram bl o c k ) 0 x f 800 0 x ff ff t h e s a m e 20 4 8 by te r a m b l oc k c an b e add r e ss ed o n 2 k b oun dari e s thr o ugh ou t the 64k ex ternal data me m o ry s p a c e. (s am e 2 048 b y te ram bl o c k ) 0x 1000 0x 17 f f r e v. 1.7 14
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1.3. jtag debug and boundary scan the c 8051f000 fam i l y has on-chi p jtag and debug ci rcui t r y t h at provi de non-i n t r usi ve, fu ll sp eed , in -circu it debug usi ng t h e product i on part i n st al l e d i n t h e end appl i c at i on usi ng t h e four-pi n jtag i/ f. the jtag port i s fully com p liant to ieee 1149.1, providing full bounda ry scan for test a nd m a nufacturing purposes. silicon labs? debug system supports in spection and m odification of m e m o ry and register s, breakpoints, watchpoints, a stack m onitor, and si ngle stepping. no additional target ram, program m e m o ry, tim ers, or com m uni cat i ons channel s are requi red. al l t h e di gi t a l and anal og peri pheral s are funct i onal and work correct l y whi l e debuggi ng. al l t h e peri pheral s (except for t h e adc ) are st al l e d when t h e m c u i s hal t e d, duri ng si ngl e st eppi ng, or at a breakpoi nt i n order t o keep t h em i n sy nc. the c 8051f000dk, c 8051f005dk, c 8051f010dk, and c 8051f015dk are devel opm ent ki t s wi t h al l t h e hardware and soft ware nece ssary t o devel op appl i cat i on code and perform i n -ci r cui t debug wi t h t h e c 8051f000/ 1/ 2, f005/ 6/ 7, f010/ 1/ 2, and f015/ 6/ 7 m c us respect i v el y . th e ki t i n cl udes soft ware wi t h a devel oper?s st udi o and debugger, an i n t e grat ed 8051 assem b l e r, and an r s -232 t o jt ag prot ocol t r ansl at or m odul e referred t o as t h e ec . it al so has a t a rget appl i cat i on board with the associated mcu installed and a l a rge prot ot y p i ng area, pl us t h e r s - 232 and jtag cabl e s, and wal l - m ount power suppl y . the devel opm ent ki t requi res a w i ndows 95/ 98/ nt/ 2000/ xp com put er wi t h one avai l a bl e r s -232 seri al port . as shown i n fi gure 1.7, t h e pc i s connect ed vi a r s -232 t o t h e ec . a si x-i n ch ri bbon cabl e connect s t h e ec t o t h e user?s appl i cat i on board, pi cki ng up t h e four jtag pi ns and vdd and gnd. the ec t a kes i t s power fro m t h e appl i cat i on board. it requi res roughl y 20m a at 2.7-3.6v. for appl i cat i ons where t h ere i s not suffi ci ent power avai l a bl e from t h e t a rget board, t h e provi ded power suppl y can be connect ed di rect l y t o t h e ec . thi s i s a vast l y superi or confi gurat i on for devel opi ng and debuggi ng em bedded appl i cat i ons com p ared t o st andard m c u em ul at ors, whi c h use on-board ?ic e c h i p s? and t a rg et cabl e s and requi re t h e m c u i n t h e appl i cat i on board to be socketed. silicon labs? debug environm ent both incr eases ease of use and preserves the perform ance of the preci si on anal og peri pheral s . figure 1.7. debug environment diagram ta r g e t p c b rs- 2 32 ec c8051 f0 05 vdd g nd jtag (x 4 ) , vd d, gnd w i n d o w s 95/98/n t /2000/x p s ilicon labs i n teg r at ed d e v e lo pm ent e n v i ronment 15 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1.4. programmable digital i/o and crossbar the st andard 8051 port s (0, 1, 2, and 3) are avai l a bl e on t h e m c us. al l four port s are pi nned out on t h e f000/ 05/ 10/ 15. port s 0 and 1 are pi nned out on t h e f001/ 06/ 11/ 16, and onl y port 0 i s pi nned out on t h e f002/07/12/17. the ports not pi nned out are still available for software use as general purpose registers. the port i/ o behave l i k e t h e st andard 8051 wi t h a few enhancem ent s . each port i/ o pi n can be confi gured as ei t h er a push-pul l or open-drai n out put . al so, t h e ?weak pul l - ups? whi c h are norm a lly fixed on an 8051 can be globa lly disabled, providing additional power saving capabilities for low power appl i cat i ons. perh ap s th e m o st u n i q u e en h a n cem en t is th e dig ital cro ssb ar. th is is essen tially a larg e d i g ital switch i n g n e two r k t h at al l o ws m a ppi ng of i n t e rnal di gi t a l sy st em resources t o port i/ o pi ns on p0, p1, and p2. (see fi gure 1.8.) unlike m i crocontrollers with standard m u ltiplexed digital i/o, all com b ina tions of functions are supported. the on-board counter/tim ers, serial buses, hw interrupts, adc start of conversion input , com p arator outputs, and ot her di gi t a l si gnal s i n t h e cont rol l e r can be confi gured t o appear on t h e port i/ o pi ns speci fi ed i n t h e c r ossbar co n t ro l reg i sters. th is allo ws th e u s er to select th e exact m i x of general purpose port i/ o and di gi t a l resources needed for hi s part i c ul ar appl i cat i on. figure 1.8. digital crossbar diagram xb r 0 , xb r 1 , x b r 2 reg i ster s pr t3cf reg i s t er ex ternal pi ns p0 p1 p2 8 8 8 ( i nter n a l digi tal sign als) por t latches p3 p3 i/ o ce l l s p3. 0 di g i t a l cr ossbar pr i o r i ty de co de r p1 i/ o ce l l s sm bu s 2 spi 4 ua rt 2 pc a 6 t0 , t1 , t2 6 sys cl k cn vs t r p3. 7 p1. 0 p1. 7 p2 i/ o ce l l s p2. 0 p2. 7 p0 i/ o ce l l s p0. 0 p0. 7 8 hi g hest pr ior i t y low est pr ior i t y h i g hest pr i ori ty low est pr i ori ty 8 8 ( p 2.0-p 2.7) ( p 1.0-p 1.7) ( p 0.0-p 0.7) 8 pr t0 c f , p r t1 c f , pr t 2 cf reg i st er s ( p 3.0-p 3.7) co m p t r . outputs 2 r e v. 1.7 16
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1.5. programmable counter array the c8051f000 mcu fam ily has an on-boa rd program m a ble counter/tim er arra y (pca) in addition to the four 16-bit general-purpose counter/tim ers. the pca consists of a dedicated 16-bit c ounter/tim er tim ebase with 5 program m a bl e capt u re/ c om pare m odul es. the t i m ebase get s i t s cl ock from one of four sources: t h e sy st em cl ock di vi ded by 12, t h e sy st em cl ock di vi ded by 4, ti m e r 0 overfl ow, or an ext e rnal c l ock input (ec i). each capt u re/ c om pare m odul e can be confi gured t o opera t e i n one of four m odes: edge-tri ggered c a pt ure, soft ware ti m e r, hi gh speed out put , or pul s e w i dt h m odul at or. the pc a c a pt ure/ c o m p are m odul e i/ o and ext e rnal c l ock input are rout ed t o t h e m c u port i/ o vi a t h e di gi t a l c r ossbar. figure 1.9. pca block diagram 16 -b it co un te r/t i m e r ca pture / com p are mo du le 1 ca ptu r e/com p a r e mod u le 0 c a pt ur e/ c o mpa r e mod u l e 2 ca ptu r e/com p a r e mod u le 3 ca pture / com p are mo du le 4 cex 1 sy ste m clo c k /1 2 t0 ov er fl o w eci crossbar cex 2 cex 3 cex 4 cex 0 port i/o /4 1.6. serial ports the c 8051f000 m c u fam i l y i n cl udes a ful l - dupl ex uar t, spi b u s, and i2c / sm b u s. each of t h e seri al buses i s fu lly im p l em en ted in h a rd ware an d m a k e s ex ten s iv e u s e o f th e cip-5 1 ? s in terru p t s, th u s req u i rin g v e ry little i n t e rvent i on by t h e c p u. the seri al buses do not ?share? res ources such as tim ers, interrupt s , o r p o r t i / o , s o a n y o r al l of t h e seri al buses m a y be used t oget h er. 17 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1.7. analog to digital converter the c8051f000/1/2/5/6/ 7 has an on-chip 12-bit sar adc with a 9- channel input m u ltiplexer and program m a ble gain am plifier. w ith a m a xim u m throughput of 100ksps, the adc offers true 12-bit accuracy with an inl of r 1lsb . the adc i n t h e c 8051f010/ 1/ 2/ 5/ 6/ 7 i s si m i l a r, but wi t h 10-bi t resol u t i on. each adc has a m a xi m u m t h roughput of 100ksps. each adc has an inl of r 1lsb, offering true 12-bit accu racy with the c8051f00x, and true 10-bit accuracy with the c8051f01x. there is also an on-board 15ppm vo ltage reference, or an external reference m a y be used vi a t h e vr ef pi n. the adc i s under ful l cont rol of t h e c i p-51 m i crocont rol l e r vi a t h e speci al funct i on r e gi st ers. one i nput channel is tied to an in tern al tem p eratu r e sen s o r , wh ile th e o t h e r ei ght channels are available exte rn ally. each p a ir o f th e ei ght ext e rnal i nput channel s can be confi gured as ei t h er t w o si ngl e-ended i nput s or a si ngl e di fferent i a l i nput . the sy st em cont rol l e r can al so put t h e adc i n t o shut down t o save power. a p r o g r am m a b l e g a in am p lifier fo llo ws th e an alo g m u ltip lex e r. th e g a in can b e set in so ftware fro m 0 . 5 to 1 6 in powers of 2. the gai n st age can be especi al l y useful wh en di fferent adc i nput channel s have wi del y vari ed i nput vol t a ge si gnal s , or when i t i s necessary t o ?zoom i n ? on a sig n a l with a larg e dc o ffset (i n di fferent i a l m ode, a dac coul d be used t o provi de t h e dc offset ). c onversi ons can be st art e d i n four way s ; a soft ware co m m a nd, an overfl ow on ti m e r 2, an overfl ow on ti m e r 3, or an external signal input. this flexibility allows the start of conversion to be triggered by software events, external hw si gnal s , or convert cont i nuousl y . a com p l e t e d conversi on causes an i n t e rrupt , or a st at us bi t can be pol l e d i n software to determ ine the end of conversion. the resu lting 10 or 12-bit data word is latched into two sfrs upon com p l e t i on of a conversi on. the dat a can be ri ght or l e ft just i f i e d i n t h ese regi st ers under soft ware cont rol . co m p are reg i sters fo r th e adc d a ta can b e co n f ig u r ed to in terru p t th e co n t ro ller wh en adc d a ta is with in a speci fi ed wi ndow. the adc can m oni t o r a key vol t a ge cont i nuousl y i n background m ode, but not i n t e rrupt t h e cont rol l e r unl ess t h e convert ed dat a i s wi t h i n t h e speci fi ed wi ndow. figure 1.10. adc diagram 100ksps sa r adc + - control & dat a sf r ' s sfr bus + - + - + - 9- t o -1 amux ( se or di ff) + - x ain 0 ain 1 ain 2 ain 3 ain 4 ain 5 ain 6 ain 7 te m p sen sor pr o g r amma ble ga i n am p v ref ref ( n ot b ond ed out on f 0 02 , f00 7 , f01 2 , and f017 r e v. 1.7 18
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1.8. comparators and dacs the c 8051f000 m c u fam i l y has t w o 12-bi t dac s and t w o com p arat ors on chi p (t he second com p arat or, c p 1, i s not bonded out on the f002, f007, f012, and f017). the mc u data and control interface to each com p arator and dac is via the special function regi sters. the mcu can place any dac or com p arator in low power shutdown m ode. the com p arat ors have soft ware program m a bl e hy st eresi s . each com p arat or can generat e an i n t e rrupt on i t s ri si ng edge, fal l i ng edge, or bot h. the com p arat ors? out put st at e can al so be pol l e d i n soft ware. these i n t e rrupt s are capabl e of waki ng up t h e m c u from i d l e m ode. the com p arat or out put s can be program m e d t o appear on t h e port i/ o pi ns vi a t h e c r ossbar. the dac s are vol t a ge out put m ode and use t h e sam e vol t a ge reference as the adc. they are especially useful as references for t h e com p arat ors or offset s for t h e di fferent i a l i nput s of t h e adc . figure 1.11. comparator and dac diagram sfr's (data and cntrl) cp1 cp1+ cp1- dac0 dac0 dac1 dac1 ref ref cp0 cp0+ cp0- cip-51 and interrupt handler crossbar cp1 cp0 (port i/o) (port i/o) + - cp0 + - cp1 (not bonded out on f002, f007, f012, and f017) 19 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 2. absolute maximum ratings* am bient tem p erature under bias ................................................................................................. ................ -55 to 125 q c storage tem p erature ............................................................................................................ ...................... -65 to 150 q c voltage on any pin (except vdd and port i/o) with respect to dgnd ................................... -0.3v to (vdd + 0.3v) voltage on any port i/o pin or /rst with respect to dgnd .................................................................... -0. 3v t o 5.8v voltage on vdd with respect to dgnd ............................................................................................ ....... -0.3v to 4.2v m a xim u m total current through vdd, av+, dgnd and agnd ..................................................................... 800m a m a xim u m output current s unk by any port pin .................................................................................... ............... 100m a m a xim u m output current sunk by any other i/o pin ............................................................................... .............. 25m a maxim u m output current sour ced by any port pin ................................................................................. ............. 100m a maxim u m output current sourced by any other i/o pin ............................................................................ ............ 25m a *not e: st resses above t hose l i s t e d under ?absol ut e m a xi m u m r a t i ngs? m a y cause perm anent dam a ge t o t h e devi ce. thi s i s a st ress rat i ng onl y and funct i onal operat i on of t h e devi ces at t hose or any ot her condi t i ons above t hose indicated in the operation listings of th is specification is not im plied. e xposure to m a xim u m rating conditions for ex ten d e d p e rio d s m a y affect d e v i ce reliab ility. 3. global dc electrical characteristics -40 q c to +8 5 q c unless otherwise specified. p a r a m e t e r c o n d i t i o n s m i n t y p max u n i t s anal og suppl y vol t a ge (not e 1) 2.7 3.0 3.6 v anal og suppl y c u rrent int e rnal r e f, adc , dac , c o m p arat ors all activ e 1 2 m a anal og suppl y c u rrent wi t h analog sub-system s inactive internal ref, adc, dac, com p arators all d i sab l ed , o s cillato r d i sab l ed 5 2 0 p a anal og-t o -di g i t a l suppl y delta ( | vdd ? av+ | ) 0 . 5 v di gi t a l suppl y vol t a ge 2.7 3.0 3.6 v di gi t a l suppl y c u rrent wi t h cpu active vdd = 2.7v, clock=25m hz vdd = 2.7v, clock=1m hz vdd = 2.7v, cl ock=32khz 1 2 . 5 0.5 10 m a ma p a di gi t a l suppl y c u rrent (shut down) oscillator not running 5 p a di gi t a l suppl y r a m dat a reten tio n vo ltag e 1 . 5 v specified operating tem p erature range - 4 0 + 8 5 q c sysclk (system clock frequency ) c 8051f005/ 6/ 7, c 8051f015/ 6/ 7 (not e 2) 0 2 5 m h z sysclk (system clock frequency ) c 8051f000/ 1/ 2, c 8051f010/ 1/ 2 (not e 2) 0 2 0 m h z tsy s l (sysclk low tim e ) 18 ns tsy s h (sysc l k hi gh ti m e ) 18 ns not e 1: anal og suppl y av+ m u st be great er t h an 1v for vdd m oni t o r t o operat e . not e 2: sysc lk m u st be at l east 32 khz t o enabl e debuggi ng. r e v. 1.7 20
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 4. pinout and package definitions table 4.1. pin definitions pin numbers name f000 f005 f010 f015 f001 f006 f011 f016 f002 f007 f012 f017 ty pe description vdd 31, 40, 62 23, 32 18, 20 digital voltage supply . dgnd 30, 41, 61 22, 33, 27, 19 17, 21 digital ground. av+ 16, 17 13, 43 9, 29 positive analog voltage supply . agnd 5, 15 44, 12 8, 30 analog ground. tck 2 2 1 8 1 4 d in jtag test clock with internal pull-up. tms 2 1 1 7 1 3 d in jtag test-mode select with internal pull-up. tdi 2 8 2 0 1 5 d in jtag test data input with internal pull- up. tdi is latched on a rising edge of tck. tdo 2 9 2 1 1 6 d out jtag test data output with internal pull-up. data is shifted out on tdo on the falling edge of tck. tdo output is a tri-state driver. xtal1 1 8 1 4 1 0 a in cry s tal input. this pin is the return for the internal oscillator circuit for a cry s tal or ceram ic res onator. f o r a precis i on internal clock, connect a cry s tal or ceramic resonator from xtal1 to xt al2. if overdriven by an external cm os clock, this becom e s the s y s t em clock. xtal2 1 9 1 5 1 1 a out cry s tal output. this pin is the exc itation driver for a cry s tal or ceram ic resonator. /rst 2 0 1 6 1 2 d i/o chip reset. open-drain output of intern al voltage supply monitor. is driven low when vdd is < 2. 7v. an external source can force a sy stem reset by driving this pin low. vref 6 3 3 a i/o voltage reference. when configured as an input, this pin is the voltage reference for the mcu. otherwise, the internal reference drives this pin. cp0+ 4 2 2 a in comparator 0 non-inverting input. cp0- 3 1 1 a in comparator 0 inverting input. cp1+ 2 4 5 a in comparator 1 non-inverting input. cp1- 1 4 6 a in comparator 1 inverting input. dac0 6 4 4 8 3 2 a out digital to analog converter output 0. the dac0 voltage output. (see section 7 dac specification for complete description). dac1 6 3 4 7 3 1 a out digital to analog converter output 1. the dac1 voltage output. (see section 7 dac specification for complete description). ain0 7 4 4 a in analog mux channel input 0. (see adc specification for complete description). ain1 8 5 5 a in analog mux channel input 1. (see adc specification for complete description). ain2 9 6 6 a in analog mux channel input 2. (see adc specification for complete description). ain3 1 0 7 7 a in analog mux channel input 3. (see adc specification for complete description). ain4 1 1 8 a in analog mux channel input 4. (see adc specification for complete description). ain5 1 2 9 a in analog mux channel input 5. (see adc specification for complete description). 21 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 pin numbers name f000 f005 f010 f015 f001 f006 f011 f016 f002 f007 f012 f017 ty pe description ain6 1 3 1 0 a in analog mux channel input 6. (see adc specification for complete description). ain7 1 4 1 1 a in analog mux channel input 7. (see adc specification for complete description). p0.0 3 9 3 1 1 9 d i/o port0 bit0. (see the port i/o sub-sy st em section for complete description). p0.1 4 2 3 4 2 2 d i/o port0 bit1. (see the port i/o sub-sy st em section for complete description). p0.2 4 7 3 5 2 3 d i/o port0 bit2. (see the port i/o sub-sy st em section for complete description). p0.3 4 8 3 6 2 4 d i/o port0 bit3. (see the port i/o sub-sy st em section for complete description). p0.4 4 9 3 7 2 5 d i/o port0 bit4. (see the port i/o sub-sy st em section for complete description). p0.5 5 0 3 8 2 6 d i/o port0 bit5. (see the port i/o sub-sy st em section for complete description). p0.6 5 5 3 9 2 7 d i/o port0 bit6. (see the port i/o sub-sy st em section for complete description). p0.7 5 6 4 0 2 8 d i/o port0 bit7. (see the port i/o sub-sy st em section for complete description). p1.0 3 8 3 0 d i/o port1 bit0. (see the port i/o sub-sy st em section for complete description). p1.1 3 7 2 9 d i/o port1 bit1. (see the port i/o sub-sy st em section for complete description). p1.2 3 6 2 8 d i/o port1 bit2. (see the port i/o sub-sy st em section for complete description). p1.3 3 5 2 6 d i/o port1 bit3. (see the port i/o sub-sy st em section for complete description). p1.4 3 4 2 5 d i/o port1 bit4. (see the port i/o sub-sy st em section for complete description). p1.5 3 2 2 4 d i/o port1 bit5. (see the port i/o sub-sy st em section for complete description). p1.6 6 0 4 2 d i/o port1 bit6. (see the port i/o sub-sy st em section for complete description). p1.7 5 9 4 1 d i/o port1 bit7. (see the port i/o sub-sy st em section for complete description). p2.0 3 3 d i/o port2 bit0. (see the port i/o sub-sy st em section for complete description). p2.1 2 7 d i/o port2 bit1. (see the port i/o sub-sy st em section for complete description). p2.2 5 4 d i/o port2 bit2. (see the port i/o sub-sy st em section for complete description). p2.3 5 3 d i/o port2 bit3. (see the port i/o sub-sy st em section for complete description). p2.4 5 2 d i/o port2 bit4. (see the port i/o sub-sy st em section for complete description). p2.5 5 1 d i/o port2 bit5. (see the port i/o sub-sy st em section for complete description). p2.6 4 4 d i/o port2 bit6. (see the port i/o sub-sy st em section for complete description). p2.7 4 3 d i/o port2 bit7. (see the port i/o sub-sy st em section for complete description). p3.0 2 6 d i/o port3 bit0. (see the port i/o sub-sy st em section for complete description). p3.1 2 5 d i/o port3 bit1. (see the port i/o sub-sy st em section for complete description). p3.2 2 4 d i/o port3 bit2. (see the port i/o sub-sy st em section for complete description). p3.3 2 3 d i/o port3 bit3. (see the port i/o sub-sy st em section for complete description). p3.4 5 8 d i/o port3 bit4. (see the port i/o sub-sy st em section for complete description). p3.5 5 7 d i/o port3 bit5. (see the port i/o sub-sy st em section for complete description). p3.6 4 6 d i/o port3 bit6. (see the port i/o sub-sy st em section for complete description). p3.7 4 5 d i/o port3 bit7. (see the port i/o sub-sy st em section for complete description). r e v. 1.7 22
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 4.1. tqfp-64 pinout diagram 1 2 3 4 5 6 7 8 9 10 11 17 18 19 20 21 22 23 24 25 26 27 48 47 46 45 44 43 42 41 40 39 38 64 63 62 61 60 59 58 57 56 55 54 vdd ag nd p0. 3 p0 . 5 p0 . 6 p0 . 7 ag nd p0. 0 p0. 1 p0. 2 p1. 5 p1. 4 p1. 3 p1. 2 p1. 1 p0 . 4 xtal2 tms tc k /rs t xtal1 dac 0 td o td i dgn d dac 1 ai n0 ai n1 ai n2 ai n3 ai n4 ai n5 ai n6 ai n7 vref av+ vdd dg nd p1. 0 12 13 14 15 16 28 29 30 31 32 37 36 35 34 33 53 52 51 50 49 p1 . 6 p1 . 7 p2 . 2 p2 . 3 p3. 6 p3. 7 p2. 6 p2. 7 p3. 0 p3. 1 p3. 2 p3. 3 cp 0- cp1+ cp1- cp 0+ p2. 0 p2. 1 p3 . 5 p3 . 4 dg nd vdd av+ p2 . 4 p2. 5 c8051f000 c8051f005 c8051f010 C8051F015 23 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 4.2. tqfp-64 package draw ing a a1 a2 b d d1 e e e1 - 0.0 5 0.9 5 0.1 7 - - - - - - - - 0. 22 12 .0 0 10 .0 0 0. 50 12 .0 0 10 .0 0 1. 20 0. 15 1. 05 0. 27 - - - - - min (mm ) nom ( mm) max (m m) 1 64 e e1 e a1 b d d1 pin 1 designator a2 a r e v. 1.7 24
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 4.3. tqfp-48 pinout diagram 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 agnd p0.3 p0.5 p0.6 p0.7 agnd p0.0 p0.1 p0.2 p1.5 p1.4 p1.3 p1.2 p1.1 p0.4 xtal2 tms tck /rst xtal1 dac0 tdo tdi dgnd dac1 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 vref av+ dgnd p1.0 p1.6 p1.7 cp0- cp1+ cp1- cp0+ av+ 13 14 15 16 17 18 19 20 21 22 23 24 dgnd vdd vdd dgnd c8051f001 c8051f006 c8051f011 c8051f016 25 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 4.4. tqfp-48 package draw ing a a1 a2 b d d1 e e e1 - 0.05 0.95 0.17 - - - - - - - 1.00 0.22 9.00 7.00 0.50 9.00 7.00 1.20 0.15 1.05 0.27 - - - - - min (mm) nom (mm) max (mm) e e1 d d1 48 1 a1 e b pin 1 identifier a2 a r e v. 1.7 26
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 4.5. lqfp-32 pinout diagram 1 agnd p0.3 p0.5 p0.6 p0.7 agnd p0.0 p0.1 p0.2 p0.4 xtal2 tms tck /rst xtal1 dac0 tdo tdi dgnd dac1 ain0 ain1 ain2 ain3 vref av+ cp0- cp0+ av+ vdd dgnd c8051f002 c8051f007 c8051f012 c8051f017 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 vdd 27 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 4.6. lqfp-32 package draw ing a a1 a2 b d d1 e e e1 - 0.05 1.35 0.30 - - - - - - - 1.40 0.37 9.00 7.00 0.80 9.00 7.00 1.60 0.15 1.45 0.45 - - - - - min (mm) nom (mm) max (mm) pin 1 identifier a1 e b 1 32 e1 d1 d e a2 a r e v. 1.7 28
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 5. adc (12-bit, c8051f000/1/2/5/6/7 only) the adc subsystem for the c8051f000/1/ 2/5/6/7 consists of a 9-channel, configurable analog m u ltiplexer (amux), a program m a ble gain am plifier (pga), and a 100ksps, 12-bit successive-a pproxim a tion-register adc wi t h i n t e grat ed t r ack-and-hol d and program m a bl e wi ndow det ect or (see bl ock di agram i n fi gure 5.1). the am ux, pga, dat a c onversi on m odes, and w i ndow det ect or are a l l confi gurabl e under soft ware cont rol vi a t h e speci al funct i on r e gi st er?s shown i n fi gure 5.1. the adc s ubsy s t e m (adc , t r ack-and-hol d and pga) i s enabl e d onl y wh en th e adcen b it in th e adc co n t ro l reg i ster (adc0 c n, fig u r e 5 . 7 ) is set to 1 . th e adc su b s ystem is in lo w power shut down when t h i s bi t i s 0. the b i as enabl e bi t (b iase) i n t h e r e f0c n regi st er (see fi gure 9.2) m u st be set t o 1 i n order t o suppl y bi as t o t h e adc . figure 5.1. 12-bit adc functional block diagram 12-bit sar adc ref + - av+ temp sensor 12 + - + - + - 9-to-1 amux (se or diff) av+ comb logic 24 12 adwint adcen sysclk + - x ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 t m r 3 o v t 2 o v c n v s t r a d b u s y ( w ) conver si on st ar t agnd agnd amx0cf ai n01i c ai n23i c ai n45i c ai n67i c amx0sl amxad0 amxad1 amxad2 amxad3 adc0cf ampg n0 ampg n1 ampg n2 adcsc0 adcsc1 adcsc2 adc0cn adlj st adwi nt adstm0 adstm1 adbusy adcint adctm adcen adc0l adc0h adc0ltl adc0lth adc0gtl adc0gth 5.1. analog multiplexer and pga eight of the amux channels are availa b l e fo r ex tern al m easu r em en ts wh ile th e n i n t h ch an n e l is in tern ally connect ed t o an on-board t e m p erat ure sensor (t em perat u re t r ansfer funct i on i s shown i n fi gure 5.3). not e t h at t h e pga gai n i s appl i e d t o t h e t e m p erat ure sensor readi ng. am ux i nput pai r s can be program m e d t o operat e i n ei t h er the differential or single-ended m ode. this allows the user to select the best m easur em ent technique for each input channel, and even accom m odates m ode changes ?on-the-fl y?. the amux defaults to all single-ended inputs upon reset. there are two registers associ ated with th e amux: th e ch an n e l sel ect i on regi st er am x0sl (fi gure 5.5), an d th e co n f ig u r atio n reg i ster amx0 cf (fig u r e 5 . 4 ) . th e tab l e in fig u r e 5 . 5 sh o w s amux fu n c tio n a lity b y channel for each possible configuration. the pga am plif ies the amux output signal by an am ount determ ined by t h e am pgn2-0 bi t s i n t h e adc c onfi gurat i on regi st er, adc 0c f (fi gure 5.6). the pga can be soft ware- program m e d for gai n s of 0.5, 1, 2, 4, 8 or 16. it defaul t s t o uni t y gai n on reset . 29 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 5.2. adc modes of operation th e adc u s es vref to d e term in e its fu ll-scale v o ltag e , t hus t h e reference m u st be properl y confi gured before perform i ng a conversi on (see sect i on 9). the adc ha s a m a xi m u m conversi on speed of 100ksps. the adc conversi on cl ock i s deri ved from t h e sy st em cl ock. c onversi on cl ock speed can be reduced by a fact or of 2, 4, 8 or 16 via the adcsc bits in the adc0cf register. this is useful to adjust conversion speed to accom m odate di fferent sy st em cl ock speeds. a conversion can be initiated in one of four ways, de pending on the program m e d stat es of the adc start of conversion mode bits (adstm1, adstm0) in adc0cn. convers ions m a y be initiated by: 1. w r i t i ng a 1 t o t h e adb usy bi t of adc 0c n; 2. a ti m e r 3 overfl ow (i .e. t i m ed cont i nuous conversi ons); 3. a ri si ng edge det ect ed on t h e ext e rnal adc convert st art si gnal , c nvstr ; 4. a ti m e r 2 overfl ow (i .e. t i m ed cont i nuous conversi ons). w r i t i ng a 1 t o adb usy provi des soft ware cont rol of t h e adc whereby conversi ons are perform ed ?on-dem a nd?. during conversion, the adbusy bit is set to 1 and restored to 0 when conversi on is com p lete. the falling edge of adb usy t r i ggers an i n t e rrupt (when enabl e d) and set s t h e adc int i n t e rrupt fl ag. note: when conversions are performed ?on-demand?, the adcint flag, not adbusy, should be polled to determine when the conversion has completed. c onvert ed dat a i s avai l a bl e i n t h e adc dat a word m s b and lsb regi st ers, adc 0h, adc 0l. c onvert ed dat a can be ei t h er l e ft or ri ght just i f i e d i n t h e adc 0h: adc 0l regi st er pai r (see exam pl e i n fi gure 5.9) dependi ng on t h e program m e d st at e of t h e adljst bi t i n t h e adc 0c n regi st er. the adc tm bi t i n regi st er adc 0c n cont rol s t h e adc t r ack-and-hol d m ode. in i t s defaul t st at e, t h e adc i nput i s continuously tracked, except when a conve rsion is in progress. setting adctm to 1 allows one of four different l o w power t r ack-and-hol d m odes t o be speci fi ed by st at es of t h e adstm 1-0 bi t s (al s o i n adc 0c n): 1. tracki ng begi ns wi t h a wri t e of 1 t o adb usy and l a st s for 3 sar cl ocks; 2. tracki ng st art s wi t h an overfl ow of ti m e r 3 and l a st s for 3 sar cl ocks; 3. tracki ng i s act i v e onl y when t h e c nvstr i nput i s l o w; 4. tracki ng st art s wi t h an overfl ow of ti m e r 2 and l a st s for 3 sar cl ocks. m odes 1, 2 and 4 (above) are useful when t h e st art of conve rsi on i s t r i ggered wi t h a soft ware com m a nd or when t h e adc i s operat e d cont i nuousl y . m ode 3 i s used when t h e st ar t of conversi on i s t r i ggered by ext e rnal hardware. in t h i s case, t h e t r ack-and-hol d i s i n i t s l o w power m ode at t i m es when t h e c nvstr i nput i s hi gh. tracki ng can al so be di sabl ed (shut down) when t h e ent i r e chi p i s i n l o w power st andby or sl eep m odes. figure 5.2. 12-bit adc track and conversion example timing 1 2 3 4 5 6 7 8 9 1 01 1 1 21 31 4 1 51 6 cnvstr (adstm[1:0]=10) adctm=1 track convert low power mode adctm=0 track or convert convert track low power or convert timer2, timer3 overflow; write 1 to adbusy (adstm[1:0]=00, 01, 11) adctm=1 track convert low power mode adctm=0 track or convert convert track low power or convert a. adc timing for external trigger source b. adc timing for internal trigger sources sar clocks sar clocks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sar clocks r e v. 1.7 30
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 5.3. temperature sensor transfer function 0 -50 50 100 (celsius) 0.500 0.600 0.700 0.800 0.900 (volts) v temp = 0.00286(temp c ) + 0.776 for pga gain = 1 1.000 figure 5.4. amx0cf: amux configuration register (c8051f00x) r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e - - - - ain67ic ain45ic a i n 2 3 i c a i n 0 1 i c 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b a bi t s 7-4: unused. read = 0000b; w r i t e = don?t care b i t 3 : ain67ic : ain6, ain7 input pai r c onfi gurat i on b i t 0: ain6 and ain7 are i ndependent si ngl ed-ended i nput s 1: ain6, ain7 are (respect i v el y ) +, - di fferent i a l i nput pai r b i t 2 : ain45ic : ain4, ain5 input pai r c onfi gurat i on b i t 0: ain4 and ain5 are i ndependent si ngl ed-ended i nput s 1: ain4, ain5 are (respect i v el y ) +, - di fferent i a l i nput pai r b i t 1 : ain23ic : ain2, ain3 input pai r c onfi gurat i on b i t 0: ain2 and ain3 are i ndependent si ngl ed-ended i nput s 1: ain2, ain3 are (respect i v el y ) +, - di fferent i a l i nput pai r b i t 0 : ain01ic : ain0, ain1 input pai r c onfi gurat i on b i t 0: ain0 and ain1 are i ndependent si ngl ed-ended i nput s 1: ain0, ain1 are (respect i v el y ) +, - di fferent i a l i nput pai r n ote: the adc dat a w o rd i s i n 2?s com p l e m e nt form at for channel s confi gured as di fferent i a l . 31 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 5.5. amx0sl: amux channel select register (c8051f00x) r/w r / w r/w r/w r / w r/w r/w r/w r e s e t v a l u e - - - - a m x a d 3 a m x a d 2 a m x a d 1 a m x a d 0 00000000 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b b bi t s 7-4: unused. read = 0000b; w r i t e = don?t care bits3-0: am xad3-0: am ux address bits 0000-1111: adc input s sel ect ed per chart bel o w a m x 0 c f b i t s 3 - 0 a m x a d 3 - 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 x x x 0000 ain0 ain1 a i n 2 a i n 3 ain4 a i n 5 ain6 a i n 7 temp sensor 0001 +(ain0 ) -(ain1) ain2 a i n 3 a i n 4 ain5 a i n 6 ain7 temp sensor 0010 ain0 a i n 1 +(ain2 ) -(ain3) ain4 a i n 5 ain6 a i n 7 temp sensor 0011 +(ain0 ) -(ain1) +(ain2 ) -(ain3) ain4 a i n 5 ain6 a i n 7 temp sensor 0100 ain0 ain1 a i n 2 a i n 3 +(ain4 ) -(ain5) a i n 6 ain7 temp sensor 0101 +(ain0 ) -(ain1) a i n 2 ain3 +(ain4 ) -(ain5) a i n 6 ain7 temp sensor 0110 ain0 a i n 1 +(ain2 ) -(ain3) +(ain4 ) -(ain5) a i n 6 ain7 temp sensor 0111 +(ain0 ) -(ain1) +(ain2 ) -(ain3) +(ain4 ) -(ain5) a i n 6 ain7 temp sensor 1000 ain0 a i n 1 ain2 ain3 a i n 4 ain5 +(ain6 ) -(ain7) temp sensor 1001 +(ain0 ) -(ain1) ain2 a i n 3 a i n 4 ain5 +(ain6 ) -(ain7) temp sensor 1010 ain0 a i n 1 +(ain2 ) -(ain3) a i n 4 ain5 +(ain6 ) -(ain7) temp sensor 1011 +(ain0 ) -(ain1) +(ain2 ) -(ain3) a i n 4 ain5 +(ain6 ) -(ain7) temp sensor 1100 ain0 ain1 a i n 2 a i n 3 +(ain4 ) -(ain5) +(ain6 ) -(ain7) temp sensor 1101 +(ain0 ) -(ain1) a i n 2 ain3 +(ain4 ) -(ain5) +(ain6 ) -(ain7) temp sensor 1110 ain0 a i n 1 +(ain2 ) -(ain3) +(ain4 ) -(ain5) +(ain6 ) -(ain7) temp sensor 1111 +(ain0 ) -(ain1) +(ain2 ) -(ain3) +(ain4 ) -(ain5) +(ain6 ) -(ain7) temp sensor r e v. 1.7 32
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 5.6. adc0cf: adc configuration register (c8051f00x) r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e a d c s c 2 a d c s c 1 a d c s c 0 - - a m p g n 2 a m p g n 1 a m p g n 0 01100000 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b c b i t s 7-5: adc sc 2-0: adc sar c onversi on c l ock peri od b i t s 000: sar c onversi on c l ock = 1 sy st em c l ock 001: sar c onversi on c l ock = 2 sy st em c l ocks 010: sar c onversi on c l ock = 4 sy st em c l ocks 011: sar c onversi on c l ock = 8 sy st em c l ocks 1xx: sar c onversi on c l ock = 16 sy st em s c l ocks (not e: t h e sar c onversi on c l ock shoul d be d 2mhz) bi t s 4-3: unused. read = 00b; w r i t e = don?t care bits2 - 0 : ampgn2 -0 : adc in tern al am p lifier gain 000: gai n = 1 001: gai n = 2 010: gai n = 4 011: gai n = 8 10x: gai n = 16 11x: gai n = 0.5 33 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 5.7. adc0cn: adc control register (c8051f00x) r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e a d c e n a d c t m a d c i n t a d b u s y ads t m 1 a d s t m 0 a d w i n t a d l j s t 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: (bit addressable) 0xe8 bit7 : adcen: adc en ab le bit 0: adc di sabl ed. adc i s i n l o w power shut down. 1: adc enabl e d. adc i s act i v e and ready for dat a conversi ons. bit6 : adctm: adc track mo d e bit 0: w h en t h e adc i s enabl e d, t r acki ng i s al way s done unl ess a conversi on i s i n process 1: tracki ng defi ned by adstm 1-0 bi t s adstm 1-0: 00: tracki ng st art s wi t h t h e wri t e of 1 t o adb usy and l a st s for 3 sar cl ocks 01: tracki ng st art e d by t h e overfl ow of ti m e r 3 and l a st for 3 sar cl ocks 10: adc t r acks onl y when c nvstr i nput i s l ogi c l o w 11: tracki ng st art e d by t h e overfl ow of ti m e r 2 and l a st for 3 sar cl ocks b i t 5 : adc int: adc c onversi on c o m p l e t e int e rrupt fl ag (m ust be cleared by software) 0: adc has not com p l e t e d a dat a conversi on si nce t h e l a st t i m e t h i s fl ag was cl eared 1: adc has com p l e t e d a dat a conversi on bit4: adbusy: adc busy bit read 0: adc conversion com p lete or no valid data has been convert ed since a reset. the falling edge of adb usy generat e s an i n t e rrupt when enabl e d. 1: adc b u sy convert i ng dat a w r ite 0: no effect 1: st art s adc c onversi on i f adstm 1-0 = 00b b i t s 3-2: adstm 1-0: adc st art of c onversi on m ode b i t s 00: adc conversi on st art e d upon every wri t e of 1 t o adb usy 01: adc conversi ons t a ken on every overfl ow of ti m e r 3 10: adc conversi on st art e d upon every ri si ng edge of c nvstr 11: adc conversi ons t a ken on every overfl ow of ti m e r 2 b i t 1 : adw int: adc w i ndow c o m p are int e rrupt fl ag (m ust be cleared by software) 0: adc w i ndow c o m p ari s on dat a m a t c h has not occurred 1: adc w i ndow c o m p ari s on dat a m a t c h occurred bit0 : adljst: adc left ju stify data bit 0: dat a i n adc 0h: adc 0l r e gi st ers i s ri ght just i f i e d 1 : data in adc0 h :adc0 l reg i sters is left j u stified r e v. 1.7 34
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 5.8. adc0h: adc data word msb register (c8051f00x) r/w r / w r/w r / w r / w r/w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 sfr address: 0 x b f figure 5.9. adc0l: adc data word lsb register (c8051f00x) r / w r/w r / w r / w r/w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 5 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b e r / w b i t 7 b i t 0 r/w r / w bits7 - 0 : adc data w o rd bits fo r adljst = 1 : bits7 - 4 are th e lo wer 4 - b its o f th e 1 2 - b it adc data w o rd . bits3 - 0 will always read 0. fo r adljst = 0 : bits7 - 0 are th e lo wer 8 - b its o f th e 1 2 - b it adc data w o rd . bits7 - 0 : adc data w o rd bits for adljst = 1: upper 8-bi t s of t h e 12-bi t adc dat a w o rd. for adljst = 0: b i t s 7-4 are t h e si gn ext e nsi on of b i t 3 . b i t s 3-0 are t h e upper 4-bi t s of t h e 12-bit adc data w o rd. b i t 6 b i t 4 note: resulting 12-bit adc data word appears in the adc data word registers as follow s : adc0h[3:0] : adc0l[7:0] , if adljst = 0 (adc0h[7:4] will be sign extension of adc0h.3 if a differential reading, otherwise = 0000b) adc0h[7:0] : adc0l[7:4] , if adljst = 1 (adc 0l[3: 0 ] = 0000b) exam ple: adc dat a w o rd c onversi on m a p, ain0 input i n si ngl e-ended m ode (am x 0c f=0x00, am x0sl=0x00) ain0 ? agnd (volts) adc0h:adc0l (adljst = 0) adc0h:adc0l (adljst = 1) ref x (4095/4096) 0x0fff 0xfff0 r e f x ? 0x0800 0x8000 r e f x (2047/ 4096) 0x07ff 0x7ff0 0 0 x 0 0 0 0 0 x 0 0 0 0 exam ple: adc dat a w o rd c onversi on m a p, ain0-ain1 di fferent i a l input pai r (am x 0c f=0x01, am x0sl=0x00) ain0 ? ain1 (volts) adc0h:adc0l (adljst = 0) adc0h:adc0l (adljst = 1) r e f x (2047/ 2048) 0x07ff 0x7ff0 0 0 x 0 0 0 0 0 x 0 0 0 0 -ref x (1/2048) 0xffff 0xfff0 -r e f 0 x f 8 0 0 0 x 8 0 0 0 35 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 5.3. adc programmable window detector the adc program m a bl e wi ndow det ect or i s very useful i n m a ny appl i cat i ons. it cont i nuousl y com p ares t h e adc out put t o user-program m e d l i m i t s and not i f i e s t h e sy st em when an out -of-band condi t i on i s det ect ed. thi s i s especially effective in an interrupt -driven system , saving code space and cp u bandwidth while delivering faster sy st em response t i m es. the wi ndow det ect or i n t e rrupt fl ag (adw int i n adc 0c n) can al so be used i n pol l e d m ode. the hi gh and l o w by t e s of t h e reference words ar e loaded into the adc great er-than and adc less-than registers (adc0gth, adc0gtl, adc 0lth, and adc0ltl). figure 5.14 and figure 5.15 show exam ple com p ari s ons for reference. not i ce t h at t h e wi ndow det ect or fl ag can be assert ed when t h e m easured dat a i s i n si de or out si de t h e user-program m e d l i m i t s , dependi ng on t h e progr am m i ng of t h e adc 0gtx and adc 0ltx regi st ers. figure 5.10. adc0gth: adc greater-than data high byte register (c8051f00x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 1 1 1 1 1 1 1 1 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 5 figure 5.11. adc0gtl: adc greater-than data low byte register (c8051f00x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 1 1 1 1 1 1 1 1 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 4 figure 5.12. adc0lth: adc less-than data high byte register (c8051f00x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 7 b i t s 7-0: the hi gh by t e of t h e adc great er-than dat a w o rd. b i t s 7-0: the low by te of the adc greater-than data w o rd. defi ni t i on: adc greater-than data w o rd = adc0gth:adc0gtl b i t s 7-0: the hi gh by t e of t h e adc less-than dat a w o rd. figure 5.13. adc0ltl: adc less-than data low byte register (c8051f00x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 6 b i t s 7-0: these bits are the low byte of the adc less-than data w o rd. defi ni t i on: adc less-than data w o rd = adc0lth:adc0ltl r e v. 1.7 36
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 5.14. 12-bit adc window interrupt examples, right justified data input voltage (ad0 - ad1) 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 adwint=1 adwint not affected adwint not affected adc data word 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 adwint=1 adwint not affected adwint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) 0x07ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xf800 adwint=1 adwint not affected adwint not affected 0x07ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xf800 adwint=1 adwint not affected -ref input voltage (ad0 - ad1) adwint=1 ref x (2047/2048) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/2048) ref x (-1/2048) -ref ref x (2047/2048 ) ref x (256/2048) ref x (-1/2048) given: amx0sl = 0x00, amx0cf = 0x00, adljst = 0, adc0lth:adc0ltl = 0x0200, adc0gth:adc0gtl = 0x0100. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0200 and > 0x0100. given: amx0sl = 0x00, amx0cf = 0x00, adljst = 0, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0x0200. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0100 or > 0x0200. given: amx0sl = 0x00, amx0cf = 0x01, adljst = 0, adc0lth:adc0ltl = 0x0100, adc0gt h :adc0gt l = 0xffff. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0100 and > 0xffff. (two?s comple me nt ma th, 0xffff = -1. ) given: amx0sl = 0x00, amx0cf = 0x01, adljst = 0, adc0l t h :adc0l t h = 0xffff, adc0gth:adc0gtl = 0x0100. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0xffff or > 0x0100. (two?s complement ma th, 0xffff = -1. ) 37 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 5.15. 12-bit adc window interrupt examples, left justified data 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 adwint=1 adwint not affected adwint not affected adc data word 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 adwint=1 adwint not affected adwint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) given: amx0sl = 0x00, amx0cf = 0x00, adljst = 1, adc0lth:adc0ltl = 0x2000, adc0gth:adc0gtl = 0x1000. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x2000 and > 0x1000. given: amx0sl = 0x00, amx0cf = 0x00, adljst = 1, adc0lth:adc0ltl = 0x1000, adc0gth:adc0gtl = 0x2000. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x1000 or > 0x2000. given: amx0sl = 0x00, amx0cf = 0x01, adljst = 1, adc0lth:adc0ltl = 0x1000, adc0gt h :adc0gt l = 0xfff0. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x1000 and > 0xfff0. (two?s compl e me nt ma t h . ) given: amx0sl = 0x00, amx0cf = 0x01, adljst = 1, adc0l t h :adc0l t h = 0xfff0, adc0gth:adc0gtl = 0x1000. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0xfff0 or > 0x1000. (two?s complement ma t h . ) 0x7ff0 0x1010 0x1000 0x0ff0 0x0000 0xfff0 0xffe0 0x8000 adwint=1 adwint not affected adwint not affected 0x7ff0 0x1010 0x1000 0x0ff0 0x0000 0xfff0 0xffe0 0x8000 adwint=1 adwint not affected -ref input voltage (ad0 - ad1) adwint=1 ref x (2047/2048) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/2048) ref x (-1/2048) -ref input voltage (ad0 - ad1) ref x (2047/2048 ) ref x (256/2048) ref x (-1/2048) r e v. 1.7 38
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 5.1. 12-bit adc electrical characteristics vdd = 3.0v, av+ = 3.0v, vref = 2.40v (refbe=0), pga gain = 1, -40 q c to +8 5 q c unless otherwise specified. p a r a m e t e r c o n d i t i o n s m i n t y p max u n i t s dc accuracy r e sol u t i o n 1 2 bi t s in teg r al no n lin earity r 1 lsb di fferent i a l nonl i n eari t y guarant eed m onot oni c r 1 lsb offset error -3 r 1 l s b full scale error differential m ode -7 r 3 l s b offset tem p erature coefficient r 0.25 ppm / q c dynamic performance (10khz sine-w ave i nput, 0 to ?1db of full scale, 100ksps) si gnal - t o -noi se pl us di st ort i on 6 6 6 9 db to tal harm o n i c disto r tio n up to th e 5 th harm oni c - 7 5 db spuri ous-free dy nam i c r a nge 8 0 db conversion rate c onversi on ti m e i n sar c l ocks 1 6 cl o c k s sar c l ock frequency c 8051f000, ?f001, ?f002 c 8051f005, ?f006, ?f007 2 . 0 2.5 mh z mh z track/ h ol d acqui si t i on tim e 1 . 5 p s throughput r a t e 100 ksps analog inputs vol t a ge conversi on range si ngl e-ended m ode (ainn ? agnd) differential m ode |(ainn+) ? (ainm -)| 0 vr e f - 1lsb v input vol t a ge any ainn pi n agnd av+ v input c a paci t a n c e 1 0 p f temperature sensor l i n e a r i t y r 0.20 q c absolute accuracy r 3 q c gain pga gain = 1 2.86 mv / q c gain error ( r 1 v ) pga gain = 1 r 33.5 p v/ q c offset pga gain = 1, tem p = 0 q c 7 7 6 m v offset error ( r 1 v ) pga gain = 1, tem p = 0 q c r 8.51 m v power specifications power suppl y c u rrent (av+ suppl i e d t o adc ) operat i ng m ode, 100ksps 450 900 p a power suppl y r e ject i on r 0.3 m v / v 39 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 6. adc (10-bit, c8051f010/1/2/5/6/7 only) the adc subsystem for the c8051f010/1/ 2/5/6/7 consists of a 9-channel, configurable analog m u ltiplexer (amux), a program m a ble gain am plifier (pga), and a 100ksps, 10-bit successive-a pproxim a tion-register adc wi t h i n t e grat ed t r ack-and-hol d and program m a bl e wi ndow det ect or (see bl ock di agram i n fi gure 6.1). the am ux, pga, dat a c onversi on m odes, and w i ndow det ect or are a l l confi gurabl e under soft ware cont rol vi a t h e speci al funct i on r e gi st er?s shown i n fi gure 6.1. the adc s ubsy s t e m (adc , t r ack-and-hol d and pga) i s enabl e d onl y wh en th e adcen b it in th e adc co n t ro l reg i ster (adc0 c n, fig u r e 6 . 7 ) is set to 1 . th e adc su b s ystem is in lo w power shut down when t h i s bi t i s 0. the b i as enabl e bi t (b iase) i n t h e r e f0c n regi st er (see fi gure 9.2) m u st be set t o 1 i n order t o suppl y bi as t o t h e adc . figure 6.1. 10-bit adc functional block diagram 10-bit sar adc ref + - av+ temp sensor 10 + - + - + - 9-to-1 amux (se or diff) av+ comb logic 20 10 adwint adcen sysclk + - x ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 t m r 3 o v t 2 o v c n v s t r a d b u s y ( w ) conversion start agnd agnd amx0cf ain01ic ain23ic ain45ic ain67ic amx0sl amxad0 amxad1 amxad2 amxad3 adc0cf ampgn0 ampgn1 ampgn2 adcsc0 adcsc1 adcsc2 adc0cn adljst adwint adstm0 adstm1 adbusy adcint adctm adcen adc0l adc0h adc0ltl adc0lth adc0gtl adc0gth 6.1. analog multiplexer and pga eight of the amux channels are availa b l e fo r ex tern al m easu r em en ts wh ile th e n i n t h ch an n e l is in tern ally connect ed t o an on-board t e m p erat ure sensor (t em perat u re t r ansfer funct i on i s shown i n fi gure 6.3). not e t h at t h e pga gai n i s appl i e d t o t h e t e m p erat ure sensor readi ng. am ux i nput pai r s can be program m e d t o operat e i n ei t h er the differential or single-ended m ode. this allows the user to select the best m easur em ent technique for each input channel, and even accom m odates m ode changes ?on-the-fl y?. the amux defaults to all single-ended inputs upon reset. there are two registers associ ated with th e amux: th e ch an n e l sel ect i on regi st er am x0sl (fi gure 6.5), an d th e co n f ig u r atio n reg i ster amx0 cf (fig u r e 6 . 4 ) . th e tab l e in fig u r e 6 . 5 sh o w s amux fu n c tio n a lity b y channel for each possible configuration. the pga am plif ies the amux output signal by an am ount determ ined by t h e am pgn2-0 bi t s i n t h e adc c onfi gurat i on regi st er, adc 0c f (fi gure 6.6). the pga can be soft ware- program m e d for gai n s of 0.5, 1, 2, 4, 8 or 16. it defaul t s t o uni t y gai n on reset . r e v. 1.7 40
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 6.2. adc modes of operation th e adc u s es vref to d e term in e its fu ll-scale v o ltag e , t hus t h e reference m u st be properl y confi gured before perform i ng a conversi on (see sect i on 9). the adc ha s a m a xi m u m conversi on speed of 100ksps. the adc conversi on cl ock i s deri ved from t h e sy st em cl ock. c onversi on cl ock speed can be reduced by a fact or of 2, 4, 8 or 16 via the adcsc bits in the adc0cf register. this is useful to adjust conversion speed to accom m odate di fferent sy st em cl ock speeds. a conversion can be initiated in one of four ways, de pending on the program m e d stat es of the adc start of conversion mode bits (adstm1, adstm0) in adc0cn. convers ions m a y be initiated by: 1. w r i t i ng a 1 t o t h e adb usy bi t of adc 0c n; 2. a ti m e r 3 overfl ow (i .e. t i m ed cont i nuous conversi ons); 3. a ri si ng edge det ect ed on t h e ext e rnal adc convert st art si gnal , c nvstr ; 4. a ti m e r 2 overfl ow (i .e. t i m ed cont i nuous conversi ons). w r i t i ng a 1 t o adb usy provi des soft ware cont rol of t h e adc whereby conversi ons are perform ed ?on-dem a nd?. during conversion, the adbusy bit is set to 1 and restored to 0 when conversi on is com p lete. the falling edge of adb usy t r i ggers an i n t e rrupt (when enabl e d) and set s t h e adc int i n t e rrupt fl ag. note: when conversions are performed ?on-demand?, the adcint flag, not adbusy, should be polled to determine when the conversion has completed. c onvert ed dat a i s avai l a bl e i n t h e adc dat a word m s b and lsb regi st ers, adc 0h, adc 0l. c onvert ed dat a can be ei t h er l e ft or ri ght just i f i e d i n t h e adc 0h: adc 0l regi st er pai r (see exam pl e i n fi gure 6.9) dependi ng on t h e program m e d st at e of t h e adljst bi t i n t h e adc 0c n regi st er. the adc tm bi t i n regi st er adc 0c n cont rol s t h e adc t r ack-and-hol d m ode. in i t s defaul t st at e, t h e adc i nput i s continuously tracked, except when a conve rsion is in progress. setting adctm to 1 allows one of four different l o w power t r ack-and-hol d m odes t o be speci fi ed by st at es of t h e adstm 1-0 bi t s (al s o i n adc 0c n): 1. tracki ng begi ns wi t h a wri t e of 1 t o adb usy and l a st s for 3 sar cl ocks; 2. tracki ng st art s wi t h an overfl ow of ti m e r 3 and l a st s for 3 sar cl ocks; 3. tracki ng i s act i v e onl y when t h e c nvstr i nput i s l o w; 4. tracki ng st art s wi t h an overfl ow of ti m e r 2 and l a st s for 3 sar cl ocks. m odes 1, 2 and 4 (above) are useful when t h e st art of conve rsi on i s t r i ggered wi t h a soft ware com m a nd or when t h e adc i s operat e d cont i nuousl y . m ode 3 i s used when t h e st ar t of conversi on i s t r i ggered by ext e rnal hardware. in t h i s case, t h e t r ack-and-hol d i s i n i t s l o w power m ode at t i m es when t h e c nvstr i nput i s hi gh. tracki ng can al so be di sabl ed (shut down) when t h e ent i r e chi p i s i n l o w power st andby or sl eep m odes. figure 6.2. 10-bit adc track and conversion example timing 12 345 678 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 cnvstr (adstm[1:0]=10) adctm=1 track convert low power mode adctm=0 track or convert convert track low power or convert timer2, timer3 overflow; write 1 to adbusy (adstm[1:0]=00, 01, 11) adctm=1 track convert low power mode adctm=0 track or convert convert track low power or convert a. adc timing for external trigger sourc e b. adc timing for internal trigger sources sar clocks sar clocks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sar clocks 41 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 6.3. temperature sensor transfer function 0 -50 50 100 (celsius) 0.500 0.600 0.700 0.800 0.900 (volts) v temp = 0.00286(temp c ) + 0.776 for pga gain = 1 1.000 figure 6.4. amx0cf: amux configuration register (c8051f01x) r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e - - - - ain67ic ain45ic a i n 2 3 i c a i n 0 1 i c 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b a bi t s 7-4: unused. read = 0000b; w r i t e = don?t care b i t 3 : ain67ic : ain6, ain7 input pai r c onfi gurat i on b i t 0: ain6 and ain7 are i ndependent si ngl ed-ended i nput s 1: ain6, ain7 are (respect i v el y ) +, - di fferent i a l i nput pai r b i t 2 : ain45ic : ain4, ain5 input pai r c onfi gurat i on b i t 0: ain4 and ain5 are i ndependent si ngl ed-ended i nput s 1: ain4, ain5 are (respect i v el y ) +, - di fferent i a l i nput pai r b i t 1 : ain23ic : ain2, ain3 input pai r c onfi gurat i on b i t 0: ain2 and ain3 are i ndependent si ngl ed-ended i nput s 1: ain2, ain3 are (respect i v el y ) +, - di fferent i a l i nput pai r b i t 0 : ain01ic : ain0, ain1 input pai r c onfi gurat i on b i t 0: ain0 and ain1 are i ndependent si ngl ed-ended i nput s 1: ain0, ain1 are (respect i v el y ) +, - di fferent i a l i nput pai r n ote: the adc dat a w o rd i s i n 2?s com p l e m e nt form at for channel s confi gured as di fferent i a l . r e v. 1.7 42
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 6.5. amx0sl: amux channel select register (c8051f01x) r/w r / w r/w r/w r / w r/w r/w r/w r e s e t v a l u e - - - - a m x a d 3 a m x a d 2 a m x a d 1 a m x a d 0 00000000 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b b bi t s 7-4: unused. read = 0000b; w r i t e = don?t care bits3-0: am xad3-0: am ux address bits 0000-1111: adc input s sel ect ed per chart bel o w a m x 0 c f b i t s 3 - 0 a m x a d 3 - 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 x x x 0000 ain0 ain1 a i n 2 a i n 3 ain4 a i n 5 ain6 a i n 7 temp sensor 0001 +(ain0 ) -(ain1) ain2 a i n 3 a i n 4 ain5 a i n 6 ain7 temp sensor 0010 ain0 a i n 1 +(ain2 ) -(ain3) ain4 a i n 5 ain6 a i n 7 temp sensor 0011 +(ain0 ) -(ain1) +(ain2 ) -(ain3) ain4 a i n 5 ain6 a i n 7 temp sensor 0100 ain0 ain1 a i n 2 a i n 3 +(ain4 ) -(ain5) a i n 6 ain7 temp sensor 0101 +(ain0 ) -(ain1) a i n 2 ain3 +(ain4 ) -(ain5) a i n 6 ain7 temp sensor 0110 ain0 a i n 1 +(ain2 ) -(ain3) +(ain4 ) -(ain5) a i n 6 ain7 temp sensor 0111 +(ain0 ) -(ain1) +(ain2 ) -(ain3) +(ain4 ) -(ain5) a i n 6 ain7 temp sensor 1000 ain0 a i n 1 ain2 ain3 a i n 4 ain5 +(ain6 ) -(ain7) temp sensor 1001 +(ain0 ) -(ain1) ain2 a i n 3 a i n 4 ain5 +(ain6 ) -(ain7) temp sensor 1010 ain0 a i n 1 +(ain2 ) -(ain3) a i n 4 ain5 +(ain6 ) -(ain7) temp sensor 1011 +(ain0 ) -(ain1) +(ain2 ) -(ain3) a i n 4 ain5 +(ain6 ) -(ain7) temp sensor 1100 ain0 ain1 a i n 2 a i n 3 +(ain4 ) -(ain5) +(ain6 ) -(ain7) temp sensor 1101 +(ain0 ) -(ain1) a i n 2 ain3 +(ain4 ) -(ain5) +(ain6 ) -(ain7) temp sensor 1110 ain0 a i n 1 +(ain2 ) -(ain3) +(ain4 ) -(ain5) +(ain6 ) -(ain7) temp sensor 1111 +(ain0 ) -(ain1) +(ain2 ) -(ain3) +(ain4 ) -(ain5) +(ain6 ) -(ain7) temp sensor 43 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 6.6. adc0cf: adc configuration register (c8051f01x) r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e a d c s c 2 a d c s c 1 a d c s c 0 - - a m p g n 2 a m p g n 1 a m p g n 0 01100000 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b c b i t s 7-5: adc sc 2-0: adc sar c onversi on c l ock peri od b i t s 000: sar c onversi on c l ock = 1 sy st em c l ock 001: sar c onversi on c l ock = 2 sy st em c l ocks 010: sar c onversi on c l ock = 4 sy st em c l ocks 011: sar c onversi on c l ock = 8 sy st em c l ocks 1xx: sar c onversi on c l ock = 16 sy st em s c l ocks (not e: c onversi on cl ock shoul d be d 2mhz.) bi t s 4-3: unused. read = 00b; w r i t e = don?t care bits2 - 0 : ampgn2 -0 : adc in tern al am p lifier gain 000: gai n = 1 001: gai n = 2 010: gai n = 4 011: gai n = 8 10x: gai n = 16 11x: gai n = 0.5 r e v. 1.7 44
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 6.7. adc0cn: adc control register (c8051f01x) r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e a d c e n a d c t m a d c i n t a d b u s y ads t m 1 a d s t m 0 a d w i n t a d l j s t 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: (bit addressable) 0xe8 bit7 : adcen: adc en ab le bit 0: adc di sabl ed. adc i s i n l o w power shut down. 1: adc enabl e d. adc i s act i v e and ready for dat a conversi ons. bit6 : adctm: adc track mo d e bit 0: w h en t h e adc i s enabl e d, t r acki ng i s al way s done unl ess a conversi on i s i n process 1: tracki ng defi ned by adstm 1-0 bi t s adstm 1-0: 00: tracki ng st art s wi t h t h e wri t e of 1 t o adb usy and l a st s for 3 sar cl ocks 01: tracki ng st art e d by t h e overfl ow of ti m e r 3 and l a st for 3 sar cl ocks 10: adc t r acks onl y when c nvstr i nput i s l ogi c l o w 11: tracki ng st art e d by t h e overfl ow of ti m e r 2 and l a st for 3 sar cl ocks b i t 5 : adc int: adc c onversi on c o m p l e t e int e rrupt fl ag (m ust be cleared by software) 0: adc has not com p l e t e d a dat a conversi on si nce t h e l a st t i m e t h i s fl ag was cl eared 1: adc has com p l e t e d a dat a conversi on bit4: adbusy: adc busy bit read 0: adc conversion com p lete or no valid data has been convert ed since a reset. the falling edge of adb usy generat e s an i n t e rrupt when enabl e d. 1: adc b u sy convert i ng dat a w r ite 0: no effect 1: st art s adc c onversi on i f adstm 1-0 = 00b b i t s 3-2: adstm 1-0: adc st art of c onversi on m ode b i t s 00: adc conversi on st art e d upon every wri t e of 1 t o adb usy 01: adc conversi ons t a ken on every overfl ow of ti m e r 3 10: adc conversi on st art e d upon every ri si ng edge of c nvstr 11: adc conversi ons t a ken on every overfl ow of ti m e r 2 b i t 1 : adw int: adc w i ndow c o m p are int e rrupt fl ag (m ust be cleared by software) 0: adc w i ndow c o m p ari s on dat a m a t c h has not occurred 1: adc w i ndow c o m p ari s on dat a m a t c h occurred bit0 : adljst: adc left ju stify data bit 0: dat a i n adc 0h: adc 0l r e gi st ers i s ri ght just i f i e d 1 : data in adc0 h :adc0 l reg i sters is left j u stified 45 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 6.8. adc0h: adc data word msb register (c8051f01x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b f figure 6.9. adc0l: adc data word lsb register (c8051f01x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b e bits7 - 0 : adc data w o rd bits fo r adljst = 1 : bits7 - 6 are th e lo wer 2 - b its o f th e 1 0 - b it adc data w o rd . bits5 - 0 will always read 0. fo r adljst = 0 : bits7 - 0 are th e lo wer 8 - b its o f th e 1 0 - b it adc data w o rd . bits7 - 0 : adc data w o rd bits for adljst = 1: upper 8-bi t s of t h e 10-bi t adc dat a w o rd. for adljst = 0: b i t s 7-2 are t h e si gn ext e nsi on of b i t 1 . b i t s 1-0 are t h e upper 2-bi t s of t h e 10-bit adc data w o rd. note: resulting 10-bit adc data word appears in the adc data word registers as follow s : adc0h[1:0] : adc0l[7:0] , if adljst = 0 (adc0h[7:2] will be sign extension of adc0h.1 if a differential reading, otherwise = 000000b) adc0h[7:0] : adc0l[7:6] , if adljst = 1 (adc 0l[5: 0 ] = 000000b) exam ple: adc dat a w o rd c onversi on m a p, ain0 input i n si ngl e-ended m ode (am x 0c f=0x00, am x0sl=0x00) ain0 ? agnd (volts) adc0h:adc0l (adljst = 0) adc0h:adc0l (adljst = 1) r e f x (1023/ 1024) 0x03ff 0xffc 0 r e f x ? 0x0200 0x8000 r e f x (511/ 1024) 0x01ff 0x7fc 0 0 0 x 0 0 0 0 0 x 0 0 0 0 exam ple: adc dat a w o rd c onversi on m a p, ain0-ain1 di fferent i a l input pai r (am x 0c f=0x01, am x0sl=0x00) ain0 ? ain1 (volts) adc0h:adc0l (adljst = 0) adc0h:adc0l (adljst = 1) r e f x (511/ 512) 0x01ff 0x7fc 0 0 0 x 0 0 0 0 0 x 0 0 0 0 -ref x (1/512) 0xffff 0xffc0 -r e f 0 x f e 0 0 0 x 8 0 0 0 r e v. 1.7 46
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 6.3. adc programmable window detector the adc program m a bl e wi ndow det ect or i s very useful i n m a ny appl i cat i ons. it cont i nuousl y com p ares t h e adc out put t o user-program m e d l i m i t s and not i f i e s t h e sy st em when an out -of-band condi t i on i s det ect ed. thi s i s especially effective in an interrupt -driven system , saving code space and cp u bandwidth while delivering faster sy st em response t i m es. the wi ndow det ect or i n t e rrupt fl ag (adw int i n adc 0c n) can al so be used i n pol l e d m ode. the hi gh and l o w by t e s of t h e reference words ar e loaded into the adc great er-than and adc less-than registers (adc0gth, adc0gtl, adc 0lth, and adc0ltl). figure 6.14 and figure 6.15 show exam ple com p ari s ons for reference. not i ce t h at t h e wi ndow det ect or fl ag can be assert ed when t h e m easured dat a i s i n si de or out si de t h e user-program m e d l i m i t s , dependi ng on t h e progr am m i ng of t h e adc 0gtx and adc 0ltx regi st ers. figure 6.10. adc0gth: adc greater-than data high byte register (c8051f01x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 1 1 1 1 1 1 1 1 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 5 figure 6.11. adc0gtl: adc greater-than data low byte register (c8051f01x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 1 1 1 1 1 1 1 1 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 4 b i t s 7-0: the hi gh by t e of t h e adc great er-than dat a w o rd. b i t s 7-0: the low by te of the adc greater-than data w o rd. defi ni t i on: adc greater-than data w o rd = adc0gth:adc0gtl figure 6.12. adc0lth: adc less-than data high byte register (c8051f01x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 7 b i t s 7-0: the hi gh by t e of t h e adc less-than dat a w o rd. figure 6.13. adc0ltl: adc less-than data low byte register (c8051f01x) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 6 b i t s 7-0: these bits are the low byte of the adc less-than data w o rd. defi ni t i on: adc less-than data w o rd = adc0lth:adc0ltl 47 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 6.14. 10-bit adc window interrupt examples, right justified data ref x 0x03ff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 adwint=1 adwint not affected adwint not affected adc data word 0x03ff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 adwint=1 adwint not affected adwint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) 0x01ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xfe00 adwint=1 adwint not affected adwint not affected 0x01ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xfe00 adwint=1 adwint not affected -ref input voltage (ad0 - ad1) adwint=1 ref x (511/512) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/512) ref x (-1/512) -ref input voltage (ad0 - ad1) ref x (511/512 ) ref x (256/512) (-1/512) given: amx0sl = 0x00, amx0cf = 0x00, adljst = 0, adc0lth:adc0ltl = 0x0200, adc0gth:adc0gtl = 0x0100. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0200 and > 0x0100. given: amx0sl = 0x00, amx0cf = 0x00, adljst = 0, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0x0200. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0100 or > 0x0200. given: amx0sl = 0x00, amx0cf = 0x01, adljst = 0, adc0lth:adc0ltl = 0x0100, adc0gt h :adc0gt l = 0xffff. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0100 and > 0xffff. (two?s comple me nt ma th, 0xffff = -1. ) given: amx0sl = 0x00, amx0cf = 0x01, adljst = 0, adc0l t h :adc0l t h = 0xffff, adc0gth:adc0gtl = 0x0100. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0xffff or > 0x0100. (two?s complement ma th, 0xffff = -1. ) r e v. 1.7 48
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 6.15. 10-bit adc window interrupt examples, left justified data 0xffc0 0x8040 0x8000 0x7fc0 0x4040 0x4000 0x3fc0 0x0000 adwint=1 adwint not affected adwint not affected adc data word 0xffc0 0x8040 0x8000 0x7fc0 0x4040 0x4000 0x3fc0 0x0000 adwint=1 adwint not affected adwint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) given: amx0sl = 0x00, amx0cf = 0x00, adljst = 1, adc0lth:adc0ltl = 0x8000, adc0gth:adc0gtl = 0x4000. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x8000 and > 0x4000. given: amx0sl = 0x00, amx0cf = 0x00, adljst = 1, adc0lth:adc0ltl = 0x4000, adc0gth:adc0gtl = 0x8000. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x4000 or > 0x8000. given: amx0sl = 0x00, amx0cf = 0x01, adljst = 1, adc0lth:adc0ltl = 0x2000, adc0gth:adc0gtl = 0xffc0. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x2000 and > 0xffc0. (two?s compl e me nt ma t h . ) given: amx0sl = 0x00, amx0cf = 0x01, adljst = 1, adc0lth:adc0lth = 0xffc0, adc0gth:adc0gtl = 0x2000. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0xffc0 or > 0x2000. (two?s complement ma t h . ) 0x7fc0 0x2040 0x2000 0x1fc0 0x0000 0xffc0 0xff80 0x8000 adwint=1 adwint not affected adwint not affected 0x7fc0 0x2040 0x2000 0x1fc0 0x0000 0xffc0 0xff80 0x8000 adwint=1 adwint not affected -ref input voltage (ad0 - ad1) adwint=1 ref x (511/512) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (128/512) ref x (-1/512) -ref input voltage (ad0 - ad1) ref x (511/512 ) ref x (128/512) ref x (-1/512) 49 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 6.1. 10-bit adc electrical characteristics vdd = 3.0v, av+ = 3.0v, vref = 2.40v (refbe=0), pga gain = 1, -40 q c to +8 5 q c unless otherwise specified. p a r a m e t e r c o n d i t i o n s m i n t y p max u n i t s dc accuracy r e sol u t i o n 1 0 bi t s in teg r al no n lin earity r ? r 1 lsb di fferent i a l nonl i n eari t y guarant eed m onot oni c r ? r 1 lsb offset error r 0.5 l s b full scale error differential m ode -1.5 r 0.5 l s b offset tem p erature coefficient r 0.25 ppm / q c dynamic performance (10khz sine-w ave i nput, 0 to ?1db of full scale, 100ksps) si gnal - t o -noi se pl us di st ort i on 5 9 6 1 db to tal harm o n i c disto r tio n up to th e 5 th harm oni c - 7 0 db spuri ous-free dy nam i c r a nge 8 0 db conversion rate c onversi on ti m e i n sar c l ocks 1 6 cl o c k s sar c l ock frequency c 8051f000, ?f001, ?f002 c 8051f005, ?f006, ?f007 2 . 0 2.5 mh z mh z track/ h ol d acqui si t i on tim e 1 . 5 p s throughput r a t e 100 ksps analog inputs vol t a ge conversi on range si ngl e-ended m ode (ainn ? agnd) differential m ode |(ainn+) ? (ainm -)| 0 vr e f - 1lsb v input vol t a ge any ainn pi n agnd av+ v input c a paci t a n c e 1 0 p f temperature sensor l i n e a r i t y r 0.20 q c absolute accuracy r 3 q c gain pga gain = 1 2.86 mv / q c gain error ( r 1 v ) pga gain = 1 r 33.5 p v/ q c offset pga gain = 1, tem p = 0 q c 7 7 6 m v offset error ( r 1 v ) pga gain = 1, tem p = 0 q c r 8.51 m v power specifications power suppl y c u rrent (av+ suppl i e d t o adc ) operat i ng m ode, 100ksps 450 900 p a power suppl y r e ject i on r 0.3 m v / v r e v. 1.7 50
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 7. dacs, 12 bit voltage mode the c 8051f000 m c u fam i l y has t w o 12-bi t vol t a ge-m ode di gi t a l t o anal og c onvert ers. each dac has an out put swing of 0v to vref-1lsb for a co rresponding input code range of 0x000 to 0xfff. using dac0 as an exam ple, th e 1 2 - b it d a ta wo rd is written to th e lo w b y te (dac0 l ) an d h i g h b y te (dac0 h ) d a ta reg i sters. data is latch e d in to dac 0 aft e r a wri t e t o t h e correspondi ng dac 0h regi st er, so the w r ite sequence should be dac0l follow e d by dac0h if th e fu ll 1 2 - b it reso lu tio n is req u i red . th e dac can b e u s ed in 8 - b it m o d e b y in itializin g dac0 l to th e desired value (typically 0x00), and writi ng data to only dac0h with the data shifted to the left. dac0 control register (dac0cn) provides a m eans to enable/disable dac0 and to m odi fy its input data form atting. the dac 0 enabl e / d i s abl e funct i on i s cont rol l e d by t h e dac 0en bi t (dac 0c n.7). w r i t i ng a 1 t o dac 0en enabl e s dac 0 whi l e wri t i ng a 0 t o dac 0en di sabl es dac 0. w h i l e di sabl ed, t h e out put of dac 0 i s m a i n t a i n ed i n a hi gh-i m pedance st at e, and t h e dac 0 suppl y current fal l s t o 1 p a o r less. also , th e bias en ab le b it (biase) in th e r e f0c n regi st er (see fi gure 9.2) m u st be set t o 1 i n or der t o suppl y bi as t o dac 0. the vol t a ge reference for dac 0 m u st al so be set properl y (see sect i on 9). in som e i n st ances, i nput dat a shoul d be shi f t e d pri o r t o a dac 0 wri t e operat i on t o properl y just i f y dat a wi t h i n t h e dac i nput regi st ers. thi s act i on woul d t y pi cal l y requi re one or m o re l o ad and shi f t operat i ons, addi ng soft ware overhead and slowing dac throughput. to alleviate this problem , the data-fo rm atting feature provides a m eans for t h e user t o program t h e ori e nt at i on of t h e dac 0 dat a word wi t h i n dat a regi st ers dac 0h and dac 0l. the t h ree dac 0df bi t s (dac 0c n.[2: 0 ] ) al l o w t h e user t o speci fy one of fi ve dat a word ori e nt at i ons as shown i n t h e dac 0c n regi st er defi ni t i on. dac 1 i s funct i onal l y t h e sam e as dac 0 descri bed above . the el ect ri cal speci fi cat i ons for bot h dac 0 and dac 1 are gi ven i n tabl e 7.1. figure 7.1. dac functional block diagram dac0 + - av+ 12 agnd 8 8 ref dac0 dac0cn dac0en dac0df2 dac0df1 dac0df0 dac0h dac0l dig. mux dac1 + - av+ 12 agnd 8 8 ref dac1 dac1cn dac1en dac1df2 dac1df1 dac1df0 dac1h dac1l dig. mux 51 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 7.2. dac0h: dac0 high byte register r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x d 3 figure 7.3. dac0l: dac0 low byte register r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x d 2 b i t s 7-0: dac 0 dat a w o rd m o st si gni fi cant b y t e . bits7 - 0 : dac0 data w o rd least sig n i fican t byte. figure 7.4. dac0cn: dac0 control register r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e dac0en - - - - d a c 0 d f 2 d a c 0 d f 1 d a c 0 d f 0 00000000 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x d 4 bit7 : dac0 e n: dac0 en ab le bit 0: dac 0 di sabl ed. dac 0 out put pi n i s di sabl ed; dac 0 i s i n l o w power shut down m ode. 1: dac 0 enabl e d. dac 0 out put i s pi n act i v e; dac 0 i s operat i onal . bi t s 6-3: unused. read = 0000b; w r i t e = don?t care bits2 - 0 : dac0 d f2 -0 : dac0 data fo rm at bits 000: the m o st si gni fi cant ny bbl e of t h e dac 0 dat a w o rd i s i n dac 0h[3: 0 ] , whi l e t h e l east si gni fi cant b y te is in dac0 l . dac0h dac0l m s b l s b 001: the m o st si gni fi cant 5-bi t s of t h e dac 0 dat a w o rd i s i n dac 0h[4: 0 ] , whi l e t h e l east si gni fi cant 7 - b its is in dac0 l [7 :1 ]. dac0h dac0l m s b l s b 010: the m o st si gni fi cant 6-bi t s of t h e dac 0 dat a w o rd i s i n dac 0h[5: 0 ] , whi l e t h e l east si gni fi cant 6 - b its is in dac0 l [7 :2 ]. dac0h dac0l m s b l s b 011: the m o st si gni fi cant 7-bi t s of t h e dac 0 dat a w o rd i s i n dac 0h[6: 0 ] , whi l e t h e l east si gni fi cant 5 - b its is in dac0 l [7 :3 ]. dac0h dac0l m s b l s b 1xx: the m o st si gni fi cant by t e of t h e dac 0 dat a w o rd i s i n dac 0h, whi l e t h e l east si gni fi cant ny bbl e is in dac0 l [7 :4 ]. dac0h dac0l m s b l s b r e v. 1.7 52
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 7.5. dac1h: dac1 high byte register r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x d 6 figure 7.6. dac1l: dac1 low byte register r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x d 5 b i t s 7-0: dac 1 dat a w o rd m o st si gni fi cant b y t e . bits7 - 0 : dac1 data w o rd least sig n i fican t byte. figure 7.7. dac1cn: dac1 control register r/w r / w r/w r/w r / w r/w r / w r / w r e s e t v a l u e d a c 1 e n - - - - d a c 1 d f 2 d a c 1 d f 1 d a c 1 d f 0 00000000 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x d 7 bit7 : dac1 e n: dac1 en ab le bit 0: dac 1 di sabl ed. dac 1 out put pi n i s di sabl ed; dac 1 i s i n l o w power shut down m ode. 1: dac 1 enabl e d. dac 1 out put i s pi n act i v e; dac 1 i s operat i onal . bi t s 6-3: unused. read = 0000b; w r i t e = don?t care bits2 - 0 : dac1 d f2 -0 : dac1 data fo rm at bits 000: the m o st si gni fi cant ny bbl e of t h e dac 1 dat a w o rd i s i n dac 1h[3: 0 ] , whi l e t h e l east sig n i fican t b y te is in dac1 l . dac1h dac1l m s b l s b 001: the m o st si gni fi cant 5-bi t s of t h e dac 1 dat a w o rd i s i n dac 1h[4: 0 ] , whi l e t h e l east sig n i fican t 7 - b its is in dac1 l [7 :1 ]. dac1h dac1l m s b l s b 010: the m o st si gni fi cant 6-bi t s of t h e dac 1 dat a w o rd i s i n dac 1h[5: 0 ] , whi l e t h e l east sig n i fican t 6 - b its is in dac1 l [7 :2 ]. dac1h dac1l m s b l s b 011: the m o st si gni fi cant 7-bi t s of t h e dac 1 dat a w o rd i s i n dac 1h[6: 0 ] , whi l e t h e l east sig n i fican t 5 - b its is in dac1 l [7 :3 ]. dac1h dac1l m s b l s b 1xx: the m o st si gni fi cant by t e of t h e dac 1 dat a w o rd i s i n dac 1h, whi l e t h e l east si gni fi cant ny bbl e i s i n dac 1l[7: 4 ] . dac1h dac1l m s b l s b 53 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 7.1. dac electrical characteristics vdd = 3.0v, av+ = 3.0v, ref = 2.40v (refbe=0), no output load unle ss otherwise specified. p a r a m e t e r c o n d i t i o n s m i n t y p max u n i t s static performance r e sol u t i o n 1 2 bi t s int e gral nonl i n eari t y for dat a w o rd r a nge 0x014 t o 0xfeb r 2 l s b di fferent i a l nonl i n eari t y guarant eed m onot oni c (codes 0x014 t o 0xfeb ) r 1 lsb ou tp u t no ise no ou tp u t filter 100khz output filter 10khz output filter 2 5 0 128 41 p vrm s offset error dat a w o rd = 0x014 r 3 r 30 mv offset tem p c o 6 ppm / q c full-scale error r 20 r 60 mv full-scale error tem p co 10 ppm / q c vdd power-suppl y rej ectio n ratio - 6 0 db out put im pedance i n shut down m ode dac n e n = 0 1 0 0 k : out put c u rrent r 300 p a out put short c i rcui t c u rrent data w o rd = 0xfff 15 m a dynamic performance vol t a ge out put sl ew r a t e load = 40pf 0.44 v/ p s ou tp u t settlin g tim e to ? lsb load = 40pf, out put swi ng from code 0xfff to 0x014 1 0 p s out put vol t a ge swi ng 0 r e f- 1lsb v startup tim e dac enable asserted 10 p s analog outputs load r e gul at i on i l = 0.01m a t o 0.3m a at code 0xfff 6 0 ppm current consumption (each dac) power suppl y c u rrent (av+ suppl i e d t o dac ) dat a w o rd = 0x7ff 110 400 p a r e v. 1.7 54
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 8. comparators the mcu fam ily has two on-chip analog voltage com p ar ators as shown in figure 8.1. the inputs of each com p arator are available at the package pins. the output of each com p arat or is optionally ava ilable at the package pins via the i/o crossbar (see section 15.1). w h en a ssigned to package pins, each com p arator output can be program m e d t o operat e i n open drai n or push-pul l m odes (see sect i on 15.3). the hysteresis of each com p arator is software-program m a ble via its resp ective com p arator control register (c pt0c n, c p t1c n ). the user can program bot h t h e am ount of hy st eresi s vol t a ge (referred t o t h e i nput vol t a ge) and the positive and negative-going sym m e try of this hyster esis around the threshold voltage. the output of the com p arator can be polled in software, or can be used as an i n t e rrupt source. each com p arat or can be i ndi vi dual l y enabl e d or di sabl ed (shut down). w h en di sabl ed, t h e com p arat or out put (i f assi gned t o a port i/ o pi n vi a t h e crossbar) defaults to the logic low stat e, its interrupt capability is suspended a nd its supply current falls to less than 1 p a. c o m p arat or 0 i nput s can be ext e rnal l y dri v en from -0.25v t o (av+) + 0.25v wi t hout dam a ge or upset . the c o m p arat or 0 hy st eresi s i s program m e d usi ng bi t s 3-0 i n t h e c o m p arat or 0 c ont rol r e gi st er c p t0c n (shown i n fi gure 8.3). the am ount of negat i v e hy steresis voltage is determ ined by the settings of the cp0hyn bits. as shown i n fi gure 8.2, set t i ngs of 10, 4 or 2m v of negat i v e hy st eresi s can be program m e d, or negat i v e hy st eresi s can be di sabl ed. in a si m i l a r way , t h e am ount of p o s itive h y steresis is d e term in ed b y th e settin g th e cp0 hyp b its. c o m p arat or i n t e rrupt s can be generat e d on bot h ri si ng-edge and fal l i ng-edge out put t r ansi t i ons. (for int e rrupt enable and priority control, see section 10.4). the cp0f if flag is set upon a com p arator 0 falling-edge interrupt, and the cp0rif flag is set upon the com p arator 0 rising-edge interrupt. once se t, these bits rem a in set until cleared by t h e c p u. the out put st at e of c o m p arat or 0 can be obt ained at any tim e by reading th e cp0 out b it. no te th e com p arator output and interr upt should be ignored until the com p arator settles after power-up. com p arator 0 is enabled by setting the cp0en bit, and is disabled by clearing this bit. no te there is a 20usec settling tim e for the com p arat or out put t o st abi l i ze aft e r set t i ng t h e c p 0en bi t or a power-up. c o m p arat or 0 can al so be program m e d as a reset source. for det a i l s , see sect i on 13. the operat i on of c o m p arat or 1 i s i d ent i cal t o t h at of c o m p arator 0, except the com p ar at or 1 i s cont rol l e d by t h e c p t1c n r e gi st er (fi gure 8.4). c o m p arat or 1 can not be program m e d as a reset source. al so, t h e i nput pi ns for c o m p arat or 1 are not pi nned out on t h e f002, f007, f012, or f017 devi ces. the com p l e t e el ect ri cal speci fi cat i ons for t h e c o m p arat ors are gi ven i n tabl e 8.1. figure 8.1. comparator functional block diagram + - av+ q q set clr d q q set clr d crossbar interrupt handler reset decision tree (synchronizer) cp0+ cp0- agnd cp t0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 + - av+ q q set clr d q q set clr d crossbar interrupt handler (synchronizer) cp1+ cp1- agnd cp t1cn cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 not available on f002, f007, f012, and f017 55 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 8.2. comparator hysteresis plot positive hysteresis voltage (programmed with cp0hysp bits) negative hysteresis voltage (programmed by cp0hysn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol r e v. 1.7 56
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 8.3. cpt0cn: comparator 0 control register r/w r r/w r / w r / w r/w r / w r / w r e s e t v a l u e c p 0 e n c p 0 o u t c p 0 r i f c p 0 f i f cp 0 h y p 1 c p 0 h y p 0 c p 0 h y n 1 c p 0 h y n 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0x9e bit7 : cp0 e n: co m p arato r 0 en ab le bit 0: c o m p arat or 0 di sabl ed. 1: c o m p arat or 0 enabl e d. bit6: cp0out: com p arator 0 output state flag 0: vol t a ge on c p 0+ < c p 0- 1: vol t a ge on c p 0+ > c p 0- b i t 5 : c p 0r if: c o m p arat or 0 r i si ng-edge int e rrupt fl ag 0: no c o m p arat or 0 r i si ng-edge int e rrupt has occurred si nce t h i s fl ag was cl eared 1: c o m p arat or 0 r i si ng-edge int e rrupt has occurred si nce t h i s fl ag was cl eared b i t 4 : c p 0fif: c o m p arat or 0 fal l i ng-edge int e rrupt fl ag 0: no c o m p arat or 0 fal l i ng-edge int e rrupt has occurred si nce t h i s fl ag was cl eared 1: c o m p arat or 0 fal l i ng-edge int e rrupt has occurred si nce t h i s fl ag was cl eared bit3 -2 : cp0 hyp1 - 0 : co m p arato r 0 po sitiv e hysteresis co n t ro l bits 0 0 : po sitiv e hysteresis disab l ed 0 1 : po sitiv e hysteresis = 2 m v 1 0 : po sitiv e hysteresis = 4 m v 1 1 : po sitiv e hysteresis = 1 0 m v bit1-0: cp0hyn1-0: com p arator 0 negative hy steresis control bits 00: negative hysteresis disabled 01: negat i v e hy st eresi s = 2m v 10: negat i v e hy st eresi s = 4m v 11: negat i v e hy st eresi s = 10m v 57 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 8.4. cpt1cn: comparator 1 control register r/w r r/w r / w r / w r/w r / w r / w r e s e t v a l u e c p 1 e n c p 1 o u t c p 1 r i f c p 1 f i f cp 1 h y p 1 c p 1 h y p 0 c p 1 h y n 1 c p 1 h y n 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0x9f bit7 : cp1 e n: co m p arato r 1 en ab le bit 0: c o m p arat or 1 di sabl ed. 1: c o m p arat or 1 enabl e d. bit6: cp1out: com p arator 1 output state flag 0: vol t a ge on c p 1+ < c p 1- 1: vol t a ge on c p 1+ > c p 1- b i t 5 : c p 1r if: c o m p arat or 1 r i si ng-edge int e rrupt fl ag 0: no c o m p arat or 1 r i si ng-edge int e rrupt has occurred si nce t h i s fl ag was cl eared 1: c o m p arat or 1 r i si ng-edge int e rrupt has occurred si nce t h i s fl ag was cl eared b i t 4 : c p 1fif: c o m p arat or 1 fal l i ng-edge int e rrupt fl ag 0: no c o m p arat or 1 fal l i ng-edge int e rrupt has occurred si nce t h i s fl ag was cl eared 1: c o m p arat or 1 fal l i ng-edge int e rrupt has occurred si nce t h i s fl ag was cl eared bit3 -2 : cp1 hyp1 - 0 : co m p arato r 1 po sitiv e hysteresis co n t ro l bits 0 0 : po sitiv e hysteresis disab l ed 0 1 : po sitiv e hysteresis = 2 m v 1 0 : po sitiv e hysteresis = 4 m v 1 1 : po sitiv e hysteresis = 1 0 m v bit1-0: cp1hyn1-0: com p arator 1 negative hy steresis control bits 00: negative hysteresis disabled 01: negat i v e hy st eresi s = 2m v 10: negat i v e hy st eresi s = 4m v 11: negat i v e hy st eresi s = 10m v r e v. 1.7 58
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 8.1. comparator electrical characteristics vdd = 3.0v, av+ = 3.0v, -40 q c to +8 5 q c unless otherwise specified. p a r a m e t e r c o n d i t i o n s m i n t y p max u n i t s r e sponse ti m e 1 (c p+) ? (c p-) = 100m v (not e 1) 4 p s r e sponse ti m e 2 (c p+) ? (c p-) = 10m v (not e 1) 12 p s c o m m on m ode r e ject i on ratio 1 . 5 4 m v / v po sitiv e hysteresis1 cpn hyp1 - 0 = 0 0 0 1 m v po sitiv e hysteresis2 cpn hyp1 - 0 = 0 1 2 4 . 5 7 m v po sitiv e hysteresis3 cpn hyp1 - 0 = 1 0 4 9 1 3 m v po sitiv e hysteresis4 cpn hyp1 - 0 = 1 1 1 0 1 7 2 5 m v negative hy steresis1 cpnhyn1-0 = 00 0 1 m v negative hy steresis2 cpnhyn1-0 = 01 2 4.5 7 m v negative hy steresis3 cpnhyn1-0 = 10 4 9 13 m v negative hy steresis4 cpnhyn1-0 = 11 10 17 25 m v invert i ng or non-i nvert i ng input vol t a ge r a nge - 0 . 2 5 ( a v + ) + 0.25 v input c a paci t a n c e 7 p f input b i as c u rrent -5 0.001 +5 na input offset vol t a ge -10 +10 m v power supply power-up ti m e c p nen from 0 t o 1 20 p s power suppl y r e ject i on 0.1 1 m v / v supply current operating mode ( each com p arator) at dc 1.5 10 p a note 1: cpnhyp1-0 = cpnhyn1-0 = 00. 59 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 9. voltage reference the vol t a ge reference ci rcui t consi s t s of a 1.2v, 15ppm / q c (t y p i cal ) bandgap vol t a ge reference generat o r and a gain-of-two output buffer am plifier. th e reference vol t a ge on vr ef can be c onnected to external devices in the sy st em , as l ong as t h e m a xi m u m l o ad seen by t h e vr ef pi n i s l e ss t h an 200 p a to agnd (see figure 9.1). if a different reference voltage is required, an external reference can be connected to the vref pin and the internal bandgap and buffer am plifier disabled in software. the external reference voltage m u st still be less than av+ - 0.3v. the r e ference c ont rol r e gi st er, r e f0c n (defi n ed i n fi gure 9.2), provi des t h e m eans t o enabl e or di sabl e t h e bandgap and buffer am pl i f i e r. the b i ase bi t i n r e f0c n enabl e s t h e bi as ci rcui t r y for t h e adc and dac s whi l e t h e r e fb e bi t enabl e s t h e bandgap reference and buffer am pl i f i e r whi c h dri v e t h e vr ef pi n. w h en di sabl ed, t h e suppl y current drawn by t h e bandgap and buffer am pl i f i e r fal l s t o l e ss t h an 1ua (t y p i cal ) and t h e out put of t h e buffer am pl i f i e r ent e rs a hi gh i m pedance st at e. if t h e i n t e rnal bandgap i s used as t h e reference vol t a ge generat o r, b i ase and r e fb e m u st bot h be set t o 1. if an external reference is used, refbe m u st be set to 0 and b i ase m u st be set t o 1. if nei t h er t h e adc nor t h e dac are bei ng used, bot h of t h ese bi t s can be set t o 0 t o conserve power. the electrical sp eci fi cat i ons for t h e vol t a ge r e ference are gi ven i n tabl e 9.1. the tem p erature sensor connects to th e highest order input of the a/d converter?s input m u ltiplexer (see figure 5.1 and fi gure 5.5 for det a i l s ). the tem pe bi t wi t h i n r e f0c n enabl e s and di sabl es t h e t e m p erat ure sensor. w h i l e di sabl ed, t h e t e m p erat ure sensor defaul t s t o a hi gh i m pedance st at e and any a/ d m easurem ent s perform ed on t h e sensor whi l e di sabl ed resul t i n m eani ngl ess dat a . figure 9.1. voltage reference functional block diagram bias generator (to adc and dac) vref en (to analog mux) rload agnd agnd external equivalent load circuit agnd r1 av+ external voltage reference circuit temp sensor en 200ua (max) (bias to adc and dac) ref 0 cn tempe biase refbe 2.4v reference en agnd r e v. 1.7 60
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 9.2. ref0cn: reference control register r/w r/w r/w r / w r/w r / w r / w r e s e t v a l u e - - - - - tem p e b i a s e r e fb e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0xd1 r / w bi t s 7-3: unused. read = 00000b; w r i t e = don?t care bit2 : tempe: tem p eratu r e sen s o r en ab le bit 0: internal tem p erature sensor off. 1: internal tem p erature sensor on. bit1 : biase: bias en ab le bit fo r adc an d dac?s 0: internal bias off. 1: internal bias on (requi red for use of adc or dac?s). bit0 : refbe: in tern al vo ltag e referen ce bu ffer en ab le bit 0: internal reference buffer off. sy stem reference can be driven from external source on vr ef pi n. 1: internal reference buffer on. sy stem re ference provi ded by i n t e rnal vol t a ge reference. table 9.1. reference electrical characteristics vdd = 3.0v, av+ = 3.0v, -40 q c to +8 5 q c unless otherwise specified. parameter c o n d i t i o n s m i n t y p max u n i t s internal reference (refbe = 1) out put vol t a ge 25 q c am bient 2 . 3 4 2 . 4 3 2 . 5 0 v vr ef short c i rcui t c u rrent 30 m a vr ef power suppl y c u rrent (suppl i e d by av+) 5 0 p a vref tem p erature coefficient 1 5 ppm / q c load r e gul at i on load = (0-t o-200 p a) to agnd (note 1) 0 . 5 ppm / p a vref turn-on tim e 1 4.7 p f t a nt al um , 0.1 p f ceram ic bypass 2 m s vref turn-on tim e 2 0.1 p f ceram ic bypass 2 0 p s vr ef turn-on ti m e 3 no by pass cap 10 p s ex ternal reference (refbe = 0) input vol t a ge r a nge 1.00 (av+) ? 0.3v v input c u rrent 0 1 p a note 1: the reference can only source current. w h en driv in g an ex tern al lo ad , it is recom m e nded t o add a l o ad resistor to agnd. 61 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 10. cip-51 cpu the mcus? system cpu is the cip-51. the cip-5 1 is fu lly co m p atib le with th e mcs-5 1 tm in stru ctio n set. st andard 803x/ 805x assem b l e rs and com p i l e rs can be used t o devel op soft ware. the m c u fam i l y has a superset of all the peripherals included with a sta ndard 8051. included are four 16-bit c ounter/tim ers (see description in section 19), a ful l - dupl ex uar t (see descri pt i on i n sect i on 18), 256 by t e s of i n t e rnal r a m , 128 by t e speci al funct i on register (sfr) address space (see secti on 10.3), and four byte-wide i/o ports (see description in section 14). the cip-51 also includes on-chip debug hard ware (see description in section 21) , and interfaces directly with the m c us? anal og and di gi t a l subsy s t e m s provi di ng a com p l e t e dat a acqui si t i on or cont rol - sy st em sol u t i on i n a si ngl e in teg r ated circu it. features the cip-51 microcontroller core im plem ents the standard 8051 organization a nd peripherals as well as additional cu sto m p e rip h e rals an d fu n c tio n s to ex ten d its cap ab ility (see fig u r e 1 0 . 1 fo r a b l o c k d i ag ram ) . th e cip-5 1 includes the following features: - r e set input - power m a nagem e nt m odes - on-chi p debug c i rcui t r y - program and dat a m e m o ry securi t y - fu lly co m p atib le with mcs-5 1 in stru ctio n set - 25 m i ps peak throughput wi t h 25m hz c l ock - 0 t o 25m hz c l ock frequency (on ?f0x5/ 6/ 7) - four by te-w ide i/o ports - ext e nded int e rrupt handl er figure 10.1. cip-51 block diagram data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus dat a bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register dat a bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8 r e v. 1.7 62
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 performance the c i p-51 em pl oy s a pi pel i n ed archi t ect ure t h at great l y i n creases i t s i n st ruct i on t h roughput over t h e st andard 8051 archi t ect ure. in a st andard 8051, al l i n st ruct i ons except for m u l and div t a ke 12 or 24 sy st em cl ock cy cl es t o execut e , and usual l y have a m a xi m u m sy st em cl ock of 12m hz. b y cont rast , t h e c i p-51 core execut e s 70% of i t s i n st ruct i ons i n one or t w o sy st em cl ock cy cl es, wi t h no i n st ruct i ons t a ki ng m o re t h an ei ght sy st em cl ock cy cl es. w i t h t h e c i p-51?s m a xi m u m sy st em cl ock at 25m hz, i t has a peak t h roughput of 25m ips. the c i p-51 has a t o t a l of 109 i n st ruct i ons. the num ber of i n st ruct i ons versus t h e sy st em cl ock cy cl es requi red t o execut e t h em i s as fo llo ws: instructions 2 6 5 0 5 1 4 7 3 1 2 1 clocks to execute 1 2 2/ 3 3 3 / 4 4 4 / 5 5 8 programming and debugging support a jtag-based serial interface is provided for in-sys tem program m i ng of the flash program m e m o ry and com m uni cat i on wi t h on-chi p debug support ci rcui t r y . the reprogram m a bl e fl ash can al so be read and changed a single by te at a tim e by the applica tion software using the m ovc and m ovx instructions. this feature allows program m e m o ry to be used for non-vol atile data storage as well as updating program code under software control. the on-chip debug support circuitry f acilitates full speed in-circuit debugging, allowing the setting of hardware breakpoi nt s and wat c h poi nt s, st art i ng, st oppi ng and si ngl e st eppi ng t h rough program execut i on (i ncl udi ng i n t e rrupt service routines), exam ination of the program ?s cal l st ack, and readi ng/ wri t i ng t h e cont ent s of regi st ers and m e m o ry . thi s m e t hod of on-chi p debuggi ng i s com p l e t e l y non-i n t r usi v e and non-i nvasi ve, requi ri ng no r a m , st ack, t i m ers, or ot her on-chi p resources. the cip-51 is supported by developm ent tools from silic on laboratories and third party vendors. silicon labs provi des an i n t e grat ed devel opm ent envi ronm ent (id e) i n cl udi ng edi t o r, m acro assem b l e r, debugger and program m e r. the ide?s debugger and program m e r interface to the cip-51 via its jtag interface to provide fast and effi ci ent i n -sy s t e m devi ce program m i ng and debuggi ng. th i r d part y m acro assem b l e rs and c com p i l e rs are al so available. 10.1. instruction set th e in stru ctio n set o f th e cip-5 1 system co n t ro ller is fu lly co m p atib le with th e stan d a rd mcs-5 1 ? in stru ctio n set. st andard 8051 devel opm ent t ool s can be used t o devel op so ft ware for t h e c i p-51. al l c i p-51 i n st ruct i ons are t h e bi nary and funct i onal equi val e nt of t h ei r m c s-51? count erpart s, i n cl udi ng opcodes, addressi ng m odes and effect on psw fl ags. however, i n st ruct i on t i m i ng i s di fferent t h an t h at of t h e st andard 8051. 10.1.1. instruction and cpu timing in m a ny 8051 i m pl em ent a t i ons, a di st i n ct i on i s m a de bet w een m achi n e cy cl es and cl ock cy cl es, wi t h m achi n e cy cl es vary i ng from 2 t o 12 cl ock cy cl es i n l e ngt h. however, t h e c i p-51 i m pl em ent a t i on i s based sol e l y on cl ock cy cl e tim in g . all in stru ctio n tim in g s are sp ecified in term s o f clo c k cycles. due to the pipelined architect ure of t h e c i p-51, m o st i n st ruct i ons execut e in the sam e num ber of clock cycles as th ere are p r o g r am b y tes in th e in stru ctio n . co n d itio n a l b r an ch in stru ctio n s tak e o n e less clo c k cycle to co m p lete when t h e branch i s not t a ken as opposed t o when t h e branch i s t a ken. tabl e 10.1 i s t h e c i p-51 inst ruct i on set sum m a ry, which includes the m n em onic, num ber of bytes, and num ber of clock cycl es for each instruction. 10.1.2. movx instruction and program mem o ry the movx instruction is typically used to access external data m e m o ry. in the cip-51, the movx instruction can access the on-chip program m e m o ry space im plem ented as re program m a ble flash m e m o ry using the control bits in t h e psc tl regi st er (see fi gure 11.1). thi s feat ure provi des a m echani s m for t h e c i p-51 t o updat e program code and use the program m e m o ry space for non-volatile data stor age. for the products with ram m a pped into external data m e m o ry space (c8051f005/06/ 07/15/16/17), movx is still used to read /write this m e m o ry with the psctl 63 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 register configured for accessing the exte rnal data m e m o ry space. refer to section 11 (flash mem o ry) for further d e tails. r e v. 1.7 64
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 10.1. cip-51 instruction set summary mnemonic description by tes clock cycles arithmetic operations add a,rn add register to a 1 1 add a,direct add direct by te to a 2 2 add a,@ri add indirect ram to a 1 2 add a,#data add im m e diate to a 2 2 addc a,rn add register to a with carry 1 1 addc a,direct add direct by te to a with carry 2 2 addc a,@ri add indirect ram to a with carry 1 2 addc a,#data add im m e diate to a with carry 2 2 sub b a,r n subt ract regi st er from a wi t h borrow 1 1 sub b a,di rect subt ract di rect by t e from a wi t h borrow 2 2 sub b a,@r i subt ract i ndi rect r a m from a wi t h borrow 1 2 sub b a,#dat a subt ract i m m e di at e from a wi t h borrow 2 2 inc a increm ent a 1 1 inc rn increm ent register 1 1 inc direct increm ent direct byte 2 2 inc @ri increm ent indirect ram 1 2 dec a decrem ent a 1 1 dec rn decrem ent register 1 1 dec direct decrem ent direct byte 2 2 dec @ri decrem ent indirect ram 1 2 inc dptr in crem en t data po in ter 1 1 mul ab mu ltip ly a an d b 1 4 div ab divide a by b 1 8 da a decim a l adjust a 1 1 logical operations anl a,rn and register to a 1 1 anl a,direct and direct by te to a 2 2 anl a,@ri and indirect ram to a 1 2 anl a,#data and im m e diate to a 2 2 anl direct,a and a to direct by te 2 2 anl direct,#data and im m e di ate to direct by te 3 3 orl a,rn or register to a 1 1 or l a,di rect or di rect by t e t o a 2 2 orl a,@ri or indirect ram to a 1 2 or l a,#dat a or i m m e di at e t o a 2 2 or l di rect ,a or a t o di rect by t e 2 2 or l di rect ,#dat a or i m m e di at e t o di rect by t e 3 3 xrl a,rn exclusive-or register to a 1 1 xr l a,di rect excl usi v e-or di rect by t e t o a 2 2 xr l a,@r i excl usi v e-or i ndi rect r a m t o a 1 2 xr l a,#dat a excl usi v e-or i m m e di at e t o a 2 2 xr l di rect ,a excl usi v e-or a t o di rect by t e 2 2 xr l di rect ,#dat a excl usi v e-or i m m e di at e t o di rect by t e 3 3 clr a clear a 1 1 c p l a c o m p l e m e nt a 1 1 rl a ro tate a left 1 1 r l c a r o t a t e a l e ft t h rough carry 1 1 r r a r o t a t e a ri ght 1 1 65 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 mnemonic description by tes clock cycles rrc a rotate a right through carry 1 1 sw ap a swap ni bbl es of a 1 1 data transfer m ov a,r n m ove regi st er t o a 1 1 m ov a,di rect m ove di rect by t e t o a 2 2 m ov a,@r i m ove i ndi rect r a m t o a 1 2 m ov a,#dat a m ove i m m e di at e t o a 2 2 m ov r n ,a m ove a t o regi st er 1 1 m ov r n ,di r ect m ove di rect by t e t o regi st er 2 2 m ov r n ,#dat a m ove i m m e di at e t o regi st er 2 2 m ov di rect ,a m ove a t o di rect by t e 2 2 m ov di rect ,r n m ove regi st er t o di rect by t e 2 2 m ov di rect ,di r ect m ove di rect by t e t o di rect 3 3 m ov di rect ,@r i m ove i ndi rect r a m t o di rect by t e 2 2 m ov di rect ,#dat a m ove i m m e di at e t o di rect by t e 3 3 m ov @r i , a m ove a t o i ndi rect r a m 1 2 m ov @r i , di rect m ove di rect by t e t o i ndi rect r a m 2 2 m ov @r i , #dat a m ove i m m e di at e t o i ndi rect r a m 2 2 m ov dptr ,#dat a 16 load dat a poi nt er wi t h 16-bi t const a nt 3 3 m ovc a,@a+dptr m ove code by t e rel a t i v e dptr t o a 1 3 m ovc a,@a+pc m ove code by t e rel a t i v e pc t o a 1 3 m ovx a,@ri m ove external data (8-bit address) to a 1 3 m ovx @ri,a m ove a to external data (8-bit address) 1 3 m ovx a,@dptr m ove external data (16-bit address) to a 1 3 m ovx @dptr,a m ove a to external data (16-bit address) 1 3 push di rect push di rect by t e ont o st ack 2 2 pop di rect pop di rect by t e from st ack 2 2 xch a,rn exchange register with a 1 1 xc h a,di rect exchange di rect by t e wi t h a 2 2 xc h a,@r i exchange i ndi rect r a m wi t h a 1 2 xc hd a,@r i exchange l o w ni bbl e of i ndi rect r a m wi t h a 1 2 boolean manipulation clr c clear carry 1 1 c l r bi t c l ear di rect bi t 2 2 setb c set carry 1 1 setb b it set d i rect b it 2 2 cpl c co m p lem e n t carry 1 1 c p l bi t c o m p l e m e nt di rect bi t 2 2 anl c,bit and direct bit to carry 2 2 anl c,/bit and com p lem e nt of direct bit to carry 2 2 orl c,b it or d i rect b it to carry 2 2 orl c,/b it or co m p lem e n t o f d i rect b it to carry 2 2 m ov c , bi t m ove di rect bi t t o carry 2 2 m ov bi t , c m ove carry t o di rect bi t 2 2 jc rel ju m p if carry is set 2 2 / 3 jnc rel jum p i f carry not set 2 2/ 3 jb b it,rel ju m p if d i rect b it is set 3 3 / 4 3 / 4 jbc b it,rel ju m p if d i rect b it is set an d clear b it 3 3 / 4 program branching jnb b it,rel ju m p if d i rect b it is n o t set 3 r e v. 1.7 66
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 mnemonic description by tes clock cycles ac all addr11 absol u t e subrout i n e cal l 2 3 lc all addr16 long subrout i n e cal l 3 4 r et r e t u rn from subrout i n e 1 5 reti return from interrupt 1 5 ajm p addr11 absol u t e jum p 2 3 ljm p addr16 long jum p 3 4 sjm p rel short jum p (rel a t i v e address) 2 3 ju m p in d i rect relativ e to dptr 1 3 jz rel jum p i f a equal s zero 2 2/ 3 jnz rel jum p i f a does not equal zero 2 2/ 3 c j ne a,di rect ,rel c o m p are di rect by t e t o a and jum p i f not equal 3 3/ 4 c j ne a,#dat a ,rel c o m p are i m m e di at e t o a and jum p i f not equal 3 3/ 4 com p are im m e diat e t o regi st er and jum p i f not equal 3 3 / 4 cjne @ri,#data,rel com p are im m e diat e t o i ndi rect and jum p i f not equal 3 4 / 5 djnz r n ,rel decrem ent regi st er and jum p i f not zero 2 2/ 3 djnz di rect ,rel decrem ent di rect by t e and jum p i f not zero 3 3/ 4 n o p n o operat i on 1 1 jmp @a+dptr cjne rn,#data,rel note s on re giste r s , ope r a nds and addr e ssing m o de s: rn - register r0-r7 of the currently selected register bank. @r i - data ram location addressed indi rectly through register r0-r1 d i rect - 8-bit internal data location?s address. this coul d be a direct-access data ram location (0x00-0x7f) or an sfr (0x80-0xff). addr 16 - 16-bit destination address used by lcall and ljmp . the destination m a y be any w here within the 64k-by t e program m e m o ry s p ace. al l m n em oni cs copy ri ght ed ? int e l c o rporat i on 1980. rel - 8-bit, signed (two?s com p lim ent) offset relative to the fi rst by te of the following instruction. used by sjmp and all conditional jum p s. #data - 8-bit constant #data 16 - 16-bit constant bit - direct-addressed bit in data ram or sfr. addr 11 - 11-bit destination address used by acall and ajmp. the destination m u st be within the sam e 2k- by te page of program memory as the fi rst by te of the following instruction. there i s one unused opcode (0xa5) t h at perform s t h e sam e funct i on as nop. 67 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 10.2. memory organiz a tion the m e m o ry organi zat i on of t h e c i p-51 sy st em c ont rol l e r i s si m i l a r t o t h at of a st andard 8051. there are t w o separate m e m o ry spaces: program m e m o ry and data m e m o ry . program and data m e m o ry share the sam e address space but are accessed via different instruc tion types. there are 256 bytes of inte rnal data m e m o ry and 64k bytes of internal program m e m o ry address space im plem ented with in the cip-51. the cip-51 m e m o ry organization is shown i n fi gure 10.2. 10.2.1. program mem o ry the cip-51 has a 64k-byte program m e m o ry space. the mcu im plem ents 32896 bytes of this program m e m o ry space as in-system , reprogram m a ble flash m e m o ry, or ganized in a contiguous bl ock from addresses 0x0000 to 0x807f. note: 512 bytes (0x7e00 ? 0x7fff) of this m e m o ry ar e reserved for factory use and are not available for user program st orage. program m e m o ry i s norm a l l y assum e d t o be read-onl y . however, t h e c i p-51 can wri t e t o program m e m o ry by setting the program store w r ite enable bit (psctl.0) and using the m ovx in struction. this feature provides a m echanism for the cip-51 to update program code and use the program m e m o ry space for non-volatile data storage. r e fer t o sect i on 11 (fl a sh m e m o ry ) for further details. 10.2.2. data mem o ry the cip-51 im plem ents 256 bytes of internal ram m a ppe d into the data m e m o ry space from 0x00 through 0xff. the l o wer 128 by t e s of dat a m e m o ry are used for general purpose regi st ers and scrat c h pad m e m o ry . ei t h er di rect or indirect addressing m a y be used to access the lower 128 bytes of data m e m o ry. locations 0x00 through 0x1f are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, m a y be addressed as bytes or as 128 bit locations accessible with the direct- bi t addressi ng m ode. 1 0 0 the upper 128 bytes of data m e m o ry are accessible only by indirect addressing. this region occupies the sam e address space as the special function registers (sfr) but is physically separate from the sfr space. the addressing m ode used by an instru ction when accessing locations above 0x7f determ ines whether the cpu accesses the upper 128 bytes of data m e m o ry space or the sfrs. in structions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f will access the uppe r 128 bytes of data m e m o ry. figure . 2 illu strates th e d a ta m e m o ry o r g a n i zatio n o f th e cip-5 1 . the c8051f005/06/07/15/ 16/17 also have 2048 bytes of ram in the ex ternal data m e m o ry space of the cip-51, accessible using the movx instruc tion. refer to section 12 (external ram) for details. 10.2.3. general purpose registers the l o wer 32 by t e s of dat a m e m o ry , l o cat i ons 0x00 t h r ough 0x1f, m a y be addressed as four banks of general - purpose regi st ers. each bank consi s t s of ei ght by t e -wi d e regi st ers desi gnat e d r 0 t h rough r 7 . onl y one of t h ese banks m a y be enabl e d at a t i m e. two bi t s i n t h e program st at us word, r s 0 (psw .3) and r s 1 (psw .4), sel ect t h e act i v e regi st er bank (see descri pt i on of t h e psw i n fi gure 1 . 6 ) . t h i s al l o ws fast cont ext swi t c hi ng when ent e ri ng subrout i n es and i n t e rrupt servi ce rout i n es. indi rect addr essi ng m odes use regi st ers r 0 and r 1 as i ndex regi st ers. 10.2.4. bit addressable locations in addition to direct access to data m e m o ry organized as bytes, the sixteen data m e m o ry locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of t h e by t e at 0x20 has bi t address 0x00 whi l e bi t 7 of t h e by t e at 0x20 has bi t address 0x07. b i t 7 of t h e by t e at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or dest i n at i on operands as opposed t o a by t e source or dest i n at i on). the m c s-51? assem b l y l a nguage al l o ws an al t e rnat e not at i on for bi t addressi ng of t h e form xx.b where xx is th e by t e address and b is th e b it p o s itio n with in th e b y te. fo r ex am p l e, th e in stru ctio n : mov c, 22h.3 m oves t h e b ool ean val u e at 0x13 (bi t 3 of t h e by t e at l o cat i on 0x22) i n t o t h e user c a rry fl ag. r e v. 1.7 68
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.2. memory map 10.2.5. stack a program m e r?s st ack can be l o cat ed any w here i n t h e 256-by t e dat a m e m o ry . the st ack area i s desi gnat e d usi ng the stack pointer (sp, 0x81) sfr. the sp will point to the last location used. the next value pushed on the stack is placed at sp+1 and then sp is increm ente d. a reset initializes the stack point er to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the firs t register (r0) of register bank 1. thus, if m o re than one register bank is to be used, the sp should be initialized to a location in the data m e m o ry not bei ng used for dat a st orage. the st ack dept h can ext e nd up t o 256 by t e s. the mcus also have built-in hardware for a stack record. the stack record is a 32-bit shift register, where each push or increm ent sp pushes one record bit onto the register, and each call or interrupt pushes two record bits onto t h e regi st er. (a pop or decrem ent sp pops one record bi t , and a r e t u rn pops t w o record bi t s , al so.) the st ack record ci rcui t r y can al so det ect an overfl ow or underfl ow on t h e st ack, and can not i f y t h e debug soft ware even wi t h t h e m c u runni ng ful l - speed debug. flash (in-system programmable in 512 byte sectors) program memory 0x0000 0x7fff (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) reserved 0x7e00 0x7dff 128 byte isp flash 0x8000 0x807f data memory general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space ram - 2048 bytes (accessable using movx command) 0x0000 0x07ff (same 2048 byte ram block ) 0x0800 0x0fff (same 2048 byte ram block ) 0xf800 0xffff the same 2048 byte ram block can be addressed on 2k boundaries throughout the 64k external data memory space. (same 2048 byte ram block ) 0x1000 0x17ff 69 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 10.3. special function registers the direct-access data m e m o ry locations from 0x80 to 0xff constitute the special functi on registers (sfrs). the sfr s provi de cont rol and dat a exchange wi t h t h e c i p-51? s resources and peri pheral s . the c i p-51 dupl i cat es t h e sfrs found in a typical 8051 im plem entation as well as im plem enting additional sfrs us ed to configure and access th e su b - system s u n i q u e to th e mcu. th is allo ws th e ad d itio n o f n e w fu n c tio n a lity wh ile retain in g co m p atib ility with th e mcs-5 1 ? in stru ctio n set. tab l e 1 0 . 3 lists th e sfrs im p l em en ted in th e cip-5 1 system co n t ro ller. the sfr registers are accessed any tim e the direct addre ssing m ode is used to access m e m o ry locations from 0x80 t o 0xff. sfr s wi t h addresses endi ng i n 0x0 or 0x8 (e.g. p0 , tc on, p1, sc on, ie, et c.) are bi t - addressabl e as wel l as byte-addressable. all other sfr s are byte-addressable only. unocc upied addresses in the sfr space are reserved for future use. accessing thes e areas will have an indeterm inate effect and should be avoided. refer to the corresponding pages of the datasheet, as indicated in table 10.3, for a de tailed description of each register. spi0cn p c a 0 c p h 3 table 10.2. special function register memory map f8 p c a 0 h p c a 0 c p h 0 p c a 0 c p h 1 p c a 0 c p h 2 p c a 0 c p h 4 w d t c n f0 b e i p 1 e i p 2 a d c 0 c n p c a 0 l p c a 0 c p l 0 p c a 0 c p l 1 p c a 0 c p l 2 p c a 0 c p l 3 p c a 0 c p l 4 r s t s r c e0 a c c xbr0 xbr1 xbr2 eie2 e i e 1 p c a 0 m d p c a 0 c p m 0 pca0cpm1 p c a 0 c p m 2 p c a 0 c p m 3 p c a 0 c p m 4 d0 p s w r e f 0 c n dac0l dac0h d a c 0 c n d a c 1 l d a c 1 h d a c 1 c n c8 t 2 c o n r c a p 2 l r c a p 2 h t l 2 t h 2 s m b 0 c r c0 smb0 c n smb0 s t a a m x 0 s l p 3 o s c x c n osci c n f l scl fl acl * * * a8 i e p r t 1 i f e m i 0 c n * * * a0 p 2 p r t 0 c f p r t 1 c f p r t 2 c f p r t 3 c f 98 s c o n s b u f s p i 0 c f g s p i 0 d a t s p i 0 c k r c p t 0 c n c p t 1 c n 90 p1 t m r 3 c n tmr3 r l l tmr3 r l h tmr3 h tmr3 l 88 t c o n psctl t m o d tl0 t l 1 t h 0 th1 c k c o n 80 p 0 s p d p l d p h p c o n 0(8) 3 ( b ) 5 ( d ) 7(f) 1 ( 9 ) 2 ( a ) 4(c ) 6 ( e ) e8 d8 p c a 0 c n smb0 dat smb0 adr adc0 g tl adc0 g th adc0 ltl adc0 lth b8 ip a m x 0 c f adc0cf adc0l adc0h b0 b i t addressabl e table 10.3. special function registers * r e fers t o a regi st er i n t h e c 8051f000/ 1/ 2/ 5/ 6/ 7 onl y . *** r e fers t o a regi st er i n t h e c 8051f005/ 06/ 07/ 15/ 16/ 17 onl y . sfr s are l i s t e d i n al phabet i cal order. al l undefi ned sfr l o cat i ons are reserved. ** r e fers t o a regi st er i n t h e c 8051f010/ 1/ 2/ 5/ 6/ 7 onl y . address register descri pt i on page no. 0 x e 0 a c c accum u l a t o r 76 0xb c adc 0c f adc c onfi gurat i on 0xe8 adc 0c n 3 4 5 adc c ont rol 0xc 5 adc 0gth adc great er-than dat a w o rd (hi gh b y t e ) 0xc 4 adc 0gtl adc great er-than dat a w o rd (low b y t e ) 0xb f adc 0h adc dat a w o rd (hi gh b y t e ) 35*, 46** 0xb e adc 0l 3 3 2 * , 4 * * * , 4 * * 3 6 4 7 * , * * 3 6 4 7 * , * * adc dat a w o rd (low b y t e ) 3 5 4 6 * , * * r e v. 1.7 70
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 address register descri pt i on page no. 0xc 7 adc 0lth adc less-than dat a w o rd (hi gh b y t e ) adc0ltl adc less-than data w o rd (low byte) 0xb a am x0c f adc m ux c onfi gurat i on 0xb b am x0sl adc m ux c h annel sel ect i on 0 x f 0 b b r e gi st e r c k c o n 0x9e c p t0c n c o m p arat or 0 c ont rol 0x9f c p t1c n c o m p arat or 1 c ont rol 0xd4 dac 0c n 52 dac 0 c ont rol 0xd3 dac 0h dac 0 dat a w o rd (hi gh b y t e ) 0xd2 dac 0l 5 2 dac 0 dat a w o rd (low b y t e ) 0xd7 dac 1c n dac 1 c ont rol 0xd6 dac 1h dac 1 dat a w o rd (hi gh b y t e ) dac 1l dac 1 dat a w o rd (low b y t e ) 0x83 dph dat a poi n t e r (hi gh b y t e ) 0x82 dpl dat a poi n t e r (low b y t e ) 0xe6 eie1 ext e nded int e rrupt enabl e 1 0xe7 eie2 ext e nded int e rrupt enabl e 2 0xf6 eip1 ext e rnal int e rrupt pri o ri t y 1 0xf7 eip2 ext e rnal int e rrupt pri o ri t y 2 external me m o ry interface control 0xb 7 flac l fl ash access li m i t 0xb 6 flsc l fl ash m e m o ry ti m i ng prescal er 0 x a 8 i e int e rrupt enabl e 7 9 0xb 8 ip int e rrupt pri o ri t y c ont rol 0xb2 oscicn internal oscillator control 0xb1 oscxcn p0 port 0 lat c h 0x90 p1 port 1 lat c h 0xa0 p2 port 2 lat c h 0xb 0 p3 port 3 lat c h 0xd8 pc a0c n 1 6 0 program m a bl e c ount er array 0 c ont rol 0xfa pc a0c p h0 pc a c a pt ure m odul e 0 dat a w o rd (hi gh b y t e ) 163 0xfb pc a0c p h1 pc a c a pt ure m odul e 1 dat a w o rd (hi gh b y t e ) 0xfc pc a0c p h2 pc a c a pt ure m odul e 2 dat a w o rd (hi gh b y t e ) 0xfd pc a0c p h3 0xfe pc a0c p h4 1 6 3 pc a c a pt ure m odul e 4 dat a w o rd (hi gh b y t e ) 0xea pc a0c p l0 pc a c a pt ure m odul e 0 dat a w o rd (low b y t e ) 0xeb pc a0c p l1 pc a c a pt ure m odul e 1 dat a w o rd (low b y t e ) pc a0c p l2 pc a c a pt ure m odul e 2 dat a w o rd (low b y t e ) 0xed pc a0c p l3 3 6 4 7 * , * * 0xc6 3 6 4 7 * , * * 3 1 4 2 * , * * 3 2 4 3 * , * * 76 0 x 8 e c l ock c ont rol 144 5 6 5 8 5 2 5 3 5 3 0xd5 5 3 7 4 7 4 8 1 8 2 8 3 8 4 0xaf emi0cn 9 2 * * * 9 0 * * * 9 1 8 0 1 0 0 external oscillator control 1 0 1 0x80 1 0 9 1 1 0 1 1 1 1 1 2 1 6 3 1 6 3 pc a c a pt ure m odul e 3 dat a w o rd (hi gh b y t e ) 1 6 3 1 6 3 1 6 3 0xec 163 pc a c a pt ure m odul e 3 dat a w o rd (low b y t e ) 1 6 3 71 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 address register descri pt i on page no. 0xee pc a0c p l4 pc a c a pt ure m odul e 4 dat a w o rd (low b y t e ) 0xda pc a0c p m 0 program m a bl e c ount er array 0 c a pt ure/ c o m p are 0 0xdb pc a0c p m 1 program m a bl e c ount er array 0 c a pt ure/ c o m p are 1 0xdc pc a0c p m 2 program m a bl e c ount er array 0 c a pt ure/ c o m p are 2 0xdd pc a0c p m 3 1 6 2 program m a bl e c ount er array 0 c a pt ure/ c o m p are 3 0xde pc a0c p m 4 program m a bl e c ount er array 0 c a pt ure/ c o m p are 4 0xf9 pc a0h pc a c ount er/ t i m er dat a w o rd (hi gh b y t e ) 0xe9 pc a0l pc a c ount er/ t i m er dat a w o rd (low b y t e ) 0xd9 pc a0m d 0 x 8 7 p c o n power c ont rol 86 0xa4 pr t0c f port 0 c onfi gurat i on 0xa5 pr t1c f port 1 c onfi gurat i on 0xad pr t1if port 1 int e rrupt fl ags 110 0xa6 pr t2c f 0xa7 pr t3c f port 3 c onfi gurat i on 0x8f psc tl program st ore r w c ont rol 0xd0 psw 7 5 program st at us w o rd 0xc b r c a p2h c ount er/ t i m er 2 c a pt ure (hi gh b y t e ) 151 0xc a r c a p2l 1 5 1 c ount er/ t i m er 2 c a pt ure (low b y t e ) r e f0c n vol t a ge r e ference c ont rol r e gi st er 0xef r s tsr c sb uf seri al dat a b u ffer (uar t) 0x98 sc on 0xc 3 sm b 0 adr 1 2 0 sm b u s 0 address 0xc 0 sm b 0 c n 0xc f sm b 0 c r 1 1 9 sm b u s 0 c l ock r a t e sm b 0 dat sm b u s 0 dat a 0xc 1 st ack poi n t e r 0 x 9 a s p i 0 c f g spi c l ock r a t e 0xf8 spi0c n spi b u s c ont rol 128 0x9b spi0dat 1 2 9 spi port 1dat a 0xc 8 t2c on c ount er/ t i m er 2 c ont rol 150 0 x 8 8 t c o n th0 c ount er/ t i m er 0 dat a w o rd (hi gh b y t e ) 0x8d th1 c ount er/ t i m er 2 dat a w o rd (hi gh b y t e ) 0x8a tl0 c ount er/ t i m er 0 dat a w o rd (low b y t e ) 0x8b tl1 c ount er/ t i m er 1 dat a w o rd (low b y t e ) tl2 c ount er/ t i m er 2 dat a w o rd (low b y t e ) 1 6 3 1 6 2 1 6 2 1 6 2 1 6 2 1 6 3 1 6 3 program m a bl e c ount er array 0 m ode 1 6 1 1 0 9 1 1 0 port 2 c onfi gurat i on 1 1 1 1 1 2 8 8 0xd1 61 r e set source r e gi st er 9 7 0x99 1 3 6 seri al port c ont rol (uar t) 1 3 7 sm b u s 0 c ont rol 1 1 8 0xc 2 120 sm b 0 sta sm b u s 0 st at us 1 2 1 0x81 sp 74 serial periphera l interface configuration 1 2 7 0x9d spi0c kr 1 2 9 c ount er/ t i m er c ont rol 142 0x8c 145 c ount er/ t i m er 1 dat a w o rd (hi gh b y t e ) 1 4 5 0xc d th2 1 5 1 1 4 5 1 4 5 0xc c 1 5 1 r e v. 1.7 72
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 address register descri pt i on page no. 0 x 8 9 t m o d tm r 3 c n ti m e r 3 c ont rol 0x95 tm r 3 h 0x94 tm r 3 l 1 5 3 ti m e r 3 low 0x93 tm r 3 r l h 1 5 3 ti m e r 3 r e l o ad hi gh 0x92 tm r 3 r ll 153 ti m e r 3 r e l o ad low w d tc n xb r 0 0xe2 xb r 1 1 0 7 port i/ o c r ossbar c onfi gurat i on 2 0xe3 xb r 2 1 0 8 port i/ o c r ossbar c onfi gurat i on 3 reserv ed c ount er/ t i m er m ode 143 0x91 1 5 2 ti m e r 3 hi gh 1 5 3 0xff w a t c hdog ti m e r c ont rol 96 0xe1 port i/ o c r ossbar c onfi gurat i on 1 1 0 5 0x84-86, 0x96-97, 0x9c , 0xa1-a3, 0xa9-ac , 0xae, 0xb 3-b 5 , 0xb 9, 0xb d, 0xc 9, 0xc e, 0xdf, 0xe4-e5, 0xf1-f5 * r e fers t o a regi st er i n t h e c 8051f000/ 1/ 2/ 5/ 6/ 7 onl y . *** r e fers t o a regi st er i n t h e c 8051f005/ 06/ 07/ 15/ 16/ 17 onl y . ** r e fers t o a regi st er i n t h e c 8051f010/ 1/ 2/ 5/ 6/ 7 onl y . 73 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 10.3.1. register descriptions fol l o wi ng are descri pt i ons of sfr s rel a t e d t o t h e operat i on of t h e c i p-51 sy st em c ont rol l e r. r e served bi t s shoul d not be set t o l ogi c l . fut u re product versi ons m a y use t h es e bi t s t o i m pl em ent new feat ures i n whi c h case t h e reset v a lu e o f th e b it will b e lo g i c 0 , selectin g th e featu r e?s d e fau lt state. detailed d e scrip tio n s o f th e rem a in in g sfrs are i n cl uded i n t h e sect i ons of t h e dat a sheet associ at ed wi t h t h ei r correspondi ng sy st em funct i on. figure 10.3. sp: stack pointer r/w r/w bit7 bit6 bit5 bit4 bit3 b i t 2 b i t 1 r / w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 1 1 1 b i t 0 sfr address: 0 x 8 1 figure 10.4. dpl: data pointer low byte r / w r / w reset value 00000000 bit7 bit6 bit5 bit4 b i t 2 b i t 0 r/w r / w r/w r / w r/w r / w b i t 3 b i t 1 sfr address: 0 x 8 2 b i t s 7-0: sp: stack pointer. the st ack poi nt er hol ds t h e l o cat i on of t h e t op of t h e st ack. the st ack poi nt er i s i n crem ent e d before every push operat i on. the sp regi st er defaul t s t o 0x07 aft e r reset . bits 7 - 0 : dpl: data po in ter lo w. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed r a m and fl ash m e m o ry . figure 10.5. dph: data pointer high byte r/w r / w r/w r / w r/w r / w r e s e t v a l u e b i t 3 b i t 2 b i t 0 0 x 8 3 r / w r / w 00000000 bit7 bit6 bit5 bit4 b i t 1 sfr address: bits 7 - 0 : dph: data po in ter hig h . the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed r a m and fl ash m e m o ry . r e v. 1.7 74
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.6. psw: program status word r/w r/w r/w r/w r/w r/w r / w parity 00000000 bit7 bit6 bit5 bit4 bit3 b i t 2 b i t 0 bit7 : cy: carry flag . th is b it is set wh en th e last arith m e tic o p e ratio n resu lts in a carry (ad d itio n ) o r a b o rro w (subt ract i on). it i s cl eared t o 0 by al l ot her ari t h m e t i c operat i ons. bit6 : ac: au x iliary carry flag . th is b it is set wh en th e last arith m e tic o p e ratio n resu lts in a carry in to (ad d itio n ) o r a borrow from (subt ract i on) t h e hi gh order ni bbl e. it i s cl eared t o 0 by al l ot her ari t h m e t i c operat i ons. bit5 : f0 : user flag 0 . thi s i s a bi t - addressabl e, general purpos e fl ag for use under soft ware cont rol . b i t s 4-3: r s 1-r s 0: r e gi st er b a nk sel ect . these bits select which register ba nk is used during register accesses. r s 1 r s 0 r e gi st er b a nk address 0 0 0 0x00-0x07 0 1 1 0x08-0x0f 1 0 2 0x10-0x17 1 1 3 0x18-0x1f not e : any i n st ruct i on whi c h changes t h e r s 1-r s 0 bi t s m u st not be i m m e di at el y fol l o wed b y th e ?mov rn , a? in stru ctio n . bit2 : ov: ov erflo w flag . thi s bi t i s set t o 1 under t h e fol l o wi ng ci rcum st ances: x an add, addc, or subb instruc tion causes a sign-change overflow. x a m u l i n st ruct i on resul t s i n an overfl ow (resul t i s great er t h an 255) . x a div i n st ruct i on causes a di vi de-by - zero condi t i on. the ov bit is cleared to 0 by the add, addc, subb, m u l, and div instructions in all other cases. bit1 : f1 : user flag 1 . thi s i s a bi t - addressabl e, general purpos e fl ag for use under soft ware cont rol . bit0 : parity: parity flag . (read only) this bit is set to 1 if the su m of the eight bits in the accum u lator is odd and cleared if the sum is even. r / w r e s e t v a l u e c y a c f 0 r s 1 r s 0 o v f 1 b i t 1 sfr address: (bit addressable) 0xd0 75 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.7. acc: accumulator r/w r/w r/w acc.4 b i t 4 (bit addressable) 0xe0 r / w r / w r/w r / w r / w r e s e t v a l u e a c c . 7 a c c . 6 a c c . 5 a c c . 3 a c c . 2 a c c . 1 a c c . 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: bits 7 - 0 : acc: accu m u lato r this register is the accum u lator for arithm e tic operations. figure 10.8. b: b register r/w r/w r / w r / w r / w r / w r e s e t v a l u e b . 7 b . 6 b . 5 b . 4 b . 3 b . 2 b . 1 b . 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 (bit addressable) r / w r/w bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf0 bits 7 - 0 : b: b reg i ster this register serves as a second accum u lator for certain arithm e tic operations. r e v. 1.7 76
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 10.4. interrupt handler the c i p-51 i n cl udes an ext e nded i n t e rrupt sy st em support i ng a t o t a l of 22 i n t e rrupt sources wi t h t w o pri o ri t y l e vel s . the allocation of interrupt sources between on-chip periphe rals and external inputs pi ns varies according to the speci fi c versi on of t h e devi ce. each i n t e rrupt source has one or m o re associ at ed i n t e rrupt -pendi ng fl ag(s) l o cat ed i n an sfr . w h en a peri pheral or ext e rnal source m eet s a val i d i n t e rrupt condi t i on, t h e associ at ed i n t e rrupt -pendi ng flag is set to lo g i c 1 . if i n t e rrupt s are enabl e d for t h e source, an i n t e rrupt request i s generat e d when t h e i n t e rrupt -pendi ng fl ag i s set . as soon as execut i on of t h e current i n st ruct i on i s com p l e t e , t h e c p u generat e s an lc all t o a predet erm i ned address t o begi n execut i on of an i n t e rrupt servi ce rout i n e (isr ) . each isr m u st end wi t h an r eti i n st ruct i on, whi c h ret u rns program execut i on t o t h e next i n st ruct i on t h at woul d have been execut e d i f t h e i n t e rrupt request had not occurred. if i n t e rrupt s are not enabl e d, t h e i n t e rrupt -pendi ng fl ag i s i gnored by t h e hardware and program execut i on cont i nues as norm a l . (the i n t e rrupt -pendi ng fl ag i s set t o l ogi c 1 regardl e ss of t h e i n t e rrupt ?s enabl e / d i s abl e st at e.) each i n t e rrupt source can be i ndi vi dual l y enabl e d or di sabl ed t h rough t h e use of an associ at ed i n t e rrupt enabl e bi t i n an sfr (ie-eie2). however, interrupts m u st fi rst be gl obal l y enabl e d by set t i ng t h e ea bi t (ie.7) t o l ogi c 1 before the individual interrupt enables are rec ognized. setting the ea bit to logic 0 di sables all interrupt sources regardless of t h e i ndi vi dual i n t e rrupt -enabl e set t i ngs. som e i n t e rrupt -pendi ng fl ags are aut o m a tically cleared by the hardware wh en the cpu vectors to the isr. however, m o st are not cleared by the ha rdware and m u st be cleared by software before returning from the isr. if an interrupt-pending flag rem a ins set after the cpu com p letes the return-from - interrupt (reti) instruction, a new in terru p t req u e st will b e g e n e rated im m e d i ately an d th e cpu will re-en t er th e isr after th e co m p letio n o f th e n e x t in stru ctio n . 10.4.1. mcu interrupt sources and vectors the m c us al l o cat e 12 i n t e rrupt sources t o on-chi p peri pheral s . up t o 10 addi t i onal ext e rnal i n t e rrupt sources are avai l a bl e dependi ng on t h e i/ o pi n confi gurat i on of t h e devi ce. so ftware can sim u late an in terru p t b y settin g an y in terru p t -p en d i n g flag to lo g i c 1 . if in terru p t s are en ab led fo r th e flag , an in terru p t req u e st will b e g e n e rated an d th e cpu will v ecto r to th e isr ad d r ess asso ciated with th e in terru p t -p en d i n g flag . mcu in terru p t so u r ces, asso ciated vect or addresses, pri o ri t y order and cont rol bi t s are su m m a rized in table 10.4. refer to the datasheet section associated with a particular on-chip peripheral for inform at i on regardi ng val i d i n t e rrupt condi t i ons for t h e peri pheral and t h e behavi or of i t s i n t e rrupt -pendi ng fl ag(s). 10.4.2. external interrupts two o f th e ex tern al in terru p t so u r ces (/int0 an d /int1 ) are co n f ig u r ab le as activ e-lo w lev e l-sen s itiv e o r activ e-lo w edge-sensitive inputs depending on the setting of it0 (tcon.0) and it1 (t con.2). ie0 (tcon.1) and ie1 (tc on.3) serve as t h e i n t e rrupt -pendi ng flag fo r th e /int0 an d /int1 ex tern al in terru p t s, resp ectiv ely. if an /int0 or /int1 external interrupt is confi gured as edge-sensitive, the corresponding interrupt-pending flag is autom a tically cleared b y th e h a rd ware wh en th e cpu v ecto r s to th e isr. w h en co n f ig u r ed as lev e l sen s itiv e, th e in terru p t - pendi ng fl ag fol l o ws t h e st at e of t h e ext e rnal i n t e rrupt ?s i nput pi n. the ext e rnal i n t e rrupt source m u st hol d t h e i nput active until the interrupt request is recognized. it m u st th en deactivate the interrupt re quest before execution of the isr co m p letes o r an o t h e r in terru p t req u e st will b e g e n e rated . the rem a ining four external interrupts (external interrupts 4-7) are active-low, edge-sensitive inputs. the interrupt- pendi ng fl ags for t h ese i n t e rrupt s are i n t h e port 1 int e rrupt fl ag r e gi st er shown i n fi gure 15.10. 77 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 10.4. interrupt summary interrupt source interrupt vector priority order interrupt-pending flag ena b le r e set 0 x 0 0 0 0 t o p n o n e al way s enabl e d ext e rnal int e rrupt 0 (/ int0) 0x0003 0 ie0 (tc on.1) ex0 (ie.0) ti m e r 0 overfl ow 0x000b 1 tf0 (tc on.5) et0 (ie.1) ext e rnal int e rrupt 1 (/ int1) 0x0013 2 ie1 (tc on.3) ex1 (ie.2) ti m e r 1 overfl ow 0x001b 3 tf1 (tc on.7) et1 (ie.3) seri al port (uar t) 0x0023 4 r i (sc on.0) ti (scon.1) es (ie.4) ti m e r 2 overfl ow (or exf2) 0x002b 5 tf2 (t2c on.7) et2 (ie.5) serial peripheral interf ace 0x0033 6 spif (spi0cn.7) w c ol (spi0cn.6) m odf (spi0cn.5) rxovrn (spi0cn.4) espi0 (eie1.0) smbus interface 0x003b 7 si (s m b 0 c n . 3 ) e s m b 0 ( e i e 1 . 1 ) adc 0 w i ndow c o m p ari s on 0x0043 8 adw int (adc 0c n.2) ew adc 0 (eie1.2) program m a bl e c ount er array 0 0x004b 9 c f (pc a 0c n.7) c c f n (pc a 0c n.n) epc a 0 (eie1.3) c o m p arat or 0 fal l i ng edge 0x0053 10 c p 0fif (c pt0c n.4) ec p0f (eie1.4) c o m p arat or 0 r i si ng edge 0x005b 11 c p 0r if (c pt0c n.5) ec p0r (eie1.5) c o m p arat or 1 fal l i ng edge 0x0063 12 ec p1f (eie1.6) c p 1fif (c pt1c n.4) 0x006b 13 ec p1r (eie1.7) ti m e r 3 overfl ow 0x0073 14 tf3 (tm r 3c n.7) et3 (eie2.0) adc 0 end of c onversi on 0x007b 15 adc int (adc 0c n.5) eadc 0 (eie2.1) ext e rnal int e rrupt 4 0x0083 16 ie4 (pr t 1if.4) ex4 (eie2.2) ext e rnal int e rrupt 5 0x008b 17 ie5 (pr t 1if.5) ex5 (eie2.3) ext e rnal int e rrupt 6 0x0093 18 ie6 (pr t 1if.6) ex6 (eie2.4) ext e rnal int e rrupt 7 0x009b 19 ie7 (pr t 1if.7) ex7 (eie2.5) unused int e rrupt locat i on 0x00a3 20 none r e served (eie2.6) ext e rnal c r y s t a l osc r eady 0x00ab 21 xtlvld (osc xc n.7) exvld (eie2.7) c o m p arat or 1 r i si ng edge c p 1r if (c pt1c n.5) 10.4.3. interrupt priorities each i n t e rrupt source can be i ndi vi dual l y program m e d t o one of t w o pri o ri t y l e vel s : l o w or hi gh. a l o w pri o ri t y i n t e rrupt servi ce rout i n e can be preem pt ed by a hi gh pri o ri t y i n t e rrupt . a hi gh pri o ri t y i n t e rrupt cannot be p r eem p t ed . each in terru p t h a s an asso ciated in terru p t p r io rity b it in an sfr (ip-eip2 ) u s ed to co n f ig u r e its p r io rity l e vel . low pri o ri t y i s t h e defaul t . if t w o i n t e rrupt s are recogni zed si m u l t a neousl y , t h e i n t e rrupt wi t h t h e hi gher p r io rity is serv iced first. if b o t h in terru p t s h a v e th e sam e p r io rity lev e l, a fix e d p r io rity o r d e r is u s ed to arb itrate. 10.4.4. interrupt latency int e rrupt response t i m e depends on t h e st at e of t h e c p u when t h e i n t e rrupt occurs. pendi ng i n t e rrupt s are sam p l e d and priority decoded each system cloc k cycle. therefore, the fastest po ssible response tim e is 5 system clock cycles: 1 clock cycle to detect the interr u p t an d 4 clo c k cycles to co m p lete th e lcall to th e isr. if an in terru p t is pendi ng when a r eti i s execut e d, a si ngl e i n st ruct i on i s execut e d before an lc all i s m a de t o servi ce t h e pendi ng i n t e rrupt . therefore, t h e m a xi m u m response t i m e for an i n t e rrupt (when no ot her i n t e rrupt i s current l y bei ng serv iced o r th e n e w in terru p t is o f g r eater p r io rity) o ccu rs wh en th e cpu is p e rfo rm in g an reti in stru ctio n fol l o wed by a div as t h e next i n st ruct i on. in t h i s case, t h e response t i m e i s 18 sy st em cl ock cy cl es: 1 cl ock cy cl e to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cycles to co m p lete th e div in stru ctio n an d 4 clock cycles to execute the lcall to th e isr . if t h e c p u i s execut i ng an isr for an i n t e rrupt wi t h equal or hi gher p r io rity, th e n e w in terru p t will n o t b e serv iced u n til th e cu rren t isr co m p letes, in clu d i n g th e reti an d fo llo win g in stru ctio n . r e v. 1.7 78
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 10.4.5. interrupt register descriptions th e sfrs u s ed to en ab le th e in terru p t so u r ces an d set th eir p r io rity lev e l are d e scrib e d b e lo w. refer to th e d a tash eet section associated with a particular on-chip peripheral for inform ation regard i ng val i d i n t e rrupt condi t i ons for t h e peri pheral and t h e behavi or of its interrupt-pending flag(s). figure 10.9. ie: interrupt enable r/w r/w r / w r / w r/w r / w r / w r e s e t v a l u e e a i e g f 0 e t 2 e s e t 1 e x 1 e t 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 0 sfr address: (bit addressable) 0xa8 r / w e x 0 b i t 1 bit7 : ea: en ab le all in terru p t s. thi s bi t gl obal l y enabl e s/ di sabl es al l i n t e rrupt s. it overri des t h e i ndi vi dual i n t e rrupt m a sk settin g s . 0: di sabl e al l i n t e rrupt sources. 1: enable each interrupt according to its individual m a sk setting. b i t 6 : iegf0: general purpose fl ag 0. thi s i s a general purpose fl ag for use under soft ware cont rol . bit5 : et2 : en ab le tim e r 2 in terru p t . th is b it sets th e m a sk in g o f th e tim e r 2 in terru p t . 0: di sabl e al l ti m e r 2 i n t e rrupt s. 1: enabl e i n t e rrupt request s generat e d by t h e tf2 fl ag (t2c on.7) bit4 : es: en ab le serial po rt (uart) in terru p t . th is b it sets th e m a sk in g o f th e serial po rt (uart) in terru p t . 0 : disab l e all uart in terru p t s. 1: enabl e i n t e rrupt request s generat e d by t h e r 1 fl ag (sc on.0) or t1 fl ag (sc on.1). bit3 : et1 : en ab le tim e r 1 in terru p t . th is b it sets th e m a sk in g o f th e tim e r 1 in terru p t . 0: di sabl e al l ti m e r 1 i n t e rrupt s. 1: enabl e i n t e rrupt request s generat e d by t h e tf1 fl ag (tc on.7). bit2 : ex1 : en ab le ex tern al in terru p t 1 . th is b it sets th e m a sk in g o f ex tern al in terru p t 1 . 0: di sabl e ext e rnal i n t e rrupt 1. 1: enabl e i n t e rrupt request s generat e d by t h e / i nt1 pi n. bit1 : et0 : en ab le tim e r 0 in terru p t . th is b it sets th e m a sk in g o f th e tim e r 0 in terru p t . 0: di sabl e al l ti m e r 0 i n t e rrupt s. 1: enabl e i n t e rrupt request s generat e d by t h e tf0 fl ag (tc on.5). bit0 : ex0 : en ab le ex tern al in terru p t 0 . th is b it sets th e m a sk in g o f ex tern al in terru p t 0 . 0: di sabl e ext e rnal i n t e rrupt 0. 1: enabl e i n t e rrupt request s generat e d by t h e / i nt0 pi n. 79 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.10. ip: interrupt priority r/w r / w p x 1 bit7 bit6 bit5 bit4 bi t s 7-6: unused. read = 11b, w r i t e = don?t care. bit5 : pt2 tim e r 2 in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e tim e r 2 in terru p t s. 0 : tim e r 2 in terru p t s set to lo w p r io rity lev e l. 1 : tim e r 2 in terru p t s set to h i g h p r io rity lev e l. bit4: ps: serial port (uart) in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e serial po rt (uart) in terru p t s. 0 : uart in terru p t s set to lo w p r io rity lev e l. 1 : uart in terru p t s set to h i g h p r io rity lev e l. bit3 : pt1 : tim e r 1 in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e tim e r 1 in terru p t s. 0 : tim e r 1 in terru p t s set to lo w p r io rity lev e l. 1 : tim e r 1 in terru p t s set to h i g h p r io rity lev e l. bit2 : px1 : ex tern al in terru p t 1 prio rity co n t ro l. th is b it sets th e p r io rity o f th e ex tern al in terru p t 1 in terru p t s. 0 : ex tern al in terru p t 1 set to lo w p r io rity lev e l. 1 : ex tern al in terru p t 1 set to h i g h p r io rity lev e l. bit1 : pt0 : tim e r 0 in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e tim e r 0 in terru p t s. 0 : tim e r 0 in terru p t set to lo w p r io rity lev e l. 1 : tim e r 0 in terru p t set to h i g h p r io rity lev e l. bit0 : px0 : ex tern al in terru p t 0 prio rity co n t ro l. th is b it sets th e p r io rity o f th e ex tern al in terru p t 0 in terru p t s. 0 : ex tern al in terru p t 0 set to lo w p r io rity lev e l. 1 : ex tern al in terru p t 0 set to h i g h p r io rity lev e l. r / w r/w r / w r / w r/w r / w r e s e t v a l u e - - p t 2 p s p t 1 p t 0 p x 0 0 0 0 0 0 0 0 0 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: (bit addressable) 0xb8 r e v. 1.7 80
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.11. eie1: extended interrupt enable 1 r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e e c p 1 r e c p 1 f e c p 0 r e c p 0 f e p c a 0 e w a d c 0 e s m b 0 e s p i 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 0 sfr address: b i t 1 0 x e b i t 7 : ec p1r : enabl e c o m p arat or 1 (c p1) r i si ng edge int e rrupt . th is b it sets th e m a sk in g o f th e cp1 in terru p t . 0: di sabl e c p 1 r i si ng edge i n t e rrupt . 1: enabl e i n t e rrupt request s generat e d by t h e c p 1r if fl ag (c pt1c n.5). b i t 6 : ec p1f: enabl e c o m p arat or 1 (c p1) fal l i ng edge int e rrupt . th is b it sets th e m a sk in g o f th e cp1 in terru p t . 0: di sabl e c p 1 fal l i ng edge i n t e rrupt . 1: enabl e i n t e rrupt request s generat e d by t h e c p 1fif fl ag (c pt1c n.4). b i t 5 : ec p0r : enabl e c o m p arat or 0 (c p0) r i si ng edge int e rrupt . th is b it sets th e m a sk in g o f th e cp0 in terru p t . 0: di sabl e c p 0 r i si ng edge i n t e rrupt . 1: enabl e i n t e rrupt request s generat e d by t h e c p 0r if fl ag (c pt0c n.5). b i t 4 : ec p0f: enabl e c o m p arat or 0 (c p0) fal l i ng edge int e rrupt . th is b it sets th e m a sk in g o f th e cp0 in terru p t . 0: di sabl e c p 0 fal l i ng edge i n t e rrupt . 1: enabl e i n t e rrupt request s generat e d by t h e c p 0fif fl ag (c pt0c n.4). b i t 3 : epc a 0: enabl e program m a bl e c ount er array (pc a 0) int e rrupt . th is b it sets th e m a sk in g o f th e pca0 in terru p t s. 0 : disab l e all pca0 in terru p t s. 1: enabl e i n t e rrupt request s generat e d by pc a0. b i t 2 : ew adc 0: enabl e w i ndow c o m p ari s on adc 0 int e rrupt . thi s bi t set s t h e m a ski ng of adc 0 w i ndow c o m p ari s on i n t e rrupt . 0: di sabl e adc 0 w i ndow c o m p ari s on int e rrupt . 1: enabl e int e rrupt request s generat e d by adc 0 w i ndow c o m p ari s ons. bit1 : esmb0 : en ab le smbu s 0 in terru p t . th is b it sets th e m a sk in g o f th e smbu s in terru p t . 0 : disab l e all smbu s in terru p t s. 1: enabl e i n t e rrupt request s generat e d by t h e si fl ag (sm b 0c n.3). bit0: espi0: enable serial pe ripheral interface 0 interrupt. th is b it sets th e m a sk in g o f spi0 in terru p t . 0: di sabl e al l spi0 i n t e rrupt s. 1: enabl e int e rrupt request s generat e d by spi0. 6 81 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.12. eie2: extended interrupt enable 2 r/w r / w r/w r / w r / w r/w r / w r / w e x v l d - e x 7 e x 6 e x 5 e x 4 e a d c 0 e t 3 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 reset value sfr address: 0 x e bit7 : exvld: en ab le ex tern al clo c k so u r ce valid (xtlvld) in terru p t . th is b it sets th e m a sk in g o f th e xtlvld in terru p t . 0 : disab l e all xtlvld in terru p t s. 1: enabl e i n t e rrupt request s generat e d by t h e xtlvld fl ag (osc xc n.7) bit6 : reserv ed . mu st w r ite 0 . read s 0 . bit5 : ex7 : en ab le ex tern al in terru p t 7 . th is b it sets th e m a sk in g o f ex tern al in terru p t 7 . 0: di sabl e ext e rnal int e rrupt 7. 1: enabl e i n t e rrupt request s generat e d by t h e ext e rnal int e rrupt 7 i nput pi n. bit4 : ex6 : en ab le ex tern al in terru p t 6 . th is b it sets th e m a sk in g o f ex tern al in terru p t 6 . 0: di sabl e ext e rnal int e rrupt 6. 1: enabl e i n t e rrupt request s generat e d by t h e ext e rnal int e rrupt 6 i nput pi n. bit3 : ex5 : en ab le ex tern al in terru p t 5 . th is b it sets th e m a sk in g o f ex tern al in terru p t 5 . 0: di sabl e ext e rnal int e rrupt 5. 1: enabl e i n t e rrupt request s generat e d by t h e ext e rnal int e rrupt 5 i nput pi n. bit2 : ex4 : en ab le ex tern al in terru p t 4 . th is b it sets th e m a sk in g o f ex tern al in terru p t 4 . 0: di sabl e ext e rnal int e rrupt 4. 1: enabl e i n t e rrupt request s generat e d by t h e ext e rnal int e rrupt 4 i nput pi n. b i t 1 : eadc 0: enabl e adc 0 end of c onversi on int e rrupt . thi s bi t set s t h e m a ski ng of t h e adc 0 end of c onversi on int e rrupt . 0: di sabl e adc 0 c onversi on int e rrupt . 1: enabl e i n t e rrupt request s generat e d by t h e adc 0 c onversi on int e rrupt . bit0 : et3 : en ab le tim e r 3 in terru p t . th is b it sets th e m a sk in g o f th e tim e r 3 in terru p t . 0: di sabl e al l ti m e r 3 i n t e rrupt s. 1: enabl e i n t e rrupt request s generat e d by t h e tf3 fl ag (tm r 3c n.7) 7 r e v. 1.7 82
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.13. eip1: extended interrupt priority 1 r / w r / w r/w r/w pcp1r pcp1f pcp0r pcp0f p s p i 0 0 x f bit7 : pcp1 r: co m p arato r 1 (cp1 ) risin g in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e cp1 in terru p t . 0 : cp1 risin g in terru p t set to lo w p r io rity lev e l. 1: c p 1 ri si ng i n t e rrupt set t o hi gh pri o ri t y l e vel . bit6 : pcp1 f: co m p arato r 1 (cp1 ) fallin g in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e cp1 in terru p t . 0 : cp1 fallin g in terru p t set to lo w p r io rity lev e l. 1 : cp1 fallin g in terru p t set to h i g h p r io rity lev e l. bit5 : pcp0 r: co m p arato r 0 (cp0 ) risin g in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e cp0 in terru p t . 0 : cp0 risin g in terru p t set to lo w p r io rity lev e l. 1: c p 0 ri si ng i n t e rrupt set t o hi gh pri o ri t y l e vel . bit4 : pcp0 f: co m p arato r 0 (cp0 ) fallin g in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e cp0 in terru p t . 0 : cp0 fallin g in terru p t set to lo w p r io rity lev e l. 1 : cp0 fallin g in terru p t set to h i g h p r io rity lev e l. b i t 3 : ppc a0: program m a bl e c ount er array (pc a 0) int e rrupt pri o ri t y c ont rol . th is b it sets th e p r io rity o f th e pca0 in terru p t . 0 : pca0 in terru p t set to lo w p r io rity lev e l. 1 : pca0 in terru p t set to h i g h p r io rity lev e l. b i t 2 : pw adc 0: adc 0 w i ndow c o m p arat or int e rrupt pri o ri t y c ont rol . thi s bi t set s t h e pri o ri t y of t h e adc 0 w i ndow i n t e rrupt . 0: adc 0 w i ndow i n t e rrupt set t o l o w pri o ri t y l e vel . 1: adc 0 w i ndow i n t e rrupt set t o hi gh pri o ri t y l e vel . bit1 : psmb0 : smbu s 0 in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e smbu s in terru p t . 0 : smbu s in terru p t set to lo w p r io rity lev e l. 1 : smbu s in terru p t set to h i g h p r io rity lev e l. bit0: pspi0: serial peripheral interface 0 interrupt priority control. th is b it sets th e p r io rity o f th e spi0 in terru p t . 0 : spi0 in terru p t set to lo w p r io rity lev e l. 1 : spi0 in terru p t set to h i g h p r io rity lev e l. r/w r/w r / w r / w r e s e t v a l u e p p c a 0 p w a d c 0 p s m b 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 6 83 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 10.14. eip2: extended interrupt priority 2 px7 px6 px5 p t 3 bit7 : pxvld: ex tern al clo c k so u r ce valid (xtlvld) in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e xtlvld in terru p t . 0 : xtlvld in terru p t set to lo w p r io rity lev e l. 1 : xtlvld in terru p t set to h i g h p r io rity lev e l. bit6 : reserv ed : mu st write 0 . read s 0 . bit5 : px7 : ex tern al in terru p t 7 prio rity co n t ro l. th is b it sets th e p r io rity o f th e ex tern al in terru p t 7 . 0 : ex tern al in terru p t 7 set to lo w p r io rity lev e l. 1 : ex tern al in terru p t 7 set to h i g h p r io rity lev e l. bit4 : px6 : ex tern al in terru p t 6 prio rity co n t ro l. th is b it sets th e p r io rity o f th e ex tern al in terru p t 6 . 0 : ex tern al in terru p t 6 set to lo w p r io rity lev e l. 1 : ex tern al in terru p t 6 set to h i g h p r io rity lev e l. bit3 : px5 : ex tern al in terru p t 5 prio rity co n t ro l. th is b it sets th e p r io rity o f th e ex tern al in terru p t 5 . 0 : ex tern al in terru p t 5 set to lo w p r io rity lev e l. 1 : ex tern al in terru p t 5 set to h i g h p r io rity lev e l. bit2 : px4 : ex tern al in terru p t 4 prio rity co n t ro l. th is b it sets th e p r io rity o f th e ex tern al in terru p t 4 . 0 : ex tern al in terru p t 4 set to lo w p r io rity lev e l. 1 : ex tern al in terru p t 4 set to h i g h p r io rity lev e l. b i t 1 : padc 0: adc end of c onversi on int e rrupt pri o ri t y c ont rol . thi s bi t set s t h e pri o ri t y of t h e adc 0 end of c onversi on int e rrupt . 0: adc 0 end of c onversi on i n t e rrupt set t o l o w pri o ri t y l e vel . 1: adc 0 end of c onversi on i n t e rrupt set t o hi gh pri o ri t y l e vel . bit0 : pt3 : tim e r 3 in terru p t prio rity co n t ro l. th is b it sets th e p r io rity o f th e tim e r 3 in terru p t s. 0 : tim e r 3 in terru p t set to lo w p r io rity lev e l. 1 : tim e r 3 in terru p t set to h i g h p r io rity lev e l. r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e p x v l d - p x 4 p a d c 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x f 7 r e v. 1.7 84
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 10.5. pow er management modes the c i p-51 core has t w o soft ware program m a bl e power m a na gem e nt m odes: idl e and st op. idl e m ode hal t s t h e cpu wh ile leav in g th e ex tern al p e rip h e rals an d in tern al clo c k s activ e. in sto p m o d e , th e cpu is h a lted , all i n t e rrupt s and t i m ers (except t h e m i ssi ng c l ock det ect or) are i n act i v e, and t h e sy st em cl ock i s st opped. si nce cl ocks are runni ng i n idl e m ode, power consum pt i on i s dependent upon t h e sy st em cl ock frequency and t h e num ber of peri pheral s l e ft i n act i v e m ode before ent e ri ng id l e . st op m ode consum es t h e l east power. fi gure 1 . descri bes t h e power c ont rol r e gi st er (pc on) used t o cont rol t h e c i p-51?s power m a nagem e nt m odes. 0 1 5 although the cip-51 has idle and stop m odes built in (as w ith any standard 8051 architecture), power m a nagem e nt of the entire mcu is better accom p lished by enabling/disa bling individual pe ripherals as needed. each analog peri pheral can be di sabl ed when not i n use and put i n t o l o w power m ode. di gi t a l peri pheral s , such as t i m ers or serial b u s es, d r aw little p o w er wh en ev er th ey are n o t in u s e. tu rn in g o ff th e o s cillato r sav e s ev en m o re p o w er, b u t requires a reset to restart the m c u. 10.5.1. idle mode set t i ng t h e idl e m ode sel ect bi t (pc on.0) causes t h e c i p-51 t o hal t t h e c p u and ent e r idl e m ode as soon as t h e in stru ctio n th at sets th e b it co m p letes. all in tern al reg i sters an d m e m o ry m a in tain th eir o r ig in al d a ta. all an alo g and di gi t a l peri pheral s can rem a i n act i v e duri ng idl e m ode. id le m o d e is term in ated wh en an en ab led in terru p t o r /rst is asserted . th e assertio n o f an en ab led in terru p t will cau se th e id le mo d e selectio n b it (pcon.0 ) to b e cleared an d th e cpu will resu m e o p e ratio n . th e p e n d i n g in terru p t will b e serv iced an d th e n e x t in stru ctio n to b e ex ecu ted after th e retu rn fro m in terru p t (reti) will b e th e in stru ctio n im m e d i ately fo llo win g th e o n e th at set th e id le mo d e select b it. if id le m o d e is term in ated b y an in tern al or ext e rnal reset , t h e c i p-51 perform s a norm a l reset sequence and begi ns program execut i on at address 0x0000. no te: if th e in stru ctio n fo llo win g th e write o f th e idle b it is a sin g l e-b y te in stru ctio n an d an in terru p t o ccu rs d u r in g th e ex ecu tio n p h a se o f th e in stru ctio n th at sets th e idle b it, th e cpu m a y n o t wak e fro m id le m o d e wh en a fu tu re i n t e rrupt occurs. any i n st ruct i ons t h at set t h e idle bi t s houl d be fol l o wed by an i n st ruct i on t h at has 2 or m o re op- code by t e s, for exam pl e: // in ?c?: pc on | = 0x01; / / set idle bi t pcon = pcon; // ... followed by a 3-cycle dum m y instruction ; in assem b ly: or l pc on, #01h ; set idle bi t mov pcon, pcon ; ... followed by a 3-cycle dum m y instruction if enabled, the w d t will eventu ally cause an internal watchdog reset and thereby term inate the idle m ode. this feature protects the system from an uni nt ended perm anent shut down i n t h e event of an i n advert ent wri t e t o t h e pc on regi st er. if t h i s behavi or i s not desi red, t h e w d t m a y be di sabl ed by soft ware pri o r t o ent e ri ng t h e idl e m ode if the w d t was initially configur ed to allow this operation. this provides the opportunity for additional p o w er sav i n g s , allo win g th e system to rem a in in th e id le m o d e in d e fin itely, waitin g fo r an ex tern al stim u l u s to wak e up t h e sy st em . r e fer t o sect i on 13.8 w a t c hdog ti m e r for m o re i n form at i on on t h e use and confi gurat i on of t h e wd t . 10.5.2. stop mode set t i ng t h e st op m ode sel ect bi t (pc on.1) causes t h e c i p-51 t o ent e r st op m ode as soon as t h e i n st ruct i on t h at set s the bit com p letes. in stop m ode, the cpu and oscilla tors are stopped, effectively shutting down all digital peri pheral s . each anal og peri pheral m u st be shut down i ndi vi dual l y pri o r t o ent e ri ng st op m ode. st op m ode can onl y be t e rm i n at ed by an i n t e rnal or ext e rnal reset . on reset , t h e c i p-51 perform s t h e norm a l reset sequence and begi ns program execut i on at address 0x0000. 85 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 if en ab led , th e missin g clo c k detecto r will cau se an in tern al reset an d th ereb y term in ate th e sto p m o d e . th e m i ssi ng c l ock det ect or shoul d be di sabl ed i f t h e c p u i s t o be put t o sl eep for l onger t h an t h e m c d t i m eout of 100 p sec. figure 10.15. pcon: pow er control register r/w r / w r/w r / w r / w r/w r / w r e s e t v a l u e s m o d g f 4 g f 3 g f 2 g f 1 g f 0 s t o p i d l e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 8 7 r / w b i t 7 : sm od: seri al port b a ud r a t e doubl er enabl e . 0: seri al port baud rat e i s t h at defi ned by seri al port m ode i n sc on. 1: seri al port baud rat e i s doubl e t h at defi ned by seri al port m ode i n sc on. b i t s 6-2: gf4-gf0: general purpose fl ags 4-0. these are general purpose fl ags for use under soft ware cont rol . bit1 : stop: sto p mo d e select. setting this bit will place the cip-51 in stop m ode . this bit will always be read as 0. 1 : go es in to p o w er d o w n m o d e . (tu r n s o ff in tern al o s cillato r). bit0 : idle: id le mo d e select. setting this bit will place the cip- 51 in idle m ode. this bit will always be read as 0. 1: goes i n t o i d l e m ode. (shut s off cl ock t o c p u, but cl ock t o ti m e rs, int e rrupt s, seri al po rts, an d an alo g perip h e rals are still activ e.) r e v. 1.7 86
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 11. flash memory these devi ces i n cl ude 32k + 128 by t e s of on-chi p , repr ogram m a bl e fl ash m e m o ry for program code and non- volatile data storage. the flash m e m o ry can be progra m m e d in-system , a single byte at a tim e, through the jtag interface or by software using the movx in struction. once cleared to 0, a flash bit m u st be erased to set it back to 1. the by t e s woul d t y pi cal l y be erased (set t o 0xff) before bei ng reprogram m e d. the write and erase operations are au to m a tically tim ed b y h a rd ware fo r p r o p e r ex ecu tio n . data p o llin g to d e term in e th e en d o f th e write/erase operat i on i s not requi red. the fl ash m e m o ry i s desi gned t o wi t h st and at l east 20,000 wri t e / e rase cy cl es. r e fer t o table 11.1 for the electrical char acteristics of the flash m e m o ry. 11.1. programming the flash memory the sim p lest m eans of program m i ng the flash m e m o ry is through the jtag interface using program m i ng tools provided by silicon labs or a third pa rty vendor. this is the only m eans for program m i ng a non-initialized device. for det a i l s on t h e jtag com m a nds t o program fl ash m e m o ry , see sect i on 21.2. the flash m e m o ry can be program m e d by software using the m ovx instruction with the address and data by te to be program m e d provided as norm a l ope rands. before writing to flash m e m o ry using m ovx, flash write operat i ons m u st be enabl e d by set t i ng t h e psw e program st ore w r i t e enabl e bi t (psc tl.0) t o l ogi c 1. w r i t i ng t o flash rem a in s en ab led u n til th e psw e b it is cleared b y so ftware. w r i t e s t o fl ash m e m o ry can cl ear bi t s but cannot set t h em . onl y an erase operat i on can set bi t s i n fl ash. therefore, the byte location to be program m e d m u st be erased befo re a new value can be written. the 32kbyte flash m e m o ry is organized in 512-byte sectors. the erase operation applie s to an entire sector (setting all bytes in the sector to 0xff). setting the psee program store erase enabl e bi t (psc tl.1) and psw e (psc tl.0) bi t t o l ogi c 1 and t h en using the movx com m a nd to write a data byte to any byte location within the sector will erase an entire 512-byte sector. the data byte written can be of any value because it is not actually written to the flash. flash erasure rem a in s en ab led u n til th e psee b it is cleared b y so ftware. th e fo llo win g seq u e n ce illu strates th e alg o r ith m fo r program m i ng t h e fl ash m e m o ry by soft ware: 1 . en ab le flash mem o ry write/erase in flscl reg i ster u s in g flascl b its. 2. set psee (psctl.1) to enable flash sector erase. 3. set psw e (psctl.0) to enable flash writes. 4. use m ovx t o wri t e a dat a by t e t o any l o cat i on wi t h i n t h e 512-by t e sect or t o be erased. 5. clear psee to disable flash sector erase. 6. use movx to write a data byte to the desired byte location within the erased 512- byte sector. repeat until fin i sh ed . (an y n u m b e r o f b y tes can b e written fro m a sin g l e b y te to an d en tire secto r .) 7 . clear th e psw e b it to d i sab l e flash writes. w r ite/erase tim in g is au to m a tically co n t ro lled b y h a rd ware b a sed o n th e p r escaler v a lu e h e ld in th e flash mem o ry tim i ng prescaler register (flscl). the 4-bit prescaler va lu e flascl d e term in es th e tim e in terv al fo r write/erase operat i ons. the flasc l val u e requi red for a gi ven sy st em cl ock i s shown i n fi gure 11.4, al ong wi t h t h e form ul a used t o deri ve t h e flasc l val u es. w h en flasc l i s se t t o 1111b, t h e wri t e / e rase operat i ons are di sabl ed. not e t h at code execut i on i n t h e 8051 i s st al l e d whi l e t h e fl ash i s bei ng program m e d or erased. table 11.1. flash memory electrical characteristics vdd = 2.7 to 3.6v, -40 q c to +8 5 q c unless otherwise specified. p a r a m e t e r c o n d i t i o n s m i n t y p max u n i t s e n d u r a n c e 2 0 k 1 0 0 k erase/ w r erase cycle tim e 10 m s w r ite cycle tim e 40 p s 87 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 11.2. non-volatile data storage the flash m e m o ry can be used for non-vol atile data storage as well as program code. this allows data such as calibration coefficients to be calculate d and stored at run tim e. data is written using the movx instruction and read usi ng t h e m ovc i n st ruct i on. the m c u i n corporat es an addi t i onal 128-by t e sect or of fl ash m e m o ry l o cat ed at 0x8000 ? 0x807f. thi s sect or can be used for program code or dat a st orage. however, i t s sm aller secto r size m a k e s it p a rticu l arly well su ited as general purpose, non-volatile scratchpad m e m o ry. even though flash m e m o ry can be written a single byte at a tim e, an en tire secto r m u st b e erased first. in o r d e r to ch an g e a sin g l e b y te o f a m u lti-b y te d a ta set, th e d a ta m u st b e m oved t o t e m porary st orage. next , t h e sect or i s erased, t h e dat a set updat e d and t h e dat a set ret u rned t o t h e ori g i n al sector. the 128-byte sector-size facilitates updating data without wasting program m e m o ry space by allowing the use of i n t e rnal dat a r a m for t e m porary st orage. (a norm a l 512-by t e sect or i s t oo l a rge t o be st ored i n t h e 256-by t e in tern al d a ta m e m o ry.) 11.3. security options the c i p-51 provi des securi t y opt i ons t o prot ect t h e fl ash m e m o ry from i n advert ent m odi fi cat i on by soft ware as wel l as prevent t h e vi ewi ng of propri e t a ry program code and const a nt s. the program st ore w r i t e enabl e (psctl.0) and the program store erase enable (psctl. 1) bits protect the flas h m e m o ry from accidental m o d i ficatio n b y so ftware. th ese b its m u st b e ex p licitly set to lo g i c 1 b e fo re so ftware can m o d i fy th e flash m e m o ry. addi t i onal securi t y feat ures prevent propri e t a ry program c ode and dat a const a nt s from bei ng read or al t e red across the jtag interface or by software running on the system controller. a set of securi t y l o ck by t e s st ored at 0x7dfe and 0x7dff prot ect t h e fl ash program m e m o ry from bei ng read or altered across the jtag interface. each bit in a security lock-b yte protects one 4kbyte bloc k of m e m o ry. clearing a bi t t o l ogi c 0 i n a r ead l o ck by t e prevent s t h e correspondi ng bl ock of fl ash m e m o ry from bei ng read across t h e jtag interface. clearing a bit in the w r ite/erase lock byte protects the bloc k from jtag erasures and/or writes. the r ead l o ck by t e i s at l o cat i on 0x7dff. the w r i t e / e rase l o ck by t e i s l o cat ed at 0x7dfe. fi gure 11.2 shows t h e location and bit definitions of the secu rity bytes. the 512-byte sector cont aining the lock bytes can be written to, but not erased by soft ware. w r i t i ng t o t h e reserved area shoul d not be perform ed. figure 11.1. psctl: program store rw control bi t s 7-2: unused. read = 000000b, w r i t e = don?t care. bit1: psee: program store erase enable. set t i ng t h i s bi t al l o ws an ent i r e page of t h e fl ash program m e m o ry t o be erased provi ded the psw e bit is also set. after setting this bit, a write to flash m e m o ry using the m ovx instruction will erase the entir e page that contains the lo cation addressed by the movx in stru ctio n . th e v a lu e o f th e d a ta b y te written d o e s n o t m a tter. 0: fl ash program m e m o ry erasure di sabl ed. 1: flash program m e m o ry erasure enabled. bit0 : psw e: pro g r am sto r e w r ite en ab le. settin g th is b it allo ws writin g a b y te o f d a ta to th e flash p r o g r am m e m o ry u s in g th e movx instruction. the location m u st be erased before writing data. 0: w r i t e t o fl ash program m e m o ry di sabl ed. 1: w r i t e t o fl ash program m e m o ry enabl e d. r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e - - - - - - p s e e p s w e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 8 f r e v. 1.7 88
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 11.2. flash program memory security bytes 0x 7e 0 0 0x 807 f 0x 800 0 0x 7d fe p r o g r a m m e mo r y sp ac e 0x 000 0 0x 7 d f f re ad l o ck by te w r it e/ er a s e lo c k b y t e so ft w a r e r e a d l i m i t res e r v ed bi t me m o ry b l o c k 7 6 5 4 0x 6 000 - 0 x 6f f f 0 x 70 00 - 0 x 7dfd 0x 5 000 - 0 x 5f f f 0x 4 000 - 0 x 4f f f 3 2 1 0 0x 2 000 - 0 x 2f f f 0x 3 000 - 0 x 3f f f 0x 1 000 - 0 x 1f f f 0x 0 000 - 0 x 0f f f 0x 7fff re ad an d w r it e / e r as e s e c u r i t y bits . ( b it 7 is msb.) (thi s b l o c k l o c k ed on l y i f al l ot he r b l oc k s are loc k e d ) 0x 7d fd flash read lock byte b i t s 7-0: each bi t l o cks a correspondi ng bl ock of m e m o ry . (b i t 7 i s m s b . ) 0: read operations are locked (disabled) for corresponding block across the jtag interface. 1: read operations are unloc ked (enabled) for co rresponding block across the jtag interface. flash write/erase lock byte b i t s 7-0: each bi t l o cks a correspondi ng bl ock of m e m o ry . 0: w r ite/erase operations are locked (disable d) for corresponding block across the jtag interface. 1: w r ite/erase operations are unlocked (enabled) for corresponding block across the jtag interface. flash access limit register (flacl) the cont ent of t h i s regi st er i s used as t h e hi gh by t e of t h e 16-bi t soft ware read l i m i t address. the 16- bit read lim it address value is calculated as 0xnn 00 where nn is replaced by the contents of this regi st er. soft ware runni ng at or above t h i s a ddress i s prohi bi t e d from usi ng t h e m ovx or m ovc in stru ctio n s to read , write, o r erase, lo catio n s b e lo w th is ad d r ess. an y attem p ts to read lo catio n s below this lim it will re turn the value 0x00. the lock bits can always be read a nd cl eared t o l ogi c 0 regardl e ss of t h e securi t y set t i ng appl i e d t o t h e bl ock cont ai ni ng t h e securi t y by t e s. thi s al l o ws addi t i onal bl oc ks t o be prot ect ed aft e r t h e bl ock cont ai ni ng t h e securi t y by t e s has been l o cked. however, t h e onl y m eans of rem ovi ng a lock once set is to eras e the entire program m e m o ry space by perform ing a jtag eras e operation (i.e. cannot be done in user firm ware). note: addressing either security by te while perfo rming a j t ag era se o p era tio n will a u to ma tica lly initia te era sure o f the entire program memory space (except for the reserved area). this erasure can only be performed via jtag. if a non-securi ty byte i n the 0x7c00-0x7dff page i s addressed duri n g erasure, onl y that page (i ncl udi ng the security by tes) will be era sed. the fl ash access li m i t securi t y feat ure (see fi gure 11.3) prot ect s propri e t a ry program code and dat a from bei ng read by soft ware runni ng on t h e c 8051f005/ 06/ 07/ 15/ 16/ 17 m c us. thi s feat ure provi des support for oem s t h at wi sh t o program t h e m c u wi t h propri e t a ry val u e-added fi rm ware before dist ri but i on. the val u e-added fi rm ware can be protected while allowing add itional code to be program m e d in re m a ining program m e m o ry space later. 89 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 th e so ftware read lim it (srl) is a 1 6 - b it ad d r ess th at estab lish e s two lo g i cal p a rtitio n s in th e p r o g r am m e m o ry space. the first is an upper partition consisting of all the program m e m o ry locations at or above the srl address, and the second is a lower partition consisting of all th e program m e m o ry locations starting at 0x0000 up to (but excluding) the srl address. software in the upper partition can execute c ode in the lower partition, but is p r o h i b ited fro m read in g lo catio n s in th e lo wer p a rtitio n u s in g th e movc in stru ctio n . (ex ecu tin g a movc instruction from the upper partition with a source address in the lower partition will always return a data value of 0x00.) software running in the lower partition can access locations in both the upper and lower partition without restriction. the value-added firm ware shoul d be placed in the lower partition. on re set, control is passed to the value-added firm ware v i a th e reset v ecto r . on ce th e v a lu e-ad d e d firm ware co m p letes its in itial ex ecu tio n , it b r an ch es to a predeterm i ned location in the upper partition. if entry poi nts are published, software running in the upper partition m a y execute program code in the lower partition, but it cannot read the contents of the lower partition. param e ters m a y be passed to the program code running in the lower partition either through the ty pical m e thod of placing them on the stack or in registers before the call or by placing them in prescribed m e m o ry locations in the upper partition. the srl address is specified using the contents of the fl ash access register. the 16-bit srl address is calculated as 0xnn00, where nn i s t h e cont ent s of t h e sr l securi t y r e gi st er. thus, t h e sr l can be l o cat ed on 256-by t e boundaries anywhere in program m e m o ry space. however, th e 512-byte erase sector size essentially requires that a 512 boundary be used. the contents of a non-initialized srl security byte is 0x00, thereby setting the srl address to 0x0000 and allowing read access to all locations in program m e m o ry space by default. figure 11.3. flacl: flash access limit (c8051f005/06/07/15/16/17 only) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b 7 b i t s 7-0: flac l: fl ash access li m i t . thi s regi st er hol ds t h e hi gh by t e of t h e 16-bi t program m e m o ry read/ w ri t e / e rase l i m i t address. the entire 16- b it access lim it address value is calculated as 0xnn00 where nn is replaced by contents of flacl. a write to this register sets the flash access lim it. this register can only be written once after any reset. any subsequent writes are ignored until the next reset. r e v. 1.7 90
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 11.4. flscl: flash memory timing prescaler r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e f o s e f r a e - - f l a s c l 10001111 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b 6 bit7 : fose: flash on e-sh o t tim e r en ab le 0: fl ash one-shot t i m er di sabl ed. 1: flash one-shot tim er enabled bit6 : frae: flash read always en ab le 0: fl ash reads per one-shot t i m er 1: flash always in read m ode bi t s 5-4: unused. read = 00b, w r i t e = don?t care. b i t s 3-0: flasc l : fl ash m e m o ry ti m i ng prescal er. this register specifies the prescaler value for a gi ven sy st em cl ock requi red t o generat e t h e correct t i m i ng for fl ash wri t e / e rase operat i ons. if t h e prescal er i s set t o 1111b, fl ash wri t e / e rase operat i ons are di sabl ed. 0000: sy st em c l ock < 50khz 0001: 50khz d sy st em c l ock < 100khz 0010: 100khz d sy st em c l ock < 200khz 0011: 200khz d sy st em c l ock < 400khz 0100: 400khz d sy st em c l ock < 800khz 0110: 1.6m hz d sy st em c l ock < 3.2m hz 0111: 3.2m hz d sy st em c l ock < 6.4m hz 1000: 6.4m hz d sy st em c l ock < 12.8m hz 1001: 12.8m hz d sy st em c l ock < 25.6m hz 1010: 25.6m hz d sy st em c l ock < 51.2m hz * 1011, 1100, 1101, 1110: r e served val u es 1111: fl ash m e m o ry w r i t e / e rase di sabl ed th e p r escaler v a lu e is th e sm allest v a lu e satisfyin g th e fo llo win g eq u a tio n : flascl > log 2 (sy s t e m c l ock / 50khz) * for t e st purposes. the c 8051f000 fam i l y i s not guarant eed for operat i on over 25m hz. 0101: 800khz d sy st em c l ock < 1.6m hz 91 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 12. external ram (c8051f005/06/07/15/16/17) the c8051f005/06/07/ 15/16/17 mcus include 2048 bytes of ram m a pped into the ex ternal data m e m o ry space. all of these address locations m a y be accessed using the external m ove instruction (movx) and the data pointer (dptr), or using m ovx indirect addre ssing m ode. if the m ovx instruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit addre ss is provided by the extern al mem o ry interface control r e gi st er (em i 0c n as shown i n fi gure 12.1). note: the movx instruction is also used for w r ites to the flash memory. see section 11 for details. the movx instru ction accesses x ram by default (i.e. pstcl.0 = 0). for any of t h e addressi ng m odes t h e upper 5-bi t s of t h e 16-b i t ext e rnal dat a m e m o ry address word are ?don?t cares?. as a resul t , t h e 2048-by t e r a m i s m a pped m odul o st y l e over t h e ent i r e 64k ext e rnal dat a m e m o ry address range. for exam pl e, t h e xr am by t e at address 0x0000 i s al so at address 0x0800, 0x1000, 0x1800, 0x2000, et c. thi s i s a useful feature when doing a linear m e m o ry fill, as the addr ess pointer doesn?t have to be reset when reaching the r a m bl ock boundary . figure 12.1. emi0cn: external memory interface control r r r r r r/w r/w r/w r e s e t v a l u e - - - - - p g s e l 2 p g s e l 1 p g s e l 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x a f b i t s 7-3: not used ? reads 00000b b i t s 2-0: pgsel[2: 0] : xr am page sel ect b i t s the xr am page sel ect b i t s provi de t h e hi gh by t e of t h e 16-bi t ext e rnal dat a m e m o ry address when usi ng an 8-bi t m ovx com m a nd, effect i v el y sel ect i ng a 256-by t e page of r a m . the upper 5-bi t s are ?don?t cares?, so t h e 2k address bl ocks are repeat ed m odul o over the entire 64k external data m e m o ry address space. 000: xxxxx000b 001: xxxxx001b 010: xxxxx010b 011: xxxxx011b 100: xxxxx100b 101: xxxxx101b 110: xxxxx110b 111: xxxxx111b r e v. 1.7 92
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 13. reset sources the reset circuitry of the mcus allows the controller to be easily placed in a pr edefined default c ondition. on entry to this reset state, the cip-51 halts program execution, forces the external port pins to a known state and initializes t h e sfr s t o t h ei r defi ned reset val u es. int e rrupt s and t i m ers are di sabl ed. on exi t , t h e program count er (pc ) i s reset , and program execut i on st art s at l o cat i on 0x0000. all o f th e sfrs are reset to p r ed efin ed v a lu es. th e reset v a lu es o f th e sfr b its are d e fin e d in th e sfr d e tailed descri pt i ons. the cont ent s of i n t e rnal dat a m e m o ry are not changed duri ng a reset and any previ ousl y st ored dat a i s preserved. however, si nce t h e st ack poi nt er sfr i s reset , t h e st ack i s effect i v el y l o st even t hough t h e dat a on t h e stack are not altered. th e i/o p o r t latch e s are reset to 0 x ff (all lo g i c o n e s), activ atin g in tern al weak p u ll-u p s wh ich tak e th e ex tern al i/o pins to a high state. the weak pull-ups are enabled during and after the reset. if the source of reset is from the vdd monitor or writing a 1 to porsf, the /rst pin is driven low until the end of the vdd reset tim eout. on exit from the reset state, the mcu uses the internal oscillator running at 2mhz as the system clock by default. r e fer t o sect i on 14 for i n form at i on on sel ect i ng and confi guri ng t h e sy st em cl ock source. the w a t c hdog ti m e r i s enabl e d usi ng i t s l ongest t i m eout i n t e rval . (sect i on 13.8 det a i l s t h e use of t h e w a t c hdog ti m e r.) there are seven sources for putting the m c u into the reset state: power-on/powe r-fail, external /rst pin, external c nvstr si gnal , soft ware com m a nded, c o m p arat or 0, m i ssi ng c l ock det ect or, and w a t c hdog ti m e r. each reset source i s descri bed bel o w: figure 13.1. reset sources diagram wdt cip-51 core missing clock detector (one- shot) wd t strobe (software reset) /rst + - vdd supply reset timeout (wired-or) system reset supply monitor pre reset funnel + - cp0+ comparator 0 cp0- (port i/o) crossbar cnvstr cnvrsef c0rsef en wd t enable en mcd enable swrsf system clock 93 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 1 3 . 1 . 3 p o w er-on r e s e t the c8051f000 fam ily incorporates a power supply m onitor that holds the mcu in the reset state until vdd rises above t h e v rst l e vel duri ng power-up. (see fi gure 13.2 for t i m i ng di agram , and refer t o tabl e 1 . 1 for t h e electrical characteristics of the power s upply m onitor circuit.) the /rst pin is asserted (low) until the end of the 100m s vdd m oni t o r t i m eout i n order t o al l o w t h e vdd suppl y t o becom e st abl e . on exit from a power-on reset, the porsf fl ag (r stsr c . 1) i s set by hardware t o l ogi c 1. al l of t h e ot her reset flags in the rstsrc register are indete rm inate. porsf is cleared by a re set from any other source. since all reset s cause program execut i on t o begi n at t h e sam e l o cat i on (0x0000), soft ware can read t h e por sf fl ag t o det e rm i n e i f a power-up was t h e cause of reset . the cont ent of i n t e rnal dat a m e m o ry shoul d be assum e d t o be undefi ned aft e r a power-on reset . 13.2. softw are forced reset w r i t i ng a 1 t o t h e por sf bi t forces a power-on r e set as descri bed i n sect i on 13.1. figure 13.2. vdd monitor timing diagram 1 3 . 3 . /rst t vol t s 1.0 2.0 logic high logic low 100ms 100ms v d d 2.70 2.40 v rst p o w er-fail r e s e t w h en a power-down transition or power irregularity causes vdd to drop below v rst , t h e power suppl y m oni t o r will drive the /rst pin low and return the cip-51 to the reset state (see figur e 13.2). w h en vdd returns to a level above v rst , th e cip-5 1 will leav e th e reset state in th e sam e m a n n e r as th at fo r th e p o w er-o n reset. no te th at ev en t hough i n t e rnal dat a m e m o ry cont ent s are not al t e red by t h e power-fai l reset , i t i s i m possi bl e t o det e rm i n e i f vdd dropped bel o w t h e l e vel requi red for dat a ret e nt i on. if t h e por sf fl ag i s set , t h e dat a m a y no l onger be val i d . r e v. 1.7 94
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 13.4. external reset the ext e rnal / r st pi n provi des a m eans for external circuitry to force the mcu into a rese t state. asserting an active-low signal on the /rst pin will cau se the mcu to enter the reset state. although there is a weak internal pul l up, i t m a y be desi rabl e t o provi de an ext e rnal pul l - up and/ or decoupl i ng of t h e / r st pi n t o avoi d erroneous n o i se-in d u ced resets. th e mcu will rem a in in reset u n til at least 1 2 clo c k cycles after th e activ e-lo w /rst sig n a l is rem o v e d . th e pinrsf flag (rstsrc.0 ) is set o n ex it fro m an ex tern al reset. th e /rst p i n is also 5 v to leran t . 13.5. missing clock detector reset the m i ssi ng c l ock det ect or i s essent i a l l y a one-shot ci rcui t t h at i s t r i ggered by t h e m c u sy st em cl ock. if t h e system clock goes away for m o re than 100 p s, th e o n e -sh o t will tim e o u t an d g e n e rate a reset. after a missin g clo c k detecto r reset, th e mcdrsf flag (rstsrc.2 ) will b e set, sig n i fyin g th e msd as th e reset so u r ce; o t h e rwise, th is bit reads 0. the state of the /rst pi n is u n a ffected b y th is reset. settin g th e msclke b it in th e oscicn reg i ster (see fi gure 14.2) enabl e s t h e m i ssi ng c l ock det ect or. 13.6. comparator 0 reset com p arator 0 can be configured as an active-low reset input by writing a 1 to the c0rsef flag (rstsrc.5). c o m p arat or 0 shoul d be enabl e d usi ng c p t0c n .7 (see fi gure 8.3) at l east 20 p s p r io r to writin g to c0 rsef to prevent any t u rn-on chat t e r on t h e out put from generat i ng an unwanted reset. w h en configured as a reset, if the non-i nvert i ng i nput vol t a ge (on c p 0+) i s l e ss t h an t h e i nvert i ng i nput vol t a ge (on c p 0-), t h e m c u i s put i n t o t h e reset state. after a co m p arato r 0 reset, th e c0 rsef fl ag (rstsrc.5 ) will read 1 sig n i fyin g co m p arato r 0 as th e reset so u r ce; o t h e rwise, th is b it read s 0 . the state of the /rst pin is unaffected b y th is reset. also , co m p arato r 0 can generat e a reset wi t h or wi t hout t h e sy st em cl ock. 13.7. external cnvstr pin reset the external cnvstr signal can be configured as an ac tive-low reset input by writi ng a 1 to the cnvrsef flag (r stsr c . 6). the c nvstr si gnal can appear on any of t h e p0, p1, or p2 i/ o pi ns as descri bed i n sect i on 15.1. (not e t h at t h e c r ossbar m u st be confi gured for t h e c nvstr si gnal t o be rout ed t o t h e appropri a t e port i/ o.) the c r ossbar shoul d be confi gured and enabl e d before t h e c nvr sef i s set t o confi gure c nvstr as a reset source. w h en co n f ig u r ed as a reset, cnvstr is activ e-lo w an d lev e l sen s itiv e. after a cnvstr reset, th e cnvrsef flag (rstsrc.6 ) will read 1 sig n i fyin g cnvstr as th e reset so u r ce; o t h e rwise, th is b it read s 0 . th e state o f th e /rst pi n i s unaffect ed by t h i s reset . 13.8. watchdog timer reset the mcu includes a program m a ble w a tchdog tim e r (w dt) r unning off the system clock. the w d t will force t h e m c u i n t o t h e reset st at e when t h e wat c hdog t i m er overfl ows. to prevent t h e reset , t h e w d t m u st be rest art e d by appl i cat i on soft ware before t h e overfl ow occurs. if the system experiences a soft ware/ h ardware m a l f unct i on preventing the software from restarting the w d t, the w d t will overflow and cau se a reset. this should prevent t h e sy st em from runni ng out of cont rol . th e w d t is au to m a tically en ab led an d started with th e d e fau lt m a x i m u m tim e in terv al o n ex it fro m all resets. if desired the w d t can be disabled by syst em software or locked on to prevent accidental disabling. once locked, the w d t cannot be disabled until the next sy stem reset. the state of the /rst pin is unaffected by this reset. 95 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 13.8.1. watchdog usage the w d t consi s t s of a 21-bi t t i m er runni ng from t h e program m e d sy st em cl ock. the t i m er m easures t h e peri od between specific writes to its control register. if th is period exceeds the program m e d lim it, a w d t reset is generated. the w d t can be enabled and disabled as needed i n soft ware, or can be perm anent l y enabl e d i f desi red. w a t c hdog feat ures are cont rol l e d vi a t h e w a t c hdog ti m e r c ont rol r e gi st er (w dtc n ) shown i n fi gure 13.3. ena b le/reset wdt the watchdog tim er is both enabled and the countdown rest arted by writing 0xa5 to the w d tcn register. the user?s appl i cat i on soft ware shoul d i n cl ude peri odi c wri t e s of 0xa5 t o w d tc n as needed t o prevent a wat c hdog t i m er overfl ow. the w d t i s enabl e d and rest arted as a result of any system reset. disable wdt w r i t i ng 0xde fol l o wed by 0xad t o t h e w d tc n regi st er di sabl es t h e w d t. the fol l o wi ng code segm ent illu strates d i sab lin g th e w d t. clr ea ; disable all interrupts mov wdtcn,#0deh ; disable software mov wdtcn,#0adh ; watchdog timer setb ea ; re-enable interrupts the writes of 0xde and 0xad m u st occur within 4 clock cycl es of each other, or the di sable operation is ignored. int e rrupt s shoul d be di sabl ed duri ng t h i s procedure t o avoi d del a y bet w een t h e t w o wri t e s. disa ble wdt lo cko u t w r iting 0xff to w d tcn locks out the disable feature. on ce locked out, the disable ope ration is ignored until the next sy st em reset . w r i t i ng 0xff does not enabl e or rese t t h e wat c hdog t i m er. appl i cat i ons al way s i n t e ndi ng t o use the watchdog should write 0xff to w d tcn in their initialization code. setting wdt interval w d tc n.[2: 0 ] cont rol t h e wat c hdog t i m eout i n t e rval . the i n t e rval i s gi ven by t h e fol l o wi ng equat i on: 4 3+w d tcn[ 2:0] x t sy sclk , ( w here t sy sclk is the system clock period) . for a 2m hz sy st em cl ock, t h i s provi des an i n t e rval range of 0.032m sec t o 524m sec. w d tc n.7 m u st be a 0 when set t i ng t h i s i n t e rval . r eadi ng w d tc n ret u rns t h e program m e d i n t e rval . w d tc n.[2: 0 ] i s 111b aft e r a sy st em reset. figure 13.3. wdtcn: watchdog timer control register r/w r / w r/w r / w r/w r / w r / w r e s e t v a l u e x x x x x 1 1 1 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x f f r / w b i t s 7-0: w d t c ont rol w r i t i ng 0xa5 bot h enabl e s and rel o ads t h e w d t. w r i t i ng 0xde fol l o wed wi t h i n 4 cl ocks by 0xad di sabl es t h e w d t. w r i t i ng 0xff l o cks out t h e di sabl e feat ure. b i t 4 : w a t c hdog st at us b i t (when r ead) r eadi ng t h e w d tc n.[4] bi t i ndi cat es t h e w a t c hdog ti m e r st at us. 0 : w d t is in activ e 1 : w d t is activ e b i t s 2-0: w a t c hdog ti m e out int e rval b i t s the w d tcn.[2:0] bits set the w a tchdog tim e out interval. w h en writing these bits, w d tc n.7 m u st be set t o 0. r e v. 1.7 96
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 13.4. rstsrc: reset source register r r / w r/w r/w r r r / w r r e s e t v a l u e j t a g r s t c n v r s e f c 0 r s e f swrsef w d t r s f m c d r s f p o r s f p i n r s f x x x x x x x x b i t 7 b i t 6 b i t 5 b i t 4 b i t 2 b i t 1 b i t 0 sfr address: 0 x e f bit3 (not e: do not use read-m odi fy -wri t e operat i ons on t h i s regi st er.) bit7 : jtagrst. jtag reset flag . 0 : jtag is n o t cu rren tly in reset state. 1 : jtag is in reset state. b i t 6 : c nvr sef: c onvert st art r e set source enabl e and fl ag w r ite 0: c nvstr i s not a reset source 1: cnvstr is a reset source (active low) read 0: source of pri o r reset was not from c nvstr 1: source of pri o r reset was from c nvstr bit5 : c0 rsef: co m p arato r 0 reset en ab le an d flag w r ite 0: c o m p arat or 0 i s not a reset source 1: com p arator 0 is a reset source (active low) read not e : the val u e read from c 0 r s ef i s not defi ned i f c o m p arat or 0 has not been enabl e d as a reset source. 0: source of pri o r reset was not from c o m p arat or 0 1: source of pri o r reset was from c o m p arat or 0 bit4: sw rsf: software reset force and flag w r ite 0: no effect 1: forces an internal rese t . / r st pi n i s not effect ed. read 0 : prio r reset so u r ce was n o t fro m write to th e sw rsf b it. 1 : prio r reset so u r ce was fro m write to th e sw rsf b it. b i t 3 : w d tr sf: w a t c hdog ti m e r r e set fl ag 0: source of pri o r reset was not from w d t t i m eout . 1: source of pri o r reset was from w d t t i m eout . b i t 2 : m c dr sf: m i ssi ng c l ock det ect or fl ag 0: source of pri o r reset was not from m i ssi ng c l ock det ect or t i m eout . 1: source of pri o r reset was from m i ssi ng c l ock det ect or t i m eout . bit1: porsf: power-on reset force and flag w r ite 0: no effect 1 : fo rces a po wer-on reset. /rst is d r iv en lo w. read 0: source of pri o r reset was not from por . 1: source of pri o r reset was from por . bit0: pinrsf: hw pin reset flag 0: source of pri o r reset was not from / r st pi n. 1: source of pri o r reset was from / r st pi n. 97 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 13.1. reset electrical characteristics -40 q c to +8 5 q c unless otherwise specified. p a r a m e t e r c o n d i t i o n s m i n t y p max u n i t s / r s t o u t p u t l o w v o l t a g e i ol = 8.5m a, vdd = 2.7 to 3.6v 0.6 v / r st input hi gh vol t a ge 0.7 x vdd v / r st input low vol t a ge 0.3 x vdd v / r st input leakage c u rrent / r st = 0.0v 20 p a vdd for /rst output valid 1.0 v av+ for /rst output valid 1.0 v vdd por threshold (v rst ) 2 . 4 0 2 . 5 5 2 . 7 0 v r e set ti m e del a y / r st ri si ng edge aft e r crossi ng reset t h reshol d 8 0 1 0 0 1 2 0 m s m i ssi ng c l ock det ect or ti m e out tim e from last system clock to reset generat i on 1 0 0 2 2 0 5 0 0 p s r e v. 1.7 98
99 rev. 1.7 c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 14. oscillator each mcu includes an internal oscillator and an external oscillator drive circuit, either of which can generate the system clock. the mcus boot from the in ternal oscillator after any reset. the internal oscillator starts up instantly. it can be enabled/disabled and its frequency can be changed using the internal oscillator control register (oscicn) as shown in figure 14.2. the internal oscilla tor?s electrical specifications are given in table 14.1. both oscillators are disabled when the /rst pin is held low. the mcus can run from the internal oscillator or external oscillator, and switch between the two at will usi ng the clksl bit in the oscicn register. the external oscillator requires an external resonator, parallel-mode crystal, capacitor, or rc network connected to the xtal1/xtal2 pins (see figure 14.1). the oscillator circuit must be configured for one of these sources in the oscxcn register. an external cmos clock can also provide the system clock via overdriving the xtal1 pin. the xtal1 and xtal2 pins are 3.6v ( not 5v) tolerant. the external osc illator can be left enabled and running even when the mcu has switched to using the internal oscillator. figure 14.1. oscillator diagram osc internal clock generator sysclk input circuit oscxcn en xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 oscicn msclke ifrdy clksl ioscen ifcn1 ifcn0 xtal1 xtal2 opt. 1 opt. 2 opt. 4 opt. 3 xtal1 xtal2 xtal1 xtal1 av+ agnd vdd av+
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 14.2. oscicn: internal oscillator control register r/w r/w r r/w r / w r / w r e s e t v a l u e m s c l k e - - i f r d y c l k s l i f c n 1 i f c n 0 b i t 7 b i t 6 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x b 2 r / w r/w i o s c e n 0 0 0 0 0 1 0 0 bit5 bit4 bit7 : msclke: missin g clo c k en ab le bit 0: m i ssi ng c l ock det ect or di sabl ed 1: m i ssi ng c l ock det ect or enabl e d; t r i ggers a reset i f a m i ssi ng cl ock i s det ect ed bi t s 6-5: unused. read = 00b, w r i t e = don?t care bit4 : ifrdy: in tern al oscillato r freq u e n c y read y flag 0: internal oscillator frequency not r unning at speed specified by the ifcn bits. 1: internal oscillator frequency runni ng at speed specified by the ifcn bits. bit3 : clksl: system clo c k so u r ce select bit 0 : uses in tern al oscillato r as system clo c k . 1 : uses ex tern al oscillato r as system clo c k . bit2 : ioscen: in tern al oscillato r en ab le bit 0 : in tern al oscillato r disab l ed 1 : in tern al oscillato r en ab led bits1 - 0 : ifcn1 - 0 : in tern al oscillato r freq u e n c y co n t ro l bits 0 0 : in tern al oscillato r typ i cal freq u e n c y is 2 m hz. 0 1 : in tern al oscillato r typ i cal freq u e n c y is 4 m hz. 1 0 : in tern al oscillato r typ i cal freq u e n c y is 8 m hz. 1 1 : in tern al oscillato r typ i cal freq u e n c y is 1 6 m hz. p a r a m e t e r table 14.1. internal oscillator electrical characteristics -40 q c to +8 5 q c unless otherwise specified. c o n d i t i o n s m i n t y p max u n i t s in tern al oscillato r frequency osc i c n .[1: 0] = 00 osc i c n .[1: 0] = 01 osc i c n .[1: 0] = 10 8 4.8 19.2 osc i c n .[1: 0] = 11 1.5 3.1 6.2 12.3 2 4 16 2.4 9.6 mh z in tern al oscillato r cu rren t consum ption (from vdd) osc i c n .2 = 1 200 p a in tern al oscillato r tem p eratu r e stab ility 4 ppm / q c in tern al oscillato r po wer supply (vdd) stability 6 . 4 %/ v r e v. 1.7 100
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 14.3. oscxcn: external oscillator control register r r/w r/w r / w r / w r/w r / w r e s e t v a l u e x o s c m d 2 x o s c m d 1 - x f c n 0 0 0 1 1 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 r / w xtlvld xoscmd0 x f c n 2 x f c n 1 sfr address: 0 x b bit7 : xtlvld: crystal oscillato r valid flag (val i d onl y w h en x o scmd = 1xx.) 0: crystal oscillator is unused or not yet stable 1: crystal oscillator is running and stable (should read 1m s after crystal oscillator is enabl e d t o avoi d t r ansi ent condi t i on). bits6 - 4 : xoscmd2 -0 : ex tern al oscillato r mo d e bits 00x: off. xtal1 pi n i s grounded i n t e rnal l y . 010: sy st em c l ock from ext e rnal c m os c l ock on xtal1 pi n. 011: sy st em c l ock from ext e rnal c m os c l ock on xtal1 pi n di vi ded by 2. 10x: rc/c oscillator mode with divide by 2 stage. 110: crystal oscillator mode 111: crystal oscillator mode with divide by 2 stage. b i t 3 : r e ser v ed. r ead = undefi ned, w r i t e = don?t care bits2 - 0 : xfcn2 - 0 : ex tern al oscillato r freq u e n c y co n t ro l bits 000-111: see t a bl e bel o w xfcn cry s tal (xoscm d = 11x) r c (xosc m d = 10x) c (xosc m d = 10x) 000 f d 12.5khz f d 25khz k fact or = 0.44 001 12.5khz < f d 30.3khz 25khz < f d 50khz k fact or = 1.4 010 30.35khz < f d 93.8khz 50khz < f d 100khz k fact or = 4.4 011 93.8khz < f d 267khz 100khz < f d 200khz k fact or = 13 100 267khz < f d 722khz 200khz < f d 400khz k fact or = 38 101 722khz < f d 2.23m hz 400khz < f d 800khz k fact or = 100 110 2.23m hz < f d 6.74m hz 800khz < f d 1.6m hz k fact or = 420 111 f > 6.74m hz 1.6m hz < f d 3.2m hz k fact or = 1400 crystal mode (c i r cui t from fi gure 14.1, opt i on 1; xosc m d = 11x) c hoose xfc n val u e t o m a t c h t h e cry s t a l or ceram i c resonat o r frequency . rc mode (c i r cui t from fi gure 14.1, opt i on 2; xosc m d = 10x) choose oscillation frequency range where: f = 1.23(10 3 ) / (r * c) , where f = freq u e n c y o f o s cillatio n in mhz c = capacitor value in pf r = pul l - up resi st or val u e i n k : c mode (c i r cui t from fi gure 14.1, opt i on 3; xosc m d = 10x) choose k factor (kf) for th e oscillation frequency desired: f = kf / (c * av+) , where f = freq u e n c y o f o s cillatio n in mhz c = capaci t o r val u e on xtal1, xtal2 pi ns i n pf av+ = anal og power suppl y on m c u i n vol t s 1 101 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 14.1. external crystal example if a crystal o r ceram ic reso n a to r were u s ed to g e n e rate th e sy st em cl ock for t h e m c u, t h e ci rcui t woul d be as shown i n fi gure 14.1, opt i on 1. for an ec s-110.5-20-4 cry s t a l , t h e resonat e frequency i s 11.0592m hz, t h e i n t r i n si c capacitance is 7pf, and the esr is 60 : . the com p ensation capacitors should be 33pf each, and the pw b parasitic cap acitan ce is estim ated to b e 2 p f . th e ap p r o p r iate ex tern al oscillato r freq u e n c y co n t ro l v a lu e (xfcn) fro m th e c r y s t a l col u m n i n t h e t a bl e i n fi gure 14.3 (osc xc n r e gi st er) shoul d be 111b. because the oscillator detect circuitry n eeds tim e to settle after the crystal osc illator is enabled, software should wait at least 1 m s b e tween en ab lin g th e crystal o s cillato r a n d p o llin g th e xtlvld b it. th e reco m m e n d p r o ced u r e is: 1 . en ab le th e ex tern al o s cillato r 2 . w a it at least 1 m s 3. poll for xtlvld ' 0 ' ==> ' 1 ' 4 . switch to th e ex tern al o s cillato r switching to the external oscillator befo re the crystal oscillator has stabilized could result in unpredictable behavior. note: crystal oscillator circuits are qu ite sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device, keeping the traces as short as possible and shield ed with ground plane from any other traces which could intr oduce noise or interference. 14.2. external rc example if an ext e rnal r c net w ork were used t o generat e t h e sy st em cl ock for t h e m c u, t h e ci rcui t woul d be as shown i n figure 14.1, option 2. the capacitor m u st be no greater than 100pf, but using a very sm all capacitor will increase th e freq u e n c y d r ift d u e to th e pw b p a rasitic cap acitan ce. to d e term in e th e req u i red ex tern al oscillato r freq u e n c y c ont rol val u e (xfc n) i n t h e osc x c n r e gi st er, fi rst sel ect t h e r c net w ork val u e t o produce t h e desi red frequency of oscillation. if the frequency desired is 100khz, let r = 246k : and c = 50pf: f = 1.23(10 3 )/ r c = 1.23(10 3 ) / [246 * 50] = 0.1m hz = 100khz xfcn t lo g 2 (f/ 2 5 k h z ) xfcn t lo g 2 (100khz/ 25khz) = l o g 2 (4) xfcn t 2, or code 010 14.3. external capacitor example if an external capacitor were used to generat e t h e sy st em cl ock for t h e m c u, t h e ci rcui t woul d be as shown i n figure 14.1, option 3. the capacitor m u st be no greater than 100pf, but using a very sm all capacitor will increase the frequency inaccuracy due to the pw b parasitic capacitance. to determ ine the required external oscillator frequency c ont rol val u e (xfc n) i n t h e osc x c n r e gi st er , select the capacitor to be used and find the frequency of oscillation from the equations below. assum e av+ = 3.0v and c = 50pf: f = kf / (c * vdd) = kf / (50 * 3) f = kf / 150 if a frequency of roughl y 90khz i s desi red, sel ect t h e k fact or from t h e t a bl e i n fi gure 14.3 as kf = 13: f = 13 / 150 = 0.087m hz, or 87khz therefore, t h e xfc n val u e t o use i n t h i s exam pl e i s 011. r e v. 1.7 102
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 15. port input/output the c r ossb ar assi gns t h e sel ect ed i n t e rnal di gi t a l resources t o t h e i/ o pi ns based on t h e pri o ri t y decode tabl e 15.1. the regi st ers xb r 0 , xb r 1 , and xb r 2 , defi ned i n fi gure 15.3, fi gure 15.4, and fi gure 15.5 are used t o sel ect an internal digital function or let an i/o pin default to being a port i/o. the crossbar functions identically for each m c u, wi t h t h e caveat t h at p2 i s not pi nned out on t h e f001/ 06/ 11/ 16, and bot h p1 and p2 are not pi nned out on t h e f002/07/12/17. digital resources assigned to port pins that are not pinned out ca nnot be accessed. 15.1. priority cross bar decoder 15.2. port i/o initializ ation the m c us have a wi de array of di gi t a l resources, whi c h ar e avai l a bl e t h rough four di gi t a l i/ o port s , p0, p1, p2 and p3. each of t h e pi ns on port s 0, 1, and 2 can be defi ned as ei t h er i t s correspondi ng port i/ o or one of t h e i n t e rnal di gi t a l resources assi gned as shown i n fi gure 15.1. th e desi gner has com p l e t e cont rol over whi c h funct i ons are assi gned, l i m i t e d onl y by t h e num ber of phy si cal i/ o pi ns avai l a bl e on t h e sel ect ed package (t he c 8051f000/ 05/ 10/ 15 have al l four port s pi nned out , t h e f001/ 06/ 11/ 16 have p0 and p1, and t h e f002/ 07/ 12/ 17 have p0). this resource assignm ent flexibility is achieved through the use of a priority crossbar decoder. (note t h at t h e st at e of a port i/ o pi n can al way s be read i n t h e correspondi ng port l a t c h regardl e ss of t h e c r ossbar settin g s ). al l port i/ os are 5v t o l e rant (r efer t o fi gure 15.2 for t h e port cell circuit.) the port i/o cells are configured as ei t h er push-pul l or open-drai n i n t h e port c onfi gurat i on r e gi st ers (pr t 0c f, pr t1c f , pr t2c f , pr t3c f ). com p lete electrical specifications for port i/ o are gi ven i n tabl e 15.2. on e o f th e d e sig n g o a ls o f th is mcu fam ily was to m a k e th e en tire p a lette o f d i g ital reso u r ces av ailab l e to th e desi gner even on reduced pi n count packages. the pri o ri t y c r ossb ar decoder provi des an el egant sol u t i on t o t h e probl em of connect i ng t h e i n t e rnal di gi t a l resources t o t h e phy si cal i/ o pi ns. the priority crossbar decode (table 15.1) assigns a priority to each i/o function, starting at the top with the smbu s. as th e tab l e illu strates, wh en selected , its two sig n a ls will b e assig n e d to pin 0 an d 1 o f i/o po rt 0 . th e decoder always fills i/o bits from lsb to msb starting with port 0, then port 1, finishing if necessary with port 2. if you choose not to use a resource, the next function down on the table will fill th e priority slot. in this way it is possi bl e t o choose onl y t h e funct i ons requi red by t h e desi gn, m a ki ng ful l use of t h e avai l a bl e i/ o pi ns. al so, any ext r a port i/ o are grouped t oget h er for m o re conveni ent use i n appl i cat i on code. r e gi st ers xb r 0 , xb r 1 and xb r 2 are used t o assi gn t h e di gi t a l i/ o resources t o t h e phy si cal i/ o port pi ns. it i s i m port a nt t o underst a nd t h at when t h e sm b u s, spi b u s, or uar t i s sel ect ed, t h e crossbar assi gns al l pi ns associ at ed wi t h t h e sel ect ed bus. it woul d be i m possi bl e for i n st ance t o assi gn t h e r x pi n from t h e uar t funct i on without also assigning the tx f unction. standard port i/os appear contiguously after th e prioritized functions have been assi gned. for exam pl e, i f y ou choose funct i ons t h at t a ke t h e fi rst 14 port i/ o (p0.[7: 0 ] , p1.[5: 0] ), y ou woul d have 18 port i/ o l e ft unused by t h e crossbar (p1.[7: 6 ] , p2 and p3). po rt i/o in itializatio n is straig h t fo rward . reg i sters xbr0 , xbr1 an d xbr2 m u st b e lo ad ed with th e ap p r o p r iate v a lu es to select th e d i g ital i/o fu n c tio n s req u i red b y th e d e sig n . settin g th e xbare b it in xbr2 to 1 en ab les th e crossbar. until the crossbar is enabled, the external pins remain as standard ports in input mode regardless of the x b rn register settings. for gi ven xb r n r e gi st er set t i ngs, one can det e rm i n e t h e i/ o pi n-out usi ng t h e prio rity deco d e tab l e; as an altern ativ e, th e co d e co n f ig u r atio n w i zard fu n c tio n o f th e ide so ftware will det e rm i n e t h e port i/ o pi n-assi gnm ent s based on t h e xb r n r e gi st er set t i ngs. the out put dri v er charact eri s t i c s of t h e i/ o pi ns are defi ned usi ng t h e port c onfi gurat i on r e gi st ers pr t0c f , pr t1c f , pr t2c f and pr t3c f (see fi gure 15.7, fi gure 15.9, fi gure 15.12, and fi gure 15.14). each port out put driver can be configured as either open drai n or push-pul l . thi s i s requi red even for t h e di gi t a l resources sel ect ed in th e xbrn reg i sters an d is n o t au to m a tic. th e o n l y ex cep tio n to th is is th e smbu s (sda, scl) an d uart receive (rx, when in m ode 0) pins which are open -drain regardless of the prtncf settings. w h en the w e akpud b it in xbr2 is 0 , a weak p u llu p is en ab led fo r al l port i/ o confi gured as open-drai n. w e akpud does 103 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 not affect t h e push-pul l port i/ o. furt herm ore, t h e weak pul l up i s t u rned off on an open-drai n out put t h at i s dri v i ng a 0 t o avoi d unnecessary power di ssi pat i on. th e th ird an d fin a l step is to in itialize th e in d i v i d u a l reso u r ces selected u s in g th e ap p r o p r iate setu p reg i sters. initialization procedures for the various digital resources m a y be found in the detailed explanation of each available function. the reset state of each re gister is shown in the figures that describe each indi vidual register. figure 15.1. port i/o functional block diagram xbr0, xbr1, xbr2 registers prt3cf register external pins p0 p1 p2 8 8 8 (internal digital s i gnals) port latches p3 p3 i/o cells p3.0 digital crossbar priority decoder p1 i/o cells smbus spi uart pca t0, t1, t2, t2ex, /int0, /int1 /sysclk cnvstr p3.7 p1.0 p1.7 p2 i/o cells p2.0 p2.7 p0 i/o cells p0.0 p0.7 8 highest priority lowest priority highest priority lowest priority 8 8 (p2.0-p2.7) (p1.0-p1.7) (p0.0-p0.7) 8 prt0cf, prt1cf, prt2cf registers (p3.0-p3.7) comptr. outputs 2 4 2 6 2 6 figure 15.2. port i/o cell block diagram dgnd /port-outenable port-output port-input push-pull vdd vdd vdd weakpud port pad (weak) r e v. 1.7 104
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 15.1. crossbar priority decode p i n i / o 0 1 2 3 456 70 123 45 670 12 345 67 sd a sc l sc k mi s o mo s i ns s tx rx ce x 0 ce x 1 ce x 2 ce x 3 ce x 4 ec i cp 0 cp 1 t0 /in t 0 t1 /in t 1 t2 t2 e x /s y s c l k cnv s t r p0 p1 p 2 in the priority decode table, a dot ( x ) is used to show the external port i/ o pin (colum n) to which each signal (row) can be assi gned by t h e user appl i cat i on code vi a program m i ng regi st ers xb r 2 , xb r 1 , and xb r 0 . 105 r e v. 1.7
r e v. 1.7 106 c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 15.3. xbr0: port i/o crossbar register 0 r/w r/w r / w r / w r/w r / w r / w r e s e t v a l u e cp0 o en ecie pca0me u a r t e n s p i 0 o e n b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x e 1 r / w sm b0oen 00000000 b i t 6 bit7 : cp0 o en: co m p arato r 0 ou tp u t en ab le bit 0: c p 0 unavai l a bl e at port pi n. 1: c p 0 rout ed t o port pi n. b i t 6 : ec ie: pc a0 c ount er input enabl e b i t 0: ec i unavai l a bl e at port pi n. 1: ec i rout ed t o port pi n. b i t s 3-5: pc a0m e : pc a m odul e i/ o enabl e b i t s 000: al l pc a i/ o unavai l a bl e at port pi ns. 001: c e x0 rout ed t o port pi n. 010: c e x0, c e x1 rout ed t o 2 port pi ns. 011: c e x0, c e x1, c e x2 rout ed t o 3 port pi ns. 100: c e x0, c e x1, c e x2, c e x3 rout ed t o 4 port pi ns. 101: c e x0, c e x1, c e x2, c e x3, c e x4 rout ed t o 5 port pi ns. 110: r e ser v ed 111: r e ser v ed bit2 : uarten: uart i/o en ab le bit 0: uar t i/ o unavai l a bl e at port pi ns. 1: rx, tx routed to 2 port pins. bit1 : spi0 o en: spi bu s i/o en ab le bit 0: spi i/ o unavai l a bl e at port pi ns. 1: miso, mosi, sck, and n ss routed to 4 port pins. bit0 : smb0 oen: smbu s bu s i/o en ab le bit 0: sm b u s i/ o unavai l a ble at p0.0, p0.1. 1: sda routed to p0.0, scl routed to p0.1.
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 15.4. xbr1: port i/o crossbar register 1 r/w r / w r/w r / w r / w r / w r e s e t v a l u e s y s c k e t 2 e x e t 2 e t 1 e t 0 e c p 1 o e n 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x e 2 r/w r / w int1e i n t 0 e bit7 : syscke: sysclk ou tp u t en ab le bit 0: sysc lk unavai l a bl e at port pi n. 1: sysc lk out put rout ed t o port pi n. bit6: t2exe: t2 ex en ab le bit 0: t2ex unavai l a bl e at port pi n. 1: t2ex rout ed t o port pi n. bit5 : t2 e: t2 en ab le bit 0: t2 unavai l a bl e at port pi n. 1: t2 rout ed t o port pi n. bit4 : int1 e: /int1 en ab le bit 0: / i nt1 unavai l a bl e at port pi n. 1: / i nt1 rout ed t o port pi n. bit3 : t1 e: t1 en ab le bit 0: t1 unavai l a bl e at port pi n. 1: t1 rout ed t o port pi n. bit2 : int0 e: /int0 en ab le bit 0: / i nt0 unavai l a bl e at port pi n. 1: / i nt0 rout ed t o port pi n. bit1 : t0 e: t0 en ab le bit 0: t0 unavai l a bl e at port pi n. 1: t0 rout ed t o port pi n. bit0 : cp1 o en: co m p arato r 1 ou tp u t en ab le bit 0: c p 1 unavai l a bl e at port pi n. 1: c p 1 rout ed t o port pi n. 107 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 15.5. xbr2: port i/o crossbar register 2 r/w r / w r/w r / w r/w r / w r / w r e s e t v a l u e weakpud x b a r e - - - - - c n v s t e b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x e 3 r / w 00000000 bit7 : w e akpud: po rt i/o w eak pu ll-u p disab l e bit 0: w eak pul l - ups enabl e d (except for port s whose i/ o are confi gured as push-pul l ) 1: w eak pul l - ups di sabl ed bit6 : xbare: cro ssb ar en ab le bit 0: crossbar disabled 1: c r ossbar enabl e d bi t s 5-1: unused. read = 00000b, w r i t e = don?t care. b i t 0 : c nvste: adc c onvert st art input enabl e b i t 0: c nvstr unavai l a bl e at port pi n. 1: c nvstr rout ed t o port pi n. ex am p l e usag e o f xbr0 , xbr1 , xbr2 : w h en selected , th e d i g ital reso u r ces fill th e po rt i/o p i n s in o r d e r (to p to b o tto m as sh o w n in tabl e 15.1) st art i ng wi t h p0.0 t h rough p0.7, and t h en p1.0 t h rough p1.7, and fi nal l y p2.0 t h rough p2.7. if t h e di gi t a l resources are not m a pped t o t h e port i/ o pi ns, t h ey defaul t t o t h ei r m a tch i n g in tern al po rt reg i ster b its. exam pl e1: if xb r 0 = 0x11, xb r 1 = 0x00, and xb r 2 = 0x40: p0.0=sda, p0.1=sc l , p0.2=c ex0, p0.3=c ex1, p0.4 ? p2.7 m a p t o correspondi ng port i/ o. exam pl e2: if xb r 0 = 0x80, xb r 1 = 0x04, and xb r 2 = 0x41: p0.0=c p0, p0.1=/ int0, p0.2 = c nvstr , p0.3 ? p2.7 m a p t o correspondi ng port i/ o. r e v. 1.7 108
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 15.3. general purpose port i/o each m c u has four by t e -wi d e, bi -di r ect i onal paral l e l port s t h at can be used general purpose i/ o. each port i s accessed through a corresponding special functi on register (sfr) that is both byte addressable and bit addressable. w h en writing to a port, the value written to the sfr is latched to m a intain the output data value at each pin. w h en reading, the logic levels of the port?s input pins are returned regardless of th e xbrn settings (i.e. even when the pin is assigned to another signal by the cro ssbar, the port register can always s till read its corresponding port i/o pin). th e ex cep tio n to th is is th e ex ecu tio n o f th e rea d - mo d ify-write in stru ctio n s . th e rea d - mo d ify-write in stru ctio n s when operat i ng on a port sfr are t h e fol l o wi ng: anl, or l, xrl, jbc, cpl, inc, dec, djnz an d mov, clr o r set, wh en th e d e stin atio n is an in d i v i d u a l b it in a p o r t sfr. fo r th ese in stru ctio n s , th e v a lu e o f th e p o r t reg i ster (n o t th e p i n ) is read , m o d i fied , an d written b ack to th e sfr. 15.4. configuring ports which are not pinned out p2 and p3 are not pi nned out on t h e f001/ 06/ 11/ 16. p1, p2, and p3 are not pi nned out on t h e f002/ 07/ 12/ 17. these port registers (and corresponding interrupts, where applicable ) are still available for soft ware use in these reduced pi n count m c us. w h et her used or not i n soft ware, i t i s recom m e nded not t o l e t t h ese port dri v ers go t o hi gh i m pedance st at e. thi s i s prevent e d aft e r reset by havi ng t h e weak pul l - ups enabl e d as descri bed i n t h e xb r 2 register. it is recom m e nded that each output driver for ports not pinned out should be configured as push-pull using the corresponding prtncf register. this will inhibit a high im pedance state ev en if the weak pull-up is disabled. figure 15.6. p0: port0 register r/w r / w r/w r / w r / w r/w r / w r / w p 0 . 7 p 0 . 6 p 0 . 1 p 0 . 0 1 1 1 1 1 1 1 1 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 0 sfr address: (bit addressable) 0x80 reset value p0.5 p0.4 p0.3 p 0 . 2 b i t 1 b i t s 7-0: p0.[7: 0] (w ri t e ? out put appears on i/ o pi ns per xb r 0 , xb r 1 , and xb r 2 r e gi st ers) 0: logi c low out put . 1: logi c hi gh out put (hi gh-i m pedance i f correspondi ng pr t0c f .n bi t = 0) (r ead ? r e gardl e ss of xb r 0 , xb r 1 , and xb r 2 r e gi st er set t i ngs). 0: p0.n pi n i s l ogi c l o w. 1: p0.n pi n i s l ogi c hi gh. figure 15.7. prt0cf: port0 configuration register r/w r / w r/w r / w r / w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 0 sfr address: 0 x a 4 r/w b i t 1 b i t s 7-0: pr t0c f .[7: 0] : out put c onfi gurat i on b i t s for p0.7-p0.0 (respect i v el y ) 0: c o rrespondi ng p0.n out put m ode i s open-drai n . 1: c o rrespondi ng p0.n out put m ode i s push-pul l . (note: w h en sda, scl, and rx appear on any of the p0 i/o, each are open-drain regardl e ss of t h e val u e of pr t0c f ). 109 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 15.8. p1: port1 register p 1 . 4 p 1 . 1 bit7 bit6 b i t 4 b i t 0 (bit addressable) r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e p 1 . 7 p 1 . 6 p 1 . 5 p 1 . 3 p 1 . 2 p 1 . 0 1 1 1 1 1 1 1 1 b i t 5 b i t 3 b i t 2 b i t 1 sfr address: 0x90 figure 15.9. prt1cf: port1 configuration register r/w r / w r / w 00000000 b i t 6 bit3 sfr address: 0 x a r / w r/w r / w r/w r / w r e s e t v a l u e b i t 7 b i t 5 b i t 4 b i t 2 b i t 1 b i t 0 5 b i t s 7-0: p1.[7: 0] (w ri t e ? out put appears on i/ o pi ns per xb r 0 , xb r 1 , and xb r 2 regi st ers) 0: logi c low out put . 1: logi c hi gh out put (hi gh-i m pedance i f correspondi ng pr t1c f .n bi t = 0) (r ead ? r e gardl e ss of xb r 0 , xb r 1 , and xb r 2 r e gi st er set t i ngs). 0: p1.n pi n i s l ogi c l o w. 1: p1.n pi n i s l ogi c hi gh. b i t s 7-0: pr t1c f .[7: 0] : out put c onfi gurat i on b i t s for p1.7-p1.0 (respect i v el y ) 0: c o rrespondi ng p1.n out put m ode i s open-drai n . 1: c o rrespondi ng p1.n out put m ode i s push-pul l . figure 15.10. prt1if: port1 interrupt flag register r/w r/w r / w r / w r / w r / w i e 7 - - - b i t 7 b i t 6 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x a d r / w r/w reset value i e 6 ie5 ie4 - 00000000 bit5 bit4 b i t 7 : ie7: ext e rnal int e rrupt 7 pendi ng fl ag. 0: no fal l i ng edge det ect ed on p1.7. 1: thi s fl ag i s set by hardware when a fal l i ng edge on p1.7 i s det ect ed. b i t 6 : ie6: ext e rnal int e rrupt 6 pendi ng fl ag. 0: no fal l i ng edge det ect ed on p1.6. 1: thi s fl ag i s set by hardware when a fal l i ng edge on p1.6 i s det ect ed. b i t 5 : ie5: ext e rnal int e rrupt 5 pendi ng fl ag. 0: no fal l i ng edge det ect ed on p1.5. 1: thi s fl ag i s set by hardware when a fal l i ng edge on p1.5 i s det ect ed. b i t 4 : ie4: ext e rnal int e rrupt 4 pendi ng fl ag. 0: no fal l i ng edge det ect ed on p1.4. 1: thi s fl ag i s set by hardware when a fal l i ng edge on p1.4 i s det ect ed. bi t s 3-0: unused. read = 0000b, w r i t e = don?t care. r e v. 1.7 110
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 15.11. p2: port2 register r/w r/w r / w r/w r / w r e s e t v a l u e p 2 . 7 p 2 . 5 p 2 . 3 b i t 6 b i t 4 b i t 2 b i t 0 sfr address: 0xa0 r / w r / w r / w p 2 . 6 p 2 . 4 p2.2 p2.1 p2.0 11111111 b i t 7 b i t b it3 b i t 1 (bit addressable) b i t s 7-0: p2.[7: 0] (w ri t e ? out put appears on i/ o pi ns per xb r 0 , xb r 1 , and xb r 2 regi st ers) 0: logi c low out put . 1: logi c hi gh out put (hi gh-i m pedance i f correspondi ng pr t2c f .n bi t = 0) (r ead ? r e gardl e ss of xb r 0 , xb r 1 , and xb r 2 r e gi st er set t i ngs). 0: p2.n is logic low. 1: p2.n i s l ogi c hi gh. figure 15.12. prt2cf: port2 configuration register r/w r / w reset value 00000000 bit7 bit6 bit5 bit4 bit3 b i t 0 b i t s 7-0: pr t2c f .[7: 0] : out put c onfi gurat i on b i t s for p2.7-p2.0 (respect i v el y ) 0: c o rrespondi ng p2.n out put m ode i s open-drai n . 1: c o rrespondi ng p2.n out put m ode i s push-pul l . r / w r/w r / w r / w r/w r / w b i t 2 b i t 1 sfr address: 0 x a 6 111 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 15.13. p3: port3 register r/w r/w r / w r / w p 3 . 1 1 1 1 1 1 1 1 1 b i t 7 b i t 6 b i t 2 b i t 0 sfr address: (bit addressable) r / w r / w r/w r / w reset value p3.7 p3.6 p3.5 p3.4 p3.3 p 3 . 2 p 3 . 0 bit5 bit4 bit3 b i t 1 0xb0 b i t s 7-0: p3.[7: 0] (w rite) 0: logi c low out put . 1: logi c hi gh out put (hi gh-i m pedance i f correspondi ng pr t3c f .n bi t = 0) (read) 0: p3.n is logic low. 1: p3.n i s l ogi c hi gh. figure 15.14. prt3cf: port3 configuration register r/w r / w r / w r/w b i t 6 b i t 4 b i t 0 sfr address: b i t s 7-0: pr t3c f .[7: 0] : out put c onfi gurat i on b i t s for p3.7-p3.0 (respect i v el y ) 0: c o rrespondi ng p3.n out put m ode i s open-drai n . 1: c o rrespondi ng p3.n out put m ode i s push-pul l . r / w r/w r / w r/w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 5 b i t 3 b i t 2 b i t 1 0 x a 7 table 15.2. port i/o dc electrical characteristics vdd = 2.7 to 3.6v, -40 q c to +8 5 q c unless otherwise specified. c o n d i t i o n s p a r a m e t e r m i n t y p max u n i t s out put hi gh vol t a g e i oh = -10ua, port i/ o push-pul l i oh = -3m a , port i/ o push-pul l i oh = -10m a, port i/ o push-pul l vdd ? 0.1 vdd ? 0.7 vdd ? 0.8 v o u t p u t l o w v o l t a g e i ol = 1 0 u a i ol = 8.5m a i ol = 25m a 1.0 0.1 0.6 v v input low vol t a ge 0.3 x vdd v r 1 p a 5 p f input hi gh vol t a ge 0.7 x vdd input leakage current dgnd < port pi n < vdd, pi n tri - st at e w eak pull-up off w eak pull-up on 30 cap acitiv e lo ad in g r e v. 1.7 112
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 16. s m b u s / i 2 c b u s the smbus serial i/o interface is com p lia nt with the system managem e nt bus sp ecification, version 1.1. it is a two - wire, b i -d irectio n a l serial b u s , wh ich is also co m p atib le with th e i 2 c serial bus. reads and writes to the interface by the system controller are byte oriented with the smbus interf ace autonom ously controlling the serial transfer of the data. data can be t r ansferred at up t o 1/ 8 th of t h e sy st em cl ock i f desi red (t hi s can be fast er t h an al l o wed by t h e sm b u s speci fi cat i on, dependi ng on t h e sy st em cl ock used). a m e t hod of ext e ndi ng t h e cl ock-l o w duration is used to accom m odate devices with different speed capabilities on the sam e bus. two types of data transfers are possible: data transfers from a m a ster transm itte r to an addressed slave receiver, and data transfers from an addressed slave transm itter to a m a ster receiver. th e m a ster device initiates both types of data transfers and provides the serial clock pulses. the smbus interface m a y operate as a m a ster or a slave. multiple m a ster devices on the sam e bus are also supported. if two or m o re m a sters attem p t to initiate a data t r ansfer si m u l t a neousl y , an arbi t r at i on schem e i s em pl oy ed wi t h a si ngl e m a st er al way s wi nni ng t h e arbi t r at i on. figure 16.1. smbus block diagram sfr bus data path control sfr bus write to smb0dat smbus control logic read smb0dat smb0adr s l v 6 g c s l v 5 s l v 4 s l v 3 s l v 2 s l v 1 s l v 0 c r o s s b a r clock divide logic sysclk smb0cr c r 7 c r 6 c r 5 c r 4 c r 3 c r 2 c r 1 c r 0 scl filter n sda control 0000000b 7 msbs 8 a b a=b 8 0 1 2 3 4 5 6 7 smb0dat 8 smb0cn s t a s i a a f t e t o e e n s m b b u s y s t o smb0sta s t a 4 s t a 3 s t a 2 s t a 1 s t a 0 scl control status generation arbitration scl synchronization scl generation (master mode) irq generation s t a 5 s t a 6 s t a 7 a b a=b smbus irq interrupt request port i/o 1 0 sda filter n 7 113 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 16.2 shows a typical smbus conf iguration. the smbus interface will work at any voltage between 3.0v and 5.0v and di fferent devi ces on t h e bus m a y operat e at di fferent vol t a ge l e vel s . the sc l (seri a l cl ock) and sda (serial data) lines are bi-directional. they m u st be connected to a positive power supply voltage through a pull-up resi st or or si m i l a r ci rcui t . w h en t h e bus i s free, bot h l i n es are pul l e d hi gh. every devi ce connect ed t o t h e bus m u st have an open-drai n or open-col l ect or out put for bot h t h e sc l and sda l i n es. the m a xi m u m num ber of devi ces on the bus is lim ited only by the requirem e nt that the ri se and fall tim es on the bus will not exceed 300ns and 1000ns, respectively. figure 16.2. typical smbus configuration 16.1. supporting documents 1. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl it is assum e d the reader is fam iliar with or has access to the following supporting docum e n t s : the i 2 c-bus and how to use it (including specifications) , philips sem i c o n d u c t o r . 2. the i 2 c-bu s s p ecifica tio n -- versio n 2 . 0 , philips sem i conductor. 3. system management bus sp ecification -- version 1.1 , sbs im plem enters forum . r e v. 1.7 114
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 16.2. operation a t y pi cal sm b u s t r ansact i on consi s t s of a star t condi t i on, fol l o wed by an address by t e , one or m o re by t e s of data, and a stop condition. the address byte and each of the data bytes are followed by an acknow ledge bit from the receiver. the address byte consists of a 7-bit address plus a direction bit. the direction bit (r/w ) occupi es t h e l east - si gni fi cant bi t posi t i on of t h e address. the di rect i on bi t i s set t o l ogi c 1 t o i ndi cat e a ?r ead? operat i on and cl eared t o l ogi c 0 t o i ndi cat e a ?w r i te? operat i on. a general cal l address (0x00 +r / w ) i s recognized by all slave devices allowing a m a ster to address m u ltiple slave devices sim u ltaneously. all tran sactio n s are in itiated b y th e m a ster, with o n e o r m o re ad d r essed slav e d e v i ces as th e targ et. th e m a ster g e n e rates th e start co n d itio n an d th en tran sm its th e ad d r ess an d d i rectio n b it. if th e tran sactio n is a w r ite o p e ratio n fro m th e m a ster to th e slav e, th e m a ster tran sm its th e d a ta a byte at a tim e waiting for an acknow ledge from the slave at the end of each byte. if it is a read operation, the slave transm its the data waiting for an acknow ledge from the m a ster at the end of each byte. at the end of the data transfer, the m a ster g e n e rates a stop co n d itio n to term in ate th e tran sactio n an d free th e b u s . fig u r e 1 . 3 illu strates a typ i cal smbus transaction. 6 serial data is transm itted on sda while the serial clock is received on scl. first, a byte is received that contains an ad d r ess an d d a ta d i rectio n b it. in th is case th e d a ta d i rectio n b it (r/w ) will b e lo g i c 1 to in d i cate a ?read? operation. if the received address m a tche s the slave?s assigned address (or a gene ral call address is received) one or m o re bytes of serial data are transm itted to the m a ster . after each byte is received, an acknowledge bit is transm itted by the m a ster. the m a ster outputs start a nd stop conditions to indicat e the beginning and end of the serial transfer. figure 16.3. smbus transaction start slave addr r/w ack data ack nack stop data tim e the smbus interface m a y be configured to operate as either a m a ster or a slave. at any particular tim e, it will be operat i ng i n one of t h e fol l o wi ng four m odes: 16.2.1. master transmitter mode serial d a ta is tran sm itted o n sda wh ile th e serial clo c k is o u t p u t o n scl. th e first b y te tran sm itted co n t ain s th e ad d r ess o f th e targ et slav e d e v i ce an d th e d a ta d i rectio n b it. in th is case th e d a ta d i rectio n b it (r/w ) will b e lo g i c 0 to indicate a ?w rite? operation. the m a st er then transm its one or m o re bytes of serial data. after each byte is transm itted, an acknowledge bit is generated by the slave. to indicate the beginning and the end of the serial t r ansfer, t h e m a st er devi ce out put s star t and stop condi t i ons. 16.2.2. master receiver mode serial data is received on sda while th e serial clock is output on scl. the first byte is transm itted by the m a ster an d co n t ain s th e ad d r ess o f th e targ et slav e an d th e d a ta d i rectio n b it. in th is case th e d a ta d i rectio n b it (r/w ) will be logic 1 to indicate a ?read? operati on. serial data is then received from the slave on sda while the m a ster outputs the serial clock. the slave tran sm its one or m o re bytes of serial da ta. after each byte is received, an acknowledge bit is transm itted by the m a ster. the m a st er outputs start and stop conditions to indicate the begi nni ng and end of t h e seri al t r ansfer. 16.2.3. slave transm itter mode 115 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 16.2.4. slave receiver mode serial data is received on sda while the serial clock is received on scl. first, a byte is received that contains an ad d r ess an d d a ta d i rectio n b it. in th is case th e d a ta d i rectio n b it (r/w ) will b e lo g i c 0 to in d i cate a ?w rite? operation. if the received address m a tche s the slave?s assigned address (or a gene ral call address is received) one or m o re bytes of serial data are received from the m a ster . after each byte is received, an acknowledge bit is transm itted by the slave. the m a ster outputs start and stop conditions to indicate the beginning and end of the serial transfer. 16.3. arbitration a m a ster m a y start a transfer only if the bus is free. the bus is free after a stop condition or after the scl and sda lines rem a ins high for a specified tim e. two or m o re m a ster d e v i ces m a y attem p t to g e n e rate a start condi t i on at t h e sam e t i m e. si nce t h e devi ces t h at generat e d t h e star t condi t i on m a y not be aware t h at ot her m a st ers are cont endi ng for t h e bus, an arbi t r at i on schem e i s em pl oy ed. the m a st er devi ces cont i nue t o t r ansm i t u n til o n e o f th e m a sters tran sm its a high lev e l, wh ile th e o t h e r(s) m a ster tran sm its a low lev e l o n sda. th e first m a ster(s) tran sm ittin g th e high lev e l o n sda lo o s es th e arb itratio n an d is req u i red to g i v e u p th e b u s . 16.4. clock low extension sm b u s provi des a cl ock sy nchroni zat i on m echani s m , si m i l a r t o i2c , whi c h al l o ws devi ces wi t h di fferent speed cap ab ilities to co ex ist o n th e b u s . a clo c k - lo w ex ten s io n is u s ed d u r in g a tran sfer in o r d e r to allo w slo w er slav e devices to com m unicate with faster m a sters. the slave can hold the scl lin e low t o ext e nd t h e cl ock l o w peri od, effectively decreasing the seri al cl ock frequency . 16.5. timeouts if t h e sc l l i n e i s hel d l o w by a sl ave devi ce on t h e bus, no furt her com m uni cat i on i s possi bl e. furt herm ore, t h e m a ster cannot force the scl line high to correct the error condition. to so lve this problem , the smbus protocol speci fi es t h at devi ces part i c i p at i ng i n a t r ansfer m u st det ect any cl ock cy cl e hel d l o w l onger t h an 25m s as a ?t i m eout ? condi t i on. devi ces t h at have det ect ed t h e t i m eout condi t i on m u st reset t h e com m uni cat i on no l a t e r t h an 10m s aft e r det ect i ng t h e t i m eout condi t i on. one of t h e m c u?s general - purpose t i m ers, operat i ng i n 16-bi t aut o -rel o ad m ode, can be used t o m oni t o r t h e sc l l i n e for t h i s t i m eout condi t i on. ti m e r 3 i s speci fi cal l y desi gned for t h i s purpose. (r efer t o t h e ti m e r 3 sect i on 19.3. for det a i l e d i n form at i on on ti m e r 3 operat i on.) 16.5.1. scl low tim e out 16.5.2. scl high (smbus free) timeout the sm b u s speci fi cat i on st i pul at es t h at i f a devi ce hol ds t h e sc l and sda l i n es hi gh for m o re t h at 50usec, t h e bus is d e sig n a ted as free. th e smb0 cr reg i ster is u s ed to d e tect th is co n d itio n wh en th e fte b it in smb0 cn is set. 16.6. smbus special function registers the smbus serial interface is accessed and controlled through five sfrs: smb0cn control register, smb0cr c l ock r a t e r e gi st er, sm b 0 adr address r e gi st er, sm b 0 dat dat a r e gi st er and sm b 0 sta st at us r e gi st er. the system device m a y have one or m o re smbus serial interfaces im plem ented. the five special function registers related to the operation of the smbus interf ace are described in the following section. r e v. 1.7 116
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 16.6.1. control register the smbus control register smb0cn is used to configure and control the smbu s interface. all of the bits in the reg i ster can b e read o r written b y so ftware. two o f th e co n t ro l b its are also affected b y th e smbu s h a rd ware. th e serial interrupt flag (si, sm b0cn.3) is set t o l ogi c 1 by t h e hardware when a val i d seri al i n t e rrupt condi t i on occurs. it can only be cleared by software. the stop flag (sto, smb0cn.4) is clear ed t o l ogi c 0 by hardware when a stop condi t i on i s present on t h e bus. setting the ensmb flag to logic 1 enab les the smbus interface. clearing the ensmb flag to logic 0 disables the smbus interface and rem oves it from the bus. mom e ntarily clearing the ensmb flag and then resetting it to logic 1 will reset a smbus com m unication. however, ensmb s hould not be used to tem por arily rem ove a device from the bus since the bus state inform ation will be lost. instead, the assert acknow ledge (aa) flag should be used to t e m porari l y rem ove t h e devi ce from t h e bus (see descri pt i on of aa fl ag bel o w). settin g th e start flag (sta, smb0 cn.5 ) to lo g i c 1 will p u t th e smbu s in a m a ster m o d e . if th e b u s is free, th e smbus hardware will generate a start condition. if the bus is not free, the smbus hardware waits for a stop condi t i on t o free t h e bus and t h en generat e s a star t condi t i on aft e r a 5 p s del a y per t h e sm b 0 c r val u e. (in accordance with the smbus prot ocol, the smbus interface also considers the bus free if the bus is idle for 50 p s and no stop condi t i on was recogni zed.) if sta i s set t o l ogi c 1 whi l e t h e sm b u s i s i n m a st er m ode and one or m o re b y tes h a v e b een tran sferred , a rep eated start co n d itio n will b e g e n e rated . to en su re p r o p e r o p e ratio n , th e sto flag should be explicitly cleared before setting sta to a logic 1. w h en the stop flag (sto, smb0cn.4) is set to logic 1 wh ile the smbus interface is in m a ster m ode, the hardware generat e s a stop condi t i on on t h e sm b u s. in a sl ave m ode , the sto flag m a y be used to recover from an error condi t i on. in t h i s case, a stop condi t i on i s not generat e d on t h e sm b u s, but t h e sm b u s hardware behaves as i f a stop condition has been received and enters the ?not addressed? slave receiver m ode. the smbus hardware autom a tically clears the sto flag to logic 0 wh en a stop condi t i on i s det ect ed on t h e bus. the serial interrupt flag (si, smb0cn .3) is set to logic 1 by hardware wh en the smbus interface enters one of 27 possible states. if interrupts are enabled for the smbus interface, an interrupt re quest is generated when the si flag i s set . the si fl ag m u st be cl eared by soft ware. w h i l e si i s set t o l ogi c 1, t h e cl ock-l o w peri od of t h e seri al cl ock will b e stretch e d an d th e serial tran sfer is su sp en d e d . the assert acknowl e dge fl ag (aa, sm b 0 c n .2) i s used t o set t h e l e vel of t h e sda l i n e duri ng t h e acknowl e dge clock cycle on the scl line. setting the aa flag to l ogic 1 will cause an acknow ledge (low level on sda) to be sent during the acknowledge cycle if the device has been addressed. setti ng the aa flag to logic 0 will cause a not acknow ledge (hi gh l e vel on sda) t o be sent duri ng acknowl e dge cy cl e. aft e r t h e t r ansm i ssi on of a byte in slave m ode, the slave can be tem porarily rem ove d from the bus by clearing the aa flag. the slave?s own address and general call address will be ignored. to resum e operation on the bus, the aa flag m u st be reset to logic 1 t o al l o w t h e sl ave?s address t o be recogni zed. settin g th e smbu s free tim e r en ab le b it (fte, smb0 cn.1 ) to logic 1 enables the smbus free tim e out feature. if sc l and sda rem a i n hi gh for t h e sm b u s free ti m e out gi ven i n t h e sm b u s c l ock r a t e r e gi st er (fi gure 16.5), t h e bus will be considered free and a start will be generated if pending. the bus free pe riod should be greater than 50 p s. set t i ng t h e sm b u s t i m eout enabl e bi t (toe, sm b 0 c n .0) t o l ogi c 1 enabl e s ti m e r 3 t o count up when t h e sc l l i n e is lo w an d tim e r 3 is en ab led . if tim e r 3 o v e rflo w s, a tim e r 3 in terru p t will b e g e n e rated , wh ich will alert th e cpu that a smbus scl low tim eout has occurred. 117 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 16.4. smb0cn: smbus control register r r/w r/w r / w r / w r/w r / w r e s e t v a l u e b u s y e n s m b s t a s t o s i a a f t e b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: (bit addressable) 0xc0 r / w toe 00000000 bit7 : busy: bu sy statu s flag . 0: smbus is free 1: sm b u s i s busy bit6 : ensmb: smbu s en ab le. this bit enables/disables th e smbus serial interface. 0: sm b u s di sabl ed. 1: smbus enabled. bit5: sta: smbus start flag. 0 : no start co n d itio n is tran sm itted . 1: w h en operating as a m a ster, a start conditi on is transm itted if the bus is free. (if the bus is not free, the start is transm itted after a stop is received.) if sta is set after one or m o re bytes have been transm itted or receive d and before a stop is received, a repeated start condition is transm itted. sto should be explicitly cleared before setting sta to l ogi c 1. bit4: sto: smbus stop flag. 0 : no stop co n d itio n is tran sm itted . 1 : settin g sto to lo g i c 1 cau ses a stop co n d itio n to b e tran sm itted . w h en a stop condition is received, hardware clears sto to logic 0. if both sta and sto are set, a stop condition is transm itted followed by a st art condition. in slave m ode, setting the sto flag causes smbus to behave as if a stop condition was received. bit3 : si: smbu s serial in terru p t flag . thi s bi t i s set by hardware when one of 27 possi bl e sm b u s st at es i s ent e red. (st a t u s code 0 x f 8 d o e s n o t cau se si to b e set.) w h en th e si in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e smbu s in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared by hardware and m u st be cleared by software. b i t 2 : aa: sm b u s assert acknowl e dge fl ag. thi s bi t defi nes t h e t y pe of acknowl e dge ret u rned duri ng t h e acknowl e dge cy cl e on t h e scl lin e. 0: a ?not acknowl e dge? (hi gh l e vel on sda) i s ret u rned duri ng t h e acknowl e dge cy cl e. 1: an ?acknowl e dge? (l ow l e vel on sda) i s ret u rned duri ng t h e acknowl e dge cy cl e. bit1 : fte: smbu s free tim e r en ab le bit 0: no t i m eout when sc l i s hi gh 1: tim e out when scl high tim e exceed s lim it specified by the smb0cr value. bit0 : toe: smbu s tim e o u t en ab le bit 0 : no tim eo u t wh en scl is lo w. 1: tim e out when scl low tim e exceeds lim it specified by tim e r 3, if enabled. r e v. 1.7 118
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 16.6.2. clock rate register figure 16.5. smb0cr: smbus clock rate register r/w r/w r / w r / w r / w 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c f r / w r / w r/w reset value bits7 - 0 : smb0 cr.[7 :0 ]: smbu s clo c k rate preset the sm b 0 c r c l ock r a t e regi st er cont rol s t h e frequency of t h e seri al cl ock sc l i n m a st e r m ode. the 8-bi t word st ored i n t h e sm b 0 c r r e gi st er prel oads a dedi cat ed 8- b it tim er. the t i m er count s up, and when i t rol l s over t o 0x00, t h e sc l l ogi c st at e t oggl es. the sm b 0 c r set t i ng shoul d be bounded by t h e fol l o wi ng equat i on, where smb0c r is th e unsi gned 8-bi t val u e i n regi st er sm b 0 c r , and sysc lk i s t h e sy st em cl ock frequency i n hz: sm b 0 c r < ((288 - 0.85 * sysc lk) / 1.125 e 6) the resul t i ng sc l si gnal hi gh and l o w t i m es are gi ven by t h e fol l o wi ng equat i ons: t low = ( 256 ? smb0c r ) / sysc lk t high # ( 258 ? smb0c r ) / sysc lk + 625 ns usi ng t h e sam e val u e of sm b 0 c r from above, t h e b u s free ti m e out peri od i s gi ven i n t h e fol l o wi ng equat i on: t bft # 10 * [ ( 256 ? smb0c r ) + 1] / sysc lk 119 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 16.6.3. data register the smbus data register smb0dat holds a byte of serial data to be transm itted or one that has j u st been received. dat a rem a i n s st abl e i n t h e regi st er as l ong as si i s set t o l ogi c 1. soft ware can safel y read or wri t e t o t h e dat a register when the si flag is set. software should not attem p t to access th e smb0dat register when the smbus is enabl e d and t h e si fl ag i s cl eared t o l ogi c 0 si nce t h e hardware m a y be i n t h e process of shi f t i ng a by t e of dat a i n or out of t h e regi st er. data in smb0dat is always shifted out msb first. after a byte has been received, the first bit of received data is l o cat ed at t h e m s b of sm b 0 dat. w h i l e dat a i s bei ng shi f t e d out , dat a on t h e bus i s si m u l t a neousl y bei ng shi f t e d in. therefore, smb0dat always contains th e last d a ta b y te p r esen t o n th e b u s . th u s , in th e ev en t o f lo st arb itratio n , the transition from m a ster transm itte r to slave receiver is m a de with the correct data in smb0dat. figure 16.6. smb0dat: smbus data register r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 2 bits7 - 0 : smb0 dat: smbu s data. th e smb0 dat reg i ster co n t ain s a b y te o f d a ta to b e tran sm itted o n th e smbu s serial interface or a byte that has just been receive d on the smbus serial interface. the cpu can read fro m o r write to th is reg i ster wh en ev er th e si serial in terru p t flag (smb0 c n.3 ) is set t o l ogi c one. the seri al dat a i n t h e regi st er rem a i n s st abl e as l ong as t h e si fl ag i s set . w h en th e si flag is n o t set, th e system m a y b e in th e p r o cess o f sh iftin g d a ta in /o u t an d th e cpu should not attem p t to access this register. 16.6.4. address register the smb0adr address register holds th e slave address for the smbus interface. in slave m ode, the seven m o st- sig n i fican t b its h o l d th e 7 - b it slav e ad d r ess. th e least sig n i fican t b it, b it 0 , is u s ed to en ab le th e reco g n itio n o f th e general call address (0x00). if bit 0 is set to logic 1, the general call address will be recognized. otherwise, the general cal l address i s i gnored. the cont ent s of t h i s regi st er are i gnored when t h e sm b u s hardware i s operat i ng i n ma s t e r mo d e . figure 16.7. smb0adr: smbus address register r/w slv6 slv5 b i t s 7-1: slv6-slv0: sm b u s sl ave address. these bits are loaded with the 7-bit slave address to wh ich the smbus will respond when operating as a slave transm itter or slave receiver. slv6 is the m o st significant bit of the address and corresponds to the first bit of the address byte received on the smbus. bit0 : gc: gen e ral call ad d r ess en ab le. this bit is used to enable gene ral call address (0x00) recognition. 0: general cal l address i s i gnored. 1: general cal l address i s recogni zed. r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e s l v 4 s l v 3 s l v 2 s l v 1 s l v 0 g c 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 3 r e v. 1.7 120
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 16.6.5. status register the sm b 0 sta st at us regi st er hol ds an 8-bi t st at us code indicating the current state of the smbus. there are 28 possible smbus states, each with a corre sponding unique status code. the five m o st signi ficant bits of the status co d e v a ry wh ile th e th ree least-sig n i fican t b its o f a v a lid st atus code are fixed at zero when si = 1. therefore, all p o ssib l e statu s co d e s are m u ltip les o f eig h t . th is facilitates th e u s e o f statu s co d e s in so ftware as an in d e x u s ed to branch t o appropri a t e servi ce rout i n es (al l o wi ng 8 by t e s of code t o servi ce t h e st at e or jum p t o a m o re ext e nsi v e service routine). for t h e purposes of user soft ware, t h e cont ent s of t h e sm b 0 st a regi st er i s onl y defi ned when t h e si fl ag i s l ogi c 1. software should never write to the sm b0sta register. doing so will yield indeterm inate results. the 28 smbus st at es, al ong wi t h t h ei r correspondi ng st at us codes, are gi ven i n tabl e 16.1. figure 16.8. smb0sta: smbus status register r/w r/w r / w sta2 sta1 sta0 11111000 bit7 bit6 bit3 b i t s 7-3: sta7-sta3: sm b u s st at us c ode. these bits contain the smbus status code. there are 28 possible status codes. each st at us code corresponds t o a si ngl e sm b u s st at e. a val i d st at us code i s present i n sm b 0 sta when t h e si fl ag (sm b 0c n.3) i s set . the cont ent of sm b 0 sta i s not defi ned wh en th e si flag is lo g i c 0 . w r itin g to th e smb0 sta reg i ster at an y tim e will yield in d e term in ate resu lts. bits2 - 0 : sta2 -sta0 : th e th ree least sig n i fican t b its of smb0sta are always read as logic 0 when the si flag is logic 1. r / w r/w r / w r / w r / w r e s e t v a l u e s t a 7 s t a 6 s t a 5 s t a 4 s t a 3 b i t 5 b i t 4 b i t 2 b i t 1 b i t 0 sfr address: 0 x c 1 121 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 16.1. smbus status codes st at us c ode (sm b 0sta) m ode smbus state 0x00 all bus error (i.e. illegal start, illegal stop, ?) 0 x 0 8 m a s t e r transm i t t e r / r e c e i v e r start condition transm itted. 0 x 1 0 m a s t e r transm i t t e r / r e c e i v e r rep eated start condition transm itted. 0x18 master transm itter slave address + w transm itted. ack received. 0x20 master transm itter slave address + w transm itted. nack received. 0x28 master transm itter data byte transm itted. ack received. 0x30 master transm itter data byte transm itted. nack received. 0x38 master transm itter arbitration lost 0x40 master receiver slave address + r transm itted. ack received. 0x48 master receiver slave address + r transm itted. nack received 0x50 master receiver data byte received. ack transm itted. 0x58 master receiver data byte received. nack transm itted. 0x60 slave receiver smb0?s ow n slave address + w received. ack transm itted. 0x68 slave receiver arbitration lost in tran sm itting slave address + r/w as m a ster. own slave address + w received. ack transm itted. 0x70 slave receiver general call addre ss (0x00) received. ack returned. slave receiver arbitration lost in tran sm itting slave address + r/w as m a ster. general call address received. ack transm itted. 0x80 slave receiver smb0?s own slave address + w received. data byte received. ack tran sm itted . 0x88 slave receiver smb0?s own slave address + w received. data byte received. nack tran sm itted . 0x90 slave receiver general call address (0x00) received. data byte received. ack tran sm itted . 0x98 slave receiver general call address (0x00) received. data byte received. nack tran sm itted . slave receiver a stop or repeated st art received while addressed as a slave. 0xa8 slave transm itter smb0?s own slave a ddress + r received. ack transm itted. 0 x b 0 slav e tran sm itter arb itratio n lo st in tran sm ittin g slav e ad d r ess + r/w as m a ster. own slave address + r received. ack transm itted. 0xb8 slave transm itter data byte transm itted. ack received. 0xc0 slave transm itter data byte transm itted. nack received. 0xd0 slave transm itter/receiver scl clock high tim e r per smb0cr tim ed out (fte=1) 0 x f 8 a l l idl e 0x78 0xa0 0xc8 slave transm itter last data byte transm itted (aa=0). ack received. r e v. 1.7 122
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 17. serial peripheral interface bus the serial peripheral interface (spi) provides access to a four-wire, full-duplex, serial bus. spi supports the co n n ectio n o f m u ltip le slav e d e v i ces to a m a ster d e v i ce o n th e sam e b u s . a sep a rate slav e-select sig n a l (nss) is u s ed to select a slav e d e v i ce an d en ab le a d a ta tran sfer b e tween th e m a ster an d th e selected slav e. mu ltip le m a sters on the sam e bus are also supported. collision detection is provided when two or m o re m a sters attem p t a data transfer at the sam e tim e. the spi can operate as either a m a ster or a slave. w h en the spi is configured as a m a ster, th e m a x i m u m d a ta tran sfer rate (b its / s ec) i s one-hal f t h e sy st em cl ock frequency . figure 17.1. spi block diagram w h en t h e spi i s confi gured as a sl ave, t h e m a xi m u m dat a t r ansfer rat e (bi t s / s ec) for ful l - dupl ex operat i on i s 1/ 10 t h e sy st em cl ock frequency , provi ded t h at t h e m a st er i ssues sc k, nss, and t h e seri al i nput dat a sy nchronousl y wi t h t h e sy st em cl ock. if t h e m a st er i ssues sc k, nss, and t h e seri al i nput dat a asy n chronousl y , t h e m a xi m u m dat a t r ansfer rat e (bi t s / s ec) m u st be l e ss t h at 1/ 10 t h e sy st em cl ock freque ncy. in the special case wh ere the m a ster only wants to transm it data to the slave and does not need to receive data from the slave (i .e. half-duplex operation), the spi slave can receive data at a m a xim u m data transfer rate (bits/sec) of ? the system clock frequenc y. this is provided that t h e m a st er i ssues sc k, nss, and t h e seri al i nput dat a sy nchronousl y wi t h t h e sy st em cl ock. sfr bus clock divide logic data path control sfr bus write to spi0dat receive data register spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic bit count logic spi0ckr s c r 7 s c r 6 s c r 5 s c r 4 s c r 3 s c r 2 s c r 1 s c r 0 spi0cfg c k p h a c k p o l b c 2 b c 1 b c 0 f r s 2 f r s 1 f r s 0 spi0cn m o d f t x b s y s l v s e l m s t e n s p i e n w c o l s p i f r x o v r n pin control interface spi clock (master mode) pin control logic c r o s s b a r port i/o read spi0dat spi irq sysclk tx data rx data sck mosi miso nss 123 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 17.2. typical spi interconnection the m a st er-i n, sl ave-out (m iso) si gnal i s an out put from a sl ave devi ce and an i nput t o t h e m a st er devi ce. it i s used to serially tran sfer d a ta fro m th e slav e to th e m a ster. data is tran sferred m o st-sig n i fican t b it first. a spi slav e places the miso pin in a high-im pedance state when the slave is not selected. master device mosi slave device nss slave device nss slave device miso sck port i/o nss vdd port i/o port i/o 17.1. signal descriptions the four si gnal s used by t h e spi (m osi, m i so, sc k, nss) are descri bed bel o w. 17.1.1. master out, slave in the m a st er-out , sl ave-i n (m osi) si gnal i s an out put from a m a st er devi ce and an i nput t o sl ave devi ces. it i s used t o serially tran sfer d a ta fro m th e m a ster to th e slav e. data is tran sferred m o st-sig n i fican t b it first. 17.1.2. master in, slave out 17.1.3. serial clock the seri al cl ock (sc k ) si gnal i s an out put from t h e m a st er devi ce and an i nput t o sl ave devi ces. it i s used t o synchronize the transfer of data between the m a ster and slave on the mosi and miso lines. 17.1.4. slave select the sl ave sel ect (nss) si gnal i s an i nput used t o sel ect t h e spi m odul e when i n sl ave m ode by a m a st er, or t o disable the spi m odule when in m a ster m ode. w h en in sl ave m ode, it is pulled low to initiate a data transfer and rem a in s lo w fo r th e d u r atio n o f th e tran sfer. r e v. 1.7 124
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 17.2. operation only a spi m a ster device can initiate a da ta transfer. the spi is placed in m a st er m ode by setting the master enable fl ag (m sten, spi0c n.1). w r i t i ng a by t e of dat a t o t h e spi dat a regi st er (spi0dat) when i n m a st er m ode st art s a data transfer. the spi m a ster im m e di ately sh ifts o u t th e d a ta serially o n th e mosi lin e wh ile p r o v i d i n g th e serial cl ock on sc k. the spif (spi0c n.7) fl ag i s set t o l ogi c 1 at the end of the transfer. if interrupts are enabled, an i n t e rrupt request i s generat e d when t h e spif fl ag i s set . the spi m a st er can be confi gured t o shi f t i n / out from one to eight bits in a transfer operation in order to accom m odate slave devices w ith different word lengths. the spifrs bi t s i n t h e spi c onfi gurat i on r e gi st er (spi0c fg.[2: 0] ) are used t o sel ect t h e num ber of bi t s t o shi f t i n / out i n a t r ansfer operat i on. w h ile th e spi m a ster tran sfers d a ta to a slave on the mosi line, the addr essed spi sl ave devi ce si m u l t a neousl y t r ansfers t h e cont ent s of i t s shi f t regi st er t o t h e spi m a st er on t h e m i so l i n e i n a ful l - dupl ex operat i on. the dat a byte received from the slave replaces the data in the m a ster?s data register. therefore, the spif flag serves as both a transm it-com p lete and receive-data-ready fl ag. the data transfer in both direc tions is synchronized with the serial clock generated by the m a ster. figur e 17.3 illustrates the full-duplex operation of an spi m a ster and an addressed slave. figure 17.3. full duplex operation w h en th e spi is en ab led an d n o t co n f ig u r ed as a m a ster, it will o p e rate as an spi slav e. an o t h e r spi d e v i ce actin g as a m a ster will in itiate a tran sfer b y d r iv in g th e nss sig n a l lo w. th e m a ster th en sh ifts d a ta o u t o f th e sh ift reg i ster on t h e m o si pi n usi ng t h e i t s seri al cl ock. the spif fl ag i s set t o l ogi c 1 at t h e end of a dat a t r ansfer (when t h e nss si gnal goes hi gh). the sl ave can l o ad i t s shi f t regi st er for t h e next dat a t r ansfer by wri t i ng t o t h e spi dat a register. the slave m u st m a ke the write to the data regist er at least one spi serial cl ock cycle before the m a ster starts th e n e x t tran sm issio n . oth e rwise, th e b y te o f d a ta alread y in th e slav e?s sh ift reg i ster will b e tran sferred . mu ltip le m a sters m a y resid e o n th e sam e b u s . a mo d e fau lt flag (modf, spi0 c n.5 ) is set to lo g i c 1 wh en th e spi is configured as a m a ster (msten = 1) and its slave select sig n a l nss is p u lled lo w. w h en th e mo d e fau lt flag is set , t h e m s ten and spien bi t s of t h e spi cont rol regi st er are cl eared by hardware, t h ereby pl aci ng t h e spi m odul e the spi dat a regi st er i s doubl e buffered on reads, but not on a wri t e . if a wri t e t o spi0dat i s at t e m p t e d duri ng a data transfer, the w c ol flag (spi0cn.6) will be set to logic 1 and the write is ignored. the current data transfer will continue uninterrupted. a read of the spi data register by the system controller actually reads the receive buffer. if the receive buffer still holds unread data from a prev ious transfer when the last bit of the current transfer is shifted into the spi shift register, a receive overrun occurs and the rxovrn flag (spi0cn.4) is set to logic 1. the new data is not transferred to the receive buffer, allowi ng the previously received data byte to be read. the data by t e causi ng t h e overrun i s l o st . rec e ive b u f f er 0 1 2 3 4 5 6 7 s p i s h ift re gis t e r s l av e d e v i c e mo s i mi s o ns s r e ce i v e b u ffe r 0 1 2 3 4 5 6 7 spi s h i f t r e gi st er m a st er d e v i c e mo s i mi s o ns s vd d b a ud rat e gener at or sc k s c k px . y 125 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 in an ?off-line? state. in a m u ltiple-m aster environm ent, the system controller should check the state of the slvsel flag (spi0 c n.2 ) to en su re th e b u s is free b e fo re settin g th e msten b it an d in itiatin g a d a ta tran sfer. 17.3. serial clock timing as shown i n fi gure 17.4, four com b i n at i ons of seri al cl ock phase and pol ari t y can be sel ect ed usi ng t h e cl ock cont rol bi t s i n t h e spi c onfi gurat i on r e gi st er (spi0c fg). the c k pha bi t (spi0c fg.7) sel ect s one of t w o cl ock phases (edge used t o l a t c h t h e dat a ). the c k pol bi t (spi0c fg.6) sel ect s bet w een an act i v e-hi gh or act i v e-l o w cl ock. b o t h m a st er and sl ave devi ces m u st be confi gured t o use t h e sam e cl ock phase and pol ari t y . not e : t h e spi shoul d be di sabl ed (by cl eari ng t h e spien bi t , spi0c n.0) whi l e changi ng t h e cl ock phase and pol ari t y . the spi c l ock r a t e r e gi st er (spi0c kr ) as shown i n fi gure 17.7 cont rol s t h e m a st er m ode seri al cl ock frequency . thi s regi st er i s i gnored when operat i ng i n sl ave m ode. figure 17.4. data/clock timing diagram sck (c k pol = 0, ck pha = 0 ) sck (c k pol = 1 , c k pha = 0 ) sck (c k pol = 1 , c k pha = 1 ) sck (c k pol = 0, ck pha = 1 ) ms b bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb miso/mosi nss r e v. 1.7 126
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 17.4. spi special function registers the spi is accessed and controlled through four special func tion registers in the system controller: spi0cn control r e gi st er, spi0dat dat a r e gi st er, spi0c fg c onfi gurat i on r e gi st er, and spi0c kr c l ock r a t e r e gi st er. the four speci al funct i on regi st ers rel a t e d t o t h e operat i on of t h e spi b u s are descri bed i n t h e fol l o wi ng sect i on. figure 17.5. spi0cfg: spi configuration register r/w r / w r r r/w r / w r / w r e s e t v a l u e c k p h a c k p o l b c 2 b c 0 s p i f r s 2 s p i f r s 1 0 0 0 0 0 1 1 1 b i t 7 b i t 5 b i t 4 b i t 3 b i t 1 b i t 0 sfr address: 0 x 9 a r b c 1 s p i f r s 0 b i t 6 bit7: ckpha: spi clock phase. thi s bi t cont rol s t h e spi cl ock phase. 0: dat a sam p l e d on fi rst edge of sc k peri od. 1: dat a sam p l e d on second edge of sc k peri od. bit6 : ckpol: spi clo c k po larity. th is b it co n t ro ls th e spi clo c k p o l arity. 0 : sck lin e lo w in id le state. 1 : sck lin e h i g h in id le state. b i t s 5-3: b c 2 -b c 0 : spi b i t c ount . in d i cates wh ich o f th e u p to 8 b its o f th e spi wo rd h a v e b een tran sm itted . bc2 - bc0 bit tra n smitted 0 0 0 b i t 0 (lsb ) 0 0 1 b i t 1 0 1 0 b i t 2 0 1 1 b i t 3 1 0 0 b i t 4 1 0 1 b i t 5 1 1 0 b i t 6 1 1 1 b i t 7 (m sb ) bits2-0: spifrs2-spifrs0: spi fram e size. th ese th ree b its d e term in e th e n u m b e r o f b its to sh ift in /o u t o f th e spi sh ift reg i ster duri ng a dat a t r ansfer i n m a st er m ode. they are i gnored i n sl ave m ode. spifrs bits shifted 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 . b i t 2 8 127 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 17.6. spi0cn: spi control register r/w r / w r/w r / w r r r/w r / w r e s e t v a l u e s p i f w c o l m o d f r x o v r n t x b s y s l v s e l m s t e n s p i e n 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: (bit addressable) 0xf8 bit7: spif: spi interrupt flag. th is b it is set to lo g i c 1 b y h a rd ware at th e en d o f a d a ta tran sfer. if in terru p t s are en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e spi0 in terru p t serv ice ro u tin e. th is b it is not autom a tically cleared by hardware. it m u st be cleared by software. bit6 : w c ol: w r ite co llisio n flag . th is b it is set to lo g i c 1 b y h a rd ware (an d g e n e rates a spi in terru p t ) to in d i cate a write to th e spi d a ta reg i ster was attem p ted wh ile a d a ta tran sfer was in p r o g r ess. it is cleared b y software. bit5 : modf: mo d e fau lt flag . thi s bi t i s set t o l ogi c 1 by hardware (and generat e s a spi i n t e rrupt ) when a m a st er m ode co llisio n is d e tected (nss is lo w an d msten = 1 ) . th is b it is n o t au to m a tically cleared b y hardware. it m u st be cleared by software. bit4: rxovrn: receive overrun flag. this bit is set to logic 1 by hardware (a nd generates a spi interrupt) when the receive b u ffer still h o l d s u n r ead d a ta fro m a p r ev io u s tran sfer an d th e last b it o f th e cu rren t tran sfer is sh ifted in to th e spi sh ift reg i ster. th is b it is n o t au to m a tically cleared b y h a rd ware. it m u st be cleared by software. bit3 : txbsy: tran sm it bu sy flag . th is b it is set to lo g i c 1 b y h a rd ware wh ile a m a ster m o d e tran sfer is in p r o g r ess. it is cleared by hardware at the end of the transfer. bit2: slvsel: slave selected flag. th is b it is set to lo g i c 1 wh en ev er th e nss p i n is lo w in d i catin g it is en ab led as a slav e. it i s cl eared t o l ogi c 0 when nss i s hi gh (sl a ve di sabl ed). bit1 : msten: master mo d e en ab le. 0: di sabl e m a st er m ode. operate in slave m ode. 1: enable m a ster m ode. operate as a m a ster. bit0 : spien: spi en ab le. th is b it en ab les/d i sab l es th e spi. 0: spi di sabl ed. 1: spi enabled. r e v. 1.7 128
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 17.7. spi0ckr: spi clock rate register r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e s c r 7 s c r 6 s c r 5 s c r 4 s c r 3 s c r 2 s c r 1 s c r 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 9 d bits7 - 0 : scr7 -scr0 : spi clo c k rate these bi t s det e rm i n e t h e frequency of t h e sc k out put when t h e spi m odul e i s confi gured for m a st er m ode operat i on. the sc k cl ock frequency i s a di vi ded down versi on of t h e sy st em cl ock, and i s gi ven i n t h e fol l o wi ng equat i ons: f sck = 0.5 * f sysclk / (spi0c kr + 1), for 0 d spi0ckr d 255, figure 17.8. spi0dat: spi data register r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 9 b bits7-0: spi0dat: spi0 transm it and receive data. the spi0dat register is used to transm it a nd receive spi data. w r iting data to spi0dat places the data im m e diately into the shift regi ster and initiates a tran sfer when in master mode. a read of spi0dat returns the contents of the receive buffer. 129 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 18. uart the uar t i s a seri al port capabl e of asy n chronous t r ansm i ssi on. the uar t can funct i on i n ful l dupl ex m ode. in all m odes, receive data is buffered in a holding register. this allows the uart to start reception of a second i n com i ng dat a by t e before soft ware has fi ni shed readi ng t h e previ ous dat a by t e . the uart has an associated serial cont rol register (scon) and a serial da ta buffer (sbuf) in the sfrs. the single sbuf location provides access to bot h transm it and receive registers. reads access the receive register and writes access the transm it regi ster autom a tically. the uar t i s capabl e of generat i ng i n t e rrupt s i f enabl e d. the uar t has t w o sources of i n t e rrupt s: a transm i t interrupt flag, ti (scon.1) set when transm ission of a da ta byte is com p lete, and a receive interrupt flag, ri (scon.0) set when reception of a data byte is com p lete . the uart interrupt flags ar e not cleared by hardware wh en th e cpu v ecto r s to th e in terru p t serv ice ro u tin e. th ey m u st be cleared m a nually b y so ftware. th is allo ws software to determ ine the cause of the uart interrupt (transm it com p lete or receive com p lete). figure 18.1. uart block diagram sbuf shift load sbuf sfr bus input shift register (9 bits) bit detector read sbuf rx control start rx clock load sbuf 0x1ff shift tx control tx clock serial port interrupt tx irq zero detector send shift sbuf sfr bus set q d clr stop bit gen. tb8 start 01 00 10 11 smod 1 0 01 00 10 11 timer 2 overflow tclk 1 0 rclk 1 0 timer 1 overflow scon s m 2 t b 8 r b 8 t i r i pcon s m o d smod data write to sbuf s m 1 s m 0 r e n enable ren t2con r c l k t c l k sysclk msb rb8 rx irq ti ri crossbar baud rate generation logic crossbar rx tx port i/o 1 0 32 64 12 sm0, sm1 {mode} 16 16 2 r e v. 1.7 130
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 18.1. uart operational modes the uart provides four operating m odes (one synchronous and three as ynchronous) selected by setting confi gurat i on bi t s i n t h e sc on regi st er. these four m ode s offer different baud rates a nd com m uni cat i on prot ocol s. the four m odes are sum m a ri zed i n tabl e 18.1 bel o w. det a i l e d descri pt i ons fol l o w. table 18.1. uart modes m ode sy nchroni zat i on b a ud c l ock dat a b i t s st art / s t op b i t s 0 s y n c h r o n o u s sysc lk/ 1 2 8 n o n e 1 asy n chronous ti m e r 1 or ti m e r 2 overfl ow 8 1 st art , 1 st op 2 asy n chronous sysc lk/ 32 or sysc lk/ 64 9 1 st art , 1 st op 3 asy n chronous ti m e r 1 or ti m e r 2 overfl ow 9 1 st art , 1 st op 18.1.1. mode 0: synchronous mode mode 0 provides synchronous , half-duplex com m unication. serial data is transm itted and received on the rx pin. the tx pin provides the shift clock for both transm it and r eceive. the mcu m u st be the m a ster since it generates t h e shi f t cl ock for t r ansm i ssi on i n bot h di rect i ons (see t h e i n t e rconnect di agram i n fi gure 18.2). eight data bits are transm itted/received, lsb first (see the tim ing diagram in figure 18.3). data transm ission begins wh en an in stru ctio n writes a d a ta b y te to th e sbuf reg i ster. th e ti tran sm it in terru p t flag (scon.1 ) is set at th e end of the eighth bit tim e. data reception begins when th e ren receive enable bit (scon.4) is set to logic 1 and the ri receive interrupt flag (scon.0) is cleared. one cycle after the eighth bit is shifted in, the ri flag is set and reception stops until software clears the ri bit. an interrupt will o ccur if enabled when eith er ti or ri is set. the m ode 0 baud rat e i s t h e sy st em cl ock frequency di vi ded by t w el ve. r x i s forced t o open-drai n i n m ode 0, and an ex tern al p u ll-u p will typ i cally b e req u i red . figure 18.2. uart mode 0 interconnect figure 18.3. uart mode 0 timing diagram 18.1.2. mode 1: 8-bit uart, variable baud rate tx (clk out) shift reg. clk c8051fxxx rx tx data 8 extra out p uts d1 d0 d2 d3 d4 d5 d6 d7 rx (data out) mode 0 transmit d0 mode 0 receive rx (data in) d1 d2 d3 d4 d5 d6 d7 tx (clk out) 131 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 m ode 1 provi des st andard asy n chronous, ful l dupl ex com m uni ca t i on usi ng a t o t a l of 10 bi t s per dat a by t e : one st art b it, eig h t d a ta b its (lsb first), an d o n e sto p b it (see th e tim in g d i ag ram in fig u r e 1 8 . 4 ) . data are tran sm itted fro m the tx pin and received at the rx pin (see the interconnecti on diagram in figure 18.5). on receive, the eight data bi t s are st ored i n sb uf and t h e st op bi t goes i n t o r b 8 (sc on.2). data tran sm issio n b e g i n s wh en an in stru ctio n writes a d a ta b y te to th e sbuf reg i ster. th e ti tran sm it in terru p t flag (scon.1) is set at the end of the transm ission (the beginning of the st op-bit tim e). data reception can begin any tim e after the ren receive enable bit (scon.4) is set to logic 1. after th e stop bit is received, the data byte will be loaded into the sbuf receive register if th e following conditions are m e t: ri m u st be logic 0, and if sm2 is l ogi c 1, t h e st op bi t m u st be l ogi c 1. if th ese co n d itio n s are m e t, th e eig h t b its o f d a ta are sto r ed in sbuf, th e sto p b it is sto r ed in rb8 , an d th e ri flag is set. if th ese co n d itio n s are n o t m e t, sbuf an d rb8 will n o t b e lo ad ed an d th e ri flag will n o t b e set. an in terru p t will o ccu r if en ab led wh en eith er ti o r ri is set. figure 18.4. uart mode 1 timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space the baud rat e generat e d i n m ode 1 i s a funct i on of t i m er overfl ow. the uar t can use ti m e r 1 operat i ng i n 8-bi t c ount er/ t i m er w i t h aut o -rel oad mode , or ti m e r 2 operat i ng i n baud rat e generat o r mode t o generat e t h e baud rate (note that the tx and rx clock sources are selected separately). on each tim er overflow event (a rollover from all ones (0xff for tim e r 1, 0xffff for tim e r 2) to zer o), a clock is sent to the baud rate logic. w h en ti m e r 1 i s sel ect ed as a baud rat e source, t h e sm od bi t (pc on.7) sel ect s whet her or not t o di vi de t h e tim e r 1 o v e rflo w rate b y two . on reset, th e smod b it is l ogi c 0, t hus sel ect i ng t h e l o wer speed baud rat e by defaul t . the sm od bi t affect s t h e baud rat e generat e d by ti m e r 1 as fol l o ws: mode 1 baud rate = ( 1 / 32) * t1_overflowrat e ( w hen the smod bit is set to logic 0) . mode 1 baud rate = ( 1 / 16) * t1_overflowrat e ( w hen the smod bit is set to logic 1) . w h en tim e r 2 is selected as a baud rate source, t h e baud rat e generat e d by ti m e r 2 i s as fol l o ws: mode 1 baud rate = ( 1 / 16) * t2_overflowrate. the ti m e r 1 overfl ow rat e i s det e rm i n ed by t h e ti m e r 1 cl ock source (t1c lk) and rel o ad val u e (th1). the frequency of t1clk can be selected as sysclk, sysclk/ 12, or an ext e rnal cl ock source. the ti m e r 1 overfl ow rate can b e calcu lated as fo llo ws: t1_overflowrate = t1clk / ( 256 ? th1) . for exam pl e, assum e tm od = 0x20. if t1m (c kc on.4) i s l ogi c 1, t h en t h e above equat i on becom e s: t1_overflowrate = ( s ysclk) / ( 256 ? th1) . if t1m (c kc on.4) i s l ogi c 0, t h en t h e above equat i on becom e s: t1_overflowrate = ( s ysclk/12) / ( 256 ? th1) . r e v. 1.7 132
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 the ti m e r 2 overfl ow rat e , when i n baud rat e generat o r mode and usi ng an i n t e rnal cl ock source, i s det e rm i n ed sol e l y by t h e ti m e r 2 16-bi t rel o ad val u e (r c a p2h: r c a p2l). the ti m e r 2 cl ock source i s fi xed at sysc lk/ 2 . the tim e r 2 overflow rate can be calculated as follows: t2_overflowrate = ( s ysclk/2) / ( 65536 ? [ r cap2h:rcap2l] ) . ti m e r 2 can be sel ect ed as t h e baud rat e generat o r fo r r x and/ or tx by set t i ng r c l k (t2c on.5) and/ or tc lk (t2 c on.4 ) , resp ectiv ely. w h en eith er rclk o r tclk is set to lo g i c 1 , tim e r 2 in terru p t s are au to m a tically d i sab l ed an d th e tim er is fo rced in to baud rat e generat o r mode wi t h sysc lk/ 2 as i t s cl ock source. if a di fferent tim eb ase is req u i red , settin g th e c/t2 b it (t2 c on.1 ) to lo g i c 1 will allo w tim e r 2 to b e clo c k e d fro m th e ex tern al i nput pi n t2. see t h e ti m e rs sect i on for com p l e t e t i m er confi gurat i on det a i l s . figure 18.5. uart modes 1, 2, and 3 interconnect diagram or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx 133 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 18.1.3. mode 2: 9-bit uart, fixed baud rate m ode 2 provi des asy n chronous, ful l - dupl ex com m uni cat i on usi ng a t o t a l of el even bi t s per dat a by t e : a st art bi t , 8 dat a bi t s (lsb fi rst ) , a program m a bl e ni nt h dat a bi t , and a st op bi t (see t i m i ng di agram i n fi gure 1 . 6 ) . on t r ansm i t , t h e ni nt h dat a bi t i s det e rm i n ed by t h e val u e i n tb 8 (sc on.3). it can be assi gned t h e val u e of t h e pari t y fl ag p i n the psw or used in m u ltiprocessor com m unications. on receive, the ninth data bit goes into rb8 (scon.2) and the st op bi t i s i gnored. 8 data tran sm issio n b e g i n s wh en an in stru ctio n writes a d a ta b y te to th e sbuf reg i ster. th e ti tran sm it in terru p t flag (scon.1) is set at the end of the transm ission (the beginning of the st op-bit tim e). data reception can begin any tim e after the ren receive enable bit (scon.4) is set to logic 1. after th e stop bit is received, the data byte will be loaded into the sb uf receive register if the following cond itions are m e t: ri m u s t b e l o g i c 0 , a n d if sm2 is l ogi c 1, t h e 9 th bi t m u st be l ogi c 1. if th ese co n d itio n s are m e t, th e eig h t b its o f d a ta are sto r ed in sbuf, th e n i n t h b it is sto r ed in rb8 an d th e ri flag is set. if th ese co n d itio n s are n o t m e t, sbuf an d rb8 will n o t b e lo ad ed an d th e ri flag will n o t b e set. an in terru p t will o ccu r if en ab led wh en eith er ti o r ri are set. the baud rat e i n m ode 2 i s a di rect funct i on of t h e sy st em cl ock frequency as fol l o ws: mode 2 baud rat e = 2 smod * ( s ysc l k / 64) . the sm od bi t (pc on.7) sel ect s whet her t o di vi de sysc lk by 32 or 64. in t h e form ul a, 2 i s rai s ed t o t h e power sm od, resul t i ng i n a baud rat e of ei t h er 1/ 32 or 1/ 64 of t h e sy st em cl ock frequency . on reset , t h e sm od bi t i s l ogi c 0, t hus sel ect i ng t h e l o wer speed baud rat e by defaul t . figure 18.6. uart modes 2 and 3 timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 18.1.4. mode 3: 9-bit uart, variable baud rate mo d e 3 is th e sam e as mo d e 2 in all resp ects ex cep t th e b a u d rate is v a riab le. th e b a u d rate is d e term in ed in th e sam e m a nner as for m ode 1. m ode 3 o p e ratio n tran sm its 1 1 b its: a start b it, 8 d a ta b its (lsb first), a p r o g r am m a b l e ni nt h dat a bi t , and a st op bi t . ti m e r 1 or ti m e r 2 overfl ows generat e t h e baud rat e just as wi t h m ode 1. in sum m a ry , m ode 3 t r ansm i t s usi ng t h e sam e prot ocol as m ode 2 but wi t h m ode 1 baud rat e generat i on. r e v. 1.7 134
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 18.2. multiprocessor communications modes 2 and 3 support m u ltiprocessor com m unication between a m a ster processor and one or m o re slave processors by speci al use of t h e ni nt h dat a bi t . w h en a m a st er processor want s t o t r ansm i t t o one or m o re sl aves, i t fi rst sends an ad d r ess b y te to select th e targ et(s). an ad d r ess b y te d i ffers fro m a d a ta b y te in th at its n i n t h b it is lo g i c 1 ; in a d a ta b y te, th e n i n t h b it is always set to lo g i c 0 . setting the sm2 bit (scon.5) of a slave processor configures its uart such th at when a stop bit is received, the uart will g e n e rate an in terru p t o n l y if th e n i n t h b it is lo g i c o n e (rb8 = 1 ) sig n i fyin g an ad d r ess b y te h a s b een received. in the uart?s interrupt handler, software will com p are the r eceived address with the slave?s own assigned 8-bit address. if the addresses m a tch, the slave will clear its sm2 bit to enab le interrupts on the reception of t h e fol l o wi ng dat a by t e (s). sl aves t h at weren?t addre ssed l eave t h ei r sm 2 bi t s set and do not generat e i n t e rrupt s on the reception of the following data by tes, thereby ignoring the data. once the entire m e ssage is received, the addressed slave resets its sm2 bit to ignore all tr ansm issions until it receives the next address byte. mu ltip le ad d r esses can b e assig n e d to a sin g l e slav e an d / o r a sin g l e ad d r ess can b e assig n e d to m u ltip le slav es, thereby enabling ?broadcas t? tran sm issio n s to m o re th an o n e slav e si m u l t a neousl y . the m a st er processor can be configured to receive all transm issions or a protocol can be im plem ented su ch that the m a ster/slave role is t e m porari l y reversed t o enabl e hal f-dupl ex t r ansm i ssi on bet w een t h e ori g i n al m a st er and sl ave(s). figure 18.7. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx vdd 135 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 table 18.2. oscillator frequencies for standard baud rates oscillator frequency (mhz ) divide factor timer 1 load value* resulting baud rate** 2 4 . 0 2 0 8 0 x f 3 1 1 5 2 0 0 ( 1 1 5 3 8 4 ) 2 3 . 5 9 2 2 0 5 0 x f 3 1 1 5 2 0 0 ( 1 1 3 4 2 3 ) 2 2 . 1 1 8 4 1 9 2 0 x f 4 1 1 5 2 0 0 1 8 . 4 3 2 1 6 0 0 x f 6 1 1 5 2 0 0 1 6 . 5 8 8 8 1 4 4 0 x f 7 1 1 5 2 0 0 1 4 . 7 4 5 6 1 2 8 0 x f 8 1 1 5 2 0 0 1 2 . 9 0 2 4 1 1 2 0 x f 9 1 1 5 2 0 0 1 1 . 0 5 9 2 9 6 0 x f a 1 1 5 2 0 0 9 . 2 1 6 8 0 0xfb 1 1 5 2 0 0 7 . 3 7 2 8 6 4 0xfc 1 1 5 2 0 0 5 . 5 2 9 6 4 8 0 x f d 1 1 5 2 0 0 3 . 6 8 6 4 3 2 0 x f e 1 1 5 2 0 0 1 . 8 4 3 2 1 6 0 x f f 1 1 5 2 0 0 2 4 . 5 7 6 3 2 0 0xec 7 6 8 0 0 2 5 . 0 4 3 4 0 x e 5 5 7 6 0 0 ( 5 7 8 7 0 ) 2 5 . 0 8 6 8 0xc a 2 8 8 0 0 2 4 . 5 7 6 8 4 8 0xc b 2 8 8 0 0 ( 2 8 9 2 1 ) 2 4 . 0 8 3 3 0xc c 2 8 8 0 0 ( 2 8 8 4 6 ) 2 3 . 5 9 2 8 1 9 0xc d 2 8 8 0 0 ( 2 8 9 1 1 ) 2 2 . 1 1 8 4 7 6 8 0 x d 0 2 8 8 0 0 1 8 . 4 3 2 6 4 0 0 x d 8 2 8 8 0 0 1 6 . 5 8 8 8 5 7 6 0xdc 2 8 8 0 0 1 4 . 7 4 5 6 5 1 2 0 x e 0 2 8 8 0 0 1 2 . 9 0 2 4 4 4 8 0 x e 4 2 8 8 0 0 1 1 . 0 5 9 2 3 8 4 0 x e 8 2 8 8 0 0 9 . 2 1 6 3 2 0 0xec 2 8 8 0 0 7 . 3 7 2 8 2 5 6 0 x f 0 2 8 8 0 0 5 . 5 2 9 6 1 9 2 0 x f 4 2 8 8 0 0 3 . 6 8 6 4 1 2 8 0 x f 8 2 8 8 0 0 1 . 8 4 3 2 6 4 0xfc 2 8 8 0 0 * assum e s sm od=1 and t1m = 1. ** num b ers i n parent hesi s show t h e act ual baud rat e . figure 18.8. sbuf: serial (uart) data buffer register r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 9 9 b i t s 7-0: sb uf.[7: 0] : seri al da ta buffer bits 7-0 (m sb-lsb) this is actually two registers; a transm it and a receive buffer register. w h en data is m oved to sbuf, it g o e s to th e tran sm it b u ffer an d is h e ld fo r serial tran sm issio n . mo v i n g a b y te to sbuf is wh at in itiates th e tran sm issio n . w h en d a ta is m o v e d fro m sbuf, it co m e s fro m th e receive buffer. r e v. 1.7 136
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 18.9. scon: serial port control register r/w r / w r/w r / w r/w r / w r / w r e s e t v a l u e s m 0 s m 1 s m 2 r e n t b 8 r b 8 t i r i b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 (bit addressable) r / w 00000000 sfr address: 0x98 b i t s 7-6: sm 0-sm 1: seri al port operat i on m ode. these bits select the seri al port operat i on m ode. sm0 sm1 mode 0 0 m ode 0: sy nchronous m ode 0 1 m ode 1: 8-b i t uar t, vari abl e b a ud r a t e 1 0 m ode 2: 9-b i t uar t, fi xed b a ud r a t e 1 1 m ode 3: 9-b i t uar t, vari abl e b a ud r a t e bit5 : sm2 : mu ltip ro cesso r co m m u n i catio n en ab le. the funct i on of t h i s bi t i s dependent on t h e seri al port operat i on m ode. m ode 0: no effect m ode 1: c h ecks for val i d st op bi t . 0: logi c l e vel of st op bi t i s i gnored. 1 : ri will o n l y b e activ ated if sto p b it is lo g i c lev e l 1 . mo d e 2 an d 3 : mu ltip ro cesso r co m m u n i catio n s en ab le. 0: logi c l e vel of ni nt h bi t i s i gnored. 1: r i i s set and an i n t e rrupt i s generat e d onl y when t h e ni nt h bi t i s l ogi c 1. bit4: ren: receive enable. this bit enables/disables the uart receiver. 0: uart reception disabled. 1: uart reception enabled. b i t 3 : tb 8: ni nt h transm i ssi on b i t . th e lo g i c lev e l o f th is b it will b e assig n e d to th e n i n t h tran sm issio n b it in mo d e s 2 an d 3 . it i s not used i n m odes 0 and 1. set or cl eared by soft ware as requi red. bit2: rb8: ninth receive bit. the bit is assigned the logic level of the ninth b it received in modes 2 and 3. in mode 1, if sm2 is logic 0, rb8 is assigned the logic level of the received stop bit. rb8 is not used in m ode 0. bit1 : ti: tran sm it in terru p t flag . set b y h a rd ware wh en a b y te o f d a ta h a s b een tran sm itted b y th e uart (after th e 8 th b it in m ode 0, or at t h e begi nni ng of t h e st op bi t i n ot her m odes). w h en t h e uar t i n t e rrupt i s en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e uart in terru p t serv ice ro u tin e. th is b it m u st b e cleared m a n u a lly b y so ftware bit0: ri: receive interrupt flag. set by hardware when a byte of data ha s been received by the uart (after the 8 th b it in m ode 0, or aft e r t h e st op bi t i n ot her m odes ? see sm 2 bi t for except i on). w h en t h e uart in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e uart in terru p t serv ice ro u tin e. th is b it m u st be cleared m a nually by software. 137 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 19. timers each mcu im plem ents four counter/tim ers: three are 16-bit counter/tim ers co m p atible with those found in the st andard 8051, and one i s a 16-bi t t i m er for use wi t h t h e adc , sm b u s, or for general purpose use. these can be used t o m easure t i m e i n t e rval s, count ext e rnal event s and generat e peri odi c i n t e rrupt request s. ti m e r 0 and ti m e r 1 are n early id en tical an d h a v e fo u r p r im ary m o d e s o f o p e ratio n . tim e r 2 o ffers ad d itio n a l cap ab ilities n o t av ailab l e i n ti m e rs 0 and 1. ti m e r 3 i s si m i l a r t o ti m e r 2, but wi t hout t h e capt u re or b a ud r a t e generat o r m odes. ti m e r 0 and ti m e r 1: t i m e r 2: tim e r 3: 16-bit count er/tim er with auto-reload 16- bit tim er with auto-reload 16-bit counter/tim er 16-bit c ounter/tim er with capture 8-bit counter/tim er with auto-re load baud rate generator two 8-bit counter/tim ers (tim er 0 only) 13-bit counter/tim er w h en functioning as a tim er, the counter/tim er registers are increm ented on each clock tick. clock ticks are derived from t h e sy st em cl ock di vi ded by ei t h er one or t w el ve as speci fi ed by t h e ti m e r c l ock sel ect bi t s (t2m -t0m ) i n ckcon. the twelve-clocks-per-tick option provides com p atibility with the older generation of the 8051 fam ily. applications that require a faster tim er can use t h e one-cl o ck-per-t i c k opt i on. w h en functioning as a counter, a counter/tim er register is increm ented on each hi gh-to-low transition at the selected i nput pi n for t0, t1, or t2. event s wi t h a frequency of up t o one-fourt h t h e sy st em cl ock?s frequency can be count ed. the i nput si gnal need not be peri odi c, but i t shoul d be hel d at a gi ven l e vel for at l east t w o ful l sy st em clock cycles to ensure the level is sam p led. the th0 register holds the eight msbs of the 13-bit count er/tim er. tl0 holds the five lsbs in bit positions tl0.4- tl0.0. the t h ree upper bi t s of tl0 ( tl0.7-tl0.5) are i ndet e rm i n at e and shoul d be m a sked out or i gnored when reading. as the 13-bit tim er re gister increm ents and overflows fro m 0x1fff (all ones) to 0x0000, the tim er o v e rflo w flag tf0 (tcon.5 ) is set an d an in terru p t will o ccu r if en ab led . 19.1. timer 0 and timer 1 tim e r 0 and tim e r 1 are accessed and c ontrolled through sfrs. each counter /tim er is im plem ented as a 16-bit register accessed as two separate by tes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the c ount er/ t i m er c ont rol (tc on) regi st er i s used t o enabl e ti m e r 0 and ti m e r 1 as wel l as i ndi cat e t h ei r st at us. b o t h counter/tim ers operate in one of four prim ary m odes sel ected by setting the mode se lect bits m1-m0 in the c ount er/ t i m er m ode (tm od) regi st er. each t i m er can be confi gured i ndependent l y . fol l o wi ng i s a det a i l e d description of each operating m ode. 19.1.1. mode 0: 13-bit counter/tim er tim e r 0 and tim e r 1 operate as a 13-bit counter/tim er in mode 0. the following desc ribes the configuration and operat i on of ti m e r 0. however, bot h t i m ers operat e i d ent i cal l y and ti m e r 1 i s confi gured i n t h e sam e m a nner as described for tim e r 0. the c/t0 bit (tmod.2) selects the count er/tim er?s clock source. clearing c/t se lects the system clock as the input for t h e t i m er. w h en c / t0 i s set t o l ogi c 1, hi gh-t o -l ow t r ansi t i ons at t h e sel ect ed i nput pi n i n crem ent t h e t i m er register. (refer to port i/o sec t i on 15.1 for i n form at i on on sel ect i ng and confi guri ng ext e rnal i/ o pi ns.) r e v. 1.7 138
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 set t i ng t h e tr 0 bi t (tc on.4) enabl e s t h e t i m er when ei t h er gate0 (tm od.3) i s 0 or t h e i nput si gnal / i nt0 i s l ogi c-l e vel one. set t i ng gate0 t o l ogi c 1 al l o ws t h e t i m er t o be cont rol l e d by t h e ext e rnal i nput si gnal / i nt0, facilitatin g p u l se wid t h m easu r em en ts. t r 0 g a t e 0 / i n t 0 c o u n t e r / t i m e r 0 x x d i s a b l e d 1 0 x enabl e d 1 1 0 di sabl e d 1 enabl e d x = don?t care 1 1 setting tr0 does not reset the tim er register. the tim er re gister should be initialized to the desired value before enabling the tim er. tl1 and th1 form t h e 13-bi t regi st er for ti m e r 1 i n t h e sam e m a nner as descri bed above for tl0 and th0. ti m e r 1 i s confi gured and cont rol l e d usi ng t h e rel e vant tc on and tm od bi t s just as wi t h ti m e r 0. 19.1.2. mode 1: 16-bit counter/tim er figure 19.1. t0 mode 0 block diagram tl0 (5 bits) th0 (8 bits) gate0 /int0 tr0 t0 sysclk 12 0 1 1 0 tclk tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt ckcon t 2 m t 1 m t 0 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 crossbar crossbar mode 1 operation is the sam e as mode 0, except that th e counter/tim er registers use all 16 bits. the counter/tim ers are enabl e d and confi gured i n m ode 1 i n t h e sam e m a nner as for m ode 0. 139 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 19.1.3. mode 2: 8-bit counter/tim er with auto-reload mode 2 configures tim e r 0 and tim e r 1 to operate as 8-bit counter/tim ers with autom a tic reload of the start value. the tl0 hol ds t h e count and th0 hol ds t h e rel o ad val u e. w h en t h e count i n tl0 overfl ows from al l ones t o 0x00, t h e t i m er overfl ow fl ag tf0 (tc on.5) i s set and t h e count er i n tl0 i s rel o aded from th0. if enabl e d, an i n t e rrupt will o ccu r wh en th e tf0 flag is set. th e relo ad v a lu e in th0 is n o t ch an g e d . tl0 m u st b e in itialized to th e d e sired val u e before enabl i ng t h e t i m er for t h e fi rst count t o be correct . w h en i n m ode 2, ti m e r 1 operat e s i d ent i cal l y t o tim e r 0. both counter/tim ers are enabled and confi gured in mode 2 in the sam e m a nner as mode 0. figure 19.2. t0 mode 2 block diagram tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 gate0 /int0 tr0 t0 sysclk 12 0 1 1 0 interrupt tclk tl0 (8 bits) reload th0 (8 bits) ckcon t 2 m t 1 m t 0 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 crossbar crossbar r e v. 1.7 140
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 19.1.4. mode 3: two 8-bit counter/timers (timer 0 only) tim e r 0 and tim e r 1 behave diffe rently in mode 3. tim e r 0 is configured as two separate 8-bit counter/tim ers held in tl0 and th0. the counter/tim er in tl0 is controlled using the tim e r 0 control/status bits in tcon and tmod: tr 0, c / t0, gate0 and tf0. it can use ei t h er t h e sy st em cl ock or an ext e rnal i nput si gnal as i t s t i m ebase. the th0 regi st er i s rest ri ct ed t o a t i m er funct i on sourced by t h e sy st em cl ock. th0 i s enabl e d usi ng t h e ti m e r 1 run cont rol bi t tr 1. th0 set s t h e ti m e r 1 overfl ow fl ag tf1 on overfl ow and t hus cont rol s t h e ti m e r 1 i n t e rrupt . tim e r 1 is in activ e in mo d e 3 , so with tim e r 0 in mo d e 3, ti m e r 1 can be t u rned off and on by swi t c hi ng i t i n t o and out of i t s m ode 3. w h en ti m e r 0 i s i n m ode 3, ti m e r 1 can be operat e d i n m odes 0, 1 or 2, but cannot be cl ocked by ext e rnal si gnal s nor set t h e tf1 fl ag and generat e an i n t e rrupt . however, t h e ti m e r 1 overfl ow can be used for baud rat e generat i on. r e fer t o sect i on 18 (uar t) for i n form at i on on confi guri ng ti m e r 1 for baud rat e generat i on. figure 19.3. t0 mode 3 block diagram tl0 (8 bits) th0 (8 bits) gate0 /int0 tr0 t0 sysclk c/t0 12 0 1 1 0 tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt ckcon t 2 m t 1 m t 0 m crossbar crossbar 141 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 19.4. tcon: timer control register r/w r/w r / w r/w r / w r e s e t v a l u e t f 1 t r 1 i e 1 i e 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 3 b i t 2 b i t 0 sfr address: (bit addressable) r / w r / w r / w tf0 tr0 it1 i t 0 b i t 4 b i t 1 0x88 b i t 7 : tf1: ti m e r 1 overfl ow fl ag. set by hardware when ti m e r 1 overfl ows. thi s fl ag can be cl eared by soft ware but i s autom a tically cleared when th e cpu v ecto r s to th e tim e r 1 in terru p t serv ice ro u tin e. 0: no ti m e r 1 overfl ow det ect ed. 1: ti m e r 1 has overfl owed. b i t 6 : tr 1: ti m e r 1 r un c ont rol . 0: ti m e r 1 di sabl ed. 1: ti m e r 1 enabl e d. b i t 5 : tf0: ti m e r 0 overfl ow fl ag. set by hardware when ti m e r 0 overfl ows. thi s fl ag can be cl eared by soft ware but i s autom a tically cleared when th e cpu v ecto r s to th e tim e r 0 in terru p t serv ice ro u tin e. 0: no ti m e r 0 overfl ow det ect ed. 1: ti m e r 0 has overfl owed. b i t 4 : tr 0: ti m e r 0 r un c ont rol . 0: ti m e r 0 di sabl ed. 1: ti m e r 0 enabl e d. bit3 : ie1 : ex tern al in terru p t 1 . th is flag is set b y h a rd ware wh en an ed g e /lev e l of t y pe defi ned by it1 i s det ect ed. it can be cleared by software but is autom a tically cleared when th e cpu vectors to the external int e rrupt 1 servi ce rout i n e i f it1 = 1. thi s fl ag i s t h e i nverse of t h e / i nt1 i nput si gnal ? s l ogi c l e vel when it1 = 0. b i t 2 : it1: int e rrupt 1 ty pe sel ect . th is b it selects wh eth e r th e co n f ig u r ed /int1 sig n a l will d e tect fallin g ed g e o r activ e-lo w lev e l-sen s itiv e in terru p t s. 0 : /int1 is lev e l trig g e red . 1: / i nt1 i s edge t r i ggered. bit1 : ie0 : ex tern al in terru p t 0 . th is flag is set b y h a rd ware wh en an ed g e /lev e l of t y pe defi ned by it0 i s det ect ed. it can be cleared by software but is autom a tically cleared when th e cpu vectors to the external int e rrupt 0 servi ce rout i n e i f it0 = 1. thi s fl ag i s t h e i nverse of t h e / i nt0 i nput si gnal ? s l ogi c l e vel when it0 = 0. b i t 0 : it0: int e rrupt 0 ty pe sel ect . th is b it selects wh eth e r th e co n f ig u r ed /int0 sig n a l will d e tect fallin g ed g e o r activ e-lo w lev e l-sen s itiv e in terru p t s. 0 : /int0 is lev e l trig g e red . 1: / i nt0 i s edge t r i ggered. r e v. 1.7 142
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 19.5. tmod: timer mode register r/w r / w r/w r / w r / w g a t e 0 t 0 m 1 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 8 9 r/w r/w r/w reset value gate1 c/t1 t 1 m 1 t 1 m 0 c/t0 t 0 m 0 00000000 bit7 bit6 bit5 bit4 bit7 : gate1 : tim e r 1 gate co n t ro l. 0: ti m e r 1 enabl e d when tr 1 = 1 i rrespect i v e of / i nt1 l ogi c l e vel . 1: tim e r 1 enabled only when tr 1 = 1 and /int1 = logic level one. b i t 6 : c / t1: c ount er/ t i m er 1 sel ect . 0: ti m e r funct i on: ti m e r 1 i n crem ent e d by cl ock defi ned by t1m bi t (c kc on.4). 1: counter function: tim e r 1 increm ented by high-to-low tr ansitions on external input pin (t1). b i t s 5-4: t1m 1 -t1m 0: ti m e r 1 m ode sel ect . these bi t s sel ect t h e ti m e r 1 operat i on m ode. t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/tim er 0 1 mode 1: 16-bit counter/tim er 1 0 mode 2: 8-bit counter /tim er with auto-reload 1 1 m ode 3: ti m e r 1 inact i v e/ st opped bit3 : gate0 : tim e r 0 gate co n t ro l. 0: ti m e r 0 enabl e d when tr 0 = 1 i rrespect i v e of / i nt0 l ogi c l e vel . 1: tim e r 0 enabled only when tr 0 = 1 and /int0 = logic level one. b i t 2 : c / t0: c ount er/ t i m er sel ect . 0: ti m e r funct i on: ti m e r 0 i n crem ent e d by cl ock defi ned by t0m bi t (c kc on.3). 1: counter function: tim e r 0 increm ented by high-to-low tr ansitions on external input pin (t0). b i t s 1-0: t0m 1 -t0m 0: ti m e r 0 m ode sel ect . these bi t s sel ect t h e ti m e r 0 operat i on m ode. t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/tim er 0 1 mode 1: 16-bit counter/tim er 1 0 mode 2: 8-bit counter /tim er with auto-reload 1 1 mode 3: two 8-bit counter/tim ers 143 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 19.6. ckcon: clock control register r/w r/w r / w r / w r/w r / w r e s e t v a l u e - t 2 m t 1 m r e s e r v e d r e s e r v e d 0 0 0 0 0 0 0 0 b i t 7 b i t 5 b i t 2 b i t 0 0 x 8 e r / w r / w - t 0 m r e s e r v e d b i t 6 b i t 4 bit3 b i t 1 sfr address: bi t s 7-6: unused. read = 00b, w r i t e = don?t care. b i t 5 : t2m : ti m e r 2 c l ock sel ect . thi s bi t cont rol s t h e di vi si on of t h e sy st em cl ock suppl i e d t o ti m e r 2. thi s bi t i s i gnored when t h e t i m er i s i n baud rat e generat o r m ode or count er m ode (i .e. c / t2 = 1). 0: ti m e r 2 uses t h e sy st em cl ock di vi ded by 12. 1: ti m e r 2 uses t h e sy st em cl ock. b i t 4 : t1m : ti m e r 1 c l ock sel ect . thi s bi t cont rol s t h e di vi si on of t h e sy st em cl ock suppl i e d t o ti m e r 1. 0: ti m e r 1 uses t h e sy st em cl ock di vi ded by 12. 1: ti m e r 1 uses t h e sy st em cl ock. b i t 3 : t0m : ti m e r 0 c l ock sel ect . thi s bi t cont rol s t h e di vi si on of t h e sy st em cl ock suppl i e d t o c ount er/ t i m er 0. 0: c ount er/ t i m er uses t h e sy st em cl ock di vi ded by 12. 1: c ount er/ t i m er uses t h e sy st em cl ock. b i t s 2-0: r e served. r ead = 000b, m u st w r i t e = 000. r e v. 1.7 144
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 19.7. tl0: timer 0 low byte r/w r / w r / w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 8 a r / w r/w r/w figure 19.8. tl1: timer 1 low byte r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 0 sfr address: 0 x 8 b r/w r / w b i t 1 figure 19.9. th0: timer 0 high byte r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 0 x 8 c sfr address: bits 7-0: tl0: tim e r 0 low byte. th e tl0 reg i ster is th e lo w b y te o f th e 1 6 - b it tim e r 0 . b i t s 7-0: th0: ti m e r 0 hi gh b y t e . the th0 regi st er i s t h e hi gh by t e of t h e 16-bi t ti m e r 0. bits 7-0: tl1: tim e r 1 low byte. th e tl1 reg i ster is th e lo w b y te o f th e 1 6 - b it tim e r 1 . figure 19.10. th1: timer 1 high byte r/w b i t 4 b i t s 7-0: th1: ti m e r 1 hi gh b y t e . the th1 regi st er i s t h e hi gh by t e of t h e 16-bi t ti m e r 1. r/w r / w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 8 d 145 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 19.2. timer 2 tim e r 2 is a 16-bit counter/tim er form ed by the two 8-bit sfrs: tl2 (low by te) and th2 (high byte). as with ti m e rs 0 and 1, ti m e r 2 can use ei t h er t h e sy st em cl ock or t r ansi t i ons on an ext e rnal i nput pi n as i t s cl ock source. the c ount er/ t i m er sel ect bi t c / t2 bi t (t2c on.1) sel ect s t h e cl ock source for ti m e r 2. c l eari ng c / t2 sel ect s t h e sy st em cl ock as t h e i nput for t h e t i m er (di v i d ed by ei t h er one or t w el ve as speci fi ed by t h e ti m e r c l ock sel ect bi t t2m in ckcon). w h en c/t2 is set to 1, high-to-low transitions at the t2 input pin increm ent the counter/tim er regi st er. (r efer t o sect i on 14 for i n form at i on on sel ect i ng and confi guri ng ext e rnal i/ o pi ns.) ti m e r 2 can al so be used t o st art an adc dat a c onversi on. tim e r 2 offers capabilities not found in tim e r 0 and tim e r 1. it operates in one of three m odes: 16-bit c ount er/ t i m er wi t h c a pt ure, 16-bi t c ount er/ t i m er wi t h aut o -r el oad or b a ud r a t e generat o r m ode. ti m e r 2?s operat i ng m ode i s sel ect ed by set t i ng confi gurat i on bi t s in th e tim e r 2 co n t ro l (t2 c on) reg i ster. belo w is a sum m a ry of the tim e r 2 operating m ode s and the t2con bits used to c onfigure the counter/tim er. detailed descriptions of each m ode follow. t c l k r c l k cp/rl2 tr2 mo d e 0 0 1 1 16-bi t c ount er/ t i m er wi t h c a pt ure 0 0 16-bi t c ount er/ t i m er wi t h aut o -r el oad 0 1 x 1 b a ud r a t e generat o r for tx 1 0 x 1 b a ud r a t e generat o r for r x 1 1 x 1 b a ud r a t e generat o r for tx and r x x x x 0 o f f 0 1 r e v. 1.7 146
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 19.2.1. mode 0: 16-bit counter/tim er with capture in this m ode, tim e r 2 operates as a 16-bit counter/tim er w ith capture facility. a high-to -low transition on the t2ex i nput pi n causes t h e 16-bi t val u e i n ti m e r 2 (th2, tl2) t o be l o aded i n t o t h e capt u re regi st ers (r c a p2h, rcap2l). ti m e r 2 can use ei t h er sysc lk, sysc lk di vi ded by 12, or hi gh-t o -l ow t r ansi t i ons on t h e ext e rnal t2 pi n as i t s cl ock source when operat i ng i n c ount er/ t i m er wi t h c a pt ure m ode. c l eari ng t h e c / t2 bi t (t2c on.1) sel ect s t h e sy st em cl ock as t h e i nput for t h e t i m er (di v i d ed by one or t w el ve as speci fi ed by t h e ti m e r c l ock sel ect bi t t2m i n ckcon). w h en c/t2 is set to logic 1, a high-to-low transition at the t2 input pin increm ents the counter/tim er register. as the 16-bit counter/tim er register incr em ents and overflows from 0xffff to 0x0000, the tf2 tim er o v e rflo w flag (t2 c on.7 ) is set an d an in terru p t will o ccu r if th e in terru p t is en ab led . counter/tim er with capture m ode is se lected by setting the capture/reload select bit cp/rl2 (t2con.0) and the ti m e r 2 r un c ont rol bi t tr 2 (t2c on.2) t o l ogi c 1. the ti m e r 2 ext e rnal enabl e exen2 (t2c on.3) m u st al so be set to logic 1 to enable a capture. if exen2 is cleared, transitions on t2ex will be ignored. figure 19.11. t2 mode 0 block diagram tl2 th2 exen2 t2ex tr2 t2 sysclk 12 0 1 1 0 interrupt tclk rcap2l rcap2h capture t2con rclk tclk exf2 exen2 tr2 c/t2 cp/rl2 tf2 ckcon t 2 m t 1 m t 0 m crossbar crossbar 147 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 19.2.2. mode 1: 16-bit counter/tim er with auto-reload the counter/tim er with auto-reload m ode sets the tf 2 tim er overflow flag when the counter/tim er register overflows from 0xffff to 0x0000. an interrupt is generated if enabled. on overflow, th e 16-bit value held in the two capture registers (rcap2h, rcap2l) is autom a tically lo aded into the counter/tim er register and the tim er is restarted. counter/tim er with auto-reload m ode is selected by clearing the cp/rl2 bit. setting tr2 to logic 1 enables and st art s t h e t i m er. ti m e r 2 can use ei t h er t h e sy st em cl ock or t r ansi t i ons on an ext e rnal i nput pi n as i t s cl ock source, as sp ecified b y th e c/t2 b it. if exen2 is set to lo g i c 1 , a h i g h - to -lo w tran sitio n o n t2 ex will also cau se tim e r 2 to be reloaded. if exen2 is cleared, transitions on t2ex will be ignored. figure 19.12. t2 mode 1 block diagram tl2 th2 tr2 t2 sysclk 12 0 1 1 0 tclk rcap2l rcap2h reload ckcon t 2 m t 1 m t 0 m interrupt t2con rclk tclk exf2 exen2 tr2 c/t2 cp/rl2 tf2 crossbar exen2 crossbar t2ex r e v. 1.7 148
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 19.2.3. mode 2: baud rate generator ti m e r 2 can be used as a baud rat e generat o r for t h e seri al port (uar t) when t h e uar t i s operat e d i n m odes 1 or 3 (refer to section 18.1 for m o re info rm at i on on uar t operat i onal m odes). in b a ud r a t e generat o r m ode, ti m e r 2 wo rk s sim ilarly to th e au to -relo ad m o d e . on o v e rflo w , th e 1 6 - b it v a lu e h e ld in th e two cap tu re reg i sters (rcap2 h, rcap2l) is autom a tically load ed into the counter/tim er register. howeve r, the tf2 overflow flag is not set and no i n t e rrupt i s generat e d. inst ead, t h e overfl ow event i s used as t h e i nput t o t h e uar t?s shi f t cl ock. ti m e r 2 overflows can be used to generate baud rates for transm it and/or receive independently. the b a ud r a t e generat o r m ode i s sel ect ed by set t i ng r c l k (t2c on.5) and/ or tc lk (t2c on.4) t o l ogi c one. w h en rclk o r tclk is set to lo g i c 1 , tim e r 2 o p e rates in th e au to -relo ad m o d e reg a rd less o f th e state o f th e c p / r l2 bi t . the baud rat e for t h e uar t, when operat i ng i n m ode 1 or 3, i s det e rm i n ed by t h e ti m e r 2 overfl ow rate: baud rat e = ti mer 2 overf l o w rat e / 16. not e , i n al l ot her m odes, t h e t i m ebase for t h e t i m er i s t h e sy st em cl ock di vi ded by one or t w el ve as sel ect ed by t h e t2 m b it in ckcon. ho wev e r, in bau d rate gen e rato r m o d e , t h e t i m ebase i s t h e sy st em cl ock di vi ded by t w o. no o t h e r d i v i so r selectio n is p o ssib l e. if a d i fferen t tim e b a se is req u i red , settin g th e c/t2 b it to lo g i c 1 will allo w th e t i m ebase t o be deri ved from t h e ext e rnal i nput pi n t2. in t h i s case, t h e baud rat e for t h e uar t i s cal cul a t e d as: baud rat e = fc lk / [ 32 * ( 65536 ? [ r c ap2h:rc ap2l] ) ] w h ere fc lk i s t h e frequency of t h e si gnal suppl i e d t o t2 an d [rcap2 h:rcap2 l] is th e 1 6 - b it v a lu e h e ld in th e capture registers. as expl ai ned above, i n b a ud r a t e gene rat o r m ode, ti m e r 2 does not set t h e tf2 overfl ow fl ag and t h erefore cannot generate an interrupt. however, if exen2 is set to logi c 1, a high-to-low transition on the t2ex input pin will set the exf2 flag and a tim e r 2 interrupt will occur if enabled. therefore, the t2ex input m a y be used as an ad d itio n a l ex tern al in terru p t so u r ce. figure 19.13. t2 mode 2 block diagram tl2 th2 exen2 t2ex tr2 t2 sysclk c/t2 2 1 0 interrupt tclk rcap2l rcap2h reload 2 16 16 timer 1 overflow rx clock tx clock tclk rclk t2co n rclk tclk exf2 exen2 tr2 c/t2 cp/rl2 tf2 crossbar crossbar pcon s m o d g f 1 g f 0 s t o p i d l e 1 0 1 0 1 0 timer 2 overflow 149 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 19.14. t2con: timer 2 control register r/w r / w r / w t f 2 e x e n 2 c p / r l 2 bit7 bit6 bit3 b i t 0 sfr address: 0xc8 b i t 7 : tf2: ti m e r 2 overfl ow fl ag. set by hardware when tim e r 2 overflows from 0xffff to 0x0000 or reload value. w h en th e tim e r 2 in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e tim e r 2 in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared b y h a rd ware an d m u st b e cleared b y so ftware. tf2 will n o t b e set wh en rclk an d / o r tclk are lo g i c 1 . bit6 : exf2 : tim e r 2 ex tern al flag . set by hardware when ei t h er a capt u re or rel o ad i s caused by a hi gh-t o -l ow t r ansi t i on on the t2ex input pin and exen2 is logic 1. w h en the tim e r 2 interrupt is enabled, setting th is b it cau ses th e cpu to v ecto r to th e tim e r 2 in terru p t serv ice ro u tin e. th is b it is n o t autom a tically cleared by hardware a nd m u st be cleared by software. bit5: rclk: receive clock flag. selects which tim er is used for the uar t?s receive clock in m odes 1 or 3. 0: tim e r 1 overflows used for receive clock. 1: tim e r 2 overflows used for receive clock. bit4 : tclk: tran sm it clo c k flag . selects wh ich tim er is u s ed fo r th e uart?s tran sm it clo c k in m o d e s 1 o r 3 . 0: ti m e r 1 overfl ows used for t r ansm i t cl ock. 1: ti m e r 2 overfl ows used for t r ansm i t cl ock. bit3: exen2: tim e r 2 external enable. enabl e s hi gh-t o -l ow t r ansi t i ons on t2ex t o t r i gger ca p t u res or rel o ads when ti m e r 2 i s not operat i ng i n b a ud r a t e generat o r m ode. 0: hi gh-t o -l ow t r ansi t i ons on t2ex i gnored. 1: hi gh-t o -l ow t r ansi t i ons on t2ex cause a capt u re or rel o ad. b i t 2 : tr 2: ti m e r 2 r un c ont rol . th is b it en ab les/d i sab l es tim e r 2 . 0: ti m e r 2 di sabl ed. 1: ti m e r 2 enabl e d. b i t 1 : c / t2: c ount er/ t i m er sel ect . 0: ti m e r funct i on: ti m e r 2 i n crem ent e d by cl ock defi ned by t2m (c kc on.5). 1: counter function: tim e r 2 increm ented by high-to-low tr ansitions on external input pin (t2). bit0 : cp/rl2 : cap t u r e/relo ad select. thi s bi t sel ect s whet her ti m e r 2 funct i ons i n capt u re or aut o -rel o ad m ode. exen2 m u st be l ogi c 1 for hi gh-t o -l ow t r ansi t i ons on t2ex t o be recogni zed and used t o t r i gger captures or reloads. if rclk or tclk is set, this bit is ignored and tim e r 2 will function in au to -relo ad m o d e . 0: aut o -rel o ad on ti m e r 2 overfl ow or hi gh-t o -l ow t r ansi t i on at t2ex (exen2 = 1). 1: c a pt ure on hi gh-t o -l ow t r ansi t i on at t2ex (exen2 = 1). r / w r/w r / w r/w r / w r e s e t v a l u e e x f 2 r c l k t c l k t r 2 c / t 2 0 0 0 0 0 0 0 0 b i t 5 b i t 4 b i t 2 b i t 1 (bit addressable) r e v. 1.7 150
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 19.15. rcap2l: timer 2 capture register low byte r/w r / w r/w r / w b i t 2 r / w r/w r/w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 1 b i t 0 sfr address: 0 x c a figure 19.16. rcap2h: timer 2 capture register high byte r/w r/w r / w 00000000 bit7 bit6 bit5 bit4 b i t 2 b i t 0 0 x c r / w r / w r / w r/w r / w r e s e t v a l u e b i t 3 b i t 1 sfr address: b figure 19.17. tl2: timer 2 low byte r/w r / w reset value 00000000 bit7 bit6 bit5 bit4 bit3 b i t 0 r / w r/w r / w r / w r/w r / w b i t 2 b i t 1 sfr address: 0 x c c figure 19.18. th2: timer 2 high byte r/w r / w r / w r/w r / w b i t 5 b i t 3 b i t 1 sfr address: 0 x c d r/w r / w r / w reset value 00000000 bit7 bit6 b i t 4 b i t 2 b i t 0 b i t s 7-0: th2: ti m e r 2 hi gh b y t e . the th2 regi st er cont ai ns t h e hi gh by t e of t h e 16-bi t ti m e r 2. b i t s 7-0: r c a p2h: ti m e r 2 c a pt ure r e gi st er hi gh b y t e . the r c a p2h regi st er capt u res t h e hi gh by t e of ti m e r 2 when ti m e r 2 i s confi gured i n capt u re m ode. w h en ti m e r 2 i s confi gured i n aut o -rel o ad m ode, i t hol ds t h e hi gh by t e of th e relo ad v a lu e. b i t s 7-0: r c a p2l: ti m e r 2 c a pt ure r e gi st er low b y t e . the r c a p2l regi st er capt u res t h e l o w by t e of ti m e r 2 when ti m e r 2 i s confi gured i n capt u re m ode. w h en ti m e r 2 i s confi gured i n aut o -rel o ad m ode, i t hol ds t h e l o w by t e of th e relo ad v a lu e. bits 7-0: tl2: tim e r 2 low byte. the tl2 regi st er cont ai ns t h e l o w by t e of t h e 16-bi t ti m e r 2. 151 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 19.3. timer 3 ti m e r 3 i s a 16-bi t t i m er form ed by t h e t w o 8-bi t sfr s, tm r 3 l (l ow by t e ) and tm r 3 h (hi gh by t e ). the i nput for ti m e r 3 i s t h e sy st em cl ock (di v i d ed by ei t h er one or t w el ve as specified by the tim e r 3 clo c k select b it t3 m in th e ti m e r 3 c ont rol r e gi st er tm r 3 c n ). ti m e r 3 i s al way s c onfigured as an auto-reload tim er, with th e relo ad v a lu e hel d i n t h e tm r 3 r ll (l ow by t e ) and tm r 3 r l h (hi gh by t e ) regi st ers. ti m e r 3 can be used t o st art an adc dat a c onversi on, for sm b u s t i m i ng (see sect i on 16.5), or as a general - purpose t i m er. ti m e r 3 does not have a count er m ode. figure 19.19. timer 3 block diagram tmr3l tmr3h tr3 sysclk 12 0 1 tclk tmr3rll tmr3rlh reload interrupt tmr3cn tr3 t3m tf3 t3m toe scl (from smbus) (to adc) crossbar figure 19.20. tmr3cn: timer 3 control register r/w r/w r/w r/w r/w r / w - tr3 t3m - sfr address: 0x91 bit7 : tf3 : tim e r3 ov erflo w flag . set by hardware when ti m e r 3 overflows from 0xffff to 0x0000. w h en the tim e r 3 in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e tim e r 3 in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared by hardware a nd m u st be cleared by software. bi t s 6-3: unused. read = 0000b, w r i t e = don?t care. b i t 2 : tr 3: ti m e r 3 r un c ont rol . th is b it en ab les/d i sab l es tim e r 3 . 0: ti m e r 3 di sabl ed. 1: ti m e r 3 enabl e d. b i t 1 : t3m : ti m e r 3 c l ock sel ect . thi s bi t cont rol s t h e di vi si on of t h e sy st em cl ock suppl i e d t o c ount er/ t i m er 3. 0: c ount er/ t i m er 3 uses t h e sy st em cl ock di vi ded by 12. 1: c ount er/ t i m er 3 uses t h e sy st em cl ock. bi t 0 : unused. read = 0, w r i t e = don?t care. r/w r / w r e s e t v a l u e t f 3 - - - 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 r e v. 1.7 152
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 19.21. tmr3rll: timer 3 reload register low byte r/w r / w r/w r / w r / w r/w r / w r / w b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 reset value 00000000 sfr address: 0x92 figure 19.22. tmr3rlh: timer 3 reload register high byte r/w r / w r/w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 r / w bit3 bit2 bit1 bit0 sfr address: 0x93 b i t s 7-0: tm r 3 r l h: ti m e r 3 r e l o ad r e gi st er hi gh b y t e . ti m e r 3 i s confi gured as an aut o -rel o ad t i m er. thi s regi st er hol ds t h e hi gh by t e of t h e relo ad v a lu e. bits 7 - 0 : tmr3 rll: tim e r 3 relo ad reg i ster lo w byte. tim e r 3 is co n f ig u r ed as an au to -relo ad tim er. th is reg i ster h o l d s th e lo w b y te o f th e relo ad v a lu e. figure 19.23. tmr3l: timer 3 low byte 00000000 bit7 bit6 bit5 bit4 0x94 r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e b i t 3 b i t 2 b i t 1 b i t 0 sfr address: figure 19.24. tmr3h: timer 3 high byte bits 7-0: tmr3l: tim e r 3 low byte. th e tmr3 l reg i ster is th e lo w b y te o f tim e r 3 . b i t s 7-0: tm r 3 h: ti m e r 3 hi gh b y t e . the tm r 3 h regi st er i s t h e hi gh by t e of ti m e r 3. r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x 9 5 153 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 20. programmable counter array the program m a ble counter array (p ca) provides enhanced tim er func tionality while requiring less cpu intervention than the standard 8051 count er/tim ers. the pca consists of a de dicated 16-bit counter/tim er and five 16-bi t capt u re/ c om pare m odul es. each capt u re/ c om pare m odul e has i t s own associ at ed i/ o l i n e (c exn) whi c h i s rout ed t h rough t h e c r ossbar t o port i/ o when enabl e d (see sect i on 15.1 for det a i l s on confi guri ng t h e c r ossbar). the counter/tim er is driven by a confi gurable tim ebase that can select between four inputs as its source: system cl ock di vi ded by t w el ve, sy st em cl ock di vi ded by four, ti m e r 0 overfl ow, or an ext e rnal cl ock si gnal on t h e ec i l i n e. the pc a i s confi gured and cont rol l e d t h rough t h e sy st em cont rol l e r?s speci al funct i on r e gi st ers. the basi c pc a bl ock di agram i s shown i n fi gure 20.1. figure 20.1. pca block diagram 16-bit counter/timer capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 capture/compare module 4 cex1 system clock /4 t0 overflow eci crossbar cex2 cex3 cex4 cex0 port i/o /12 00 01 10 cps=11 r e v. 1.7 154
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 20.1. capture/compare modules each m odul e can be confi gured t o operat e i ndependent l y i n one of four operat i on m ode s: edge-t ri ggered c a pt ure, soft ware ti m e r, hi gh speed out put , or pul s e w i dt h m odul at or. each m odul e has speci al funct i on r e gi st ers (sfr s) associ at ed wi t h i t i n t h e c i p-51 sy st em cont rol l e r. these regi st ers are used t o exchange dat a wi t h a m odul e and confi gure t h e m odul e?s m ode of operat i on. table 20.1 sum m a rizes the bit settings in the pca0cpmn registers used to place the pca capture/com pare m odules i n t o di fferent operat i ng m odes. set t i ng t h e ec c f n bi t i n a pc a0c p m n regi st er enabl e s t h e m odul e?s c c f n i n t e rrupt . not e : pc a0 i n t e rrupt s m u st be gl obal l y enabl e d before i ndi vi dual c c f n i n t e rrupt s are recogni zed. pc a0 i n t e rrupt s are gl obal l y enabl e d by set t i ng t h e ea bi t (ie.7) and t h e epc a 0 bi t (eie1.3) t o l ogi c 1. see fi gure 2 . for det a i l s on t h e pc a i n t e rrupt confi gurat i on. 0 2 table 20.1. pca0cpm register settings for pca capture/compare modules e c o m c a p p c a p n m a t t o g p w m e c c f operation m o d e x 1 0 0 0 0 x cap t u r e trig g e red b y p o s itiv e ed g e o n cexn x 0 1 0 0 0 x c a pt ure t r i ggered by negat i v e edge on cexn x 1 0 x 1 0 0 c a pt ure t r i ggered by t r ansi t i on on c e xn 1 0 0 1 0 0 x soft w a r e ti m e r 1 0 0 1 1 0 x hi gh s p e e d out put 1 0 0 x 0 1 x pul s e w i dt h m odul at o r x = don?t care figure 20.2. pca interrupt block diagram pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l e c f c p s 1 c p s 0 0 1 pca module 0 pca module 1 eccf1 0 1 eccf0 0 1 pca module 2 eccf2 0 1 pca module 3 eccf3 0 1 pca module 4 eccf4 pca counter/ timer overflow 0 1 interrupt priority decoder epca0 (eie1.3) 0 1 ea (ie.7) 0 1 pca0cpmn e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n (for n = 0 to 4) 155 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 20.1.1. edge-triggered capture mode in this m ode, a valid transition on the cexn pin causes th e pca to capture the value of the pca counter/tim er and l o ad i t i n t o t h e correspondi ng m odul e?s 16-bi t capt u re/ c om pare regi st er (pc a 0c pln and pc a0c p hn). the c a ppn and c a pnn bi t s i n t h e pc a0c p m n regi st er are u s ed to select th e typ e o f tran sitio n th at trig g e rs th e cap tu re: lo w-to - h i g h tran sitio n (p o s itiv e ed g e ), h i g h - to -lo w tran sitio n (n eg ativ e ed g e ), o r eith er tran sitio n (p o s itiv e o r n e g a tiv e edge). w h en a capture occurs, the ca pt ure/ c o m p are fl ag (c c f n) i n pc a0c n i s set t o l ogi c 1 and an i n t e rrupt req u e st is g e n e rated if ccf in terru p t s are en ab led . th e ccfn b it is n o t au to m a tically cleared b y h a rd ware wh en th e cpu v ecto r s to th e in terru p t serv ice ro u tin e, and m u st be cleared by software. figure 20.3. pca capture mode diagram pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 0 pca0cpmn e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 00 0 0 1 0 1 (t o ccf n) pca interrupt r e v. 1.7 156
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 20.1.2. software tim er (com pare) mode in software tim e r m ode, the pca counter/tim er is com p ared to the m odule?s 16-bit capture/com pare register (pc a 0c phn and pc a0c p ln). w h en a m a t c h occurs, t h e cap t u r e/co m p are flag (ccfn ) in pca0 cn is set to l ogi c 1 and an i n t e rrupt request i s generat e d i f c c f i n t e rrupt s are enabl e d. the c c f n bi t i s not aut o m a t i cal l y cleared by hardware when the cpu vect o r s to th e in terru p t serv ice ro u tin e, and m u st be cleared by software. settin g th e ecomn an d matn b its in th e pca0 cpmn reg i ster en ab les so ftware tim e r m o d e . figure 20.4. pca softw are timer mode diagram figure 20.5. pca high speed output mode diagram 20.1.3. high speed output mode in this m ode, each tim e a m a tch occu rs between the pca tim e r counter a nd a m odule?s 16-bit capture/com pare register (pca0cphn and pca0cpln) the logic level on the m odule?s associated cexn pin will toggle. setting the togn, m a tn, and ec om n bi t s i n t h e pc a0c p m n regi st er enabl e s t h e hi gh-speed out put m ode. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln pca0cpmn e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 00 00 pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt 0 1 pca0cpmn e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 00 0 x cexn crossbar port i/o toggle enb enb 0 1 write to pca0cpln write to pca0cphn reset 0 1 togn 157 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 20.1.4. pulse width modulator mode al l of t h e m odul es can be used i ndependent l y t o genera t e pul se wi dt h m odul at ed (pw m ) out put s on t h ei r respect i v e cexn pin. the frequency of the output is dependent on the tim ebase for the pca counter/tim er. the duty cycle of t h e pw m out put si gnal i s vari ed usi ng t h e m odul e?s pc a0c p ln capt u re/ c om pare regi st er. w h en t h e val u e i n t h e low byte of the pca counter/tim er (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be set. w h en the count value in pca0l overflows, the cexn output will be reset (see figure 20.6). also, when the counter/tim er low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded autom a tically with the val u e st ored i n t h e pc a0c p hn wi t hout soft ware i n t e rvent i on. it i s good pract i ce t o wri t e t o pc a0c p hn i n st ead of pca0 cpln to av o i d g litch e s in th e d i g ital co m p arato r . settin g th e ecomn an d pw mn b its in th e pca0 cpmn regi st er enabl e s pul s e w i dt h m odul at or m ode. figure 20.6. pca pwm mode diagram 8- bi t c o m p ar ato r pc a 0 l pca0cpln pc a 0 c p hn cex n e n abl e ove r f l ow pca tim e b a se 00 x 0 x q q set cl r s r ma tc h pc a 0 c p m n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n enb enb 0 1 wr i t e t o pca0 cpl n wr i t e t o pc a0c p hn re set cro s s b ar por t i/o r e v. 1.7 158
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 20.2. pca counter/timer the 16-bit pca counter/tim er consists of two 8-bit sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/tim er and pca0l is the low byte (lsb). reading pca0l autom a ti cally latches the value of pca0 h at th e sam e tim e. by read in g th e pca0 l reg i ster first, th is allo ws th e pca0 h v a lu e to b e h e ld (at th e tim e pca0 l was read ) u n til th e u s er read s th e pca0 h reg i ster. read in g pca0 h o r pca0 l d o e s n o t d i stu r b th e counter operation. the cps1 and cps0 bits in the pca0md register select the tim ebase for the counter/tim er as shown i n tabl e 20.2. timebase w h en the counter/tim er overflows from 0xffff to 0x0000, the c ounter overflow flag (cf) in pca0md is set to l ogi c 1 and an i n t e rrupt request i s generat e d i f c f i n t e rrupt s are enabl e d. set t i ng t h e ec f bi t i n pc a0m d t o l ogi c 1 en ab les th e cf flag to g e n e rate an in terru p t req u e st. th e cf b it is n o t au to m a tically cl eared by hardware when the c p u vect ors t o t h e i n t e rrupt servi ce rout i n e, and m u st be cl eared by soft ware. (not e: pc a0 i n t e rrupt s m u st be globally enabled before cf interrupts are recognized. pca0 interrupts are gl obally enabled by setting the ea bit (ie.7) and t h e epc a 0 bi t i n eie1 t o l ogi c 1.) c l eari ng t h e cidl b it in th e pca0 md reg i ster allo ws th e pca to cont i nue norm a l operat i on whi l e t h e m i crocont rol l e r core i s i n idl e m ode. table 20.2. pca timebase input options c p s 1 c p s 0 0 0 sy st em cl ock di vi ded by 12 0 1 sy st em cl ock di vi ded by 4 1 0 ti m e r 0 overfl ow 1 hi gh-t o -l ow t r ansi t i ons on ec i (m ax rat e = sy st em cl ock di vi ded by 4) 1 figure 20.7. pca counter/timer block diagram pca0h pca0l pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 sysclk/12 sysclk/4 timer 0 overflow eci 00 01 10 11 pca0md c i d l e c f c p s 1 c p s 0 snapshot register to sfr bus overflow to pca interrupt system idle 0 1 cf pca0l read or write to pca modules 159 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 20.3. register descriptions for pca the sy st em devi ce m a y i m pl em ent one or m o re program m a bl e c ount er array s . fol l o wi ng are det a i l e d descri pt i ons of t h e speci al funct i on regi st ers rel a t e d t o t h e operat i on of t h e pc a. the c i p-51 sy st em c ont rol l e r sect i on of t h e dat a sheet provi des addi t i onal i n form at i on on t h e sfr s and t h ei r use. figure 20.8. pca0cn: pca control register b i t 7 : c f : pc a c ount er/ t i m er overfl ow fl ag. set by hardware when the pca counter/t im er overflows from 0xffff to 0x0000. w h en the counter/tim er overflow (cf) interrupt is enabled, setting this bit causes the cpu to v ecto r to th e cf in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared b y hardware and m u st be cl eared by soft ware. b i t 6 : c r : pc a c ount er/ t i m er r un c ont rol . thi s bi t enabl e s/ di sabl es t h e pc a c ount er/ t i m er. 0: pc a c ount er/ t i m er di sabl ed. 1: pc a c ount er/ t i m er enabl e d. bi t 5 : unused. read = 0, w r i t e = don?t care. b i t 4 : c c f 4: pc a m odul e 4 c a pt ure/ c o m p are fl ag. th is b it is set b y h a rd ware wh en a m a tch o r cap tu re o ccu rs. w h en th e ccf in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e ccf in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared b y h a rd ware and m u st be cl eared by software. b i t 3 : c c f 3: pc a m odul e 3 c a pt ure/ c o m p are fl ag. th is b it is set b y h a rd ware wh en a m a tch o r cap tu re o ccu rs. w h en th e ccf in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e ccf in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared b y h a rd ware and m u st be cl eared by software. b i t 2 : c c f 2: pc a m odul e 2 c a pt ure/ c o m p are fl ag. th is b it is set b y h a rd ware wh en a m a tch o r cap tu re o ccu rs. w h en th e ccf in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e ccf in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared b y h a rd ware and m u st be cl eared by software. b i t 1 : c c f 1: pc a m odul e 1 c a pt ure/ c o m p are fl ag. th is b it is set b y h a rd ware wh en a m a tch o r cap tu re o ccu rs. w h en th e ccf in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e ccf in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared b y h a rd ware and m u st be cl eared by software. b i t 0 : c c f 0: pc a m odul e 0 c a pt ure/ c o m p are fl ag. th is b it is set b y h a rd ware wh en a m a tch o r cap tu re o ccu rs. w h en th e ccf in terru p t is en ab led , settin g th is b it cau ses th e cpu to v ecto r to th e ccf in terru p t serv ice ro u tin e. th is b it is n o t au to m a tically cleared b y h a rd ware and m u st be cl eared by software. r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e c f c r - c c f 4 c c f 3 c c f 2 c c f 1 c c f 0 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: (bit addressable) 0xd8 r e v. 1.7 160
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 20.9. pca0md: pca mode register r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e c i d l - - - - c p s 1 c p s 0 e c f 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0 x d 9 b i t 7 : c i dl: pc a c ount er/ t i m er idl e c ont rol . speci fi es pc a behavi or when c p u i s i n idl e m ode. 0 : pca co n tin u e s to fu n c tio n n o r m a lly wh ile th e system co n t ro ller is in id le mo d e . 1: pc a operat i on i s suspended whi l e t h e sy st em cont rol l e r i s i n idl e m ode. bi t s 6-3: unused. read = 0000b, w r i t e = don?t care. b i t s 2-1: c ps1-c ps0: pc a c ount er/ t i m er pul s e sel ect . these bi t s sel ect t h e t i m ebase source for t h e pc a count er. cps1 cps0 timebase 0 0 sy st em cl ock di vi ded by 12 0 1 sy st em cl ock di vi ded by 4 1 0 ti m e r 0 overfl ow 1 1 hi gh-t o -l ow t r ansi t i ons on ec i (m ax rat e = sy st em cl ock di vi ded by 4) b i t 0 : ec f: pc a c ount er/ t i m er overfl ow int e rrupt enabl e . thi s bi t set s t h e m a ski ng of t h e pc a c ount er/ t i m er overfl ow (c f) i n t e rrupt . 0: di sabl e t h e c f i n t e rrupt . 1: enabl e a pc a c ount er/ t i m er overfl ow i n t e rrupt request when c f (pc a 0c n.7) i s set . 161 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 20.10. pca0cpmn: pca capture/compare registers r/w r / w r/w r / w - cappn m a t n p w m n e c c f n b i t 6 bit3 sfr address: pca0cpm n address: pca0cpm 0 = 0xda (n = 0) pc a0c p m 1 = 0xdb (n = 1) pc a0c p m 2 = 0xdc (n = 2) pca0cpm 3 = 0xdd (n = 3) pc a0c p m 4 = 0xde (n = 4) bi t 7 : unused. read = 0, w r i t e = don?t care. b i t 6 : ec om n: c o m p arat or funct i on enabl e . thi s bi t enabl e s/ di sabl es t h e com p arat or funct i on for pc a m odul e n . 0: di sabl ed. 1: enabl e d. bit5 : cappn : cap t u r e po sitiv e fu n c tio n en ab le. this bit enables/disables the pos itive edge capture for pca m odule n . 0: di sabl ed. 1: enabl e d. b i t 4 : c a pnn: c a pt ure negat i v e funct i on enabl e . thi s bi t enabl e s/ di sabl es t h e negat i v e edge capt u re for pc a m odul e n . 0: di sabl ed. 1: enabl e d. bit3 : matn : match fu n c tio n en ab le. thi s bi t enabl e s/ di sabl es t h e m a t c h funct i on for pc a m odul e n . w h en enabled, m a tches o f t h e pc a count er wi t h a m odul e?s capt u re/ c om pare regi st er cause t h e c c f n bi t i n pca0md register to be set. 0: di sabl ed. 1: enabl e d. b i t 2 : togn: toggl e funct i on enabl e . thi s bi t enabl e s/ di sabl es t h e t oggl e funct i on for pc a m odul e n . w h en enabled, m a tches of t h e pc a count er wi t h a m odul e?s capt u re/ c om pare regi st er cause t h e l ogi c l e vel on t h e c e xn pi n t o t oggl e. 0: di sabl ed. 1: enabl e d. b i t 1 : pw m n : pul s e w i dt h m odul at i on m ode enabl e . thi s bi t enabl e s/ di sabl es t h e com p arat or funct i on for pc a m odul e n . w h en enabled, a pul se wi dt h m odul at ed si gnal i s out put on t h e c e xn pi n. 0: di sabl ed. 1: enabl e d. bit0 : eccfn : cap t u r e/co m p are flag interrupt enable. th is b it sets th e m a sk in g o f th e cap t u r e/co m p are flag (ccfn ) in terru p t . 0: di sabl e c c f n i n t e rrupt s. 1: enable a capture/com p are flag i n t e rrupt request when c c f n i s set . r / w r/w r / w r / w r e s e t v a l u e e c o m n c a p n n t o g n 0 0 0 0 0 0 0 0 b i t 7 b i t 5 b i t 4 b i t 2 b i t 1 b i t 0 0 x d a - 0 x d e r e v. 1.7 162
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 20.11. pca0l: pca counter/timer low byte r/w r / w r/w r / w r / w r/w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 3 b i t 2 b i t 1 sfr address: 0 x e 9 r / w bit5 bit4 b i t 0 figure 20.12. pca0h: pca counter/timer high byte r/w r / w bit7 bit6 b i t 1 0 x f r / w r/w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 5 b i t 4 b i t 3 b i t 2 b i t 0 sfr address: 9 b i t s 7-0: pc a0l: pc a c ount er/ t i m er low b y t e . the pc a0l regi st er hol ds t h e l o w by t e (lsb ) of t h e 16-bi t pc a c ount er/ t i m er. b i t s 7-0: pc a0h: pc a c ount er/ t i m er hi gh b y t e . the pc a0h regi st er hol ds t h e hi gh by t e (m sb ) of t h e 16-bi t pc a c ount er/ t i m er. not e th e v a lu e read is actu a lly fro m th e sn ap sh o t reg i ster in o r d e r to syn c h r o n i ze it with pca0 l. figure 20.13. pca0cpln: pca capture module low byte r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 sfr address: 0xe a - 0xe e b i t 0 pc a0c p ln address: pc a0c p l0 = 0xea (n = 0) pc a0c p l1 = 0xeb (n = 1) pc a0c p l2 = 0xec (n = 2) pc a0c p l3 = 0xed (n = 3) pca0cpl4 = 0xee (n = 4) b i t s 7-6: pc a0c p ln: pc a c a pt ure m odul e low b y t e . the pc a0c p ln regi st er hol ds t h e l o w by t e (lsb ) of t h e 16-bi t capt u re m odul e n . figure 20.14. pca0cphn: pca capture module high byte r/w r / w r/w r / w r / w r/w r / w r / w r e s e t v a l u e 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 sfr address: 0xfa - 0xfe pca0cphn address: pca0cph0 = 0xfa (n = 0) pc a0c p h1 = 0xfb (n = 1) pc a0c p h2 = 0xfc (n = 2) pca0cph3 = 0xfd (n = 3) pc a0c p h4 = 0xfe (n = 4) b i t s 7-0: pc a0c p hn: pc a c a pt ure m odul e hi gh b y t e . th e p ca0 c phn r eg ister hol ds t h e h i g h b y t e ( m s b ) of t h e 1 6 - bi t capt u re m odul e n . 163 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 21. jtag (ieee 1149.1) each mcu has an on-chip jtag interface and logic to s upport boundary scan for producti on and in-system testing, flash read and write operations, and non-intrusive in-circu it debug. the jtag interface is fully com p liant with the ieee 1149.1 specification. refer to this specification for detailed descriptions of the te st interface and boundary- scan architecture. access of the jtag inst ruct i on r e gi st er (ir ) and dat a r e gi st ers (dr ) are as descri bed i n t h e test access port and operation of the ieee 1149.1 specification. the jtag interface is via four dedicated pins on the mcu, which are tck, tms, tdi, and tdo. these pins are all 5 v to leran t . through t h e 16-bi t jtag inst ruct i on r e gi st er (ir ), any of t h e ei ght i n st ruct i ons shown i n fi gure 21.1 can be com m a nded. there are t h ree dat a r e gi st ers (dr ? s) associ at ed wi t h jtag b oundary -scan, and four associ at ed wi t h fl ash read/ w ri t e operat i ons on t h e m c u. figure 21.1. ir: jtag instruction register r e s e t v a l u e 0 x 0 0 0 4 b it15 b it0 ir val u e inst ruct i on descri pt i on 0x0000 extest selects the boundary data register for control and observability of all devi ce pi ns 0x0002 sam p le/ preload selects the boundary data register for observability and presetting the scan-path latches 0x0004 idc ode sel ect s devi ce id r e gi st er 0xffff bypass selects bypass data register 0x0082 flash control selects flashc on register to control how th e interface logic responds to reads and writes to the flashdat register 0x0083 fl ash dat a sel ect s flashdat regi st er for reads and wri t e s t o t h e fl ash m e m o ry 0x0084 fl ash address sel ect s flashadr regi st er wh i c h hol ds t h e address of al l fl ash read, wri t e , and erase operat i ons 0x0085 fl ash scal e sel ect s flashsc l r e gi st er whi c h cont rol s t h e prescal er used t o generat e t i m i ng si gnal s for fl ash operat i ons r e v. 1.7 164
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 21.1. boundary scan the dat a r e gi st er i n t h e b oundary scan pat h i s an 87-bi t shi f t regi st er. the b oundary dr provi des cont rol and o b s erv a b ility o f all th e d e v i ce p i n s as well as th e sfr b u s an d w eak pu llu p featu r e v i a th e extest an d sample c o mma n d s . table 21.1. boundary data register bit definitions extest provides access to both capture and update ac tions, while sam p le only perform s a capture. bit action target c a pt ure r e set enabl e from m c u 0 up d a te reset en ab le to /rst p i n c a pt ure r e set i nput from / r st pi n 1 updat e r e set out put t o / r st pi n c a pt ure ext e rnal c l ock from xtal1 pi n 2 updat e n o t u s e d c a pt ure w eak pul l up enabl e from m c u 3 updat e w eak pul l up enabl e t o port pi ns c a pt ure sfr address b u s bi t from c i p-51 (e.g. b i t 4 =sfr a0, b i t 5 =sfr a1?) 4- 11 up d a te sfr ad d r ess bu s b it to sfr ad d r ess bu s (e.g . bit4 =xsfra0 , bit5 =xsfra1 ) c a pt ure sfr dat a b u s bi t read from sfr (e.g. bit12=sfr d0, bit13=sfrd1?) 12- 19 up d a te sfr data bu s b it written to sfr (e.g . bit1 2 = sfrd0 , bit1 3 = sfrd1 ?) c a pt ure sfr w r i t e st robe from c i p-51 20 update sfr w r ite strobe to sfr bus c a pt ure sfr r ead st robe from c i p-51 21 update sfr read strobe to sfr bus c a pt ure sfr r ead/ m odi fy / w ri t e st robe from c i p-51 22 up d a te sfr read /mo d i fy/w rite stro b e to sfr bu s c a pt ure p0.n out put enabl e from m c u (e.g. bit23=p0.0, bit25=p0.1, etc.) 23, 25, 27, 29, 31, 33, 35, 37 updat e p0.n out put enabl e t o pi n (e.g. b i t 23=p0.0oe, b i t 25=p0.1oe, et c.) c a pt ure p0.n i nput from pi n (e.g. b i t 24=p0.0, b i t 26=p0.1, et c.) 24, 26, 28, 30, 32, 34, 36, 38 updat e p0.n out put t o pi n (e.g. b i t 24=p0.0, b i t 26=p0.1, et c.) c a pt ure p1.n out put enabl e from m c u (e.g. bit39=p1.0, bit41=p1.1, etc.) 39, 41, 43, 45, 47, 49, 51, 53 updat e p1.n out put enabl e t o pi n (e.g. b i t 39=p1.0oe, b i t 41=p1.1oe, et c.) c a pt ure p1.n i nput from pi n (e.g. b i t 40=p1.0, b i t 42=p1.1, et c.) 40, 42, 44, 46, 48, 50, 52, 54 updat e p1.n out put t o pi n (e.g. b i t 40=p1.0, b i t 42=p1.1, et c.) c a pt ure p2.n out put enabl e from m c u (e.g. bit55=p2.0, bit57=p2.1, etc.) 55, 57, 59, 61, 63, 65, 67, 69 updat e p2.n out put enabl e t o pi n (e.g. b i t 55=p2.0oe, b i t 57=p2.1oe, et c.) c a pt ure p2.n i nput from pi n (e.g. b i t 56=p2.0, b i t 58=p2.1, et c.) 56, 58, 60, 62, 64, 66, 68, 70 updat e p2.n out put t o pi n (e.g. b i t 56=p2.0, b i t 58=p2.1, et c.) c a pt ure p3.n out put enabl e from m c u (e.g. bit71=p3.0, bit73=p3.1, etc.) 71, 73, 75, 77, 79, 81, 83, 85 updat e p3.n out put enabl e t o pi n (e.g. b i t 71=p3.0oe, b i t 73=p3.1oe, et c.) c a pt ure p3.n i nput from pi n (e.g. b i t 72=p3.0, b i t 74=p3.1, et c.) 72, 74, 76, 78, 80, 82, 84, 86 updat e p3.n out put t o pi n (e.g. b i t 72=p3.0, b i t 74=p3.1, et c.) 165 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 21.1.1. ex test instruction the extest instruction is accessed via the ir. the bounda ry dr provides control a nd observability of all the devi ce pi ns as wel l as t h e sfr bus and w eak pul l up feat ure. al l i nput s t o on-chi p l ogi c are set t o one. 21.1.2. sample instruction the sample instruction is accessed via the ir. the b oundary dr provides observab ility and presetting of the scan-path latches. 21.1.3. bypass instruction the bypass instruction is accessed via th e ir. it provides access to the standa rd 1-bit jtag bypass data register. 21.1.4. idcode instruction the idcode instruction is accessed via the ir. it provides access to the 32-bit device id register. figure 21.2. deviceid: jtag device id register r e s e t v a l u e version part number manufacturer id 1 (varies) b i t 3 1 b i t 2 8 b i t 1 2 b i t 1 1 b i t 1 b i t 0 b i t 2 7 versi on = 0000b (r evi s i on a) or = 0001b (r evi s i on b ) part num b er = 0000 0000 0000 0000b or = 0000 0000 0000 0010b manufacturer id = 0010 0100 001b (silicon laboratories) r e v. 1.7 166
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 21.2. flash programming commands the flash m e m o ry can be program m e d directly over the jt ag interface using the flash c ontrol, flash data, flash address, and flash scale registers. these indirect data registers are accesse d via the jtag instruction register. r ead and wri t e operat i ons on i ndi rect dat a regi st ers are pe rfo rm ed b y first settin g th e ap p r o p r iate dr ad d r ess in th e ir reg i ster. each read o r write is th en in itiated b y wr itin g th e ap p r o p r iate in d i rect op eratio n co d e (in d o p c o d e ) to t h e sel ect ed dat a regi st er. incom i ng com m a nds t o t h i s regi st er have t h e fol l o wi ng form at : 19: 1 8 1 7 : 0 indopc o d e w r i t e dat a indopcode: these bit set the operation to perform according to the following table: i n d o p c o d e o p e r a t i o n 0 x p o l l 1 0 r e a d 1 1 w r i t e the pol l operat i on i s used t o check t h e b u sy bi t as descri bed bel o w. al t hough a c a pt ure-dr i s perform ed, no update-dr is allowed for the poll operation. since upda tes are disabled, polling can be accom p lished by shifting i n / out a si ngl e bi t . th e read o p e ratio n in itiates a read fro m th e reg i ster ad d r essed b y th e ir. read s can b e in itiated b y sh iftin g o n l y 2 b its in to th e in d i rect reg i ster. after th e read o p e ratio n is in itiated , p o llin g o f th e bu sy b it m u st b e p e rfo rm ed to d e term in e wh en th e o p e ratio n is co m p lete. th e write o p e ratio n in itiates a write o f w r itedata to th e reg i ster ad d r essed b y th e ir. reg i sters o f an y wid t h u p to 18 bits can be written. if the register to be written contains fewer than 18 bits , the data in w r itedata should be left- justified, i.e. its msb should occupy bit 17 above. this allows shorter registers to be written in fewer jtag clock cycles. fo r ex am p l e, an 8 - b it reg i ster co u l d b e written b y sh iftin g o n l y 1 0 b its. after a w r ite is in itiated , th e bu sy bit should be polled to determ ine when th e next operation can be initiated. the contents of the instruction register shoul d not be al t e red whi l e ei t h er a read or wri t e operat i on i s i n progress. out goi ng dat a from t h e i ndi rect dat a r e gi st er has t h e fol l o wi ng form at : 1 9 1 8 : 1 0 0 r e a d d a t a busy th e bu sy b it in d i cates th at th e cu rren t o p e ratio n is n o t co m p lete. it g o e s h i g h wh en an o p e ratio n is in itiated an d returns low when com p lete. read and w r ite com m a nds are ignored while busy is high. in fact, if polling for busy to b e lo w will b e fo llo wed b y an o t h e r read o r write o p e ratio n , jtag writes o f th e n e x t o p e ratio n can b e m a d e wh ile checking for busy to be low. they will be ignored until busy is read lo w, at which tim e the new operation will initiate. this bit is placed at bit 0 to allow polling by single-bit shifts. w h en waiting for a read to com p lete and b u sy i s 0, t h e fol l o wi ng 18 bi t s can be shi f t e d out t o obt ai n t h e resul t i ng dat a . r eaddat a i s al way s ri ght -just i f i e d. thi s al l o ws regi st ers short e r t h an 18 bi t s t o be read usi ng a reduced num ber of shi f t s . for exam pl e, t h e resul t from a by t e -read requi res 9 bi t shi f t s (b usy + 8 bi t s ). 167 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 21.3. flashcon: jtag flash control register r e s e t v a l u e w r m d 3 w r m d 2 w r m d 1 w r m d 0 r d m d 3 r d m d 2 r d m d 1 r d m d 0 0 0 0 0 0 0 0 0 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 b i t 6 this register determ ines how the flash interf ace logic will respond to reads and writes to the flashdat register. b i t s 7-4: w r m d 3-0: w r i t e m ode sel ect b i t s . the w r ite mode select bits control how th e interface logic responds to writes to the flashdat register per the following values: 0000: a flashdat write replaces the data in the flashdat register, but is otherwise i gnored. 0001: a flashdat write initiates a write of flashdat into the m e m o ry location addressed by the flashadr register. flashadr is increm ented by one when co m p lete. 0010: a flashdat write initiates an erasure (set s all bytes to 0xff) of the flash page containing the address in flashadr. fl ashdat m u st be 0xa5 for the erase to occur. flashadr i s not affect ed. if flashadr = 0x7dfe ? 0x7dff, t h e ent i r e user space will be erased (i.e. entire flas h m e m o ry except for reserved area 0x7e00 ? 0x7fff). (all other values for w r m d 3-0 are reserved.) b i t s 3-0: r d m d 3-0: r ead m ode sel ect b i t s . the read mode select bits control how th e interface logic responds to reads to the flashdat register per the following values: 0000: a flashdat read provi des t h e dat a i n t h e fashdat regi st er, but i s ot herwi s e i gnored. 0001: a flashdat read initiates a read of the byte addressed by th e flashadr register i f no operat i on i s current l y act i v e. thi s m ode i s used for bl ock reads. 0010: a flashdat read initiates a read of th e byte addressed by flashadr only if no operat i on i s act i v e and any dat a from a prev ious read has already been read from flashdat. this m ode allows single by tes to be read (or the last by te of a block) without initiating an extra read. (all other values for rdm d 3-0 are reserved.) figure 21.4. flashadr: jtag flash address register r e s e t v a l u e 0 x 0 0 0 0 b it15 b i t 0 thi s regi st er hol ds t h e address for al l jtag fl ash read, write, and erase operations. this register autoincrem ents after each read or write, regardless of whet her the operation succeeded or failed. b i t s 15-0: fl ash operat i on 16-bi t address. r e v. 1.7 168
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 figure 21.5. flashdat: jtag flash data register r e s e t v a l u e d a t a 7 d a t a 5 d a t a 4 d a t a 3 d a t a 2 f a i l f b u s y 0000000000 b i t 9 b i t 8 b i t 7 b i t 6 b i t 4 b i t 3 b i t 2 b i t 1 d a t a 6 d a t a 1 data0 b i t 5 b i t 0 this register is used to read or write data to the flash m e m o ry across the jtag interface. bits9 - 2 : data7 -0 : flash data byte. bit1 : fail: flash fail bit. 0: previ ous fl ash m e m o ry operat i on was successful . 1: previ ous fl ash m e m o ry operat i on fai l e d. usual l y i ndi cat es t h e associ at ed m e m o ry lo catio n was lo ck ed . bit0 : fbusy: flash bu sy bit. 0: flash interface logic is not busy. 1: flash interface logic is processing a reque st. reads or writes while fbusy = 1 will n o t in itiate an o t h e r o p e ratio n figure 21.6. flashscl: jtag flash scale register r e s e t v a l u e f o s e f r a e - f l s c l 3 f l s c l 1 0 0 0 0 0 0 0 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 - f l s c l 2 f l s c l 0 this register controls the flash read tim ing circuit and the prescaler requi red t o generat e t h e correct t i m i ng for fl ash operat i ons. bit7 : fose: flash on e-sh o t en ab le bit. 0: fl ash read st robe is a full clock-cycle wide. 1: fl ash read st robe i s 50nsec. bit6 : frae: flash read always bit. 0: the fl ash out put enabl e and sense am pl i f i e r enable are on only when needed to read the f l a s h me mo r y . 1: the fl ash out put enabl e and sense am pl i f i e r enable are always on. this can be used to l i m i t t h e vari at i ons i n di gi t a l suppl y current due t o swi t c hi ng t h e sense am pl i f i e rs, t h ereby reduci ng di gi t a l l y i nduced noi se. bi t s 5-4: unused. read = 00b, w r i t e = don?t care. bits3 - 0 : flscl3 -0 : flash prescaler co n t ro l bits. the flsc l3-0 bi t s cont rol t h e prescal er used t o generat e t i m i ng si gnal s for fl ash operations. its value should be written before any flash operations are initiated. the value written should be the sm allest integer for which: flscl[3:0] > log 2 (f sysclk / 50khz) w h ere f sysclk i s t h e sy st em cl ock frequency . al l fl ash read/ w ri t e / e rase operat i ons are di sal l o wed when flsc l [ 3: 0 ] = 1111b. 169 r e v. 1.7
c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 21.3. debug support each m c u has on-chi p jtag and debug ci rcui t r y t h at provi de non-i n t r usi ve, f u l l speed, i n -ci r cui t debug usi ng t h e product i on part i n st al l e d i n t h e end appl i c at i on using the four pin jtag i/f. silicon labs? debug system supports i n spect i on and m odi fi cat i on of m e m o ry and regi st ers, se t t i ng breakpoi nt s, wat c hpoi nt s, si ngl e st eppi ng, and run and hal t com m a nds. no addi t i onal t a rget r a m , program m e m o ry , or com m uni cat i ons channel s are requi red. al l t h e di gi t a l and anal og peri pheral s are funct i onal and work co rrect l y (rem a i n i n sy nc) whi l e debuggi ng. the w d t i s di sabl ed when t h e m c u i s hal t e d duri ng si ngl e st eppi ng or at a breakpoi nt . the c 8051f000dk, c 8051f005dk, c 8051f010dk, and c 8051f015dk are devel opm ent ki t s wi t h al l t h e hardware and software necessary to develop application code and perform in-circuit debugging with each mcu in t h e c 8051f000 fam i l y . each ki t i n cl udes an int e grat ed devel opm ent envi ronm ent (ide) whi c h has a debugger and i n t e grat ed 8051 assem b l e r. it has an r s -232 t o jtag prot ocol t r ansl at or m odul e referred t o as t h e ec . there i s al so a t a rget appl i cat i on board wi t h a c 8051f000, f005, f010, or f015 i n st al l e d and wi t h a l a rge prot ot y p i ng area. the ki t al so i n cl udes r s -232 and jtag cabl e s, and wal l - m ount power suppl y . r e v. 1.7 170
171 rev. 1.7 c8051f000/1/2/5/6/7 c8051f010/1/2/5/6/7 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for erro rs and omissions, and disclaims responsibility for any consequen ces resulting from the use of information included herein. addi tionally, silicon laboratories assumes no responsibility for the fun ctioning of undescribed features or parameters. s ilicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liability arising out of the application or use of any produc t or circuit, and specificall y disclaims any and all liability, including without limitation consequentia l or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered tr ademarks of their respective holders

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