1991 advanced micro devices, inc. publication # rev. amendment issue date 15923 a /0 6/91 fddi on copper with amd phy components by eugen gershon advanced micro devices
1991 advanced micro devices, inc. 1 publication # rev. amendment issue date 15923 a /0 6/91 fddi on copper with amd phy components by eugen gershon introduction this application note outlines an implementation using amd phy components found in either the supernet 1 or supernet 2 families to drive and receive signals over shielded twisted pair media. the circuit described meets the electrical specification of the interoperable solution (pid 16011a) endorsed by amd, chipcom, dec, motorola, and synoptics. this interoperable solu- tion (ios) is designed to minimize the cost of fddi con- nections confined within 100 meter range by replacing the optical transceiver and fiber with a shielded twisted pair (stp) transceiver and stp cabling. if a design util- izes amds supernet 1 or supernet 2 chipsets, no major changes are required; only a simple interface cir- cuit from the phy transmitter to the cable and another interface from the cable to the phy receiver are neces- sary. the interface can be implemented at minimal cost and with no more board space requirements than avail- able optical media interface connectors (mics). we built the circuit described herein using surface mount devices on a small daughter board that was form factor and pin-out compatible with the mic device found on one of our demonstration platforms. when optical pmd devices are removed from the board, the signals at their interface to the system should be kept intact, both in logical content and as voltage/current levels C see figure 1. the optical transmitter accepts both serial data out from the phy transmitter and output disable control (not used in ios), at p-ecl lev- els. similarly, the optical receiver supplies serial data in to the phy receiver and carrier detect status (here called link detect) at the same p-ecl levels. one new signal handled by the copper interface circuit is a status signal, incorporated into link detect, that shows that the cable is connected at both ends. it is detected by both transmitter and receiver because each one uses a sepa- rate twisted pair. this solution is designed to work on stp cable, 150 ohm, type 1 or 2. it specifies a maximum fddi sig- nal attenuation of 12 db (a factor of 4) at 100 meters. link detect phy transmitter t copper interface stp z0 = 150 w connection detected serial data out connection detected sufficient power level (signal detect) and d a t a i n phy receiver r copper interface stp z0 = 150 w serial data in d a t a o u t 15923a-001a figure 1. block diagram
fddi on copper with amd phy components 2 the transmit waveform going to the cable is required to meet a template based on a differential p-ecl output waveform, such as at the pdt (endec) outputs. this means that amd parts can be used to drive the stp ca- ble directly (source terminations should be added as re- quired by the ios specifications). also, the attenuated signal coming out of the cable at the receiver end is suffi- cient to allow clock and data recovery by the pdr (eds) without any need for amplification. transmitter interface the main coupling component to the cable is a trans- former, which should be designed for the speed (rise and fall time) and the frequency spectrum of the fddi signal. figure 2 shows the data path. the transformer shown is a 1:1 transformer with center taps made by pulse engineering, inc. r1 and r2 are biasing resistors for the output driver stage inside the pdt (endec). the output voltages are roughly 3 volts for low and 4 volts for high, therefore the resistor values can be calcu- lated from the average dc current: 3.5 v/r1 = 10 to 20 ma. r3 and r4 combined with the output impedance of the driver and with the transformer series impedance form the cable termination (150 ohms) at the transmitter end. r3 and r4 will reduce the output signal to the cable by a factor of two. the pdt output driver sees a differen- tial impedance of about 300 ohms in parallel with the 540 ohm biasing resistors. this requires less than its full driving capability of 100 ohms differential. ios specifies no precompensation at the transmitter end in order to minimize high frequency power levels in the transmitted signal spectrum, which improves the fcc-related performance. receiver interface the main coupling component at the receiver end is also the transformer. figure 3 shows the data path. r4, r5 and r6 are bias resistors to bring the input stage of the pdr (eds) to its dc operating point of about 3.5 volts. r5 provides a small offset voltage between rx and ry to keep the inputs (and outputs) stable in the absence of a carrier. the bias voltage level is isolated from the transformer secondary by c3 and c4. it is also possible to include the transformer in the dc path in order to avoid the need for capacitors c3 and c4. in this case a two-transformer option is a better choice. the r1, r2 and r3//r5 combination, and the parallel loading of link detect (not shown) give the proper cable termination at the receiver end (150 ohms). r1 and r2 with their paral- lel capacitors c1 and c2 form a high-pass filter that compensates for the high-frequency attenuation and phase shift in the cable. there are many possible cor- rect schemes for compensation. amds parts can run a 100 meter link without compensation in most cases, pro- vided the signal is not deteriorated by low performance transformers or external noise. however, in the interest of providing a robust implementation over the ios speci- fication, compensation has been included. ty r3 68 w either one 1:1 transformer with center taps (as shown), or two simple 1:1 transformers r4 68 w r1 270 w r2 270 w t1 ftp 4.0 stp 150 w tx 15923a-002a am79865 physical data transmitter (pdt) figure 2. transmitter interface for data out
fddi on copper with amd phy components 3 cable continuity detection as mentioned before ios requires a dc path to check cable connection between two (master and slave) stations. the cable continuity signal is one part of link detect status, which is comprised of both cable conti- nuity and minimum signal level. t1 ftp 4.0 either one 1:1 transformer with center taps (as shown), or two simple 1:1 transformers stp 150 w rx r6 6 k w r4 30 k w r5 150 w +5 v ry r3 10 k w c4 1 m c3 1 m r1 75 w r2 75 w c1 150 p c2 150 p 15923a-003a am79866 physical data receiver (pdr) figure 3. receive interface for data in figure 4 shows the required dc path for which there are two interoperable options. the simpler of the two solu- tions (shown) reports continuity if at least one of the wires in the twisted pair is connected. the second option requires both wires to be connected in order to report continuity, but its implementation uses more compo- nents. for example, the second option requires two transformers at each twisted pair end and cannot be im- plemented with one center-tapped transformer. both implementation options are shown in the ios document, appendix 1. the s-port cable continuity test will signal a high at the emitter output or a low at the collector output when the cable is connected. an m-port needs to check that the voltage across the re- sistor is within a window. a low voltage indicates no connection; a high voltage indicates a loop-back condi- tion. in both cases cable continuity signal is false. signal level detection the circuit for input signal level detection is based on a fast comparator. in figures 5 and 6 the comparator is built from a 4 transistor amplifier and a peak detector. in figure 7, a fast ic comparator is used. other implemen- tations are shown in the ios document. if the input sig- nal level is 50 mv or more peak-to-peak, and the cable is connected, the output level of link detect goes to high (4 volts).
fddi on copper with amd phy components 4 r3 68 w r4 68 w r1 270 w r2 270 w t1 ftp 4.0 t1 ftp 4.0 r1 75 w r2 75 w c1 150 p c2 150 p r3 68 w r4 68 w r1 270 w r2 270 w t1 ftp 4.0 t1 ftp 4.0 r1 75 w r2 75 w c1 150 p c2 150 p transmit transmit receive receive m-port s-port +5 v optocoupler vmin vmax window comparator 15923a-004a figure 4. the simple option for cable continuity detection lay-out during the time we have been experimenting with the copper interface, it has become apparent that one major source of problems is the computer noise coupled into the transmitted and received signals. little serial induc- tors were added to the serial lines that come from the pdt or endec (tx, ty), and go to the pdr or eds (rx, ry), to filter high frequency components that do not belong to the fddi signal. the protoypes we have built for preliminary testing were based on fastcards (endec and eds). the whole in- terface circuit, including data path, bias resistors and link detect, was plugged into the odl footprint. the newer generation of fastcards based on pdt/rs will use exactly the same interface. detailed schematics of an s-port and an m-port are shown in figures 5 and 6 respectively. since fcc compliance is dependent on both the circuit characteristics and the system lay-out and configura- tion, test results will vary from implementation to imple- mentation. however, the circuit includes noise sup- pressing elements to minimize emi.
fddi on copper with amd phy components 5 ty r29 270 w r28 270 w tx l10 0.15 m h l11 0.15 m h c5 1 m s-port t1 ftp 4.0 r6 150 w r3 10 k w c4 1 m c3 1 m l1 0.15 m h l2 0.15 m h r4 10 k w l5 0.15 m h l6 0.15 m h receive link detect r1 75 w r2 75 w c1 150 p c2 150 p l8 1.5 m h transmit r26 68 w r27 68 w t2 ftp 4.0 r21 250 w +5 v cable continuity detected r23 1 k w r24 600 w 4n32 5 4 1 2 r11 75 w l7 2.5 m h r8 300 w r9 3 k w r10 2 k w +5 v c6 1 m r13 3 k w r12 150 w r14 2 k w r19 1 k w signal level detected c9 1 m r15 2 k w r16 3 k w r17 150 w c8 1 m r18 300 w d1 1n6263 r20 10 k w r22 400 w q1 q1, q2, q4: 2n2369 or pn2369 or equivalent q3: 2n3639, pn3639, 2n3546 or equivalent q3 q2 r7 6 k w r5 30 k w +5 v rx ry l3 1.5 m h l4 1.5 m h r31 4 k w r30 500 w 15923a-005a q4 am79866 physical data receiver (pdr) am79865 physical data transmitter (pdt) figure 5. schematic for the s-port
fddi on copper with amd phy components 6 m-port figure 6. schematic for the m-port ty r29 270 w r28 270 w tx l10 0.15 m h l11 0.15 m h c5 1 m t1 ftp 4.0 r6 150 w r3 10 k w c4 1 m c3 1 m l1 0.15 m h l2 0.15 m h r4 10 k w l5 0.15 m h l6 0.15 m h receive link detect r1 75 w r2 75 w c1 150 p c2 150 p l8 1.5 m h r26 68 w r27 68 w t2 ftp 4.0 r21 650 w cable continuity detected r24 600 w r11 75 w l7 2.5 m h r8 300 w r9 3 k w r10 2 k w +5 v c6 1 m r13 3 k w r12 150 w r14 2 k w r19 1 k w signal level detected c9 1 m c7 1 m r15 2 k w r16 3 k w r17 150 w c8 1 m r18 300 w d1 1n6263 r20 10 k w r22 400 w q1 q4 q1, q2, q4: 2n2369 or pn2369 or equivalent q3: 2n3639, pn3639, 2n3546 or equivalent q3 q2 r7 6 k w r5 30 k w +5 v rx ry l3 1.5 m h l4 1.5 m h r31 4 k w r30 500 w r23 4 k w l9 1.5 m h +5 v r25 100 w transmit +5 v +5 v + C C + +5 v r32 1.5 k w r33 3.5 k w r34 3.5 k w r35 1.5 k w r36 1 k w u1 lm393 or lm2311 15923a-006a am79866 physical data receiver (pdr) am79865 physical data transmitter (pdt)
fddi on copper with amd phy components 7 u2 r14 250 w +5 v l8 1.5 m h c5 1 m r9 10 k w cable continuity detected r12 30 k w r10 20 k w r11 500 w +5 v r15 1 k w C + +5 v r13 500 w signal level detected c6 1 m u1 4n32 c7 10 n link detect d1 1n6263 r16 50 k w 1 2 5 4 +5 v ty r20 270 w r19 270 w tx l9 0.15 m h l10 0.15 m h s-port t1 ftp 4.0 r6 150 w r3 10 k w c4 1 m c3 1 m l1 0.15 m h l2 0.15 m h r4 10 k w l5 0.15 m h l6 0.15 m h receive r1 75 w r2 75 w c1 150 p c2 150 p transmit r17 68 w r18 68 w t2 ftp 4.0 l7 2.5 m h r8 300 w r7 6 k w r5 30 k w +5v rx ry l3 1.5 m h l4 1.5 m h C5 v lm361 strobe 15923a-007a am79866 physical data receiver (pdr) am79865 physical data transmitter (pdt) figure 7. alternative schematic for the s-port using a fast comparator for signal detect
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