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1. general description the pcf8562 is a peripheral device which interfaces to almost any liquid crystal display (lcd) with low multiplex rates. it gene rates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 32 segments. the pcf8562 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardwar e subaddressing and by display memory switching (static and duplex drive modes). aec-q100 compliant (pcf8562tt/s400) for automotive applications. 2. features and benefits ? single chip lcd controller and driver ? selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing ? selectable display bias configuration: static, 1 2 or 1 3 ? internal lcd bias generation with voltage-follower buffers ? 32 segment drives: ? up to sixteen 7-segment numeric characters ? up to eight 14-segment alphanumeric characters ? any graphics of up to 128 elements ? 32 4-bit ram for display data storage ? auto-incremented display data loading across device subaddress boundaries ? display memory bank switching in static and duplex drive modes ? versatile blinking modes ? independent supplies possible for lcd and logic voltages ? wide power supply range: from 1.8 v to 5.5 v ? wide logic lcd supply range: ? from 2.5 v for low-threshold lcds ? up to 6.5 v for guest-host lcds and high-threshold twisted nematic lcds ? low power consumption ? 400 khz i 2 c-bus interface ? no external components ? manufactured in silicon gate cmos process pcf8562 universal lcd driver fo r low multiplex rates rev. 05 ? 19 may 2010 product data sheet
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 2 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 3. ordering information 4. marking table 1. ordering information type number package name description version pcf8562tt/2 tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 pcf8562tt/s400/2 tssop48 plastic thin sh rink small outline package; 48 leads; body width 6.1 mm sot362-1 table 2. marking codes type number marking code pcf8562tt/2 pcf8562tt pcf8562tt/s400/2 pcf8562tt/s400
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 3 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 5. block diagram fig 1. block diagram of pcf8562 001aac262 lcd voltage selector clock select and timing blinker timebase oscillator input filters i 2 c-bus controller power-on reset clk sync osc scl sda sa0 backplane outputs display controller bp0 22 21 20 13 12 15 v dd 14 11 10 19 16 17 18 23 24 25 bp2 bp1 bp3 display segment outputs display register output bank select and blink control 26 to 48, 1 to 9 s0 to s31 a0 a1 a2 pcf8562 lcd bias generator v ss v lcd command decoder write data control display ram 40 4-bit data pointer and auto increment subaddress counter
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 4 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 6. pinning information 6.1 pinning top view. for mechanical details, see figure 20 . fig 2. pinning diagram for pcf8562 pcf8562tt s23 s22 s24 s21 s25 s20 s26 s19 s27 s18 s28 s17 s29 s16 s30 s15 s31 s14 sda s13 scl s12 sync s11 clk s10 v dd s9 osc s8 a0 s7 a1 s6 a2 s5 sa0 s4 v ss s3 v lcd s2 bp0 s1 bp2 s0 bp1 bp3 001aac263 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 5 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 6.2 pin description 7. functional description the pcf8562 is a versatile peripheral device designed to interface any microprocessor or microcontroller with a wide va riety of lcds. it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 32 segments. the possible display configur ations of the pcf8562 depend on the number of active backplane outputs required. a selection of display configurations is shown in ta b l e 4 . all of these configurations can be implem ented in the typical system shown in figure 3 . table 3. pin description symbol pin description sda 10 i 2 c-bus serial data input and output scl 11 i 2 c-bus serial clock input sync 12 cascade synchronization input or output clk 13 external clock input or output v dd 14 supply voltage osc 15 internal oscillator enable input a0 to a2 16 to 18 subaddress inputs sa0 19 i 2 c-bus address input; bit 0 v ss 20 ground supply voltage v lcd 21 lcd supply voltage bp0 to bp3 22 to 25 lcd backplane outputs s0 to s22, s23 to s31 26 to 48, 1 to 9 lcd segment outputs table 4. display configurations number of: 7-segment numeric 14-segment numeric dot matrix backplanes segments digits indicator symbols characters indicator symbols 4 128 16 16 8 16 128 dots (4 32) 3 96 12 12 6 12 96 dots (3 32) 2 64 8 8 4 8 64 dots (2 32) 1 32 4 4 2 4 32 dots (1 32)
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 6 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates the host microprocessor or microcontroller maintains the 2-line i 2 c-bus communication channel with the pcf8562. the internal oscillator is enabled by connecting pin osc to pin v ss . the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connec tions required to complete the system are to the power supplies (v dd , v ss and v lcd ) and the lcd panel chosen for the application. 7.1 power-on reset at power-on the pcf8562 resets to the following starting conditions: ? all backplane outputs are set to v lcd ? all segment outputs are set to v lcd ? the selected drive mode is: 1:4 multiplex with 1 3 bias ? blinking is switched off ? input and output bank selectors are reset ? the i 2 c-bus interface is initialized ? the data pointer and the subaddress counter are cleared (set to logic 0) ? display is disabled data transfers on the i 2 c-bus must be avoided for 1 ms following power-on to allow the reset action to complete. 7.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between v lcd and v ss . the middle resistor can be bypassed to provide a 1 2 bias voltage level for the 1:2 multiplex configuration. the lcd voltage can be temperature compensated externally using the supply to pin v lcd . the resistance of the power lines must be kept to a minimum. fig 3. typical system configuration host micro- processor/ micro- controller t r 2c b sda scl osc 32 segment drives 4 backplanes lcd panel (up to 128 elements) pcf8562 a0 16 15 11 10 14 21 17 18 19 20 a1 a2 sa0 v dd v ss v ss v dd v lcd 001aac26 4 r
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 7 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.3 lcd voltage selector the lcd voltage selector coordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the mode-set command from the command decoder. the biasing configurations that apply to the preferred modes of operatio n, together with the biasing characteristics as functions of v lcd and the resulting discrimina tion ratios (d) are given in ta b l e 5 . a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode a suitable choice is v lcd >3v th . multiplex drive modes of 1:3 and 1:4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller. bias is calculated by , where the values for a are a = 1 for 1 2 bias a = 2 for 1 3 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 : (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : (3) table 5. biasing characteristics lcd drive mode number of: lcd bias configuration backplanes levels static 1 2 static 0 1 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 1:3 multiplex 3 4 1 3 0.333 0.638 1.915 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 v off rms () v lcd ------------------------ - v on rms () v lcd ----------------------- - d v on rms () v off rms () ------------------------ - = 1 1a + ------------ - v on rms () a 2 2a n ++ n 1a + () 2 ----------------------------- - v lcd = v off rms () a 2 2a ? n + n 1a + () 2 ----------------------------- - v lcd = d v on rms () v off rms () ---------------------- - a1 + () 2 n 1 ? () + a1 ? () 2 n 1 ? () + ------------------------------------------- - ==
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 8 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates using equation 3 , the discrimination for an lcd drive mode of 1:3 multiplex with 1 2 bias is and the discrimination for an lcd drive mode of 1:4 multiplex with 1 2 bias is . the advantage of these lcd drive modes is a reduction of the lcd full scale voltage v lcd as follows: ? 1:3 multiplex ( 1 2 bias): ? 1:4 multiplex ( 1 2 bias): these compare with when 1 3 bias is used. it should be noted that v lcd is sometimes referred as the lcd operating voltage. 3 1.732 = 21 3 ---------- 1.528 = v lcd 6v off rms () 2.449v off rms () == v lcd 43 () 3 --------------------- - 2.309v off rms () == v lcd 3v off rms () =
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 9 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.4 lcd drive mode waveforms 7.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. the backplane (bpn) and segment drive (s n ) waveforms for this mode are shown in figure 4 . (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp0 (t). (4) v off(rms) = 0 v. fig 4. static driv e mode waveforms mgl745 v ss v lcd v ss v lcd v ss v lcd v lcd ? v lcd ? v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 10 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.4.2 1:2 multiplex drive mode the 1:2 multiplex drive mode is used when tw o backplanes are provided in the lcd. this mode allows fractional lcd bias voltages of 1 2 bias or 1 3 bias as shown in figure 5 and figure 6 . (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = 0.791v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp1 (t). (4) v off(rms) = 0.354v lcd . fig 5. waveforms for the 1:2 multiplex drive mode with 1 2 bias mgl746 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd / 2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd / 2 v lcd / 2 v lcd / 2 ? v lcd ? v lcd ? v lcd / 2 ? v lcd / 2 s n sn+1 t fr
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 11 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = 0.745v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp1 (t). (4) v off(rms) = 0.333v lcd . fig 6. waveforms for the 1:2 multiplex drive mode with 1 3 bias mgl747 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd ? v lcd 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 s n s n+1 t fr v ss v lcd 2v lcd / 3 v lcd / 3
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 12 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies (see figure 7 ). (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = 0.638v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp1 (t). (4) v off(rms) = 0.333v lcd . fig 7. waveforms for the 1:3 multiplex drive mode with 1 3 bias mgl748 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 (a) waveforms at driver. bp2 s n s n+1 s n+2 t fr v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd v ss v lcd 2v lcd / 3 v lcd / 3
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 13 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies (see figure 8 ). (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = 0.577v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp1 (t). (4) v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:4 multiplex drive mode with 1 3 bias mgl749 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd v ss v lcd 2v lcd / 3 v lcd / 3
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 14 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.5 oscillator 7.5.1 internal clock the internal logic of the pcf8562 and its lcd dr ive signals are timed either by its internal oscillator or by an external clock. the internal oscillator is enabled by connecting pin osc to pin v ss . 7.5.2 external clock pin clk is enabled as an external clock input by connecting pin osc to v dd . the lcd frame signal frequency is determined by the clock frequency (f clk ). a clock signal must always be supplied to the device; removing the clock freezes the lcd in a dc state. 7.6 timing the pcf8562 timing controls the internal da ta flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. the timing also generates the lcd frame signal whose frequency is derived from the clock frequency. the frame signal frequency is a fix ed division of the clock frequency from either the internal or an external clock: . 7.7 display register the display latch holds the display data wh ile the corresponding multiplex signals are generated. there is a one-to-one relationshi p between the data in the display latch, the lcd segment outputs and each column of the display ram. 7.8 segment outputs the lcd drive section includes 32 segment outputs s0 to s31 which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. when less than 32 segment outputs are required, the unused segment outputs should be left open-circuit. 7.9 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which must be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required, the unused outputs can be left open-circuit. in the 1:3 multiplex drive mode, bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied togethe r to give enhanced drive capabilities. in the 1:2 multiplex drive mode, bp0 and bp2, bp1 and bp3 all carry the same signals and may also be paired to in crease the drive capabilities. in the static drive mode the same signal is ca rried by all four backplane outputs and they can be connected in parallel for very high drive requirements. f fr f clk 24 ------- =
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 15 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.10 display ram the display ram is a static 32 4-bit ram which stores lcd data. a logic 1 in the ram bit-map indicates the on-state of the corresponding lcd element; similarly, a logic 0 indicates the off-state. there is a one -to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. the display ram bit map figure 9 shows the rows 0 to 3 which correspond with the backplane outputs bp0 to bp3, and the columns 0 to 31 which correspond with the segment outputs s0 to s31. in multiplexed lcd applications the segment data of the first, second, third and fourth row of the display ram are time-multiplexed with bp0, bp1 , bp2 and bp3 respectively. when display data is transmitted to the pcf8562, the display bytes received are stored in the display ram in accordance with the selected lcd drive mode. the data is stored as it arrives and does not wait for an acknowledg e cycle as with the commands. depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. to illustrate the filling order, an example of a 7-s egment numeric displa y showing all drive modes is given in figure 10 ; the ram filling organization depi cted applies eq ually to other lcd types. the following applies to figure 10 : ? in the static drive mode, the eight transmitt ed data bits are placed in row 0 of eight successive 4-bit ram words. ? in the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into row 0 and 1 of four succes sive 4-bit ram words. ? in the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to three successive 4-bit ram words, with bit 3 of the third address left unchanged. it is not recommended to use this bit in a displa y because of the difficult addressing. this last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. ? in the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2 and 3 of two successive 4-bit ram words. display ram bit map showing direct relation ship between ram addresses and segment outputs; also between bits in a ram word and the backplane outputs. fig 9. display ram bit map 0 0 1 2 3 1 2 3 4 27 28 29 30 31 display ram addresses/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 001aac265
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 16 of 37 nxp semiconductors pcf8562 universal lcd driver for low multiplex rates x = data bit unchanged. fig 10. relationship between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c-bus 001aaj64 6 acbdpf egd msb lsb bdpcadgfe msb lsb abfgecddp msb lsb cba f geddp msb lsb drive mode static 1:2 multiplex 1:3 multiplex 1:4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte bp0 bp0 bp1 bp0 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 rows display ram rows/backplane outputs (bp) byte1 columns display ram address/segment outputs (s) n a b x x 0 1 2 3 f g x x e c x x d dp x x n + 1 n + 2 n + 3 byte1 byte2 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n b dp c x 0 1 2 3 a d g x f e x x n + 1 n + 2 byte1 byte2 byte3 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n + 1 n a c b dp 0 1 2 3 f e g d byte1 byte2 byte3 byte4 byte5 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) s n+2 s n+3 s n+1 s n dp a f b g e c d s n+2 s n+1 s n+7 s n s n+3 s n+5 s n+6 s n+4 dp a f b g e c d s n s n+1 s n+2 dp a f b g e c d s n+1 s n dp a f b g e c d
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 17 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the se quence commences with the initialization of the data pointer by the load-data-pointer command (see section 7.17 ). following this command, an arriving data byte is stored at the display ram address indicated by the data pointe r. the filling order shown in figure 10 . after each byte is stored, the contents of the data pointer is automatically incremented by a value dependent on the selected lcd drive mode: ? in static drive mode by eight ? in 1:2 multiplex drive mode by four ? in 1:3 multiplex drive mode by three ? in 1:4 multiplex drive mode by two if an i 2 c-bus data access is terminated early then the state of the data pointer is unknown. the data pointer should be re-written prior to further ram accesses. 7.12 subaddress counter the storage of display data is determined by the contents of the subaddress counter. storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to a0, a1 and a2. the subaddress counter value is defined by the device-select command (see section 7.17 ). if the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremente d as if data storage had taken place. the subaddress counter is also incremented when the data pointer overflows. the hardware subaddress must not be changed while the device is being accessed on the i 2 c-bus interface. 7.13 output bank selector the output bank selector selects one of the four rows per display ram address for transfer to the display register. the actual row selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode, all ram addresses of row 0 are selected, these are followed by the contents of row 1, row 2 and then row 3. ? in 1:3 multiplex mode, row 0, 1 and 2 are selected sequentially ? in 1:2 multiplex mode, row 0 and 1 are selected ? in static mode, row 0 is selected the pcf8562 includes a ram bank switching fe ature in the static and 1:2 drive modes. in the static drive mode, t he bank-select command (see section 7.17 ) may request the contents of row 2 to be selected for display instead of the contents of row 0. in 1:2 mode,
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 18 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates the contents of rows 2 and 3 may be selected instead of rows 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.14 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. the bank-select command (see section 7.17 ) can be used to load display data in row 2 in static drive mode or in rows 2 and 3 in 1:2 mo de. the input bank selector functions are independent of the output bank selector. 7.15 blinker the pcf8562 has a very versatile display blinking capab ility. the whole display can blink at a frequency selected by the blink-select command (see ta b l e 1 3 ). each blink frequency is a fraction of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected (see table 6 ). an additional feature allows an arbitrary sele ction of lcd segments to blink in the static and 1:2 drive modes. this is implemented without any communication overheads by the output bank selector which al ternates the displayed data between the data in the display ram bank and the data in an alternative ram bank at the blink frequency. this mode can also be implemented by the blink-select command (see section 7.17 ). in the 1:3 and 1:4 drive modes, where no al ternative ram bank is available, groups of lcd segments can blink selectively by changing the display ram data at fixed time intervals. the entire display can blink at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit e at the required rate using the mode-set command (see section 7.17 ). [1] blink modes 1, 2 and 3 and the nominal blink frequenc ies 0.5 hz, 1 hz and 2 hz correspond to an oscillator frequency (f clk ) of 1536 hz (see section 11 ). table 6. blinking frequencies [1] blink mode normal operating mode ratio nominal blink frequency off - blinking off 12 hz 21 hz 3 0.5 hz f clk 768 --------- - f clk 1536 ------------ - f clk 3072 ------------ -
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 19 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.16 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.16.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 11 ). 7.16.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition - s. a low-to-high transition of the data line while the clock is high is defined as the stop condition - p (see figure 12 ). 7.16.3 system configuration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 13 ). fig 11. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 12. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 20 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.16.4 acknowledge the number of data bytes that can be transferred from transmitter to receiver between the start and stop conditions is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high -level signal on the bus that is asserted by the transmitter during which time the ma ster generates an extra acknowledge related clock pulse. an addressed slave receiver must generate an acknowledge after receiving each byte. also a master receiver must generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. the acknowledging device must pull-down the sda line during the acknowledge clock pulse so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowle dge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition (see figure 14 ). 7.16.5 i 2 c-bus controller the pcf8562 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pcf8562 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferre d command data and on the hardware subaddress. fig 13. system configuration mga80 7 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig 14. acknowledgement of the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 21 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 7.16.6 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 7.16.7 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are reserved for the pcf8562. the least significant bit of the slave address that a pcf8562 will respon d to is defined by the level tied to its sa0 input. the pcf8562 is a write-only device and will not respond to a read access. the i 2 c-bus protocol is shown in figure 15 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of two possible pcf8562 slave addresses available. all pcf8562s whose sa0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. this i 2 c-bus transfer is ignored by all pcf8562s whose sa0 inputs are set to the alternative level. after an acknowledgement, one or more command bytes follow, that define the status of each addressed pcf8562. the last command byte sent is identified by resetting its most signif icant bit, continuation bit c, (see figure 16 ). the command bytes are also acknowledged by all addressed pcf8562s on the bus. after the last command byte, one or more display data bytes may follow. display data bytes are stored in the display ram at the ad dress specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated. fig 15. i 2 c-bus protocol fig 16. format of command byte mdb07 8 s a 0 s 011100 0ac command a p a display data slave address r/w acknowledge by all addressed pcf8576ds acknowledge by a0, a1 and a2 selected pcf8576d only 1 byte update data pointers and if necessary, subaddress counter n 1 byte(s) n 0 byte(s) msa833 rest of opcode c msb lsb
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 22 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates an acknowledgement after each byte is asserted only by the pcf8562s that are addressed via address lines a0, a1 and a2. after the last display byte, the i 2 c-bus master asserts a stop condition (p). alternately a start may be asserted to restart an i 2 c-bus access. 7.17 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. the commands available to the pcf8562 are defined in ta b l e 7 . [1] not used. all available commands carry a continuation bit c in their most significant bit position as shown in figure 16 . when this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. if this bit is reset, it indicates that the command byte is the last in the transfe r. further bytes will be re garded as display data (see ta b l e 8 ). table 7. definition of pcf8562 commands command operation code reference bit 7 6 5 4 3 2 1 0 mode-set c 1 0 [1] ebm1m0 ta b l e 9 load-data-pointer c 0 0 p4 p3 p2 p1 p0 ta b l e 1 0 device-select c1100a2a1a0 ta b l e 11 bank-select c 1 1 1 1 0 i o ta b l e 1 2 blink-select c 1 1 1 0 a bf1 bf0 ta b l e 1 3 table 8. c bit description bit symbol value description 7c continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue; next byte will be a command too
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 23 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates [1] the possibility to disable the display allows implementation of blinking under external control. table 9. mode-set command bits description bit symbol value description 7c0, 1see ta b l e 8 6, 5 - 10 fixed value 4 - - unused 3e display status 0 disabled (blank) [1] 1 enabled 2b lcd bias configuration 0 1 3 bias 1 1 2 bias 1 to 0 m[1:0] lcd drive mode selection 01 static; bp0 10 1:2 multiplex; bp0, bp1 11 1:3 multiplex; bp0, bp1, bp2 00 1:4 multiplex; bp0, bp1, bp2, bp3 table 10. load-data-pointer command bits description bit symbol value description 7c0, 1see ta b l e 8 6, 5 - 00 fixed value 4 to 0 p[4:0] 00000 to 11111 5 bit binary value, 0 to 31; transferred to the data pointer to define one of 32 display ram addresses table 11. device-select command bits description bit symbol value description 7c0, 1see ta b l e 8 6 to 3 - 1100 fixed value 2 to 0 a[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 24 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates [1] the bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. [1] normal blinking is assumed when the lcd multiplex drive modes 1:3 or 1:4 are selected. [2] alternate ram bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. 7.18 display controller the display controller executes the command s identified by the command decoder. it contains the device?s status registers and co ordinates their effects. the display controller is also responsible for loadi ng display data into t he display ram in the correct filling order. 7.19 multiple chip operation for large display configurations or for more segments (> 128 elements) to drive please refer to the pc f8576d device. the contact resistance between the sync input/output on each cascaded device must be controlled. if the resist ance is too high, the device will no t be able to sync hronize properly; this is particularly applicable to chip-on-glass applications. the maximum sync contact resistance allowed for the number of devices in cascade is given in ta b l e 1 4 . table 12. bank-select command bits description bit symbol value description static 1:2 multiplex [1] 7c0, 1see ta b l e 8 6 to 2 - 11110 fixed value 1i input bank selection ; storage of arriving display data 0 ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 0o output bank selection ; retrieval of lcd display data 0 ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 table 13. blink-select co mmand bits description bit symbol value description 7c0, 1see ta b l e 8 6 to 3 - 1110 fixed value 2a blink mode selection 0 normal blinking [1] 1 alternate ram bank blinking [2] 1 to 0 bf[1:0] blink frequency selection 00 off 01 1 10 2 11 3
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 25 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 8. internal circuitry table 14. sync contact resistance number of devices maximum contact resistance 2 6000 3to5 2200 6to10 1200 10 to 16 700 fig 17. device protection circuits sa0 v dd v dd v ss v ss v lcd v ss sda 001aac269 v ss scl v ss clk v dd v ss osc v dd v ss sync v dd v ss a0, a1, a2 v dd v ss bp0, bp1, bp2, bp3 v lcd v ss s0 to s31 v lcd v ss
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 26 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 9. limiting values [1] pass level; human body model (hbm) according to jesd22-a114. [2] pass level; machine model (mm), according to jesd22-a115. [3] pass level; charged-device model (cdm), according to jesd22-c101. [4] pass level; latch-up testing, according to jesd78. [5] according to the nxp store and transport conditions (document snw-sq-623 ) the devices have to be stored at a temperature of +5 c to +45 c and a humidity of 25 % to 75 %. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. table 15. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 6.5 v v lcd lcd supply voltage ? 0.5 +7.5 v v i input voltage on each of the pins clk, sda, scl, sync , sa0, osc, a0 to a2 ? 0.5 +6.5 v v o output voltage on each of the pins s0 to s31, bp0 to bp3 ? 0.5 +7.5 v i i input current ? 10 +10 ma i o output current ? 10 +10 ma i dd supply current ? 50 +50 ma i dd(lcd) lcd supply current ? 50 +50 ma i ss ground supply current ? 50 +50 ma p tot total power dissipation - 400 mw p o output power - 100 mw v esd electrostatic discharge voltage hbm [1] - 2000 v mm [2] - 200 v cdm [3] - 2000 v i lu latch-up current [4] - 100 ma t stg storage temperature [5] ? 65 +150 c
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 27 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 10. static characteristics [1] v lcd > 3 v for 1 3 bias. [2] lcd outputs are open-circuit; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [3] when tested, i 2 c pins scl and sda have no diode to v dd and may be driven to the v i limiting values given in ta b l e 1 5 (see figure 17 too). [4] propagation delay of driver between clock (clk) and lcd driving signals. [5] periodically sampled, not 100 % tested. [6] outputs measured one at a time. table 16. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage [1] 2.5 - 6.5 v i dd supply current f clk = 1536 hz [2] -820 a i dd(lcd) lcd supply current f clk = 1536 hz [2] -2460 a logic v p(por) power-on reset supply voltage 1.0 1.3 1.6 v v il low-level input voltage on pins clk, sync , osc, a0 to a2, sa0, scl, sda v ss -0.3v dd v v ih high-level input voltage on pins clk, sync , osc, a0 to a2, sa0, scl, sda [3] [4] 0.7v dd -v dd v i ol low-level output current v ol = 0.4 v; v dd =5v on pins clk and sync 1- - ma on pin sda 3 - - ma i oh(clk) high-level output current on pin clk v oh =4.6v; v dd =5v ? 1- - ma i l leakage current v i =v dd or v ss ; on pins clk, scl, sda, a0 to a2 and sa0 ? 1- +1 a i l(osc) leakage current on pin osc v i =v dd ? 1- +1 a c i input capacitance [5] --7pf lcd outputs v o output voltage variation on pins bp0 to bp3 and s0 to s31 ? 100 - +100 mv r o output resistance v lcd = 5 v [6] on pins bp0 to bp3 - 1.5 - k on pins s0 to s31 - 6.0 - k
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 28 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 11. dynamic characteristics [1] typical output duty factor: 50 % measured at the clk output pin. [2] not tested in production. [3] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . table 17. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit clock f clk(int) internal clock frequency [1] 1440 1850 2640 hz f clk(ext) external clock frequency 960 - 2640 hz t clk(h) high-level clock time 60 - - s t clk(l) low-level clock time 60 - - s synchronization t pd(sync_n) sync propagation delay - 30 - ns t sync_nl sync low time 1 - - s t pd(drv) driver propagation delay v lcd = 5 v [2] --30 s i 2 c-bus [3] pin scl f scl scl clock frequency - - 400 khz t low low period of the scl clock 1.3 - - s t high high period of the scl clock 0.6 - - s pin sda t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns pins scl and sda t buf bus free time between a stop and start condition 1.3 - - s t su;sto set-up time for stop condition 0.6 - - s t hd;sta hold time (repeated) start condition 0.6 - - s t su;sta set-up time for a repeated start condition 0.6 - - s t r rise time of both sda and scl signals f scl = 400 khz - - 0.3 s f scl < 125 khz - - 1.0 s t f fall time of both sda and scl signals - - 0.3 s c b capacitive load for each bus line - - 400 pf t w(spike) spike pulse width on the i 2 c-bus--50ns
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 29 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates fig 18. driver timing waveforms fig 19. i 2 c-bus timing waveforms 001aac26 8 0.7v dd 0.3v dd 0.7v dd 0.3v dd sync clk 0.5 v 0.5 v t pd(lcd) t pd(sync) bp0 to bp3, and s0 to s31 t pd(sync) t syncl (v dd = 5 v) 1/f clk t clkl t clkh sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 30 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 12. package outline fig 20. package outline sot362-1 (tssop48) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot362-1 99-12-27 03-02-19 w m a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 124 48 25 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.25 8.3 7.9 0.50 0.35 0.8 0.4 0.08 0.8 0.4 p e v m a a t ssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362 -1 a max. 1.2 0 2.5 5 mm scale mo-153
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 31 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 13. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 32 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 21 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 8 and 19 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 21 . table 18. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 19. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 33 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 15. abbreviations msl: moisture sensitivity level fig 21. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 20. abbreviations acronym description cmos complementary metal oxide semiconductor cdm charged-device model hbm human body model ito indium tin oxide lcd liquid crystal display lsb least significant bit mm machine model msb most significant bit msl moisture sensitivity level pcb printed circuit board ram random access memory rms root mean square scl serial clock line sda serial data line smd surface mount device
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 34 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 16. revision history table 21. revision history document id release date data sheet status change notice supersedes pcf8562_5 20100519 product data sheet - pcf8562_4 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? corrected marking code of s400 type pcf8562_4 20090318 product data sheet - pcf8562_3 pcf8562_3 20081202 product data sheet - pcf8562_2 pcf8562_2 20070122 product data sheet - pcf8562_1 pcf8562_1 20050801 product data sheet - -
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 35 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
pcf8562_5 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 05 ? 19 may 2010 36 of 37 nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are da ta sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcf8562 universal lcd driver fo r low multiplex rates ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 19 may 2010 document identifier: pcf8562_5 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 lcd bias generator . . . . . . . . . . . . . . . . . . . . . 6 7.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 lcd drive mode waveforms . . . . . . . . . . . . . . . 9 7.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 7.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 10 7.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 12 7.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 13 7.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 7.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 7.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.11 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.12 subaddress counter . . . . . . . . . . . . . . . . . . . . 17 7.13 output bank selector . . . . . . . . . . . . . . . . . . . 17 7.14 input bank selector . . . . . . . . . . . . . . . . . . . . . 18 7.15 blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.16 characteristics of the i 2 c-bus. . . . . . . . . . . . . 19 7.16.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.16.2 start and stop conditions . . . . . . . . . . . . . 19 7.16.3 system configuration . . . . . . . . . . . . . . . . . . . 19 7.16.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.5 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 20 7.16.6 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.7 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 7.17 command decoder . . . . . . . . . . . . . . . . . . . . . 22 7.18 display controller . . . . . . . . . . . . . . . . . . . . . . 24 7.19 multiple chip operation . . . . . . . . . . . . . . . . . . 24 8 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 10 static characteristics. . . . . . . . . . . . . . . . . . . . 27 11 dynamic characteristics . . . . . . . . . . . . . . . . . 28 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 13 handling information . . . . . . . . . . . . . . . . . . . 31 14 soldering of smd packages . . . . . . . . . . . . . . 31 14.1 introduction to soldering. . . . . . . . . . . . . . . . . 31 14.2 wave and reflow soldering. . . . . . . . . . . . . . . 31 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 32 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 32 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 34 17 legal information . . . . . . . . . . . . . . . . . . . . . . 35 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 35 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18 contact information . . . . . . . . . . . . . . . . . . . . 36 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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