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| 1 LTC2400 features descriptio u applicatio s u typical applicatio u 24-bit m power no latency ds tm adc in so-8 n weight scales n direct temperature measurement n gas analyzers n strain-gage transducers n instrumentation n data acquisition n industrial process control n 6-digit dvms total unadjusted error vs output code n 24-bit adc in so-8 package n 4ppm inl, no missing codes n 4ppm full-scale error n single conversion settling time for multiplexed applications n 0.5ppm offset n 0.3ppm noise n internal oscillatorno external components required n 110db min, 50hz/60hz notch filter n reference input voltage: 0.1v to v cc n live zeroextended input range accommodates 12.5% overrange and underrange n single supply 2.7v to 5.5v operation n low supply current (200 m a) and auto shutdown the ltc ? 2400 is a 2.7v to 5.5v micropower 24-bit converter with an integrated oscillator, 4ppm inl and 0.3ppm rms noise. it uses delta-sigma technology and provides single cycle settling time for multiplexed appli- cations. through a single pin the LTC2400 can be config- ured for better than 110db rejection at 50hz or 60hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency in the range 1hz to 120hz. the internal oscillator requires no external frequency setting components. the converter accepts any external reference voltage from 0.1v to v cc . with its extended input conversion range of C12.5% v ref to 112.5% v ref , the LTC2400 smoothly resolves the offset and overrange problems of preceding sensors or signal conditioning circuits. the LTC2400 communicates through a flexible 3-wire digital interface which is compatible with spi and microwire tm protocols. v cc f o v ref sck v in sdo gnd cs reference voltage 0.1v to v cc analog input range 0.12v ref to 1.12v ref = internal osc/50hz rejection = external clock source = internal osc/60hz rejection 3-wire spi interface 1 f 2.7v to 5.5v LTC2400 2400 ta01 v cc output code (decimal) 0 8,338,608 16,777,215 linearity error (ppm) 2400 ta02 10 8 6 4 2 0 ? ? ? ? ?0 v cc = 5v v ref = 5v t a = 25 c f o = low , ltc and lt are registered trademarks of linear technology corporation. no latency ? s is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation.
2 LTC2400 symbol parameter conditions min typ max units v in input voltage range (note 14) l C 0.125 ? v ref 1.125 ? v ref v v ref reference voltage range l 0.1 v cc v c s(in) input sampling capacitance 10 pf c s(ref) reference sampling capacitance 15 pf i in(leak) input leakage current cs = v cc l C10 1 10 na i ref(leak) reference leakage current v ref = 2.5v, cs = v cc l C10 1 10 na order part number consult factory for military grade parts. s8 part marking (notes 1, 2) supply voltage (v cc ) to gnd ....................... C 0.3v to 7v analog input voltage to gnd ....... C 0.3v to (v cc + 0.3v) reference input voltage to gnd .. C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range LTC2400c ............................................... 0 c to 70 c LTC2400i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c t jmax = 125 c, q ja = 130 c/w LTC2400cs8 LTC2400is8 2400 2400i parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , (note 5) l 24 bits integral nonlinearity v ref = 2.5v (note 6) l 2 10 ppm of v ref v ref = 5v (note 6) l 4 15 ppm of v ref offset error 2.5v v ref v cc l 0.5 2 ppm of v ref offset error drift 2.5v v ref v cc 0.01 ppm of v ref / c full-scale error 2.5v v ref v cc l 4 10 ppm of v ref full-scale error drift 2.5v v ref v cc 0.02 ppm of v ref / c total unadjusted error v ref = 2.5v 5 ppm of v ref v ref = 5v 10 ppm of v ref output noise v in = 0v (note 13) 1.5 m v rms normal mode rejection 60hz 2% (note 7) l 110 130 db normal mode rejection 50hz 2% (note 8) l 110 130 db power supply rejection, dc v ref = 2.5v, v in = 0v 100 db power supply rejection, 60hz 2% v ref = 2.5v, v in = 0v, (notes 7, 15) 110 db power supply rejection, 50hz 2% v ref = 2.5v, v in = 0v, (notes 8, 15) 110 db the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) absolute m axi m u m ratings w ww u package/order i n for m atio n uu w co n verter characteristics u a alog i put a d refere ce u u u u 1 2 3 4 8 7 6 5 top view f o sck sdo cs v cc v ref v in gnd s8 package 8-lead plastic so 3 LTC2400 symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 9) l 2.5 v sck 2.7v v cc 3.3v (note 9) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 9) l 0.8 v sck 2.7v v cc 5.5v (note 9) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o i in digital input current 0v v in v cc (note 9) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 9) 10 pf sck v oh high level output voltage i o = C 800 m a l v cc C 0.5v v sdo v ol low level output voltage i o = 1.6ma l 0.4v v sdo v oh high level output voltage i o = C 800 m a (note 10) l v cc C 0.5v v sck v ol low level output voltage i o = 1.6ma (note 10) l 0.4v v sck i oz high-z output leakage l C10 10 m a sdo the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 12) l 200 300 m a sleep mode cs = v cc (note 12) l 20 30 m a the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) digital i puts a d digital outputs u u power require e ts w u 4 LTC2400 the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) f eosc external oscillator frequency range l 2.56 307.2 khz t heo external oscillator high period l 0.5 390 m s t leo external oscillator low period l 0.5 390 m s t conv conversion time f o = 0v l 130.66 133.33 136 ms f o = v cc l 156.80 160 163.20 ms external oscillator (note 11) l 20480/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 10) 19.2 khz external oscillator (notes 10, 11) f eosc /8 khz d isck internal sck duty cycle (note 10) l 45 55 % f esck external sck frequency range (note 9) l 2000 khz t lesck external sck low period (note 9) l 250 ns t hesck external sck high period (note 9) l 250 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 10, 12) l 1.64 1.67 1.70 ms external oscillator (notes 10, 11) l 256/f eosc (in khz) ms t dout_esck external sck 32-bit data output time (note 9) l 32/f esck (in khz) ms t 1 cs to sdo low z l 0 150 ns t2 cs - to sdo high z l 0 150 ns t3 cs to sck (note 10) l 0 150 ns t4 cs to sck - (note 9) l 50 ns t kqmax sck to sdo valid l 200 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7 to 5.5v unless otherwise specified. note 4: internal conversion clock source with the f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f o = 0v (internal oscillator) or f eosc = 153600hz 2% (external oscillator). note 8: f o = v cc (internal oscillator) or f eosc = 128000hz 2% (external oscillator). note 9: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 10: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 13: the output noise includes the contribution of the internal calibration operations. note 14: for reference voltage values v ref > 2.5v the extended input of C 0.125 ? v ref to 1.125 ? v ref is limited by the absolute maximum rating of the analog input voltage pin (pin 3). for 2.5v < v ref 0.267v + 0.89 ? v cc the input voltage range is C 0.3v to 1.125 ? v ref . for 0.267v + 0.89 ? v cc < v ref v cc the input voltage range is C 0.3v to v cc + 0.3v. note 15: the dc voltage at v cc = 4.1v, and the ac voltage applied to v cc is 2.8v p-p ti i g characteristics u w 5 LTC2400 total unadjusted error (3v supply) inl (3v supply) negative input extended total unadjusted error (3v supply) positive input extended total unadjusted error (3v supply) total unadjusted error (5v supply) inl (5v supply) negative input extended total unadjusted error (5v supply) offset error vs reference voltage positive input extended total unadjusted error (5v supply) typical perfor a ce characteristics uw input voltage (v) 0 ?0 error (ppm) ? 0 5 10 0.5 1.0 1.5 2.0 2400 g01 2.5 3.0 t a = 55 c, 45 c, 25 c, 90 c v cc = 3v v ref = 3v input voltage (v) 0 ?0 error (ppm) ? 0 5 10 0.5 1.0 1.5 2.0 2400 g02 2.5 3.0 t a = 55 c, 45 c, 25 c, 90 c v cc = 3v v ref = 3v input voltage (v) 0.30 ?0 error (ppm) ? 0 5 10 0.25 0.20 0.15 0.10 2400 g03 0.05 0 v cc = 3v v ref = 3v t a = 90 c t a = 25 c t a = 45 c t a = 55 c input voltage (v) 3.0 ?0 error (ppm) ? 0 5 10 t a = 55 c v cc = 3v v ref = 3v 3.1 3.2 2400 g04 3.3 t a = 45 c t a = 90 c t a = 25 c input voltage (v) 0 error (ppm) 2 6 10 4 2400 g05 ? ? 0 4 8 ? ? ?0 1 2 3 5 t a = 55 c, 45 c, 25 c, 90 c v cc = 5v v ref = 5v input voltage (v) 0 error (ppm) 0 5 4 2400 g06 ? ?0 1 2 3 5 10 t a = 55 c, 45 c, 25 c, 90 c v cc = 5v v ref = 5v input voltage (v) 0.30 ?0 error (ppm) ? 0 5 10 0.25 0.20 0.15 0.10 2400 g07 0.05 0 v cc = 5v v ref = 5v t a = 90 c t a = 25 c t a = 45 c t a = 55 c input voltage (v) 5.0 ?0 error (ppm) ? 0 5 10 t a = 55 c v cc = 5v v ref = 5v 5.1 5.2 2400 g08 5.3 t a = 45 c t a = 90 c t a = 25 c reference voltage 0 4 5 6 34 2400 g09 3 2 12 5 1 0 ? offset error (ppm) v cc = 5v t a = 25 c 6 LTC2400 rms noise vs reference voltage offset error vs v cc offset error vs temperature noise histogram full-scale error vs temperature full-scale error vs reference voltage rms noise vs code out full-scale error vs v cc rms noise vs v cc typical perfor a ce characteristics uw reference voltage (v) 0 rms noise (ppm of v ref ) 10 15 4 2400 g10 5 0 1 2 3 5 20 v cc = 5v t a = 25 c v cc 2.7 rms noise (ppm) 0 2.5 5.0 3.2 3.7 4.2 4.7 2400 g12 5.2 v ref = 2.5v t a = 25 c output code (ppm) 0 number of readings 500 1000 1500 v cc = 5v v ref = 5v v in = 0v 0.5 0 0.5 1.0 2400 g14 1.5 ?.0 code out (hex) 0 rms noise (ppm) 0.50 0.75 ffffff 2400 g18 0.25 0 7fffff 1.00 v cc = 5v v ref = 5v v in = 0.3v to 5.3v t a = 25 c temperature ( c) ?5 5.0 offset error (ppm) 2.5 0 2.5 5.0 ?0 5 20 45 2400 g13 70 95 120 v cc = 5v v ref = 5v v in = 0v temperature ( c) ?5 5.0 full-scale error (ppm) 2.5 0 2.5 5.0 ?0 5 20 45 2400 g15 70 95 120 v cc = 5v v ref = 5v v in = 5v reference voltage (v) 0 full-scale error (ppm) 5.0 7.5 4 2400 g16 2.5 0 1 2 3 5 10.0 v cc = 5v v in = v ref v cc 2.7 0 full-scale error (ppm) 2 1 3 5 4 6 3.2 3.7 4.2 4.7 2400 g17 5.2 v ref = 2.5v v in = 2.5v t a = 25 c v cc 2.7 5.0 offset error (ppm) 2.5 0 2.5 5.0 3.2 3.7 4.2 4.7 2400 g11 5.2 v ref = 2.5v t a = 25 c 7 LTC2400 conversion current vs temperature sleep current vs temperature psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc rejection vs frequency at v in rejection vs frequency at v in rejection vs frequency at v in typical perfor a ce characteristics uw temperature ( c) ?5 supply current ( a) 220 20 2400 g19 190 170 ?0 5 45 160 150 230 210 200 180 70 95 120 v cc = 5.5v v cc = 4.1v v cc = 2.7v temperature ( c) ?5 supply current ( a) 20 25 30 20 70 2400 g20 15 10 ?0 5 45 95 120 5 0 v cc = 2.7v, 5.5v frequency at v cc (hz) 0 130 rejection (db) 110 ?0 ?0 ?0 ?0 ?0 50 100 150 200 2400 g21 250 v cc = 4.1v v in = 0v t a = 25 c f 0 = 0 frequency at v cc (hz) 15200 120 rejection (db) 100 ?0 ?0 ?0 0 15250 15300 15350 15400 1635 g22 15450 15500 ?0 v cc = 4.1v v in = 0v t a = 25 c f o = 0 frequency at v cc (hz) 1 ?20 rejection (db) ?00 ?0 ?0 ?0 ?0 0 100 10k 1m 2400 g23 v cc = 4.1v v in = 0v t a = 25 c f o = 0 15,360hz 153,600hz frequency at v in (hz) 1 120 rejection (db) 100 ?0 ?0 ?0 ?0 0 50 100 150 200 2400 g24 250 v cc = 5v v ref = 5v v in = 2.5v f o = 0 input frequency deviation from notch frequency (%) 12 8 404812 rejection (db) 2400 g25 ?0 ?0 ?0 ?0 100 110 120 130 140 frequency at v in (hz) 15100 120 rejection (db) 100 ?0 ?0 ?0 ?0 0 15200 15300 15400 15500 2400 g26 v cc = 5v v ref = 5v v in = 2.5v f o = 0 sample rate = 15.36khz 2% rejection vs frequency at v in input frequency 0 ?0 ?0 0 2400 f26 ?0 100 f s /2 f s 120 140 ?0 rejection (db) 8 LTC2400 inl vs output rate resolution vs output rate typical perfor a ce characteristics uw v cc (pin 1): positive supply voltage. bypass to gnd (pin 4) with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. v ref (pin 2): reference input. the reference voltage range is 0.1v to v cc . v in (pin 3): analog input. the input voltage range is C 0.125 ? v ref to 1.125 ? v ref . for v ref > 2.5v, the input voltage range may be limited by the pin absolute maxi- mum rating of C 0.3v to v cc + 0.3v. gnd (pin 4): ground. shared pin for analog ground, digital ground, reference ground and signal ground. should be connected directly to a ground plane through a mini- mum length trace or it should be the single-point-ground in a single point grounding system. cs (pin 5): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low on cs wakes up the adc. a low-to-high transition on this pin disables the sdo digital output. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. output rate (hz) 0 inl (bits) 12 18 20 60 2400 g27 10 8 15 20 25 10 5 303540455055 24 22 16 14 v cc = 5v v ref = 5v t a = 25 c f 0 = external output rate (hz) 0 resolution (bits)* 12 18 20 60 2400 g28 10 8 15 20 25 10 5 303540455055 24 22 16 14 v cc = 5v v ref = 5v t a = 25 c f o = external *resolution = log(v ref /rms noise) log (2) sdo (pin 6): three-state digital output. during the data output period, this pin is used for serial data output. when the chip select cs is high (cs = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods this pin can be used as a conversion status output. the conversion status can be observed by pulling cs low. sck (pin 7): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as digital input for the external serial interface. a weak internal pull-up is automatically activated in internal serial clock operation mode. the serial clock mode is determined by the level applied to sck at power up and the falling edge of cs. f o (pin 8): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to v cc (f o = v cc ), the converter uses its internal oscillator and the digital filter first null is located at 50hz. when the f o pin is connected to gnd (f o = ov), the converter uses its internal oscillator and the digital filter first null is located at 60hz. when f o is driven by an external clock signal with a frequency f eosc, the converter uses this signal as its clock and the digital filter first null is located at a frequency f eosc /2560. pi n fu n ctio n s uuu 9 LTC2400 fu ctio al block diagra uu w test circuits figure 1. LTC2400 state transition diagram applicatio n s i n for m atio n wu u u autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc v in sdo sck v ref cs f o (int/ext) 2400 fd 3.4k sdo 2400 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 3.4k sdo 2400 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc converter operation cycle the LTC2400 is a low power, delta-sigma analog-to- digital converter with an easy to use 3-wire serial interface. its operation is simple and made up of three states. the converter operating cycle begins with the conversion, followed by a low power sleep state and concluded with the data output (see figure 1). the 3-wire interface con- sists of serial data output (sdo), a serial clock (sck) and a chip select (cs). initially, the LTC2400 performs a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced by convert sleep data output 2400 f01 0 1 cs and sck 10 LTC2400 an order of magnitude. the part remains in the sleep state as long as cs is logic high. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result. the data output corresponds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck, see figure 3. the data output state is concluded once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion cycle and the cycle repeats. through timing control of the cs and sck pins, the LTC2400 offers several flexible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require program- ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter (commonly known as sinc or comb filter). for high resolution, low frequency applications, this filter is typi- cally designed to reject line frequencies of 50 or 60hz plus their harmonics. in order to reject these frequencies in excess of 110db, a highly accurate conversion clock is required. the LTC2400 incorporates an on-chip highly accurate oscillator. this eliminates the need for external frequency setting components such as crystals or oscilla- tors. clocked by the on-chip oscillator, the LTC2400 rejects line frequencies (50 or 60hz 2%) a minimum of 110db. ease of use the LTC2400 data output has no latency, filter settling or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing an analog input voltage is easy. the LTC2400 performs offset and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation de- scribed above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with re- spect to time, supply voltage change and temperature drift. power-up sequence the LTC2400 automatically enters an internal reset state when the power supply voltage v cc drops below approxi- mately 2.2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selec- tion which is performed at the initial power-up. (see the 2-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with duration of approximately 0.5ms. the por signal clears all internal registers. following the por signal, the LTC2400 starts a normal conversion cycle and follows the normal succession of states described above. the first conversion result following por is accurate within the specifications of the device. reference voltage range the LTC2400 can accept a reference voltage from 0v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. a decrease in reference voltage will not signifi- cantly improve the converters effective resolution. on the other hand, a reduced reference voltage will improve the overall converter inl performance. the recommended range for the LTC2400 voltage reference is 100mv to v cc . input voltage range the converter is able to accommodate system level offset and gain errors as well as system level overrange situa- tions due to its extended input range, see figure 2. the LTC2400 converts input signals within the extended input range of C 0.125 ? v ref to 1.125 ? v ref . applicatio n s i n for m atio n wu u u 11 LTC2400 applicatio n s i n for m atio n wu u u 2400 f02 v cc + 0.3v 9/8v ref v ref 1/2v ref 0.3v 1/8v ref 0 normal input range extended input range absolute maximum input range figure 2. LTC2400 input range for large values of v ref this range is limited by the absolute maximum voltage range of C 0.3v to (v cc + 0.3v). beyond this range the input esd protection devices begin to turn on and the errors due to the input leakage current increase rapidly. input signals applied to v in may extend below ground by C 300mv and above v cc by 300mv. in order to limit any fault current, a resistor of up to 5k may be added in series with the v in pin without affecting the performance of the device. in the physical layout, it is important to maintain the parasitic capacitance of the connection between this series resistance and the v in pin as low as possible; therefore, the resistor should be located as close as practical to the v in pin. the effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the analog input/reference current section. in addition a series resistor will introduce a temperature dependent offset error due to the input leak- age current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. output data format the LTC2400 serial output data stream is 32 bits long. the first 4 bits represent status information indicating the sign, input range and conversion state. the next 24 bits are the conversion result, msb first. the remaining 4 bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. bit 31 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. the sign bit changes state during the zero code. bit 28 (forth output bit) is the extended input range (exr) indicator. if the input is within the normal input range 0 v in v ref , this bit is low. if the input is outside the normal input range, v in > v ref or v in < 0, this bit is high. the function of these bits is summarized in table 1. table 1. LTC2400 status bits bit 31 bit 30 bit 29 bit 28 input range eoc dmy sig exr v in > v ref 0 011 0 < v in v ref 0 010 v in = 0 + /0 C 0 0 1/0 0 v in < 0 0 001 bit 27 (fifth output bit) is the most significant bit (msb). bits 27-4 are the 24-bit conversion result msb first. bit 4 is the least significant bit (lsb). bits 3-0 are sub lsbs below the 24-bit level. bits 3-0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and any sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 (eoc) can be captured on the first rising edge of sck. bit 30 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted 12 LTC2400 applicatio n s i n for m atio n wu u u table 2. LTC2400 output data format bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 4 bit 3-0 input voltage eoc dmy sig exr msb lsb sub lsbs* v in > 9/8 ? v ref 001100011...1x 9/8 ? v ref 001100011...1x v ref + 1lsb 0 0 1 1 0 0 0 0 0 ... 0 x v ref 001011111...1x 3/4v ref + 1lsb 0 0 1 0 1 1 0 0 0 ... 0 x 3/4v ref 001010111...1x 1/2v ref + 1lsb 0 0 1 0 1 0 0 0 0 ... 0 x 1/2v ref 001001111...1x 1/4v ref + 1lsb 0 0 1 0 0 1 0 0 0 ... 0 x 1/4v ref 001000111...1x 0 + /0 C 0 0 1/0** 0 0 0 0 0 0 ... 0 x C1lsb 0 0 0111 1 11...1 x C1/8 ? v ref 000111100...0x v in < C1/8 ? v ref 000111100...0x *the sub lsbs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. **the sign bit changes state during the 0 code. figure 3. output data timing out on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating a new conversion cycle has been initiated. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 sum- marizes the output data format. as long as the voltage on the v in pin is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any input value from C 0.125 ? v ref to 1.125 ? v ref . for input voltages greater than 1.125 ? v ref , the conversion result is clamped to the value corresponding to 1.125 ? v ref . for input voltages below C 0.125 ? v ref , the conversion result is clamped to the value corresponding to C 0.125 ? v ref . frequency rejection selection (f o pin connection) the LTC2400 internal oscillator provides better than 110db normal mode rejection at the line frequency and all its harmonics for 50hz 2% or 60hz 2%. for 60hz rejec- tion, f o (pin 8) should be connected to gnd (pin 4) while for 50hz rejection the f o pin should be connected to v cc (pin 1). msb ext sig ? 1 2 3 4 5 272832 bit 0 bit 27 bit 4 lsb 24 bit 28 bit 29 bit 30 sdo sck cs eoc bit 31 sleep data output conversion 2400 f03 hi-z 13 LTC2400 table 3. LTC2400 state duration state operating mode duration convert internal oscillator f o = low 133ms (60hz rejection) f o = high 160ms (50hz rejection) external oscillator f o = external oscillator 20480/f eosc s with frequency f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = 0 and sck data output internal serial clock f o = low/high as long as cs = low but not longer than 1.67ms (internal oscillator) (32 sck cycles) f o = external oscillator with as long as cs = low but not longer than 256/f eosc ms frequency f eosc khz (32 sck cycles) external serial clock with as long as cs = low but not longer than 32/f sck ms frequency f sck khz (32 sck cycles) applicatio n s i n for m atio n wu u u the selection of 50hz or 60hz rejection can also be made by driving f o to an appropriate logic level. a selection change during the sleep or data output states will not disturb the converter operation. if the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be synchronized with an outside source, the LTC2400 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz (1hz notch frequency) to be detected. the exter- nal clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the LTC2400 provides better than 110db normal mode rejection in a frequency range f eosc /2560 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 4. whenever an external clock is not present at the f o pin, the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the LTC2400 input frequency deviation from notch frequency (%) 12 8 404812 rejection (db) 2400 g25 ?0 ?0 ?0 ?0 100 110 120 130 140 figure 4. LTC2400 normal mode rejection when using an external oscillator of frequency f eosc operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3 summarizes the duration of each state as a function of f o . 14 LTC2400 table 4. LTC2400 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 5, 6 external sck, 2-wire i/o external sck sck figure 7 internal sck, single cycle conversion internal cs cs figures 8, 9 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 10 internal sck, autostart conversion internal c ext internal figure 11 applicatio n s i n for m atio n wu u u serial interface the LTC2400 transmits the conversion results and re- ceives the start of conversion command through a syn- chronous 3-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. serial clock input/output (sck) the serial clock signal present on sck (pin 7) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the LTC2400 creates its own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the cs pin. if sck is high or floating at power- up or during this transition, the converter enters the inter- nal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data output (sdo) the serial data output pin, sdo (pin 6), drives the serial data during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 5) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = 0. chip select input (cs) the active low chip select, cs (pin 5), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the LTC2400 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state (i.e., after the first rising edge of sck occurs with cs = 0). finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . tying a capacitor to cs will reduce the output rate and power dissipation by a factor proportional to the capacitors value, see figures 12 to 14. serial interface timing modes the LTC2400s 3-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/external serial clock, 2- or 3-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 4 for a summary. 15 LTC2400 applicatio n s i n for m atio n wu u u external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 5. the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of cs, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift regis- ter. the device remains in the sleep state until the first rising edge of sck is seen while cs is low. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first rising edge and the 32nd falling edge of sck, see figure 6. on the rising edge of cs, the device aborts the data output state and imme- diately initiates a new conversion. this is useful for sys- tems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. eoc bit 31 sdo sck (external) cs v cc f o v ref sck v in sdo gnd cs v ref 0.1v to v cc v in 0.12v ref to 1.12v ref 1 f 2.7v to 5.5v LTC2400 test eoc msb sub lsb exr sig bit 0 lsb bit 4 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2400 f05 conversion = 50hz rejection = external oscillator = 60hz rejection hi-z hi-z hi-z v cc test eoc test eoc figure 5. external serial clock, single cycle operation 16 LTC2400 external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 7. cs may be permanently tied to ground (pin 4), simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 0.5ms after v cc exceeds 2.2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion enters the low power sleep state. on the falling edge of eoc, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the first rising edge of sck. data is applicatio n s i n for m atio n wu u u shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 32nd falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 8. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. v cc f o v ref sck v in sdo gnd cs v ref 0.1v to v cc v in 0.12v ref to 1.12v ref = 50hz rejection = external oscillator = 60hz rejection 1 f 2.7v to 5.5v LTC2400 sdo sck (external) cs data output conversion sleep sleep test eoc test eoc data output hi-z hi-z hi-z conversion 2400 f06 msb exr sig bit 8 bit 27 bit 9 bit 28 bit 29 bit 30 eoc bit 31 bit 0 eoc hi-z v cc test eoc figure 6. external serial clock, reduced data output length 17 LTC2400 applicatio n s i n for m atio n wu u u eoc bit 31 sdo sck (external) cs v cc f o v ref sck v in sdo gnd cs v ref 0.1v to v cc v in 0.12v ref to 1.12v ref 1 f 2.7v to 5.5v LTC2400 msb exr sig bit 0 lsb 24 bit 4 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2400 f07 conversion = 50hz rejection = external oscillator = 60hz rejection v cc sdo sck (internal) cs msb exr sig bit 0 lsb 24 bit 4 test eoc bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 sleep data output conversion conversion 2400 f08 18 LTC2400 applicatio n s i n for m atio n wu u u once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if cs remains low. in order to prevent the device from exiting the low power sleep state, cs must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 23 m s if the device is using its internal oscillator (f 0 = logic low or high). if f o is driven by an external oscillator of frequency f eosc , then t eoctest is 3.6/f eosc . if cs is pulled high before time t eoctest , the device remains in the sleep state. the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data output cycle begins on this first rising edge of sck and concludes after the 32nd rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high (eoc = 1), sck stays high, and a new conversion starts. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first and 32nd rising edge of sck, see figure 9. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic sdo sck (internal) cs >t eoctest msb exr sig bit 8 test eoc test eoc bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 eoc bit 0 sleep data output hi-z hi-z hi-z hi-z hi-z data output conversion conversion sleep 2400 f09 19 LTC2400 applicatio n s i n for m atio n wu u u high state. this will cause the device to exit the internal serial clock mode on the next falling edge of cs. this can be avoided by adding an external 10k pull-up resistor to the sck pin or by never pulling cs high when sck is low. whenever sck is low, the LTC2400s internal pull-up at pin sck is disabled. normally, sck is not externally driven if the device is in the internal sck timing mode. however, certain applications may require an external driver on sck. if this driver goes hi-z after outputting a low signal, the LTC2400s internal pull-up remains disabled. hence, sck remains low. on the next falling edge of cs, the device is switched to the external sck timing mode. by adding an external 10k pull-up resistor to sck, this pin goes high once the external driver goes hi-z. on the next cs falling edge, the device will remain in the internal sck timing mode. a similar situation may occur during the sleep state when cs is pulsed high-low-high in order to test the conver- sion status. if the device is in the sleep state (eoc = 0), sck will go low. once cs goes high (within the time period defined above as t eoctest ), the internal pull-up is activated. for a heavy capacitive load on the sck pin, the internal pull-up may not be adequate to return sck to a high level before cs goes low again. this is not a concern under normal conditions where cs remains low after detecting eoc = 0. this situation is easily overcome by adding an external 10k pull-up resistor to the sck pin. internal serial clock, 2-wire i/o, continuous conversion this timing mode uses a 2-wire, all output (sck and sdo) interface. the conversion result is shifted out of the device by an internally generated serial clock (sck) signal, see figure 10. cs may be permanently tied to ground (pin 4), simplifying the user interface or isolation barrier. the internal serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 0.5ms after v cc exceeds 2.2v. an internal weak pull-up is active during the por cycle; therefore, the internal serial clock timing mode is automatically selected if sck is not externally driven low (if sck is loaded such that the internal pull-up cannot pull the pin high, the external sck mode will be selected). sdo sck (internal) cs lsb 24 msb exr sig bit 4 bit 0 bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 sleep data output conversion conversion 2400 f10 v cc f o v ref sck v in sdo gnd cs v ref 0.1v to v cc v in 0.12v ref to 1.12v ref 1 f 2.7v to 5.5v LTC2400 = 50hz rejection = external oscillator = 60hz rejection v cc figure 10. internal serial clock, continuous operation 20 LTC2400 during the conversion, the sck and the serial data output pin (sdo) are high (eoc = 1). once the conversion is complete, sck and sdo go low (eoc = 0) indicating the conversion has finished and the device has entered the low power sleep state. the part remains in the sleep state a minimum amount of time (1/2 the internal sck period) then immediately begins outputting data. the data output cycle begins on the first rising edge of sck and ends after the 32nd rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high (eoc = 1) indicating a new conversion is in progress. sck remains high during the conversion. internal serial clock, autostart conversion this timing mode is identical to the internal serial clock, 2-wire i/o described above with one additional feature. instead of grounding cs, an external timing capacitor is tied to cs. while the conversion is in progress, the cs pin is held high by an internal weak pull-up. once the conversion is complete, the device enters the low power sleep state and an internal 25na current source begins discharging the capacitor tied to cs, see figure 11. the time the converter spends in the sleep state is determined by the value of the external timing capacitor, see figures 12 and 13. once the voltage at cs falls below an internal threshold ( ? 1.4v), the device automatically begins outputting data. the data output cycle begins on the first rising edge of sck and ends on the 32nd rising edge. data is shifted out the sdo applicatio n s i n for m atio n wu u u sdo hi-z hi-z sck (internal) cs v cc gnd 2400 f11 v cc f o v ref sck v in sdo gnd c ext cs v ref 0.1v to v cc v in 0.12v ref to 1.12v ref 1 f 2.7v to 5.5v LTC2400 bit 0 sig bit 29 bit 30 sleep data output conversion conversion eoc bit 31 = 50hz rejection = external oscillator = 60hz rejection v cc figure 11. internal serial clock, autostart operation 21 LTC2400 pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. after the 32nd rising edge, cs is pulled high and a new conversion is immediately started. this is useful in appli- cations requiring periodic monitoring and ultralow power. figure 14 shows the average supply current as a function of capacitance on cs. it should be noticed that the external capacitor discharge current is kept very small in order to decrease the con- verter power dissipation in the sleep state. in the autostart mode the analog voltage on the cs pin cannot be observed without disturbing the converter operation using a regular oscilloscope probe. when using this configuration, it is important to minimize the external leakage current at the cs pin by using a low leakage external capacitor and properly cleaning the pcb surface. the internal serial clock mode is selected every time the voltage on the cs pin crosses an internal threshold volt- age. an internal weak pull-up at the sck pin is active while cs is discharging; therefore, the internal serial clock timing mode is automatically selected if sck is floating. it is important to ensure there are no external drivers pulling sck low while cs is discharging. digital signal levels the LTC2400s digital interface is easy to use. its digital inputs (f o , cs and sck in external sck mode of operation) accept standard ttl/cmos logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100 m s. however, some considerations are required to take advantage of exceptional accuracy and low supply current. the digital output signals (sdo and sck in internal sck mode of operation) are less of a concern because they are not generally active during the conversion state. in order to preserve the LTC2400s accuracy, it is very important to minimize the ground path impedance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. the gnd pin should be connected to a low resistance ground plane through a minimum length trace. the use of multiple via holes is recommended to further reduce the applicatio n s i n for m atio n wu u u capacitance on cs (pf) 1 5 6 7 1000 10000 2400 f12 4 3 10 100 100000 2 1 0 t sample (sec) v cc = 5v v cc = 3v figure 12. cs capacitance vs t sample capacitance on cs (pf) 0 sample rate (hz) 3 4 5 1000 100000 2400 f13 2 1 0 10 100 10000 6 7 8 v cc = 5v v cc = 3v figure 13. cs capacitance vs output rate capacitance on cs (pf) 1 0 supply current ( a rms ) 50 100 150 200 250 300 10 100 1000 10000 2400 f14 100000 v cc = 5v v cc = 3v figure 14. cs capacitance vs supply current 22 LTC2400 connection resistance. the LTC2400s power supply cur- rent flowing through the 0.01 w resistance of the common ground pin will develop a 2.5 m v offset signal. for a reference voltage v ref = 2.5v, this represents a 1ppm offset error. in an alternative configuration, the gnd pin of the converter can be the single-point-ground in a single point grounding system. the input signal ground, the reference signal ground, the digital drivers ground (usually the digital ground) and the power supply ground (the analog ground) should be connected in a star configuration with the com- mon point located as close to the gnd pin as possible. the power supply current during the conversion state should be kept to a minimum. this is achieved by restrict- ing the number of digital signal transitions occurring during this period. while a digital input signal is in the range 0.5v to (v cc C 0.5v), the cmos input receiver draws additional current from the power supply. it should be noted that, when any one of the digital input signals (f o , cs and sck in external sck mode of operation) is within this range, the LTC2400 power supply current may increase even if the signal in question is at a valid logic level. for micropower operation and in order to minimize the potential errors due to additional ground pin current, it is recommended to drive all digital input signals to full cmos levels [v il < 0.4v and v oh > (v cc C 0.4v)]. severe ground pin current disturbances can also occur due to the undershoot of fast digital input signals. under- shoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propaga- tion delay from the driver to LTC2400. for reference, on a regular fr-4 board, signal propagation velocity is ap- proximately 183ps/inch for internal traces and 170ps/inch for surface traces. thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly diffi- cult when shared control lines are used and multiple reflections may occur. the solution is to carefully termi- nate all transmission lines close to their characteristic impedance. applicatio n s i n for m atio n wu u u v ref v in v cc r sw 5k average input current: i in = 0.25(v in ?0.5 ?v ref )fc eq i ref(leak) i ref(leak) v cc r sw 5k c eq 10pf (typ) r sw 5k i in(leak) i in 2400 f15 i in(leak) switching frequency f = 153.6khz for internal oscillator (f o = logic low or high) f = f eosc for external oscillators gnd figure 15. LTC2400 equivalent analog input circuit parallel termination near the LTC2400 pin will eliminate this problem but will increase the driver power dissipation. a series resistor between 27 w and 56 w placed near the driver or near the LTC2400 pin will also eliminate this problem without additional power dissipation. the actual resistor value depends upon the trace impedance and connection topology. driving the input and reference the analog input and reference of the typical delta-sigma analog-to-digital converter are applied to a switched ca- pacitor network. this network consists of capacitors switching between the analog input (v in ), ground (pin 4) and the reference (v ref ). the result is small current spikes seen at both v in and v ref . a simplified input equivalent circuit is shown in figure 15. the key to understanding the effects of this dynamic input current is based on a simple first order rc time constant model. using the internal oscillator, the LTC2400s inter- nal switched capacitor network is clocked at 153,600hz corresponding to a 6.5 m s sampling period. fourteen time constants are required each time a capacitor is switched in order to achieve 1ppm settling accuracy. therefore, the equivalent time constant at v in and v ref should be less than 6.5 m s/14 = 460ns in order to achieve 1ppm accuracy. 23 LTC2400 applicatio n s i n for m atio n wu u u c in 2400 f17 intput signal source r source v in LTC2400 c par @ 20pf figure 17. an rc network at v in r source ( ) 1 offset error (ppm) 30 40 50 10k 2400 f18 20 10 0 10 100 1k 100k v cc = 5v v ref = 5v v in = 0v t a = 25 c c in = 100pf c in = 1000pf c in = 0pf c in = 0.01 f figure 18. offset vs r source (small c) r source ( ) 1 full-scale error (ppm) ?0 ?0 0 10k 2400 f19 ?0 ?0 ?0 10 100 1k 100k v cc = 5v v ref = 5v v in = 5v t a = 25 c c in = 0pf c in = 100pf c in = 1000pf c in = 0.01 f figure 19. full-scale error vs r source (small c) r source ( ) 0 offset error (ppm) 100 200 300 50 150 250 200 400 600 800 2400 f20 1000 100 0 300 500 700 900 v cc = 5v v ref = 5v v in = 0v t a = 25 c c in = 1 f c in = 10 f c in = 0.1 f c in = 0.01 f figure 20. offset vs r source (large c) 0 tue v ref /2 v in 2400 f16 v ref figure 16. offset/full-scale shift input current (v in ) if complete settling occurs on the input, conversion re- sults will be uneffected by the dynamic input current. if the settling is incomplete, it does not degrade the linearity performance of the device. it simply results in an offset/ full-scale shift, see figure 16. to simplify the analysis of input dynamic current, two separate cases are assumed: large capacitance at v in (c in > 0.01 m f) and small capaci- tance at v in (c in < 0.01 m f). if the total capacitance at v in (see figure 17) is small (< 0.01 m f), relatively large external source resistances (up to 20k for 20pf parasitic capacitance) can be tolerated without any offset/full-scale error. figures 18 and 19 show a family of offset and full-scale error curves for various small valued input capacitors (c in < 0.01 m f) as a function of input source resistance. for large input capacitor values (c in > 0.01 m f), the input spikes are averaged by the capacitor into a dc current. the gain shift becomes a linear function of input source resistance independent of input capacitance, see figures 20 and 21. the equivalent input impedance is 1.66m w . this results in 1.5 m a of input dynamic current at the extreme values of v in (v in = 0v and v in = v ref , when 24 LTC2400 v ref = 5v). this corresponds to a 0.3ppm shift in offset and full-scale readings for every 1 w of input source resistance. in addition to the input current spikes, the input esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na ( 10na max), results in a fixed offset shift of 10 m v for a 10k source resistance. reference current (v ref ) similar to the analog input, the reference input has a dynamic input current. this current has negligible effect on the offset. however, the reference current at v in = v ref is similar to the input current at full-scale. for large values of reference capacitance (c vref > 0.01 m f), the full-scale error shift is 0.3ppm/ w of external reference resistance independent of the capacitance at v ref , see figure 22. if the capacitance tied to v ref is small (c vref < 0.01 m f), an input resistance of up to 20k (20pf parasitic capacitance at v ref ) may be tolerated, see figure 23. unlike the analog input, the integral nonlinearity of the device can be degraded with excessive external rc time constants tied to the reference input. if the capacitance at node v ref is small (c vref < 0.01 m f), the reference input can tolerate large external resistances without reduction in inl, see figure 24. if the external capacitance is large (c vref > 0.01 m f), the linearity will be degraded by 0.15ppm/ w independent of capacitance at v ref , see figure 25. applicatio n s i n for m atio n wu u u resistance at v ref ( ) 0 0 full-scale error (ppm) 100 200 300 400 500 600 200 400 600 800 2400 f22 1000 c vref = 10 f c vref = 0.01 f c vref = 0.1 f v cc = 5v v ref = 5v v in = 5v t a = 25 c c vref = 1 f figure 22. full-scale error vs r vref (large c) resistance at v ref ( ) 1 30 40 50 1k 2400 f23 20 10 10 100 100k 10k 0 ?0 ?0 full-scale error (ppm) v cc = 5v v ref = 5v v in = 5v t a = 25 c c vref = 100pf c vref = 1000pf c vref = 0.01 f c vref = 0pf figure 23. full-scale error vs r vref (small c) resistance at v ref ( ) 1 ?0 inl error (ppm) 0 10 20 30 40 50 10 100 1k 10k 2400 f24 100k v cc = 5v v ref = 5v t a = 25 c c vref = 0pf c vref = 100pf c vref = 1000pf c vref = 0.01 f figure 24. inl error vs r vref (small c) r source ( ) 0 300 full-scale error (ppm) 250 200 150 100 ?0 0 200 400 600 800 2400 f21 1000 c in = 0.01 f v cc = 5v v ref = 5v v in = 5v t a = 25 c c in = 0.1 f c in = 1 f c in = 10 f figure 21. full-scale error vs r source (large c) 25 LTC2400 applicatio n s i n for m atio n wu u u input frequency 0 ?0 ?0 0 2400 f26 ?0 100 f s /2 f s 120 140 ?0 rejection (db) figure 26. sinc 4 filter rejection resistance at v ref ( ) 0 ?0 inl error (ppm) 0 40 60 80 400 800 1000 160 2400 f25 20 200 600 100 120 140 c vref = 0.01 f c vref = 0.1 f c vref = 1 f c vref = 10 f v cc = 5v v ref = 5v t a = 25 c figure 25. inl error vs r vref (large c) in addition to the dynamic reference current, the v ref esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na ( 10na max), results in a fixed full-scale shift of 10 m v for a 10k source resistance. antialiasing one of the advantages delta-sigma adcs offer over con- ventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the LTC2400 significantly simplifies antialiasing filter requirements. the digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (f s ), see figure 26. the modulator sampling frequency is 256 ? f o , where f o is the notch frequency (typically 50hz or 60hz). the bandwidth of signals not rejected by the digital filter is narrow ( ? 0.2%) compared to the bandwidth of the frequencies rejected. as a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the LTC2400. if passive rc components are placed in front of the LTC2400 the input dynamic current should be considered (see input current section). in cases where large effective rc time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current. the modulator contained within the LTC2400 can handle large-signal level perturbations without saturating. signal levels up to 40% of v ref do not saturate the analog modu- lator. these signals are limited by the input esd protection to 300mv below ground and 300mv above v cc . 26 LTC2400 typical applicatio n s u synchronization of multiple LTC2400s since the LTC2400s absolute accuracy (total unadjusted error) is 10ppm, applications utilizing multiple matched adcs are possible. simultaneous sampling with two LTC2400s one such application is synchronizing multiple LTC2400s, see figure 27. the start of conversion is synchronized to the rising edge of cs. in order to synchronize multiple LTC2400s, cs is a common input to all the adcs. to prevent the converters from autostarting a new con- version at the end of data output read, 31 or fewer sck clock signals are applied to the LTC2400 instead of 32 (the 32nd falling edge would start a conversion). the exact timing and frequency for the sck signal is not critical since it is only shifting out the data. in this case, two LTC2400s simultaneously start and end their conversion cycles under the external control of cs. increasing the output rate using multiple LTC2400s a second application uses multiple LTC2400s to increase the effective output rate by 4 , see figure 28. in this case, four LTC2400s are interleaved under the control of sepa- rate cs signals. this increases the effective output rate from 7.5hz to 30hz (up to a maximum of 60hz). addition- ally, the one-shot output spectrum is unfolded allowing further digital signal processing of the conversion results. sck and sdo may be common to all four LTC2400s. the four cs rising edges equally divide one LTC2400 conver- sion cycle (7.5hz for 60hz notch frequency). in order to synchronize the start of conversion to cs, 31 or less sck clock pulses must be applied to each adc. both the synchronous and 4 output rate applications use the external serial clock and single cycle operation with reduced data output length (see serial interface timing modes section and figure 6). an external oscillator clock is applied commonly to the f o pin of each LTC2400 in order to synchronize the sampling times. both circuits may be extended to include more LTC2400s. 31 or less clock cycles cs sck1 sck2 2400 f27 sdo1 sdo2 31 or less clock cycles LTC2400 #1 v cc v ref v in gnd f o sck sdo cs sck2 sck1 cs sdo1 sdo2 LTC2400 #2 v cc v ref v in gnd f o sck sdo cs controller external oscillator (153,600hz) v ref (0.1v to v cc ) figure 27. synchronous conversionextendable 27 LTC2400 typical applicatio n s u cs1 cs2 cs3 2400 f28 cs4 sck 31 or less clock pulses sdo LTC2400 #1 v cc v ref v in gnd f o sck sdo cs sck sdo cs1 cs2 cs3 cs4 LTC2400 #2 v cc v ref v in gnd f o sck sdo cs LTC2400 #3 v cc v ref v in gnd f o sck sdo cs LTC2400 #4 v cc v ref v in gnd f o sck sdo cs controller external oscillator (153,600hz) v ref (0.1v to v cc ) figure 28. 4 output rate LTC2400 system differential to single-ended analog conditioning the circuits in figures 29 and 30 use the ltc1043 dual precision, switched capacitor building block. each circuit uses one-half of an ltc1043 to perform a differential to single-ended conversion over an input common mode range that includes the power supplies. the ltc1043 samples a differential input voltage, holds it on c s and transfers it to a ground-referenced capacitor c h . the voltage on c h is applied to the LTC2400s input and converted to a digital value. the ltc1043 achieves its best differential to single-ended conversion when its internal switching frequency oper- ates at a nominal 300hz, as set by the 0.01 m f capacitor c1, and when 1 m f capacitors are used for c s and c h . c s and c h should be a film-type capacitor such as mylar or polypropylene. simple differential front-end for the LTC2400 the circuit in figure 29 is ideal for wide dynamic range differential signals in applications where absolute accu- racy is secondary to high resolution, have large signal swings, source impedances under 500 w and use a 5v or 5v supply. the circuit achieves a nonlinearity of 35ppm (a linearity accuracy of 14.5 bits), noise of 1.5 m v rms and 21-bit resolution. the circuit exhibits a typical 2.75mv zero offset. however, this is not an offset that simply shifts the output code by a constant value. it is a gain error that alters the transfer functions slope. the gain error revolves around midscale (v ref /2). this gain error can be corrected in software by measuring the error at 0v input and using the result to create a correction factor. 28 LTC2400 typical applicatio n s u 5v 0.1 f v in sdo sck cs chip select serial serial 3 2 1 4 5 6 7 8 v ref v refin v cc 0.1 f 5v gnd LTC2400 f o 11 4 7 8 12 c s 1 f ext c h 1 f large magnitude differential input c1 0.01 f 0.1 f 2400 f29 ?v 1/2 ltc1043 13 16 14 17 figure 29. simple rail-to-rail circuit converts differential signals to single-ended signals LTC2400 high accuracy differential to single-ended converter for 5v supplies the circuit in figure 30 is ideal for low level differential signals in applications that have a 5v supply and need high accuracy without calibration. the circuit combines an ltc1043 and ltc1050 as a differential to single-ended amplifier that has an input common mode range that includes the power supplies. resistors r1 and r2 set the ltc1050s gain at 101. the circuit schematic shows an optional resistor r s . this resistor can be placed in series with the LTC2400s input to limit current if the input goes below C 300mv. the resistor does not degrade the converters performance as long as any capacitance, stray or otherwise, connected between the LTC2400s input and ground is less than 100pf. higher capacitance will increase offset and full- scale errors (see input current section). the circuit achieves a nonlinearity of 1ppm, input re- ferred noise of 0.05 m v rms (averaging 64 samples), 19.6 bits resolution for a full-scale input of 40mv, and an overall accuracy of 20 bits when using an ltc1236-5 precision 5v reference. multiple inputs the simple circuit shown in figure 31 takes advantage of the LTC2400s single conversion settling. the ltc1391 serially programmed multiplexer allows accurate conver- sions on each of its eight channels without introducing any offset, gain or linearity errors with its input signal between 0v and v ref , as long as the total capacitance connected to the LTC2400s input is less than 1000pf. a small 2ppm (typ) error occurs when an active input channels signal voltage reaches C300mv (typ). if the excursion below ground is above C 200mv (typ), the error is less than the LTC2400s 0.3ppm rms noise. on the topside, the selected input signals magnitude can go above the 5v supply with no linearity degradation or increased noise. figure 31s circuit can tolerate overdrive on the unselected channel without conversion degradation as long as the overdrive is less than 250mv above the supply voltage or 250mv below ground. the linearity performance is similar to that shown in the typical performance characteristics section. errors caused by channel-to-channel crosstalk are less than the LTC2400s typical input noise. this remains the case for a frequency range of 1hz to 153.6khz (the LTC2400s internal clock frequency or 10f s ). when the frequency reaches 1.536mhz (4v p-p ), the rms noise typi- cally doubles and the linearity is degraded by 30ppm (typ). 29 LTC2400 v in sdo sck cs cs sdo sck 3 2 1 4 5 6 7 8 v ref v refin v cc 0.1 f 0.1 f 5v 5v gnd LTC2400 f o 2400 f31 v + d v data 2 data 1 cs clk gnd ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 s0 s1 s2 s3 s4 s5 s6 s7 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ltc1391 figure 31. multiplex 8-signal sources with the ltc1391 and maintain the LTC2400s conversion accuracy typical applicatio n s u v in sdo sck cs chip select serial serial 3 3 7 4 6 r1 9.09k r s * 5.1k r2 90.9k *optional: limits input current if the input voltage goes below 300mv 2 2 1 4 5 6 7 8 v ref v refin v cc 0.1 f 5v gnd LTC2400 f o 0.1 f 5v 5v ?v 0.1 f 0.1 f 11 4 7 8 12 c s 1 f ext c h 1 f differential input v fs = 40mv bridge- typical input c1 0.01 f 0.1 f 2400 f30 ?v 1/2 ltc1043 13 16 14 17 350 agnd or ? ext 350 350 350 + ltc1050 figure 30. differential to single-ended converter for low level inputs, such as bridges, maintains the LTC2400s high accuracy 30 LTC2400 typical applicatio n s u sample driver for LTC2400 spi interface the LTC2400 has a very simple serial interface that makes interfacing to microprocessors and microcontrollers very easy. shown in figures 32 and 34 are listings of sample source codes that can be used to initiate conversions and retrieve data from the LTC2400. the listing in figure 32 was created by parallax, inc. (916- 624-8333), for the basic stamp. this code uses indi- vidual port lines to control the LTC2400s conversion and 'LTC2400 sample driver '03/17/99 this program is an example showing how to access the ' LTC2400 using the basic stamp2 from parallax. since ' the bs2 is based on a 16-bit architecture, only the ' upper 16 bits of the 24-bit result are displayed, ' although all 24 bits are retrieved. adlo var word 'a/d result - lower 16 bits adhi var word 'a/d result - upper 8 bits ctr var byte 'loop counter temp var bit 'temporary bit used for shift sdo con 0 'serial data connected to p0 sck con 1 'serial clock connected to p1 cs con 2 'chip select connected to p2 pwr con 3 'stamp supplies power connected to p3 '(uses only 0.3ma!) init dira = $e 'set up data direction 'pwr, cs, and sck are outputs 'sdo is an input outa = $0 'initialize outputs 'pwr, cs, and sck are low pause 100 'wait 100ms for i/o to settle high pwr 'power up the LTC2400 pause 1 'wait 1ms for power-on sequence high cs 'disable the device until we start 'wish to read it. pause 125 'eight times second low cs 'enable the LTC2400 for ctr = 0 to 31 high sck 'cycle clock 32 times gosub shiftl retrieve the 32-bit result. a fourth port line is used to power the LTC2400, a vivid example of the converters micropower operation. the programs main sequence activates the LTC2400s serial interface, uses a loop to retrieve the 32 conversion bits, and then places the converters interface in a high impedance state and start- ing the next conversion. all bits are retained in variables adlo and adhi. the code can be found on their web site, www.parallaxinc.com. 31 LTC2400 figure 32. this basic stamp code is an example of how easy it is to retrieve data from the LTC2400 adlo.bit0 = in0 'and sample data line low sck next high cs 'disable the LTC2400 adhi = (adhi<<4)+((adlo&$f000)>>12) debug ?adhi 'discard the lower eight bits goto start 'and display (debug command). shiftl temp = adlo.bit15 'this routine simply adlo = adlo<<1 'performs a 1 bit adhi = adhi<<1 'left shift on two adhi.bit0 = temp '16 bit variables return typical applicatio n s u figure 33. connecting the LTC2400 to a 68hc11 mcu using the spi serial interface LTC2400 sck sdo cs 7 6 5 sck (pd4) miso (pd2) ss (pd5) 68hc11 2400 f33 the listing in figure 34 is a simple assembler routine for the 68hc11 microcontroller. it uses port d, configuring it for spi data transfer between the controller and the LTC2400. figure 33 shows the simple 3-wire spi connection. the code begins by declaring variables and allocating four memory locations to store the 32-bit conversion result. this is followed by initializing port ds spi configuration. the program then enters the main sequence. it activates the LTC2400s serial interface by setting the ss output low, sending a logic low to cs. it next waits in a loop for a logic low on the data line, signifying end-of-conversion. after the loop is satisfied, four spi transfers are com- pleted, retrieving the conversion. the main sequence ends by setting ss high. this places the LTC2400s serial interface in a high impedance state and initiates another conversion. ***************************************************** * this example program transfers the LTC2400's 32-bit output * * conversion result into four consecutive 8-bit memory locations. * ***************************************************** *68hc11 register definition portd equ $1008 port d data register * " C , C , ss* ,csk ;mosi,miso,txd ,rxd" ddrd equ $1009 port d data direction register spsr equ $1028 spi control register * "spie,spe ,dwom,mstr;spol,cpha,spr1,spr0" spsr equ $1029 spi status register * "spif,wcol, C ,modf; C , C , C , C " spdr equ $102a spi data register; read-buffer; write-shifter * * ram variables to hold the LTC2400's 32 conversion result 32 LTC2400 typical applicatio n s u * din1 equ $00 this memory location holds the LTC2400's bits 31 - 24 din2 equ $01 this memory location holds the LTC2400's bits 23 - 16 din3 equ $02 this memory location holds the LTC2400's bits 15 - 08 din4 equ $03 this memory location holds the LTC2400's bits 07 - 00 * ********************** * start getdata routine * ********************** * org $c000 program start location init1 lds #$cfff top of c page ram, beginning location of stack ldaa #$2f C,C,1,0;1,1,1,1 * C, C, ss*-hi, sck-lo, mosi-hi, miso-hi, x, x staa portd keeps ss* a logic high when ddrd, bit 5 is set ldaa #$38 C,C,1,1;1,0,0,0 staa ddrd ss*, sck, mosi are configured as outputs * miso, txd, rxd are configured as inputs *ddrd's bit 5 is a 1 so that port d's ss* pin is a general output ldaa #$50 staa spcr the spi is configured as master, cpha = 0, cpol = 0 * and the clock rate is e/2 * (this assumes an e-clock frequency of 4mhz. for higher e- * clock frequencies, change the above value of $50 to a value * that ensures the sck frequency is 2mhz or less.) getdata pshx pshy psha ldx #$0 the x register is used as a pointer to the memory locations * that hold the conversion data ldy #$1000 bclr portd, y %00100000 this sets the ss* output bit to a logic * low, selecting the LTC2400 trflp1 ldaa #$0 load accumulator a with a null byte for spi transfer staa spdr this writes the byte in the spi data register and starts * the transfer wait1 ldaa spsr this loop waits for the spi to complete a serial transfer/exchange by reading the spi status register bpl wait1 the spif (spi transfer complete flag) bit is the spsr's msb * and is set to one at the end of an spi transfer. the branch * will occur while spif is a zero. ldaa spdr load accumulator a with the current byte of LTC2400 data that was just received staa 0,x transfer the LTC2400's data to memory inx increment the pointer cpx #din4+1 has the last byte been transferred/exchanged? bne trflp1 if the last byte has not been reached, then proceed to the * next byte for transfer/exchange bset portd,y %00100000 this sets the ss* output bit to a logic high, * de-selecting the LTC2400 pula restore the a register puly restore the y register pulx restore the x register rts figure 34. this is an example of 68hc11 code that captures the LTC2400s conversion results over the spi serial interface shown in figure 33 33 LTC2400 thermocouple applications figure 35 shows a thermocouple interface circuit that demonstrates the practicality of direct connection to the LTC2400 using even the lowest output thermocouples (in this case, a type s thermocouple, with a full-scale output of 18mv). this topology is the least costly solution for thermocouple sensing. as shown, it is capable of resolving approxi- mately 0.25 c without averaging. since the LTC2400 does not exhibit any easily discernible quantization effects, averaging can significantly extend the resolution for slow changing processes. in this circuit, a 1n4148 diode provides cold junction compensation by producing, at the positive terminal of the thermocouple, an approximation of the average seebeck coefficient for a type s thermocouple over the temperature range expected at the cold junction (0 c to 40 c). if the operating range is less, the coefficient can be adjusted to produce a better match for the range anticipated. this basic circuit can be used with other thermocouples by changing the divide ratio to suit the seebeck coefficient of the type chosen (see table). typical applicatio n s u this circuit produces a dc offset at the cold junction reference point, of 1mv to 15mv, which must be nulled out in software. this dc offset, resulting from the forward voltage of the diode, is variable from device to device and must be calibrated for each unit. since the temperature coefficient of the 1n4148 diode is not guaranteed, a trim should be provided to accommo- date a coefficient from 1.7mv/ c to 2.3mv/ c. alterna- tively, a transistor can be used as a sensor with omega engineering thermocouple circuit board connectors that are available with to-92 transistor retainer clips, placing the transistor in physical contact with the cold junction. the 1m resistor r tc shown is intended as an open-circuit detection scheme, producing full scale at the input of the LTC2400. note that this resistor contributes to the offset and must have low tc, as should the resistors r2 and r3. since r1 provides forward bias for the diode, its tempera- ture coefficient is not as critical. the circuit in figure 35 uses only 12% of the LTC2400s input range and is able to accommodate the full-scale output of all thermocouple types. the commonly used v in sdo sck cs 3 thermocouple 2 1 r1 43.2k 4 5 6 7 5v 5v 10k 8 v ref v cc 0.1 f gnd LTC2400 f o 2400 f35 r tc 1m cu + cu 1n4148 cold junction isothermal r2* 2mv/ c 60hz *25ppm, 1% tolerance single point ground 50hz ?b r3* 100 *20 c t a 50 c thermocouple type j k s seebeck coefficient* 50.2 v/ c 39.2 v/ c 6.15 v/ c r2 3.83k 4.99k 32.4k figure 35. diode cold junction compensation 34 LTC2400 typical applicatio n s u thermocouple with the highest output is type e, at about 70mv. this circuit does not provide curvature correction for the seebeck effect at the cold junction. if the applica- tion requires very high accuracy, the temperature of the cold junction should be determined via a separate input to the a/d, using an rtd for example. the cold junction compensation can be performed by implementing the thermocouples nbs polynominal curvature correction in software. (the input to the LTC2400 can be multi- plexed using the ltc1391 with little degradation.) if a separate temperature sensor is used to monitor the cold junction, the connection from the thermocouple to the LTC2400 can be direct. the junctions formed at the point where the thermocouple leads meet different metal (e.g., copper traces) must be equal in temperature, and the cold junction sensor must be mounted at that point. any temperature differential between the leads, or any differ- ential between the leads and the temperature sensor will introduce an error into the reading. figure 36 shows an inexpensive circuit with removal of the dc offset. the output of the lt ? 1077 is attenuated in order to produce the required coefficient, as well as reduce the noise and offset error contribution. if used with a ther- mistor, this circuit can be modified to produce curvature correction. the removal of the offset associated with diode forward voltage, or the 273 k overhead on some mono- lithic temperature sensors, simplifies the use of substan- tial gain after the thermocouple. chopper amplifiers such as the ltc1050 can extend the noise floor of the LTC2400 by as much as a factor of 10 to 20. the use of a gain of 20 in front of the LTC2400 can extend the resolution of a thermocouple application to 0.02 c or better. if absolute accuracy is not important, the use of a low noise bipolar amplifier, such as the lt1028, can extend the resolution an additional order of magnitude. note that achieving high accuracy in the circuit in figure 36 requires a calibration sequence for circuit offset and gain correction. v in sdo sck cs 3 6.1 v/ c r5 1k 6 3 r 1mv/ c 2 7 4 5v + 2 1 r2 174k* v + v 4 *recommended 0.1%, 5ppm irc afd series chip resistors 5 6 7 5v 10k 60hz select r3 for thermocouple type s: 6.19 k: 39.2 j: 49.9 e: 61.9 50hz 8 v ref v cc 0.1 f 5v gnd LTC2400 f o 2400 f35 r3 1k* r6 6.19 r1 226 * r4 10k* + lt1077 lm334 so-8 figure 36. inexpensive amplifier improves cold junction compensation 35 LTC2400 typical applicatio n s u v in sdo sck cs 3 type s 6 2 5 4 5v + 2 1 4 5 6 7 5v 10k 60hz 50hz 8 v ref v cc 0.1 f gnd LTC2400 f o 2400 f36 v in s lt1025 r gnd figure 37. the lt1025 complete cold junction solution a simpler, and potentially less expensive solution is the use of the lt1025 as shown in figure 37. the lt1025 incorporates the functions of temperature sensor, a precision divider chain required to produce the appropriate correction for five different types of thermo- couples, as well as curvature correction. the lt1025 must be located at the cold junction. the use of a thermal mass around the cold junction, as well as protection from air currents, is advisable. simple platinum rtd interface if high temperature resolution is required over a more limited range, figure 38 can resolve approximately 0.01 c without additional amplification. the resistance of a platinum rtd changes by approximately 0.31 w / c at t a = 25 c. the 100 w to 300 w source impedance of this circuit does not compromise the stability, accuracy or noise level of the LTC2400. v in sdo sck cs 3 fs 5v 2 r1* 12.1k pt rtd 100 1 4 *vishay s102 or equivalent 5 6 7 5v 10k 60hz 50hz 8 v ref v cc 0.1 f 5v gnd LTC2400 f o 2400 f37 figure 38. simplest platinum rtd interface 36 LTC2400 typical applicatio n s u the 12.1k resistor should be a precision resistor such as a vishay s102 series, or must be temperature stabilized. the excitation current is low enough for most sensors that the self-heating effect is near the noise floor of the LTC2400. the use of a bipolar amplifier configuration shown in figure 39 offers a potential resolution of 0.001 c in order to achieve these results, the following effects must be considered. variation in the self-heating of the rtd element due to air currents is the most difficult challenge. if the rtd is mounted in a sealed glass enclo- sure and painted black, the LTC2400 can detect the arrival of a person in the room. this is also true of infrared thermocouple sensors (thermopiles) that can also be used directly with the LTC2400. a variation of this circuit with two rtds can detect small differential temperatures in order to determine heat inflow or outflow from a process. in order for this circuit to be practical, the ambient tem- perature of the amplifier and resistors must be controlled or the resistors must exhibit very low temperature coeffi- cients. precision resistor networks are always a good alternative and are available from vishay or caddock. half-bridge strain gauge the circuit in figure 40 is a ratiometric half-bridge circuit with direct connection to the LTC2400. the use of two thin-film strain gauges in a half-bridge configuration can produce 2mv/v output and approximately 12-bit resolu- tion. the 175 w source impedance seen by the LTC2400 does not compromise operation. the optional resistor shown can be up to 5k and will provide surge and transient protection for the LTC2400 if the strain gauges are located some distance from the LTC2400, or if the strain bearing member is not well grounded and may be subject to esd discharge. thin- film strain elements form coupling capacitance to the strain bearing member to which they are bonded. if noise + lt1028 6 to LTC2400 3 2 300 1k 5v ?v v ref r3* 9.09k r4** 100 r2* 9.09k pt rtd 100 must be 5ppm/ c or better, an array is recommended must be very stable < 5ppm/ c * ** r1* 9.09k 0.1 f 2400 f38 fs v in sdo sck cs 3 5v 2 350 strain element r1 5k optional 350 strain element 1 4 5 6 7 8 v ref v cc 0.1 f gnd LTC2400 f o 2400 f39 5v 10k 60hz 50hz figure 39. extremely high resolution rtd interface figure 40. half-bridge connection for strain gauges 37 LTC2400 typical applicatio n s u pick- up from the strain bearing member is largely 60hz, the LTC2400 will reject it. if serious high frequency noise is present on the strain bearing member, it may be necessary to add buffering in order to allow the use of noise suppression. stable relaxation oscillator for external clock applications that require that the notch produced by the LTC2400s sinc 4 filter be placed at some frequency other than 50hz or 60hz require an external clock. the fre- quency required is 2560 the required notch frequency. simple relaxation oscillators built from logic gates with hysteresis such as the 74hc14 are not stable with tem- perature, supply voltage changes, or from device to device. if for example, a remote weigh scale application requires rejection of a resonance at 11hz, the frequency must be set to 28.16khz. in many instances, these frequencies could be produced digitally with a phase lock loop or with digital hc04 c1 c1 may vary from 30pf to 4000pf stable operation at higher frequencies requires values of resistor to be reduced 2400 f40 r1 100k d c b a r3 47k c3 15pf f out (khz) = r2 47k c2 15pf 9.5 ?10 ? c1 (pf) figure 41. stable relaxation low power oscillator for notch tuning dividers, but they are too low to be produced directly by a quartz oscillator. quartz stability is generally not required, as the notches are wide enough that an oscillator with 0.1% to 1% stability is adequate. in instances where digital generation of these frequencies is not practical due to power, space or cost limitations, and notches in the range of 4hz to 120hz are required, the circuit in figure 41 can be used. the frequency can be varied over this range by changing capacitor c1 over the range of 4000pf to 30pf. for the resistor values shown, the output frequency in khz is approximately 9.5e-6 divided by c1 (c1 in pf). the circuit produces a controlled amount of hysteresis dependent only on resistor matching and self biases itself around the input threshold. all gates must be in the same package, and no loads should be driven from the outputs driving feedback paths. if there are spare gates, they can be used in parallel with gates b and d for improved drive of feedback paths. 38 LTC2400 typical applicatio n s u the performance of the LTC2400 can be verified using the demonstration board dc228, see figure 42 for the sche- matic. this circuit uses the computers serial port to generate power and the spi digital signals necessary for starting a conversion and reading the result. it includes a labview application software program (see figure 43) which graphically captures the conversion results. it can be used to determine noise performance, stability, and with an external source, linearity. as exemplified in the schematic, the LTC2400 is extremely easy to use. this demonstration board and associated software is available by contacting linear technology. 1 j5 db9 6 9 2 7 3 8 4 5 + u3-6 74hc14 u3-5 74hc14 r2 51k csrts 2400 f42 notes: unless otherwise specified install shunts on pin 2 and 3 of jp1 and jp2 u3-2 74hc14 u3-1 74hc14 r1 51k r3 100 w j6 ext v + 8v to 15v d1 bav74lt1 c4 0.1 m f jp1 8 7 6 5 1 2 3 4 c5 100 m f 16v c6 22 m f c3 10 m f c1 10 m f c2 10 m f j4 ground j3 input j1 v refin j2 v refout sclkdtr u3-4 74hc14 u3-3 74hc14 doutcts out in gnd u2 lt1236acs8-5 5v v cc v ref v in gnd f o sck sdo cs u1 LTC2400 23 1 2 3 60hz 50hz 62 4 43 98 12 13 10 11 56 21 1 jp2 onboard ref external ref figure 42. 24-bit a/d demo board schematic figure 43. display graphic 39 LTC2400 package i for atio u u w dimensions in inches (millimeters) unless otherwise noted. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. pcb layout a d fil uw component side silkscreen solder side silkscreen 40 LTC2400 2400fa lt/tp 0300 2k rev a ? printed in usa ? linear technology corporation 1998 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com related parts part number description comments lt1019 precision bandgap reference, 2.5v, 5v 3ppm/ c drift, 0.05% max lt1025 micropower therocouple cold junction compensator ltc1043 dual precision instrumentation switched capacito building blockr precise charge, balanced switching, low power ltc1050 precision chopper stabilized op amp no external components 5 m v offset, 1.6 m v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/ c drift lt1460 micropower series reference 0.075% max, 10ppm/ c max drift, 2.5v, 5v and 10v versions ltc2401/ltc2402 1-/2-channel 24-bits adcs 3 m v noise, 10-pin msop package, ground sensing ltc2404/ltc2408 4-/8-channel 24-bit adcs same performance as LTC2400 ltc2420 20-bit micropower adc 6 m v noise, pin-compatible with LTC2400 pcb layout a d fil uw component side component side solder mask component side paste mask solder side solder side solder mask solder side paste mask |
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