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AT2008 8 channels adpcm processor page 1 of 19 ?2001 atelic systems, inc. atelic systems, inc. AT2008 application note preliminary 8 channels adpcm processor version 1.0 january 29, 2001 description the AT2008 is an eight full - duplex channels adpcm processor. it follows the g.726 itu standard for adpcm compression for 40k, 3 2k, 24k and 16k bit rates with selectable m - law and a - law input/output. this chip can operate on 16 channels of pcm to adpcm compression, 16 channels of adpcm to pcm decompression, 8 channels of full - duplex operation in an 8khz frame basis, or any combina tion of m - channels of compression plus n - channels of decompression when m+n <= 16. using the 3 - wire command serial port, each individual half - channel can be dynamically configured to perform the adpcm algorithm at different bit rates, idle or reset of the algorithm. it can also be programmed to set up different input/output time slots, or to select, (1) bypass without compression, (2) idle, or (3) reset of the algorithm. features 8 full channels of itu g.726 adpcm adpcm coding and decoding with bypass mo de per channel selectable m - law and a - law input/output up to 8 synchronous signals for direct interface with popular combo/codec. on - chip time slot assignment available internal clock generator and frame sync. generator simple 3 - wire serial command port fo r chip configuration on - chip power - up/power down/reset the two clock pins (clka and clkp) used as pcm/adpcm data clocks, and the fsy pin used for frame sync signals can be programmed to become either as input pins or as output pins. (the defaults are as input pins). applications dect voip / vodsl wireless pbx systems default settings 3 - wire serial command is required to configure the chip running adpcm in 8 full channels.
AT2008 8 channels adpcm processor page 2 of 19 ?2001 atelic systems, inc. pin description pin symbol type description 16 xin i x chan nel data in . sampled on the falling edge of clk p during selected time slots with msb first. 20 xout o x channel data out . updated on the rising edge of clk p during selected time slots with msb first. 27 yin i y channel data in . sampled on the falling ed ge of clk a during selected time slots with msb first. 25 fsy i/o y channel frame sync . master y channel frame sync. signal followed by the first time slot of transmission. it can be either input or output by initial setup sequence. 24 yout o y channel d ata out . updated on the rising edge of clk a d uring selected time slots with msb first. 2 rstz i reset . low active signal to force chip reset. 13 12 xtal1/mclk xtal2 i o crystal in & out . 14.318 mhz crystal connected * * * . 17 clkp i/o pcm clock . it can be either input created by external control circuit, or output generated by internal control circuit. 26 clka i/o adpcm clock . it can be either input created by external control circuit, or output generated by internal control circuit. 18 15 11 10 9 8 5 1 sync1 sync2 sync3 sync4 sync5 sync6 sync7 sync8 o o o o o o o o sync 1 . frame sync. for 1 st codec. sync 2 . frame sync. for 2 nd codec. sync 3 . frame sync. for 3 rd codec. sync 4 . frame sync. for 4 th codec. sync 5 . frame sync. for 5 th codec. sync 6 . frame sy nc. for 6 th codec. sync 7 . frame sync. for 7 th codec. sync 8 . frame sync. for 8 th codec. 4 3 tm1 tm0 i i tm1 &tm0 . tie to ground for normal operation. 7 6 a1 a0 i i a1 & a0 . address id key for 3 - wire serial port. if match, 3 - wire serial port can be enabl ed for configuration. 22 sdi/sdo i/o serial data in . data for configuration on the fly by 3 - wire serial port. sampled on the rising edge of sclk with lsb first. serial data out . output data after sending read memory command by 3 - wire serial port. sampled on the rising edge of sclk with lsb first. 21 sclk i serial clock . used to write to the 3 - wire serial port registers or output data from 3 - wire serial port registers. 23 scsz i serial port chip select . low active to enable 3 - wire serial port. 28 v dd - p ower . 3.3 volts. 14 19 vss1 vss2 - - ground . 0 volt. * * * for clock source other than 14.318mhz, please contact atelic systems.
AT2008 8 channels adpcm processor page 3 of 19 ?2001 atelic systems, inc. AT2008 pin assignment 28 - pin sop sync8 1 28 rstz 2 27 tm0 3 26 tm1 4 25 sync7 5 24 a0 6 23 a1 7 22 sync6 8 21 sync5 9 20 sync4 10 19 sync3 11 18 xtal2 12 17 xtal1 13 16 vss1 14 15 vdd yin ckla fsy yout scsz sdi/sdo sclk xout vss2 sync1 clkp xin sync2 AT2008 sop pin assignment 1. when there are multiple AT2008 used on the same system, a1, a0 a re used to identify the chip. 2. a1, a0 are for chip id. values are from 00 to 03. they should be connected to microcontroller i/o line or hard wired to either v cc or ground.
AT2008 8 channels adpcm processor page 4 of 19 ?2001 atelic systems, inc. AT2008 block diagram 8-bit pcm 8-bit pcm adpcm signal adpcm signal law to linear lawa lawa adpcm bypass adpcm reset adpcm bypass linear to law m u x m u x adpcm encoder adpcm reset m u x adpcm decoder m u x adpcm reset encode channel decode channel note: a dotted line with arrow mark indicate the control bit in the per channel control command, such as lawa, adpcm bypass and adpcm reset. please refer to page 9 for detail information. only two half channel is shown above. AT2008 has additional capab ility to process up to 16 half channels simultaneously.
AT2008 8 channels adpcm processor page 5 of 19 ?2001 atelic systems, inc. power the AT2008 is powered by a 3.3 v source and draws 100 ma at full operation and < 1 ma in powerdown mode. initialization there are two different classes of resets available on the AT2008 chip. for the default reset, hold the rstz pin low for 50 ms. this reset will bring the chip to a functioning default state. in the default state, the following parameters are set: 1. pins fsy, clkp, clka default to input (chip will receive these signals from external source) 2. 4 half channels of 32k m - law adpcm decoder running on half channels 0 - 3 3. 4 half channels of 32k m - law adpcm encoder running on half channels 4 - 7 a second type of reset involving the use of the 3 - wire serial interface can also be used direct the pin i/o configurations of fsy, clkp, and clka durin g reset.
AT2008 8 channels adpcm processor page 6 of 19 ?2001 atelic systems, inc. chip id setup the two chip id pins a0 and a1 (pins 6,7) should also be set during chip initialization. the ?chip id? is used to differentiate between AT2008 chips in a system that uses more than one AT2008 chip. when using only one chip, it is recommended to tie a0 and a1 to digital zero. thus, when programming the AT2008 chip, you can use the chip id = ?00? to substitute wherever you see a1, a0. the maximum number of AT2008 can be used in a system is 4, and a chip id must be assigned to ea ch AT2008 in a system. the format of a0 and a1 should be specified according to the following table: a1 a0 description 0 0 AT2008 chip id=0 0 1 AT2008 chip id=1 1 0 AT2008 chip id=2 1 1 AT2008 chip id=3 programming the AT2008 using the serial port to input commands commands for the AT2008 are entered using the 3 - wire serial interface. the ?three wires? refer to the three pins which control the interface: sdi/sdo (serial data in/serial data out), sclk (serial clock), and scsz (serial chip select). when scsz is enabled (low), the sdi is sampled every sclk signal. sampled bits are collected into an 8 - bit register and read by the dsp. the scsz signal can be held more than 8 - bits at a time in 8 - bit multiples forming a command sequence. different comm and sequences form the bulk of AT2008 programming. byte 1 sdi sclk scsz generic 3-byte command sequence lsb b1 b2 b3 b4 b5 b6 b7 byte 2 byte 3 command sequence overview the AT2008 understands four different types of command sequences. 1. the pll command sequences sets the operating speed of the chip. 2. the mcu7byte comma nd sequence set the adpcm algorithms, bit - slots, bit - rate and encode or decode channel. 3. the per channel control command sequence sets the adpcm bypass, reset and law format. 4. chip power - up and power - down commands.
AT2008 8 channels adpcm processor page 7 of 19 ?2001 atelic systems, inc. pll command sequence the pll command sequ ence is a 3 - byte command sequence that sets the operating speed of the AT2008 to be a multiple of the input crystal mhz. format of pll command sequence byte 1 0 1 f3 f2 f1 f0 a1 a0 byte 2 n6 n5 n4 n3 n2 n1 n0 m5 byte 3 m4 m3 m2 m1 m0 p2 p1 p0 a[1:0] refers to the chip id (please refer to section talking about chip id) n[6:0] = n, binary number used for frequency multiplier m[5:0] = m, binary number used for frequency divider p[2:0] = table specialized frequency divider (please refer to table). f[3:0] = divider for clkp & clka generator. f(clka/clkp) = f(xtal) / f[3:0] table for p, frequency multiplier p = 0 bypass, pllclk = xtalclk regardless of n, m. p = 1 16 p = 2 8 p = 3 4 p = 4 2 p = 5 1 p = 6 no pllclk, pllclk = 0 hz (chip disabled!) p = 7 no pllclk, pllclk = 0 hz (chip disabled!) the system clock uses n , m , and p to determine the speed of the system clock using the following formula: system clock = (crystal_clk * n * 4) / (m * p) by default, the chip is set to run at 86 mhz using a 14.3 mhz crystal input. mcu7byte command sequence this command sequence allows the user to specify the adpcm algorithm, i/o bit - slots. the command sequence length is variable, and is dependent on the number of channels that are specified. the command sequence consists of a header byte, a data portion consisting of 7 bytes for every channel specified, and a footer byte. the total number of bytes in the command sequence will be 2+7n where n = number of half channels specified. the channels should be sorted by the user in increasing order of ?input begin bit?. all the yin channels should be placed in sorted order before all the xin channels. below is a sample of mcu7byte command sequence for two ?half channels?.
AT2008 8 channels adpcm processor page 8 of 19 ?2001 atelic systems, inc. note: the format of data fields in/out, adpcm_ind, dec and rate are specified below. in/out description 0 0 input on xin, output on xout 0 1 input on xin, output on yout 1 0 input on yin, output on xout 1 1 input on yin, output on yout default: input is on xin, output is on xout for adpcm encoding functions. input is on yin, output is on yout for adpcm decoding functions. adpcm_ind description 0 no resource is allocated for adpcm operation 1 allocate resource for adpcm operation default: 1, allocate resource for adpcm operation dec description 0 adpcm (input is pcm, output is adpcm) encode channel 1 adpcm (input is adpcm, output is pcm) decode channel default: 1 for channel 0, 1, 2, 3; 0 for channel 4, 5, 6, 7. rate description 0 0 16k adpcm bitrate 0 1 24k adpcm bitrate 1 0 32k adpcm bitrate 1 1 40k adpcm bitrate default: 10 for 32k adpcm bit - rate command byte [7:0] descrip tion 0 0 0 0 0 0 a1 a0 chip setup command header with a1, a0 chip id in/out 0 adpcm_ind 0 0 0 0 specify channel in/out source and adpcm indicator. 0 dec 0 1 1 1 rate adpcm, configuration command for channel #0 0 0 0 0 0 0 0 0 system rese rved input begin bit input end bit output begin bit chan 0 data output end bit these commands specify the begin and ending bits of input data and output data for channel #0 in/out 0 adpcm_ind 0 0 0 0 specify channel in/out source and adpcm indi cator 0 dec 0 1 1 1 rate adpcm, configuration command for channel #1 0 0 0 0 0 0 0 0 system reserved input begin bit input end bit output begin bit chan 1 data output end bit these commands specify the begin and ending bits of input data and output data for channel #1 1 1 1 1 1 1 1 1 footer of chip setup.
AT2008 8 channels adpcm processor page 9 of 19 ?2001 atelic systems, inc. per channel control command sequence the per channel control command sequence allows the user to specify some parameters for each half channel. the command sequence length is variable, and is dependent on the number of channels that are specified. the format of the command consists of a header, a begin channel number byte, and a d ata portion containing information of each channel. the total number of bytes in the command sequence will be 2+2n where n = number of half channels specified. below is a sample of per channel control command sequence for two half channels. note: the format of each data fields like adpcm reset, adpcm bypass, lawa, lawp and idle are specified below. adpcm reset description 0 normal operation without reset of adpcm 1 reset adpcm internal states default: 1 when adpcm reset bit is ?1?, adpcm encoder will output ?ff?, adpcm decoder will output ?ff? for u - law and ?d5 ? for a - law. adpcm bypass descripti on 0 normal operation with adpcm 1 bypass adpcm default: 0 lawa description 0 u - law 1 a - law default: 0 idle description 0 normal operation 1 the output is tri - state during its time slot. once this bit is cleared, it will come back to normal o peration default: 0 command by te [7:0] description 0 0 1 1 0 0 a1 a0 per channel control command header with a1, a0 chip id channel configuration begin to begin on first channel, set to 0 high byte 0 0 0 0 0 0 0 0 ch0 low byte 0 0 0 adpcm reset a dpcm bypass lawa 0 idle configuration for channel 0 high byte 0 0 0 0 0 0 0 0 ch1 low byte 0 0 0 adpcm reset adpcm bypass lawa 0 idle configuration for channel 1
AT2008 8 channels adpcm processor page 10 of 19 ?2001 atelic systems, inc. chip power - up power - down command the chip power - up / power - down command is a single command byte which enables and disables the AT2008 chip. power - up chip mode will: 1. stop the sample processing 2. power - up the pll to the specified mult iplier frequency 3. reset algorithms on the chip. power - down chip mode will: 1. stop the sample processing. 2. switch the system clock to the power down clock running approximately at 125 hz. 0 0 0 1 0 0 a1 a0 power - up chip command 0 0 0 0 1 0 a1 a0 power - dow n chip command note: a1, a0 refers to the chip id.
AT2008 8 channels adpcm processor page 11 of 19 ?2001 atelic systems, inc. reference designs and additional notes using the AT2008 with other combo chips AT2008 combo 0 dx dr combo 1 combo 2 combo 3 xin(16) fsy(25) sync.1(18) yout(24) clkp(17) sync2(15) sync3(11) sync4(10) (20)xout (27)yin tm1 tm0 when there are multiple AT2008 used on the same systems, a1, a0 are used to identify the chip. a1, a0 are for chip id. values are from 00-03. they should be connected to microcontroller i/o lines or wired to either vcc or ground. note: sdi, sclk, scsz are for 3-wire commands and should be connected to microcontroller i/o pins. clka and fsy. typical application of default setting uses national single channel combo (quad combo can be used to replace the 4 single combo) clka sdi sclk scsz
AT2008 8 channels adpcm processor page 12 of 19 ?2001 atelic systems, inc. sample command sequences: adpcm 32k, m m - law, 8 - half channel s: for convenience, each half duplex channel is assigned a number corresponding to the internal processing order of the channels. channels 0 through channel 3 correspond with adpcm decode channels and channels 4 through channel 7 corresponds with adpcm e ncode channels. the following is brief description of what each half duplex channel is running: channel 0: (decode adpcm channel) mcu7byte command: decode (i.e. input is adpcm sample sequence) u - law output, 32k adpcm algorithm. input time slot: @yin[0 :3] (beginning bit=0, ending bit=3) output time slot: @yout[0:7] (beginning bit=0, ending bit=7) channel 1: (decode adpcm channel) mcu7byte command: decode u - law output, 32k adpcm algorithm. input time slot: @yin[16:19] output time slot: @yout[16:23] c hannel 2: (decode adpcm channel) mcu7byte command: decode u - law output, 32k adpcm algorithm. input time slot: @yin[32:35] output time slot: @yout[32:39] channel 3: (decode adpcm channel) mcu7byte command: decode u - law output, 32k adpcm algorithm. i nput time slot: @yin[48:51] output time slot: @yout[48:55] channel 4: (encode adpcm channel) mcu7byte command: encode (i.e. output is adpcm sample sequence) u - law input, 32k adpcm algorithm. input time slot: @xin[0:7] output time slot: @xout[0:3] chan nel 5: (encode adpcm channel) mcu7byte command: encode (i.e. output is adpcm sample sequence) u - law input, 32k adpcm algorithm. input time slot: @xin[16:23] output time slot: @xout[16:19] channel 6: (encode adpcm channel) mcu7byte command: encode ( i.e. output is adpcm sample sequence)
AT2008 8 channels adpcm processor page 13 of 19 ?2001 atelic systems, inc. u - law input, 32k adpcm algorithm. input time slot: @xin[32:39] output time slot: @xout[32:35] channel 7: (encode adpcm channel) mcu7byte command: encode (i.e. output is adpcm sample sequence) u - law input, 32k adpc m algorithm. input time slot: @xin[48:55] output time slot: @xout[48:51] the following is command sequences of per channel control and mcu7byte: command bytes specifying per channel control 30 // begin per channel control. this byte is fixed. 00 // begin at 0 channel. this byte is usually fixed (usually begin specifying at 0). 00 // 0 channel high byte. 00 // 0 channel low byte. 00 // 1 channel high byte. 00 // 1 channel low byte. 00 // 2 channel high byte. 00 // 2 channel l ow byte. 00 // 3 channel high byte. 00 // 3 channel low byte. 00 // 4 channel high byte. 00 // 4 channel low byte. 00 // 5 channel high byte. 00 // 5 channel low byte. 00 // 6 channel high byte. 00 // 6 channel low byte. 00 / / 7 channel high byte. 00 // 7 channel low byte. command bytes specifying mcu7byte definition. 00 // begin mcu7byte definition. d0 // [7]: input; [6]:output; 0==x; 1==y, channel 0, yin - yout 5e // algorithm setup, default value = 5eh for expan d 00 // 00 // begin input slot bit, adpcm 03 // end input slot bit, adpcm 00 // begin output slot bit, pcm 07 // end output slot bit, pcm d0 // [7]: input; [6]:output; 0==x; 1==y, channel 1, yin - yout 5e // algorithm setup, default valu e = 5eh for expand 00 // 10 // begin input slot bit, adpcm 13 // end input slot bit, adpcm 10 // begin output slot bit, pcm 17 // end output slot bit, pcm d0 // [7]: input; [6]:output; 0==x; 1==y, channel 2, yin - yout
AT2008 8 channels adpcm processor page 14 of 19 ?2001 atelic systems, inc. 5e // algorith m setup, default value = 5eh for expand 00 // 20 // begin input slot bit, adpcm 23 // end input slot bit, adpcm 20 // begin output slot bit, pcm 27 // end output slot bit, pcm d0 // [7]: input; [6]:output; 0==x; 1==y, channel 3, y in - yout 5e // algorithm setup, default value = 5eh for expand 00 // 30 // begin input slot bit, adpcm 33 // end input slot bit, adpcm 30 // begin output slot bit, pcm 37 // end output slot bit, pcm 10 // [7]: input; [6]:output ; 0==x; 1==y, channel 4, xin - xout 1e // algorithm setup, default value = 1eh for compress 00 // 00 // begin input slot bit, pcm 07 // end input slot bit, pcm 00 // begin output slot bit, adpcm 03 // end output slot bit, adpcm 1 0 // [7]: input; [6]:output; 0==x; 1==y, channel 5, xin - xout 1e // algorithm setup, default value = 1eh for compress 00 // 10 // begin input slot bit, pcm 17 // end input slot bit, pcm 10 // begin output slot bit, adpcm 13 / / end output slot bit, adpcm 32 // [7]: input; [6]:output; 0==x; 1==y, channel 6, xin - xout 1e // algorithm setup, default value = 1eh for compress 00 // 20 // begin input slot bit, pcm 27 // end input slot bit, pcm 20 // begin ou tput slot bit, adpcm 23 // end output slot bit, adpcm 10 // [7]: input; [6]:output; 0==x; 1==y, channel 7, xin - xout 1e // algorithm setup, default value = 1eh for compress 00 // 30 // begin input slot bit, pcm 37 // end input slot b it, pcm 30 // begin output slot bit, adpcm 33 // end output slot bit, adpcm ff // end of mcu7byte commands
AT2008 8 channels adpcm processor page 15 of 19 ?2001 atelic systems, inc. electrical characteristics: (0 c to 70 c) dc electrical characteristics (v dd =3.3v+20% - 10%) parame ter symbol minimum typical maximum units notes active supply current ivcc 40 ma 1,2 power down i vccpd < 1 ma 3 input leakage i i - 1.0 +1.0 m a output leakage i o - 1.0 +1.0 m a 4 output current (2.4v) i oh 1.2 ma output current (0.4 v) i ol 4 ma notes: 1. clkp = clka = 2.048mhz; mclk = 10mhz. 2. outputs open; inputs swinging full supply levels; 8 channel full duplex operation. 3. power down; xtal = high; fsx, fsy, clka, clkp all 0. 4. xout and yout are 3 - stated. pcm interface (0 c to 70 c) ac electrical characteristics (v dd =3.3v+20% - 10%) parameter symbol minimum typical maximum units notes clkp, clka period t pxy 244 3906 ns 1 clkp, clka pulse width t wxyl t wxy h 100 ns clkp, clka rise fall times t rxy t fxy 10 20 ns hold time from clkp, clka to fsy t hold 0 ns 2 setup time from fsy high to clkp, clka low t sf 50 ns 2 setup time for xin, yin to clkp, clka low t sd 50 ns 2 hold time from xin, yin to clk p, clka low t hd 50 ns 2 delay time from clkp, clka to valid xout, yout t dxyo 10 150 ns 3 notes: 1. maximum width of fsy is clkp/clka period (except for signaling frame). 2. measured at v ih = 2.0v, v il = 0.8v, and 10ns maximum rise and fall times. 3. load = 150 pf + 2lsttl loads. 4. for lsb of pcm or adpcm byte.
AT2008 8 channels adpcm processor page 16 of 19 ?2001 atelic systems, inc. master clock/reset (0 c to 70 c) ac electrical characteristics (v dd =3.3v+20% - 10%) parameter symbol minimum typical maximum units notes mclk period t pm 69.84 10 0 125 ns 1 mclk rise/fall times t rm , t fm 10 ns rstz pulse width t rst 1 ms note: 1. mclk = 14mhz or 10mhz. serial port (0 c to 70 c) ac electrical characteristics (v dd =3.3v+20% - 10%) parameter symbol minimum typical maximum units notes sdi to sclk set up t dc 55 ns 1 sclk period t p 1 m s 1 sclk to sdi hold t cdh 55 ns 1 sclk low time t cl 250 500 ns 1 sclk high time t ch 250 500 ns 1 sclk rise and fall time t r , t f 100 ns 1 scsz to sclk setup t cc 50 ns 1 sclk to scsz hold t cch 250 ns 1 scsz inactive time t cwh 250 ns 1 sclk setup to scsz falling t scc 50 ns 1 note: 1. measured at v ih = 2.0v, v il = 0.8v, and 10ns maximum rise and fall time.
AT2008 8 channels adpcm processor page 17 of 19 ?2001 atelic systems, inc. timi ng diagrams master clock/reset ac timing diagram mclk rst t rst t rm t fm t pm t wmh twml sclk sclk sdi t scc t cc t ch t r t f t cch t cwh t cwh t cl t p t dc t cdh note: sclk may be either high or low when scsz is taken low. 3 wire timing diagram
AT2008 8 channels adpcm processor page 18 of 19 ?2001 atelic systems, inc. pcm interface ac timing diagram clkp clka fsy fsy xin yin xout yout 3 - state t hold t rxy t fxy t pxy t wxyh t wxyl t hf t sf t hf (msb) (msb) t dxyo t sd t hd t dxyz
AT2008 8 channels adpcm processor page 19 of 19 ?2001 atelic systems, inc. package information d c b a e eb f 28 pin sop AT2008 package information min normal max a 2.286 2.337 2.388 b 0.305 0.406 0.508 c 0.991 1.041 1.092 d 17.856 17.907 17.958 e 7.442 7.493 7.544 eb 10.312 10.414 10.516 f 0.635 -- -- g 1.194 1.27 1.346 dimension in mm. g

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