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1 precision edge ? sy89833l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 description guaranteed ac performance over temperature and voltage: ? dc-to > 2ghz throughput ? <600ps propagation delay (in-to-q) ? <20ps within-device skew ? <190ps rise/fall times ultra-low jitter design ? <1ps rms cycle-to-cycle jitter ? <10ps pp total jitter ? <1ps rms random jitter ? <10ps pp deterministic jitter unique input termination and vt pin accepts dc- and ac-coupled inputs high-speed lvds outputs 3.3v power supply operation industrial temperature range: C40 c to +85 c available in 16-pin (3mm x 3mm) mlf ? package features 3.3v ultra-precision 1:4 lvds fanout buffer/translator with internal termination precision edge ? sy89833l applications processor clock distribution sonet clock distribution fibre channel clock distribution gigabit ethernet clock distribution 1 the sy89833l is a 3.3v, high-speed 2ghz differential low voltage differential swing (lvds) 1:4 fanout buffer optimized for ultra-low skew applications. within device skew is guaranteed to be less than 20ps over supply voltage and temperature. the differential input buffer has a unique internal termination design that allows access to the termination network through a vt pin. this feature allows the device to easily interface to different logic standards. a vref-ac reference is included for ac-coupled applications. the sy89833l is part of micrels high-speed clock synchronization family. for 2.5v applications, the sy89832u provides similar functionality while operating from a 2.5v 5% supply. for applications that require a different i/o combination, consult the micrel website at: www.micrel.com, and choose from a comprehensive product line of high- speed, low-skew fanout buffers, translators and clock generators. functional block diagram typical performance precision edge is a registered trademark of micrel, inc. micro leadframe and mlf are registered trademarks of amkor technology, inc. 622mhz output time (321.9ps/div.) C15mv offset (50mv/div.) in /in dq q3 /q3 q2 /q2 q1 /q1 q0 /q0 en (lvttl/cmos) vt 50 ? 50 ? vref-ac 1:4 precision edge ?
2 precision edge ? sy89833l micrel inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 package/ordering information ordering information (1) package operating package lead part number type range marking finish sy89833lmi mlf-16 industrial 833l sn-pb sy89833lmitr (2) mlf-16 industrial 833l sn-pb SY89833LMG (3) mlf-16 industrial 833l with pb-free nipdau bar line indicator pb-free SY89833LMGtr (2, 3) mlf-16 industrial 833l with pb-free nipdau bar line indicator pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs. pin number pin name pin function 15, 16 q0, /q0 lvds differential (outputs): normally terminated with 100 ? across the pair (q, /q). see lvds 1, 2 q1, /q1 outputs section, figure 2a. unused outputs should be terminated with a 100 ? resistor across 3, 4 q2, /q2 each pair. 5, 6 q3, /q3 8e n this single-ended ttl/cmos-compatible input functions as a synchronous output enable. the synchronous enable ensures that enable/disable will only occur when the outputs are in a logic low state. note that this input is internally connected to a 25k ? pull-up resistor and will default to logic high state (enabled) if left open. 9, 12 /in, in differential inputs: these input pairs are the differential signal inputs to the device. inputs accept ac- or dc-coupled differential signs as small as 100mv. each pin of a pair internally terminates to a vt pin through 50 ? . note that these inputs will default to an intermediate state if left open. pleae refer to the input interface applications section for more details. 10 vrefCac reference voltage: these outputs bias to v cc C1.4v. they are used when ac coupling the inputs (in, /in). for ac-coupled applications, connect vref-ac to vt pin and bypass with 0.01 f low esr capacitor to v cc . see input interface applications section for more details. maximum sink/source current is 1.5ma. due to the limited drive capability, each vref-ac pin is only intended to drive its respective vt pin. 11 vt input termination center-tap: each side of the differential input pair terminates to a vt pin. the vt pins provide a center-tap to a termination network for maximum interface flexibility. see input interface applications section for more detaiils. 13 gnd ground. gnd pins and exposed pad must be connected to the most negative potential of the device ground. 7, 14 vcc positive power supply: bypass with 0.1 f//0.01 f low esr capacitors and place as close to each vcc pin as possible. pin description 13 14 15 16 12 11 10 9 1 2 3 4 8 7 6 5 q1 /q1 q2 / q2 in vt vref-ac /in /q0 q0 vcc gnd q3 /q3 vcc en 16-pin mlf ? (mlf-16) in /in en q /q 0 1101 1 0110 xx00 (1) 1 (1) note 1. on next negative transition of the input signal (in). truth table
3 precision edge ? sy89833l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 absolute maximum ratings (1) supply voltage (v cc ) .................................. C0.5v to +4.0v input voltage (v in ) ............................... C0.5v to v cc +0.3v lvds output current (i out ) ..................................... 10ma input current source or sink current on (in, /in) .................. 50ma v ref-ac current source or sink current on (i vt ) .......................... 2ma maximum operating junction temperature .............. 125 c lead temperature (soldering, 20 sec.) ..................... 260 c storage temperature (t s ) ....................... C65 c to +150 c operating ratings (2) supply voltage range .............................. +3.0v to +3.60v ambient temperature (t a ) ......................... C40 c to +85 c package thermal resistance (3) mlf ? ( ja ) still-air ............................................................. 60 c/w mlf ? ( jb ) .......................................................... 33 c/w t a = C40 c to +85 c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply voltage range 3.0 3.3 3.6 v i cc power supply current no load, max. v cc .75 100 ma r in input resistance (in-to-vt) 45 50 55 ? r diff-in differential input resistance 90 100 110 ? (in-to-/in) v ih input high voltage 0.1 v cc +0.3 v (in, /in) v il input low voltage C0.3 v ih C 0.1 v (in, /in) v in input voltage swing note 3, see figure 2c. 0.1 v cc v (in, /in) v diff_in differential input voltage note 3, see figure 2d. 0.2 v |iin| input current 45 ma in, /in v refCac reference voltage note 5 v cc C1.525 v cc C1.425 v cc C1.325 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng con ditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the pcb . jb and ja values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established . 5. due to the internal termination (see "input buffer structure" section) the input current depends on the applied voltages at i n, /in and vt inputs. do not apply a combination of voltages that causes the input current to exceed the maximum limit! dc electrical characteristics (4)
4 precision edge ? sy89833l micrel inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 v cc = 3.3v 10%, r l = 100 ? across the outputs; t a = C40 c to +85 c symbol parameter condition min typ max units v out output voltage swing see figure 2c. 250 325 mv v diff_out differential output voltage swing see figure 2d. 500 650 mv v ocm output common mode voltage 1.125 1.275 v ? v ocm change in common mode voltage C50 50 mv v cc = 3.3v 10%, t a = C40 c to +85 c symbol parameter condition min typ max units v ih input high voltage 2.0 v cc v v il input low voltage 0 0.8 v i ih input high current C125 30 a i il input low current C300 a note: 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established . lvds outputs dc electrical characteristics (6) lvttl/cmos dc electrical characteristics (6)
5 precision edge ? sy89833l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 timing diagram t s in /q q t pd t h en v cc /2 v cc /2 t pd v in v out /in v cc = +3.3v 10%; r l = 100 ? across the outputs; t a = C40 c to +85 c unless otherwise stated. symbol parameter condition min typ max units f max maximum frequency v out 200mv 2.0 ghz t pd propagation delay in-to-q v in < 400mv 400 500 600 ps in-to-q v in 400mv 330 440 530 ps t skew within-device skew note 8 520ps part-to-part skew note 9 200 ps t s set-up time en to in, /in note 10 300 ps t h hold time en to in, /in note 10 500 ps t jitter data random jitter (rj) note 11 1ps rms deterministic jitter (dj) note 12 10 ps pp clock cycle-to-cycle jitter note 13 1ps rms total jitter (tj) note 14 10 ps pp t r , t f output rise/fall times at full output swing. 60 110 190 ps (20% to 80%) notes: 7. high-frequency ac parameters are guaranteed by design and characterization. 8. within device skew is measured between two different outputs under identical input transitions. 9. part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the ed ges at the respective inputs. 10. set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. for async hronous applications, set-up and hold times do not apply. 11. random jitter is measured with a k28.7 pattern, measured at f max . 12. deterministic jitter is measured at 2.5gbps with both k28.5 and 2 23 C1 prbs pattern. 13. cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t jitter_cc = t n Ct n+1 , where t is the time between rising edges of the output signal. 14. total jitter definition: with an ideal clock input frequency of f max (device), no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. ac electrical characteristics (7)
6 precision edge ? sy89833l micrel inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 typical operating characteristics 0 100 200 300 400 500 600 0 200 400 600 800 propagation delay (ps) input voltage swing (mv) propagation delay vs. input voltage swing 0 50 100 150 200 250 300 350 0 0.5 1 1.5 2 2.5 amplitude (mv) frequency (ghz) output swing vs. frequency v cc = 3.3v, gnd = 0v, v in = 400mv, r l = 100 ? across the outputs, t a = 25 c, unless otherwise stated.
7 precision edge ? sy89833l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 155mhz output time (1.29ns/div.) C 15mv offset (150mv/div.) functional characteristics 622mhz output time (321.9ps/div.) C 15mv offset (150mv/div.) 1ghz output time (200ps/div.) C 10mv offset (150mv/div.) v cc = 3.3v, gnd = 0v, v in = 400mv, r l = 100 ? across the outputs; t a = 25 c, unless otherwise stated.
8 precision edge ? sy89833l micrel inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 input stage
figure 1. simplified differential input buffer lvds outputs lvds specifies a small swing of 325mv typical, on a nominal 1.20v common mode above ground. the common 100 ? gnd v out v oh , v ol v oh , v ol figure 2a. lvds differential measurement v out, v in 325mv (typical) figure 2c. single-ended swing 50 ? gnd v ocm , ? v ocm 50 ? figure 2b. lvds common mode measurement 650mv v diff_in, v diff_out figure 2d. differential swing mode voltage has tight limits to permit large variations in ground noise between an lvds driver and receiver.
9 precision edge ? sy89833l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 related product and support documents input interface applications nc cml in /in vt nc sy89833l v cc = 3.3v v cc = 3.3v vref-ac figure 3a. dc-coupled cml input interface cml in /in vt v cc = 3.3v v cc = 3.3v v cc sy89833l vref-ac 0.01 f figure 3b. ac-coupled cml input interface lvp ecl in /in vt v cc = 3.3v v cc = 3.3v sy89833l vref-ac v cc C2v nc 50 ? 0.01 f v cc figure 3c. dc-coupled lvpecl input interface in /in vt rpd 100 ? rpd 100 ? v cc = 3.3v v cc = 3.3v sy89833l vref-ac v cc 0.01 f lvp ecl figure 3d. ac-coupled lvpecl input interface nc lvds in /in vt nc sy89833l v cc = 3.3v v cc = 3.3v vref-ac figure 3e. lvds input interface part number function data sheet link sy89830u 2.5v/3.3v/5v 2.5ghz 1:4 pecl/ecl http://www.micrel.com/product-info/products/sy89830u.shtml clock driver with 2:1 differential input mux sy89831u ultra-precision 1:4 lvpecl fanout buffer/ http://www.micrel.com/product-info/products/sy89831u.shtml translator with internal termination sy89832u 2.5v ultra-precision 1:4 lvds fanout buffer/ http://www.micrel.com/product-info/products/sy89832u.shtml translator with internal termination sy89834u 2.5/3.3v two input, 1ghz lvttl/cmos-to-lvpecl http://www.micrel.com/product-info/products/sy89834u.shtml 1:4 fanout buffer/translator 16-mlf ? manufacturing guidelines http://www.amkor.com/products/notes_papers/mlf_appnote_0301.pdf exposed pad application note hbw solutions new products and termination app. note http://www.micrel.com/product-info/as/solutions.shtml
10 precision edge ? sy89833l micrel inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 august 2007 16-pin epad micro leadframe ? (mlf-16) pa c kage ep- exposed pad die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 16-pin mlf ? package (always solder, or equivalent, the exposed pad to the pcb) package notes: 1. package meets level 2 moisture sensitivity classification, and are shipped in dry-pack form. 2. exposed pads must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this datasheet is believed to be accurate and reliable. however, no responsibility is as sumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is at purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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