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1 dac1221 dac1221 16-bit low power digital-to-analog converter features l 16-bit monotonicity guaranteed over C40 c to +85 c l low power: 1.2mw l voltage output l settling time: 2ms to 0.012% l max linearity error: 30ppm l on-chip calibration applications l process control l ate pin electronics l closed-loop servo-control l smart transmitters l portable instruments l vco control description the dac1221 is a digital-to-analog (d/a) converter offering 16-bit monotonic performance over the speci- fied temperature range. it utilizes delta-sigma technol- ogy to achieve inherently linear performance in a small package at very low power. the output range is two times the external reference voltage. on-chip calibration circuitry dramatically reduces offset and gain errors. the dac1221 features a synchronous serial interface. in single converter applications, the serial interface can be accomplished with just two wires, allowing low- cost isolation. for multiple converters, a cs signal allows for selection of the appropriate d/a converter. the dac1221 has been designed for closed-loop control applications in the industrial process control market, and high resolution applications in the test and measurement market. it is also ideal for remote appli- cations, battery-powered instruments, and isolated sys- tems. the dac1221 is available in a ssop-16 package. ? 1999 burr-brown corporation pds-1519b printed in u.s.a. may, 2000 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson blvd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? immediate p roduct info: (800) 548-6132 dac1221 for most current data sheet and other product information, visit www.burr-brown.com clock generator serial interface second-order d? modulator instruction register command register data register offset register full-scale register microcontroller first-order switched capacitor filter second-order continuous time post filter modulator control c 2a c 2b c 3 c 1 x in x out v ref cs dv dd dgnd av dd agnd sdio v out sclk sbas113
2 dac1221 specifications all specifications t min to t max , av dd = dv dd = +3v, f xin = 2.5mhz, v ref = +1.25v, c 1 = 2.2nf, c 2 = 150pf, c 3 = 6.8nf, unless otherwise noted. dac1221e parameter conditions min typ max units accuracy monotonicity 16 bits linearity error (1) 30 ppm of fsr offset error (2) v out = 20mv, calpin = 1 (6) 190 m v offset error drift (3) 50 m v/ c midscale error (2) v out = v ref , calpin = 1 (6) 20 m v midscale error drift (3) 50 m v/ c gain error (2) calpin = 1 (6) 0.015 % gain error drift (3) 3 ppm/ c power-supply rejection ratio at dc, db = C20log( d v out / d v dd )57db analog output output voltage (4) 0 2 ? v ref v output current (1) 0.25 ma capacitive load 500 pf short-circuit current 10 ma short-circuit duration gnd or v dd indefinite dynamic performance settling time (1,5) to 0.012% 1.8 2 ms output-noise voltage 1hz to 2khz 45 m vrms reference input input voltage 1.125 1.25 1.375 v input impedance 1m w digital input/output logic family ttl-compatible cmos logic levels (all except x in ) v ih 2.0 dv dd + 0.3 v v il C0.3 0.8 v v oh i oh = C0.8ma 2.4 v v ol i ol = 1.6ma 0.4 v input-leakage current 10 m a x in frequency range (f xin ) 1.0 2.5 mhz data format user programmable offset twos complement or straight binary power supply requirements power-supply voltage 2.7 3.3 v supply current analog current 320 m a digital current 70 m a power dissipation normal mode 1.2 1.6 mw sleep mode 0.25 mw temperature range specified performance C40 +85 c notes: (1) valid from agnd + 20mv to 2 ? v ref . (2) applies after calibration. (3) recalibration can remove these errors. (4) ideal output voltage. (5) using external low-pass filter with 2khz corner frequency. (6) see command register for description of calpin.
3 dac1221 the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. absolute maximum ratings (1) av dd to dv dd ................................................................................... 0.3v av dd to agnd ........................................................................ C0.3v to 4v dv dd to dgnd ....................................................................... C0.3v to 4v agnd to dgnd ............................................................................... 0.3v v ref voltage to agnd .......................................................... 1.0v to 1.5v digital input voltage to dgnd .............................. C0.3v to dv dd + 0.3v digital output voltage to dgnd ........................... C0.3v to dv dd + 0.3v package power dissipation ............................................. (t jmax C t a )/ q ja maximum junction temperature (t jmax ) ..................................... +150 c thermal resistance, q ja ssop-16 ............................................................................... 200 c/w lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. pin configuration top view ssop pin descriptions pin name description 1dv dd digital supply, +3v nominal 2x out digital, system clock output 3x in digital, system clock input 4 dgnd digital ground 5av dd analog supply, +3v nominal 6 dnc do not connect 7c 3 analog, filter capacitor 8c 2b analog, filter capacitor 9c 1 analog, filter capacitor 10 c 2a analog, filter capacitor 11 v out analog output voltage 12 v ref analog, reference input 13 agnd analog ground 14 cs digital, chip select input 15 sdio digital, serial data input/output 16 sclk digital, clock input for serial data transfer 1 2 3 4 5 6 7 8 dv dd x out x in dgnd av dd dnc c 3 c 2b sclk sdio cs agnd v ref v out c 2a c 1 16 15 14 13 12 11 10 9 dac1221e package specified drawing temperature package ordering transport product package number range marking number (1) media dac1221e ssop-16 322 C40 c to +85 c dac1221e dac1221e rails " " " " " dac1221e/2k5 tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 de vices per reel). ordering 2500 pieces of dac1221e/2k5 will get a single 2500-piece tape and reel. package/ordering information
4 dac1221 typical performance curves at t a = +25 c, av dd = dv dd = +3.0v, f xin = 2.5mhz, v ref = 1.25v, c 1 = 2.2nf, c 2 = 150pf and c 3 = 6.8nf. power supply rejection ratio vs frequency frequency (hz) 10 100 1000 10000 100000 psrr (db) 70 60 50 40 30 20 10 0 full scale output swing time (ms) 01234 output (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 time (ms) settling time: 20mv to fs 0246810 ? around fs ( v) 300 0 ?00 ?00 ?00 ?200 ?500 settling time: fs to 20mv time (ms) 0246810 ? around 20mv ( v) 1500 1200 900 600 300 0 ?00 offset vs temperature temperature ( c) ?5 25 75 ?0 0 50 100 offset (mv) 4 2 0 ? ? ? (can be corrected with calibration) output noise voltage vs frequency frequency (hz) 10 100 1000 10000 10000 noise (nv/ ? hz) 10000 1000 100 10 1
5 dac1221 linearity error vs code 16-bit input code normalized 0 0.2 0.4 0.6 0.8 1 linearity error (ppm of fsr) 25 20 15 10 5 0 ? gain error vs temperature temperature ( c) ?0 ?5 05075 25 100 gain error (%) 0.020 0.015 0.010 0.005 0.000 ?.005 ?.010 ?.015 (can be corrected with calibration) typical performance curves at t a = +25 c, av dd = dv dd = +3.0v, f xin = 2.5mhz, v ref = 1.25v, c 1 = 2.2nf, c 2 = 150pf and c 3 = 6.8nf.
6 dac1221 figure 1. capacitor connections. theory of operation the dac1221 is a precision, high dynamic range, self- calibrating, 16-bit, delta-sigma digital-to-analog converter. it contains a second-order delta-sigma modulator, a first- order switched-capacitor filter, a second-order continuous- time post filter, a microcontroller including the instruction, command and calibration registers, a serial interface, and a clock generator circuit. the design topology provides low system noise and good power-supply rejection. the modulator frequency of the delta-sigma d/a converter is controlled by the system clock. the dac1221 also includes complete onboard calibration that can correct for internal offset and gain errors. the calibration registers are fully readable and writable. this feature allows for system calibration. the various settings, modes, and registers of the dac1221 are read or written via a synchronous serial interface. this interface operates as an externally clocked interface. definition of terms differential nonlinearity error the differential nonlinearity error is the difference between an actual step width and the ideal value of 1 lsb. if the step width is exactly 1 lsb, the differential nonlinearity error is zero. a differential nonlinearity specification of less than 1 lsb guarantees monotonicity. drift the drift is the change in a parameter over tempera- ture. full-scale range (fsr) this is the magnitude of the typical analog output voltage range which is 2 ? v ref . for example, when the converter is configured with a 1.25v reference, the full-scale range is 2.5v. gain error this error represents the difference in the slope between the actual and ideal transfer functions. linearity error the linearity error is the deviation of the actual transfer function from an ideal straight line between the data end points. least significant bit (lsb) weight this is the ideal change in voltage that the analog output will change with a change in the digital input code of 1 lsb. monotonicity monotonicity assures that the analog output will increase or stay the same for increasing digital input codes. offset error the offset error is the difference between the expected and actual output, when the output is zero. the value is calculated from measurements made when v out = 20mv. settling time the settling time is the time it takes the output to settle to its new value after the digital code has been changed. f xin the frequency of the crystal oscillator or cmos- compatible input signal at the x in input of the dac1221. analog operation the system clock is divided down to provide the sample clock for the modulator. the sample clock is used by the modulator to convert the multi-bit digital input into a 1-bit digital output stream. the use of a 1-bit dac provides inherent linearity. the digital output stream is then con- verted into an analog signal via the 1-bit dac and then filtered by the 1st-order switched-capacitor filter. the output of the switched-capacitor filter feeds into the continuous time filter. the continuous time filter uses exter- nal capacitors, c 1 and c 2 , to adjust the settling time. the connections for capacitors are shown in figure 1. c 1 con- nects to v ref . c 2 connects between the c 2 pins. c 3 is connected between c 3 and v ref , and is used for calibration. calibration the dac1221 offers a self-calibration mode which auto- matically calibrates the output offset and gain. the calibra- tion is performed once and then normal operation is re- sumed. in general, calibration is recommended immediately after power-on and whenever there is a significant change in the operating environment. the amount of change which should cause re-calibration is dependent on the application. where high accuracy is important, re-calibration should be done on changes in temperature and power supply. after a calibration has been accomplished, the offset cali- bration register (ocr) and the full-scale calibration reg- ister (fcr) contain the results of the calibration. note that the values in the calibration registers will vary from configuration to configuration and from part to part. v ref c 2a c 1 c 3 c 2b 12 11 10 9 7 8 dac1221 c 3 6.8nf c 1 2.2nf c 2 150pf note: c 1 and c 2 should be npo type capacitors.
7 dac1221 + opa336 2 7 3 1 6 4 +3v +3v 87.6k w ref1004-1.2 20k w 0.10 f 10 f 0.1 f + 10 f 0.10 f to v ref pin 100 w figure 2. recommended external voltage reference circuit for best low noise operation with the dac1221. self calibration a self-calibration is performed after the bits 01 have been written to the command register operation mode bits (md1 and md0). this initiates a self-calibration on the next clock cycle. the offset correction code is determined by a repeated sequence of auto-zeroing the calibration compara- tor to the offset reference and then comparing the dac output to the offset reference value. the end result is the averaged, offset twos complement adjusted, and placed in the ocr. the gain correction is done in a similar fashion, except the correction is done against v ref to eliminate common-mode errors. the fcr result represents the gain code and is not offset twos complement adjusted. the calibration function takes between 300ms and 500ms (for f xin = 2.5mhz) to complete. once calibration is initi- ated, further writing of register bits is disabled until calibra- tion completes. the status of calibration can be verified by reading the status of the command register operation mode bits (md1 and md0). these bits will return to normal mode 00 when calibration is complete. it is recommended that the output be connected during calibration. the output isolation is controlled by the calpin bit in the cmr register. setting the calpin bit will connect the output and clearing the bit will disconnect and isolate the output. although it is recommended to connect the output during calibration, the load impedance should be such that the dac1221 is not required to sink any current, but is able to source up to the specified maximum. output mode the output of the dac1221 can be synchronously reset. by setting the clr bit in the cmr, the data input register is cleared to zero. this will result in an output of 0v when df = 1, or v ref when df = 0. the settling time is determined by the disf and adpt bits of the command register. the default state of disf = 0 and adpt = 0 enables fast settling, unless the output step is small ( ? 40mv). however, the dac1221 can be forced to always use fast settling if the adpt bit is set to 1. if disf is set to 1, all fast settling is disabled. the crst bit of the cmr can be used to reset the offset and calibration registers. by setting the crst bit, the contents of the calibration registers are reset to 0. reference input the reference input voltage of 1.25v can be directly con- nected to v ref pin. the recommended reference circuit for the dac1221 is shown in figure 2. digital operation system configuration the dac1221 is controlled by 8-bit instruction codes (insr) and 16-bit command codes (cmr) via the serial interface, which is externally clocked. the dac1221 microcontroller (mc) consists of an alu and a register bank. the mc has three states: power-on reset, calibration, and normal operation. in the power-on reset state, the mc resets all the registers to their default states. in the calibration state, the mc performs offset and gain self-calibration. in the normal state, the mc performs d/a conversions. the dac1221 has five internal registers, as shown in table i. two of these, the instruction register (insr) and the command register (cmr), control the operation of the converter. the instruction register utilizes an 8-bit instruc- tion code to control the serial interface to determine whether the next operation is either a read or a write, to control the word length, and to select the appropriate register to read/write. communication with the dac1221 is controlled via the insr. under normal operation, the insr is written as the first part of each serial communication. the instruc- tion that is sent determines what type of communication will occur next. it is not possible to read the insr. the com- mand register has a 16-bit command code to set up the insr instruction register 8 bits dir data input register 16 bits cmr command register 16 bits ocr offset calibration register 24 bits fcr full-scale calibration register 24 bits table i. dac1221 registers.
8 dac1221 table ii. instruction register. msb lsb r/w mb1 mb0 0 a3 a3 a1 a0 note: insr is a write-only register with the msb (most significant byte and bit) written first, independent of the bd bit. a3 a2 a1 a0 0 0 0 0 data input register byte 1 msb 0 0 0 1 data input register byte 0 lsb 0 0 1 0 reserved 0 0 1 1 reserved 0 1 0 0 command register byte 1 msb 0 1 0 1 command register byte 0 lsb 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 offset cal register byte 2 msb 1 0 0 1 offset cal register byte 1 1 0 1 0 offset cal register byte 0 lsb 1 0 1 1 reserved 1 1 0 0 full-scale cal register byte 2 msb 1 1 0 1 full-scale cal register byte 1 1 1 1 0 full-scale cal register byte 0 lsb 1 1 1 1 reserved table iii. a3 - a0 addressing. msb byte 1 adpt calpin 1 0 1 0 crst 0 byte 0 lsb 0 clr df disf bd msb md1 md0 table iv. command register. r/w 0 write 1 read mb1 mb0 0 0 1 byte 0 1 2 bytes 1 0 3 bytes dac1221 operation mode, settling mode and data format. the data input register (dir) contains the value for the next conversion. the offset and full-scale calibration reg- isters (ocr and fcr) contain data used for correcting the internal conversion value after it is placed into the dir. the data in these two registers may be the result of a calibration routine, or they may be values which have been written directly via the serial interface. instruction register (insr) each serial communication starts with the 8 bits of insr being sent to the dac1221. the read/write bit, the number of bytes (n), and the starting register address are defined in table ii. when the n bytes have been transferred, the instruction is complete. a new communication cycle is initiated by sending a new insr (under restrictions outlined in the interfacing section). r/w (read/write) bit for a write operation to occur, this bit of the insr must be 0. for a read, this bit must be 1, as shown: mb1, mb0 (multiple bytes) bits these two bits are used to control the word length (number of bytes) of the read or write operation, as shown: a3 C a0 (address) bits these four bits select the begin- ning register location that will be read from or written to, as shown in table iii. each subsequent byte will be read from or written to the next higher location (increment address). if the bd bit in the command register is set, each subsequent byte will be read from or written to the next lower location (decrement address). this bit does not affect insr register or the write operation for the cmr register. if the next location is reserved in table iii, the results are unknown. reading or writing continues until the number of bytes specified by mb1 and mb0 have been transferred. command register (cmr) the cmr controls all of the functionality of the dac1221. the new configuration is latched in on the negative transi- tion of sclk for the last bit of the last byte of data being written to the command register. the organization of the cmr is comprised of 16 bits of information in 2 bytes of 8 bits each. adpt (adaptive filter disable) bit the adpt bit de- termines if the adaptive filter is enabled or disabled. when the adaptive filter is enabled, the dac1221 does fast settling only when there is an output step of larger than ? 40mv. for small changes in the data, fast settling is not necessary. when adpt = 1, the adaptive filter is disabled and the dac1221 will not look at the size of a step to determine the necessity of using fast settling. in either case, fast settling can be defeated if disf = 1. adpt 0 enabled (default) 1 disabled
9 dac1221 calpin (calibration pin) bit the calpin bit deter- mines if the output is isolated or connected during calibration. crst 0 off (default) 1 reset crst (calibration reset) bit the crst bit resets the offset and full-scale calibration registers, as shown: offset two's straight complement binary v out df = 0 df = 1 (default) 8000 0000 0 0000 8000 v ref 7fff ffff 2 ? v ref input code disf (disable fast settling) bit the disf bit disables the fast settling option. if this bit is zero the fast settling performance is determined by the adpt bit. disf 0 fast settling (default) 1 disable fast settling bd (byte order) bit the bd bit controls the order in which bytes of data are transferred (either most significant byte first (msbf) or least significant byte first (lsbf)), as shown: bd bit: 0 (default) 1 0 (default) 1 register insr write only write only msbf msbf cmr msbf lsbf msbf msbf dir msbf lsbf msbf lsbf ocr msbf lsbf msbf lsbf fcr msbf lsbf msbf lsbf read write care must be observed in reading the command register if the state of the bd bit is unknown. if a two byte read is started at address 0100 with bd = 0, it will read 0100, then 0101. however, if bd = 1, it will read 0100, then 0011. if the bd bit is unknown, all reads of the command register are best performed as read commands of one byte. msb (bit order) bit the msb bit controls the order in which bits within a byte of data are read or written (either most significant bit first or least significant bit first), as follows: md1 md0 0 0 normal mode 0 1 self-cal 1 0 sleep (default) 1 1 reserved msb 0 msb first (default) 1 lsb first md1 C md0 (operating mode) bits the operating mode bits control the calibration functions of the dac1221. the normal mode is used to perform conversions. the self- calibration mode is a one-step calibration sequence that calibrates both the offset and full scale. offset calibration register (ocr) the ocr is a 24-bit register containing the offset correction factor that is used to apply a correction to the digital input before it is transferred to the modulator. the results of the self-calibration process will be written to this register. the ocr is both readable and writable via the serial inter- face. for applications requiring a more accurate calibration, a calibration can be performed, the results averaged, and a more precise offset calibration value written back to the ocr. the actual ocr value will change from part to part and with configuration, temperature, and power supply. in addition, be aware that the contents of the ocr are not used to directly correct the digital input. rather, the correc- tion is a function of the ocr value. this function is linear and two known points can be used as a basis for interpolat- ing intermediate values for the ocr. the results of calibration are averaged, offset two's comple- ment adjusted, and placed in the ocr. calpin 0 output isolated (default) 1 output connected clr (clear) bit the clr bit synchronously resets the data input register to zero. the analog output will be based on the df bitif 1, the output will be 0v; if 0, the output will be v ref . df (data format) bit the df bit controls the format of the input data, shown in hexadecimal (either offset twos complement or straight binary), as shown: msb byte 2 ocr23 ocr22 ocr21 ocr20 ocr19 ocr18 ocr17 ocr16 byte 1 ocr15 ocr14 ocr13 ocr12 ocr11 ocr10 ocr9 ocr8 byte 0 lsb ocr7 ocr6 ocr5 ocr4 ocr3 ocr2 ocr1 ocr0 table v. offset calibration register.
10 dac1221 msb byte 2 fcr23 fcr22 fcr21 fcr20 fcr19 fcr18 fcr17 fcr16 byte 1 fcr15 fcr14 fcr13 fcr12 fcr11 fcr10 fcr9 fcr8 byte 0 lsb fcr7 fcr6 fcr5 fcr4 fcr3 fcr2 fcr1 fcr0 table vi. full-scale calibration register. msb byte 1 dir15 dir14 dir13 dir12 dir11 dir10 dir9 dir8 byte 0 lsb dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 table vii. data input register. full-scale calibration register (fcr) the fcr is a 24-bit register which contains the full-scale correction factor that is applied to the digital input before it is transferred to the modulator. the contents of this register will be the result of a self-calibration, or written to by the user. the fcr is both readable and writable via the serial inter- face. for applications requiring a more accurate calibration, a calibration can be performed, the results averaged, and a more precise value written back to the fcr. the actual fcr value will change from part to part and with configuration, temperature, and power supply. in addition, be aware that the contents of the fcr are not used to directly correct the digital input. rather, the correc- tion is a function of the fcr value. this function is linear and two known points can be used as a basis of interpolating intermediate values for the fcr. the contents of the fcr are in unsigned binary format. this is not affected by the df bit in the command register. data input register (dir) the dir is a 16-bit register which contains the digital input value (see table vii). the register is latched on the falling edge of the last bit of the last byte sent. the contents of the dir are then loaded into the modulator. this means that the dir register can be updated after sending 1 or 2 bytes, which is determined by the mb1 and mb0 bits in the instruction register. the contents of the dir can be offset twos complement or straight binary. sleep mode the sleep mode is entered after the bit combination 10 has been written to the cmr operation mode bits (md1 and md0). this mode ends when these bits are changed to a value other than 10. communication with the dac1221 can continue during sleep mode. when a new mode (other than sleep) has been entered, the dac1221 will execute a very brief internal power-up sequence of the analog and digital circuitry. in addition, the settling of the external v ref and other circuitry must be taken into account to determine the amount of time required to resume normal operation. once serial communication is resumed, the sleep mode is exited by changing the md1 - md0 bits to any other mode. when a new mode (other than sleep) has been entered, the dac1221 will execute a very brief internal power-up se- quence of the analog and digital circuitry. in addition, the settling of the external v ref and other circuitry must be taken into account to determine the amount of time required to resume normal operation. serial interface the dac1221 includes a flexible serial interface which can be connected to microcontrollers and digital signal proces- sors in a variety of ways. along with this flexibility, there is also a good deal of complexity. this section describes the trade-offs between the different types of interfacing methods in a top-down approachstarting with the overall flow and control of serial data, moving to specific interface examples, and then providing information on various issues related to the serial interface. reset, power-on reset and brown-out the dac1221 contains an internal power-on reset circuit. if the power supply ramp rate is greater than 50mv/ms, this circuit will be adequate to ensure the device powers up correctly. due to oscillator settling considerations, commu- nication to and from the dac1221 should not occur for at least 25ms after power is stable. if this requirement cannot be met or if the circuit has brown- out considerations, the timing diagram of figure 3 can be used to reset the dac1221. this accomplishes the reset by controlling the duty cycle of the sclk input. sleep mode is the default state after power on or reset. the output is high impedance during sleep mode.
11 dac1221 t 1 t 3 t 4 t 2 t 2 sclk reset on falling edge figure 3. resetting the dac1221. t 1 : > 512 ? t xin < 800 ? t xin t 2 : > 10 ? t xin t 3 : > 1024 ? t xin < 1800 ? t xin t 4 : 3 2048 ? t xin < 2400 ? t xin i/o recovery if serial communication stops during an instruction or data transfer for longer than 100ms (for f xin = 2.5mhz), the dac1221 will reset its serial interface. this will not affect the internal registers. the main controller must not continue the transfer after this event, but must restart the transfer from the beginning. this feature is very useful if the main control- ler can be reset at any point. after reset, simply wait 200ms (for f xin = 2.5mhz) before starting serial communication. isolation the serial interface of the dac1221 provides for simple isolation methods. an example of an isolated two-wire interface is shown in figure 4. using cs the serial interface may make use of the cs signal, or this input may simply be tied low. there are several issues associated with choosing to do one or the other. the cs signal does not directly control the tri-state condition of the sdio output. these signals are normally in the tri-state condition. they only become active when serial data is being transmitted from the dac1221. if the dac1221 is in the middle of a serial transfer and the sdio is an output, taking cs high will not tri-state the output signal. if there are multiple serial peripherals utilizing the same serial i/o lines and communication may occur with any peripheral at any time, the cs signal must be used. the cs signal is then used to enable communication with the dac1221. timing the maximum serial clock frequency cannot exceed the dac1221 x in frequency divided by 10. table viii and figures 5 through 9 define the basic digital timing character- istics of the dac1221. figure 5 and the associated timing symbols apply to the x in input signal. figures 6 through 9 and associated timing symbols apply to the serial interface signals (sclk, sdio, and cs). the serial interface is discussed in detail in the serial interface section. 1 2 3 4 5 6 7 8 dv dd x out x in dgnd av dd dnc c 3 c 2b sclk sdio cs agnd v ref v out c 2a c 1 16 15 14 13 12 11 10 9 dac1221 c 1x 5.6pf c 2x 5.6pf av dd xtal v ref dv dd p1.1 p1.0 8051 opto coupler opto coupler isolated power c 2 c 3 c 1 = dgnd = agnd = isolated figure 4. isolation for two-wire interface.
12 dac1221 symbol description min nom max units f xin x in clock frequency 1 2.5 mhz t xin x in clock period 400 1000 ns t 1 x in clock high 0.4 ? t xin ns t 2 x in clock low 0.4 ? t xin ns t 3 sclk high 5 ? t xin ns t 4 sclk low 5 ? t xin ns t 5 data in valid to sclk falling edge (setup) 40 ns t 6 sclk falling edge to data in not valid (hold) 20 ns t 7 data out valid after rising edge of sclk (hold) 0 ns t 8 sclk rising edge to new data out valid (delay) (1) 50 ns t 9 falling edge of last sclk for insr to rising edge of first 13 ? t xin ns sclk for register data ns t 10 falling edge of cs to rising edge of sclk 11 ? t xin ns t 11 falling edge of last sclk for insr to sdio as output 8 ? t xin 10 ? t xin ns t 12 sdio as output to rising edge of first sclk for register data 4 ? t xin ns t 13 falling edge of last sclk for register data to sdio tri-state 4 ? t xin 6 ? t xin ns t 14 falling edge of last sclk for register data to rising edge 41 ? t xin ns of first sclk of next insr (cs tied low) t 15 rising edge of cs to falling edge of cs (using cs) 22 ? t xin ns note: (1) with 10pf load. table viii. digital timing characteristics. t xin t 1 x in t 2 t 3 t 4 t 5 t 7 t 6 t 8 sclk sdio t 14 t 9 in7 in0 in1 inm in1 in0 in7 write register data in7 out0 out1 outm in1 in0 in7 read register data sclk sdio sdio cs sclk sdio t 15 t 10 in7 in0 in1 in0 in1 in7 inm t 10 t 9 write register data sdio in7 out0 out1 in0 in1 in7 outm read register data figure 5. x in clock timing. figure 6. serial input/output timing. figure 7. serial interface timing (cs always low). figure 8. serial interface timing (using cs).
13 dac1221 out msb out0 t 12 t 10 t 9 sdio is an input sdio is an output in7 t 13 t 11 in0 cs sclk sdio start writing start reading external device generates 8 serial clock cycles and transmits instruction register data via sdio cs taken high for t 15 periods minimum (or cs tied low) external device generates n serial clock cycles and transmits specified register data via sdio cs state more instructions? end high yes no low no is next instruction a read? yes cs state from read flowchart high low to read flowchart external device generates 8 serial clock cycles and transmits instruction register data via sdio sdio input to output transition cs state more instructions? end high yes no low no is next instruction a write? yes cs state to write flowchart high low to write flowchart external device generates n serial clock cycles and receives specified register data via sdio sdio transitions to tri-state condition cs taken high for t 15 periods minimum (or cs tied low) figure 9. sdio input to output transition timing. figure 10. flowchart for writing and reading register data.
14 dac1221 layout power supplies the dac1221 requires the digital supply (dv dd ) to be no greater than the analog supply (av dd ) +0.3v. in the majority of systems, this means that the analog supply must come up first, followed by the digital supply and v ref . failure to observe this condition could cause permanent damage to the dac1221. inputs to the dac1221, such as sdio or v ref , should not be present before the analog and digital supplies are on. violating this condition could cause latch-up. if these sig- nals are present before the supplies are on, series resistors should be used to limit the input current. the best scheme is to power the analog section of the design and av dd of the dac1221 from one +3v supply, and the digital section (and dv dd ) from a separate +3v supply. the analog supply should come up first. this will ensure that sclk, sdio, cs and v ref do not exceed av dd , that the digital inputs are present only after av dd has been estab- lished, and that they do not exceed dv dd . the analog supply should be well regulated and low noise. for designs requiring very high resolution from the dac1221, power supply rejection will be a concern. see the psrr vs frequency curve in the typical performance curves sec- tion of this data sheet for more information. the requirements for the digital supply are not as strict. however, high frequency noise on dv dd can capacitively couple into the analog portion of the dac1221. this noise can originate from switching power supplies, very fast microprocessors, or digital signal processors. if one supply must be used to power the dac1221, the av dd supply should be used to power dv dd . this connec- tion can be made via a 10 w resistor which, along with the decoupling capacitors, will provide some filtering between dv dd and av dd . in some systems, a direct connection can be made. experimentation may be the best way to determine the appropriate connection between av dd and dv dd . grounding the analog and digital sections of the design should be carefully and cleanly partitioned. each section should have its own ground plane with no overlap between them. agnd should be connected to the analog ground plane, as well as all other analog grounds. dgnd should be connected to the digital ground plane, and all digital signals referenced to this plane. the dac1221 pinout is such that the converter is cleanly separated into an analog and digital portion. this should allow simple layout of the analog and digital sections of the design. for a single converter system, agnd and dgnd of the dac1221 should be connected together, underneath the converter. do not join the ground planes. instead, connect the two with a moderate signal trace. for multiple convert- ers, connect the two ground planes at one location, as central to all of the converters as possible. in some cases, experi- mentation may be required to find the best point to connect the two planes together. the printed circuit board can be designed to provide different analog/digital ground connec- tions via short jumpers. the initial prototype can be used to establish which connection works best. decoupling good decoupling practices should be used for the dac1221 and for all components in the design. all decoupling capaci- tors, and specifically the 0.1 m f ceramic capacitors, should be placed as close as possible to the pin being decoupled. a 1 m f to 10 m f capacitor, in parallel with a 0.1 m f ceramic capacitor, should be used to decouple av dd to agnd. at a minimum, a 0.1 m f ceramic capacitor should be used to decouple dv dd to dgnd, as well as for the digital supply on each digital component.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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