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advanced panel-2 v ideo graphic array TP6508 topro technology incorporation specification version: 2.1 revision: 2.02 1999/11/25 topro
ii revision history revision date . comment . 2.02 88.04.12 change for topro version . 2.1 88.10.13 update sreg ce bit-3 register description . update 'active' & 'function' descriptions of fpvcc , fpvee , fpback pins in pin descriptions chapter . update "lcd panel power sequencing" in function descriptions chapter .
iii TP6508 target spec. list revision history ............................................................................................................... ii i. general description .................................................................................................... 1 ii. feature .................................................................................................................... ... 3 iii. pin configurations ................................................................................................... 5 isa bus interface connections .................................................................................................. ........... 5 pci local bus interface connections ............................................................................................ ....... 6 iv. functional block diagram ....................................................................................... 7 system block diagram ........................................................................................................... .............. 7 vga block diagram .............................................................................................................. .............. 8 true-color palette dac block diagram ........................................................................................... ... 9 dual frequency synthesizer block diagram ....................................................................................... 10 panel controller block diagram ................................................................................................. ....... 11 graphics engine diagram ........................................................................................................ ........... 12 memory configuration block diagram ..................................................................... 13 v. pin descriptions ........................................................................................................ 15 vi. function descriptions ............................................................................................ 26 host bus interface ............................................................................................................. ................. 26 sequencer controller (seqc) .................................................................................................... ........ 26 crt controller (crtc) .......................................................................................................... ........... 26 attribute controller (atc) ..................................................................................................... ............ 27 graphics controller (gfxc) ..................................................................................................... ......... 27 address multiplexer (amux) ..................................................................................................... ...... 27 crt fifo (display fifo) ........................................................................................................ ......... 28 attribute fifo ................................................................................................................. ................... 28 write buffer ................................................................................................................... ..................... 28 dual frequency synthesizer ..................................................................................................... ........... 28 true-color palette dac (tdac) .................................................................................................. .... 29 graphics engine controller (gec) ............................................................................................... ..... 29 command fifo ............................................................................................................................... ... 32 hardware cursor controller ..................................................................................................... ......... 32 pc video controller ............................................................................................................ ............... 33 lcd line buffer ............................................................................................................................... .. 33 panel controller ............................................................................................................... .................. 34 power management controller (p.m.c.) ........................................................................................... .39 vii. registers ................................................................................................................ 4 2 ibm standard register .......................................................................................................... ............. 42 backward compatible register description ...................................................................................... 4 8 extended sequencer register description ........................................................................................ .. 51 extended crtc register description ............................................................................................. ... 64 panel control register description ............................................................................................. ....... 67 pci local bus configuration register description ............................................................................ 80 graphics engine control register description ................................................................................... 85
iv viii. absolute maximum rating ................................................................................ 96 ix. dc electrical characteristic ................................................................................. 97 dc characteristics ............................................................................................................. ................ 97 dac characteristics ............................................................................................................ ............... 98 dc drive characteristics ....................................................................................................... ............ 98 x. ac electrical characteristic ................................................................................... 99 bios rom interface timing spec. ................................................................................................ ... 99 isa bus interface timing spec. ................................................................................................. ..... 100 pci local bus interface timing spec. ........................................................................................... . 101 memory bus interface timing spec. .............................................................................................. . 102 color-key pc video & vafc interface timing ............................................................................... 104 ramdac & feature connector interface timing ........................................................................... 104 xi. timing diagrams .................................................................................................. 105 bios rom read cycle ............................................................................................................ ........ 105 isa bus interface timing .................................................................................................................. 106 pci local bus interface timing (32-bit data bus) ............................................................................ 107 16-bit txt crt cycle ........................................................................................................... ......... 108 16-bit cpu/gfx crt/shadow frame buffer cycle ....................................................................... 109 32-bit txt crt cycle ........................................................................................................... ......... 110 32-bit cpu/gfx crt/shadow frame buffer cycle ........................................................................ 111 16-bit read-modify-write cycle ................................................................................................. .... 112 32-bit read-modify-write cycle ................................................................................................. .... 113 refresh cycle cycle(cas before ras) .......................................................................................... 11 4 external frame buffer interface timing (16-bit) .............................................................................. 11 5 ramdac & feature connector interface timing ........................................................................... 116 color-key pc video & vafc interface timing ............................................................................... 117 xii. appendix .............................................................................................................. 118 a. monitor specification ....................................................................................................... ........... 118 b. TP6508 vga modes ............................................................................................................ ....... 119 c. rast operation code list .................................................................................................... ......... 121 d. memory address table ........................................................................................................ ....... 124 e. mclk & vclk frequency programming table.......................................................................... 129 f. pins selection configuration................................................................................................ ......... 131
p.1 i. general description the TP6508 is an advanced single-chip flat panel vga controller . it's used for notebook or portable computer system with simple operation and powerful features. also it contains all of the functions and supports logic required to implement the ibm vga display standards and enhanced display modes on lcd, plasma,el panel and tv display at register and bios level compatiable. a simultaneous display technology is implemented in TP6508 to be used for crt/flat panel, lcd/ tv display. for minimum chip-count or board-space, it is designed to complete a video subsystem with only one 256kx16 dram(512k bytes). this video subsystem can support all panel type without any glue logic or external frame buffer. like general vga graphics chips, the TP6508 includes crt controller (crtc), attribute con- troller (atrc), graphic controller (gfxc), address multiplexer (amux) , sequential controller (seqc) and adds a graphics engine controller (gec) to provide vga display functions and to speed up the system operation. with the deeper crt fifo , and the multiple level cpu command fifo (write buffer) / read cache , the TP6508 supports higher system performance even in minimum memory configurations. in order to complete a video subsystem by two chips, vga controller and dram, the TP6508 uses 208pin qfp to integrate clock generator(dual frequency synthesizers), true-color ramdac, display controller, flat panel controller, video-in interface, graphics engine controller and power management controller to minimizes the form factor requirement for vga subsystem. in addition to an isa bus connection, it can be connected directly to pci standard local bus interface to provide additional graphics performance without any glue logic. TP6508 can support flat panel display, resolution up to 1024x768 mono, 800x600 hi-color, 640x480 true-color. unlike on crt, the pixels on a flat panel display are real,discrete entities of a fixed size. this results in problems when different display modes are mapped onto one panel. the TP6508 provides approach to keep the vertical resolution of the display mode constant but center the active display area vertically on the panel. the flat panel interface supports monochrome/color stn lcd panel, color tft lcd panel, plasma panel and, el panel. providing direct panel interface to (dd) dual-panel,dual-drive for color and monochrome and (ss) single-panel,single-drive (supports 8,9,12,15,16,18,24-bit data). for single-panel/single-drive panel which refresh data rate is not high, the TP6508 can set some of the video memory as the frame buffer for panel display to decrease video memory chip counts to one (a 256kx16dram).
p.2 when the TP6508 is interfaced to a dual-scan mono stn lcd panel , an additional dram isn't needed with the shadow frame buffer technology . this shadow frame buffer build in video memory that is used by the chipset to accelerate panel refresh rate without using high frequency clocks , thus reducing power, and allowing vertical refresh rates from 60 hz to 160 hz for improved contrast and freedom from flicker. the TP6508 serves as a dram controller for the display memory,it handle dram refresh, display refresh, display memory access by cpu and supply the control signal of dram with dual- write or dual-cas. the TP6508 offers two types dram to make various memory configurations including of 512k , 1024k , 2048k memory size for different market. TP6508 support 256k x 4-bit , or 256k x 16-bit dram memory to simplify vga system and implement high resolution display simultaneously. with random memory cycle allocation skill and the multiple level cpu write buffer, the TP6508 provide better system performance and achieve zero wait state during memory write accesses. when using dram 256kx16 by 1 or dram 256kx4 by 4, memory size is 512k byte and data width is 16 bits. when using 256kx16 by 2 or 256kx4 by 8, memory size is 1m byte and data size is 32 bits. TP6508 can support the crt display resolution up to 1024x768 256 color non-interlace, 800x600 hi-color,640x480 true color at 1m byte display memory. when using 256kx16 by 4 , memory size is 2m byte and data size is 32 bits. all display-memory can be linear addressing. the video-in interface accept video signal from pc-video. providing the power sequential control for flat panel . fpvcc signal is applied to the digital +5v voltage of flat panel, fpvee signal is applied to the analog driver's bias voltage of flat panel, and fpback signal is applied to the invertor for the backlight of flat panel, their on/off sequence is programmable. anotherway TP6508 providing intelligent control by timer to switch power mode (on including cover-close,standby,suspend,off) to save the power of TP6508 and display. the TP6508 graphics chip has been designed to optimize cost/performance trade-off consider- ations. the video clock rate depends upon the mode used, and is up to 135 mhz. the memory clock input is optional and depends on the display drams access-time . it can be up to 75 mhz.
p.3 ii. feature . 208-pin single chip design . ibm vga hardware compatible . integrates ramdac - support 24-bit true-color resolution - up to 135 mhz pixel rate - low power control - implement monitor-sense feature . integrates clock generator - programmable dual frequency synthesizer - up to 135 mhz clock rate for vclk synthesier - up to 75 mhz clock rate for mclk synthesier - external power-down mode clock source optional . memory dram configuration support - support symmetric or asymmetric ras/cas address dram - support dual-cas or dual-we addressing dram - 512k bytes memory:four 256kx4-bit /one 256kx16-bit - 1m bytes memory:eigh 256kx4-bit /two 256kx16-bit - 2m bytes memory:sixteen 256kx4-bit/four 256kx16-bit . bus support - isa bus with zero-wait state assertion - 32-bit data width pci local bus . provide linear addressing - relocation vga memory address at over 1m-byte address location . integrates stn panel support - support dual/single scan mono stn lcd panel, up to 64 simultaneous grays - support dual/single scan color stn lcd panel up to 64k simultaneous colors, and 61 3 visual color - provide 8 and 16 bit panel interfaces . integrates color tft panel support - support normal or crt-like tft lcd panel - support 9/12/15 or 18/24 bit panel interface, and up to 16.8m simultaneous colors . support panel resolution up to 800x600 for stn and tft lcd flat panel . simultaneous display operation - simultaneous lcd and crt display - simultaneous plasma and crt display - simultaneous el and crt display - simultaneous lcd and tv display . vga bios decoding - provide 64k-byte or 32k-byte vga bios decoding
p.4 . dual-scan stn frame buffer - shadow frame buffer onto display memory for mono or color lcd panel - pseudo frame buffer for color lcd panel (no additional drams required) - external frame buffer for color lcd panel (external additional drams required) . provide pc video interface - provide vesa advanced feature connector(vafc) interface - provide color-key pc video interface . high performance architecture - provide 4 stages cpu write buffer - provide 8 stages command fifo for graphics engine access - offer 20 stages crt fifo and 8 stages attribute fifo . integrates hardware cursor function - 64 by 64 pixels (2-bit) - offer color 0,1,inversion and transparency operation . windows performance-improvement feature - bit block transfer (8/16/24 bit color mode) including of image read/write - color expansion (8/16/24 bit mode) - line drawing (8/16/24 bit mode) - rectangular clipping (8/16/24 bit mode) - rectangular fill and pattern fill(8/16/24 bit mode) . graphics engine i/o command addressing - programmable i/o base command - memory mapping i/o command . intelligent power management - built-in power management controller - multiple level power down modes (on/standby/suspend/off mode) - automatic activity monitoring - flexible mode transition control (pin control/timer out/register programming /vga access and keyboard request trigger return) - automatic flat panel power sequencing - programmable slow refresh rate . enhanced mode includes: - 132x25 or 132x44 text mode - 640x480/256 colors (windows acceleration mode support optional) - 640x480/65536 colors (windows acceleration mode support optional) - 640x480/16.8m colors (windows acceleration mode support optional) - 800x600/16 colors - 800x600/256 colors (windows acceleration mode support optional) - 800x600/65536 colors (windows acceleration mode support optional) - 800x600/16.8m colors - 1024x768/16 colors - 1024x768/256 colors (windows acceleration mode support optional) - 1024x768/65536 colors (windows acceleration mode support optional) - 1280x1024/16 colors - 1280x1024/256 colors (windows acceleration mode support optional) - 1600x1280/16 colors interlace display mode
p.5 iii. pin configurations isa bus interface connections 157 158 159 wea*/weah* casah*/casa* mvdda vp14/cascl*/wecl*/vr6 vp15/casch*/casc*/vr7 wec*/wech*/pclk 102 103 104 90 91 92 93 94 95 96 97 98 99 100 101 ca0/p16 ca1/p17 ca2/p18 ca3/p19 ca4/p20 ca5/p21 ca6/p22 ca7/p23 ca8/vg1 ca9/vg0 vrdy/rasc*/key vclk/oec*/vr1 160 161 162 163 164 165 166 167 168 169 170 171 casal*/weal* mad0 mad1 mad2 mad3 mad4 mad5 mad6 mad7 mad8 mad9 mvssa 172 173 174 175 176 177 178 179 180 181 182 183 mad10 mad11 mad12 mad13 mad14 mad15 cvdd2 sa2 sa3 sa4 sa5 off/exvclk/eprom* dvss2 cvdd1 78 79 80 81 82 83 84 85 86 87 88 89 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 67 68 69 70 71 72 73 74 75 76 77 p0 p1 p2 p3 p4 p5 m lp flm shfclk cvss1 184 185 186 187 188 189 190 191 192 193 194 cvss2 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 195 196 197 198 199 200 201 202 203 204 205 206 xtalo avss2 avdd2 avdd3 sa16 la17 la18 la19 la20 la21 la22 xtali/exmclk/osc vsync dvdd avss1 dvss1 avdd1 fpvcc fpvee/fpback red green blue hsync 55 56 57 58 59 60 61 62 63 64 65 66 rset 53 54 acti/vb0 fpback/vb1 207 208 avss3 reset 123456789 s d 0 s d 2 s d 3 s d 4 s d 1 s d 5 s d 7 s d 6 s a 0 b v d d 2 s d 8 s d 9 b v s s 3 s d 1 0 s d 1 1 s d 1 2 s d 1 3 s d 1 4 s d 1 5 s b h e * a e n i r q r o m c s * l a 2 3 i o r d * b v s s 2 i o w r * i o r d y* * m e m w * a l e s a 1 o w s n c b v d d 1 r e f * m e m r * b v s s 1 n c n c n c n c n c i o c s 1 6 * n c n c n c n c n c n c n c r a s a * o e a b * a a 9 / v r 0 a a 8 / c f g 8 / l v # a a 7 / c f g 7 / t s # a a 6 / c f g 6 / a d # a a 5 / c f g 5 / o s # a a 4 / c f g 4 / e c # a a 3 / c f g 3 / r c # a a 2 / c f g 2 / 2 x # a a 1 / c f g 1 / i s a # a a 0 / c f g 0 / l b # m b d 1 5 m b d 1 4 m v d d b m b d 1 3 m b d 1 2 m v s s b m b d 1 1 m b d 1 0 m b d 9 m b d 8 m b d 7 m b d 6 m b d 5 m b d 4 m b d 3 m b d 2 m b d 1 m b d 0 c a s b l * / w e b l * c a s b h * / c a s b * w e b * / w e b h * m v s s c r a s b * m c d 0 / v b 2 / e v i d # m c d 1 5 / v r 5 / v p 1 3 m c d 1 4 / v r 4 / v p 1 2 m c d 1 3 / v r 3 / v p 1 1 m c d 1 2 / v r 2 / g r d y m c d 1 1 / v g 7 / v p 1 0 m c d 1 0 / v g 6 / v p 9 m c d 9 / v g 5 / v p 8 m c d 7 / v g 3 / v p 6 m c d 6 / v g 2 / v p 5 m c d 8 / v g 4 / v p 7 m c d 5 / v b 7 / v p 4 m c d 4 / v b 6 / v p 3 m c d 3 / v b 5 / v p 2 m c d 2 / v b 4 / v p 1 m v d d c m c d 1 / v b 3 / v p 0 b v s s 4 m e m c s 1 6 * 1 5 6 1 5 5 1 5 4 5 2 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 2 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 9 2 8 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 1 5 3 1 5 2 1 5 1 1 5 0 1 4 9 1 4 8 1 4 7 1 4 6 1 1 0 1 0 5 1 4 5 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 1 8 1 1 9 1 2 0 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 0 9 1 0 8 1 0 7 1 0 6 TP6508
p.6 pci local bus interface connections 157 158 159 wea*/weah* casah*/casa* mvdda vp14/cascl*/wecl*/vr6 vp15/casch*/casc*/vr7 wec*/wech*/pclk 102 103 104 90 91 92 93 94 95 96 97 98 99 100 101 ca0/p16 ca1/p17 ca2/p18 ca3/p19 ca4/p20 ca5/p21 ca6/p22 ca7/p23 ca8/vg1 ca9/vg0 vrdy/rasc*/key vclk/oec*/vr1 160 161 162 163 164 165 166 167 168 169 170 171 casal*/weal* mad0 mad1 mad2 mad3 mad4 mad5 mad6 mad7 mad8 mvssa 172 173 174 175 176 177 178 179 180 181 182 183 dvss2 cvdd1 78 79 80 81 82 83 84 85 86 87 88 89 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 67 68 69 70 71 72 73 74 75 76 77 p0 p1 p2 p3 p4 p5 m lp flm shfclk cvss1 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 xtalo avss2 avdd2 avdd3 clk xtali/exmclk/osc vsync dvdd avss1 dvss1 avdd1 fpvcc fpvee/fpback red green blue hsync 55 56 57 58 59 60 61 62 63 64 65 66 rset 53 54 acti/vb0 fpback/vb1 207 208 avss3 rst# 123456789 a d 0 a d 2 a d 3 a d 4 a d 1 a d 5 a d 7 a d 6 c b e 0 # b v d d 2 a d 8 a d 9 b v s s 3 a d 1 0 a d 1 1 a d 1 2 a d 1 3 a d 1 4 a d 1 5 c b e 1 # p a r s e r r # p e r r # n c s t o p b v s s 2 d e v s e l # t r d y # i r d y # f r a m e # c b e 2 # a d 2 3 b v d d 1 c b e 3 # i d s e l b v s s 1 a d 3 1 r a s a * o e a b * a a 9 / v r 0 a a 8 / c f g 8 / l v # a a 7 / c f g 7 / t s # a a 6 / c f g 6 / a d # a a 5 / c f g 5 / o s # a a 4 / c f g 4 / e c # a a 3 / c f g 3 / r c # a a 2 / c f g 2 / 2 x # a a 1 / c f g 1 / i s a # a a 0 / c f g 0 / l b # m b d 1 5 m b d 1 4 m v d d b m b d 1 3 m b d 1 2 m v s s b m b d 1 1 m b d 1 0 m b d 9 m b d 8 m b d 7 m b d 6 m b d 5 m b d 4 m b d 3 m b d 2 m b d 1 m b d 0 c a s b l * / w e b l * c a s b h * / c a s b * w e b * / w e b h * m v s s c r a s b * m c d 0 / v b 2 / e v i d # m c d 1 5 / v r 5 / v p 1 3 m c d 1 4 / v r 4 / v p 1 2 m c d 1 3 / v r 3 / v p 1 1 m c d 1 2 / v r 2 / g r d y m c d 1 1 / v g 7 / v p 1 0 m c d 1 0 / v g 6 / v p 9 m c d 9 / v g 5 / v p 8 m c d 7 / v g 3 / v p 6 m c d 6 / v g 2 / v p 5 m c d 8 / v g 4 / v p 7 m c d 5 / v b 7 / v p 4 m c d 4 / v b 6 / v p 3 m c d 3 / v b 5 / v p 2 m c d 2 / v b 4 / v p 1 m v d d c m c d 1 / v b 3 / v p 0 b v s s 4 1 5 6 1 5 5 1 5 4 5 2 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 2 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 9 2 8 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 1 5 3 1 5 2 1 5 1 1 5 0 1 4 9 1 4 8 1 4 7 1 4 6 1 1 0 1 0 5 1 4 5 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 1 8 1 1 9 1 2 0 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 0 9 1 0 8 1 0 7 1 0 6 a d 2 2 a d 2 1 a d 2 0 a d 1 6 a d 3 0 a d 2 4 a d 2 5 a d 2 6 a d 2 7 a d 2 8 a d 2 9 a d 1 7 a d 1 8 a d 1 9 mad9 mad10 mad11 mad12 mad13 mad14 mad15 cvdd2 off/exvclk cvss2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc TP6508
p.7 iv. functional block diagram system block diagram TP6508 display memory 256 x 16bit (512kb/1mb/2mb) 256 x 16bit 256 x 16bit (512kb) tv encoder ntsc/pal system internal built in 1280 x 1024 / 256 , 800 x600 / 16.8m colors flat panel/crt display system internal built-in ture-color dac rgb to ntsc/pal l o g i c h o s t clock generator color/mono lcd/plasma/el panel dram-a dram-b dram-c pc video pc video interface optional frame buffer t v [sp508b05.ds4 86/04/15 l.r.y.] vga monitor isa bus pci bus panel
p.8 vga block diagram crtc.. seq.. graph.. cntl.. panel. cntl.. address.. da ta.. TP6508 da ta.. [sp508b01.ds4 84.08.21] isa/local bus.. attrib.. cntl.. r. . g. . b. . dac.. ture-color.. pallette.. clock. reference. source. flat .. panel.. fifo crt.. display.. c. g.. dual frequency. synthesizer.. amux.. decoder.. vlck.. mclk.. write.. buf.. hsync.. vsync.. 14.318mhz.. md.. ma.. memory.. display.. shadow. frame buffer. 512k dram crt/atrr power. cn tl.. graphics. cntl.. engine. command. fifo. pc video. cntl.. video interface. video processer. mpeg decoder. management. 2mb memory
p.9 t rue-color palette dac block diagram p0-p23 r g b mux mux mux bus control dac dac dac latch 8 24 ( 16/15 ) 8 8 8 8 8 8 8 8 /rd /wr r g b rd0-rd7 cntl sense compare mode control sel 256*18 sram vref pseudo mode hicolor-15tm hicolor-16tm hicolor-24tm gp0-gp23 power controller dacoff msoff [sp508b02.ds4 85/03/11 l.r.y.] pixel read mask reg. address register command register
p.10 dual fr equency synthesizer block diagram mmd0-6 mn0-6 mp mo powerdown feedback divider 1 input divider 1 phase comp 1 charge pump vco 1 /en osc buffer output buf fer input divider 2 phase comp 2 charge pump vco 2 /en output feedback divider 2 input latch 2 vd0-6 vn0-6 xtali xtalo vcl k mcl k 14.318mhz buf fer input latch 1 vclkd vclkn 7 vclkp vp mclkd mclkn mclkp vclko mclko vo divider / 2 divider / 2 vp vo 7 1 1 7 1 1 7 divider / 2 divider / 2 mp mo [sp508b03.ds4 85/03/11 l.r.y.] c.g. power management control
p.11 panel contr oller block diagram line buffer sum to gray d f f d f f d f f amplitute modulator amplitute modulator m u x d f f m u x d f f d f f m u x dither dither dither amplitute modulator dith panel interface display memory (frame buffer) flat panel 1 1 1 fp0-23 6 6 6 6 6 6 rgbi emulation [sp508b04.ds4 85/03/11 l.r.y.] amplitute modulator
p.12 [sp508b12.ds4 85.08.21] line drawing address caculation bit block address address path data path mux. clipping address translation lx(10:0) ly(10:0) bx(10:0) by(10:0) x(10:0) y(10:0) source x source y source x source y destin. x destin. y map enable row adr(9:0) col adr(9:0) pattern x pattern y mux. adr data alignment source fifo host data output mux. 256 rop. pattern fifo md[31:0] sd' [31:0] line drawing color select background color md[31:0] foreground color sd[31:0] md[31:0] graphics engine diagram
p.13 memory configuration block diagram ras0* cas0* md[7:0] cas1* md[15:8] vga dram 512kx8 512kx8 ras0* cas0* md[7:0] ras0* cas1* md[15:8] vga dram cas2* cas3* md[23:16] md[31:24] vga dram 256kx16 512 k memory dram(s) configuration 1024k memory dram(s) configuration b. c. [sp508b06.ds4 84/05/23] ras0* cas0* cas1* md[7:0] md[15:8] 256kx16 ras0* cas0* m0d[15:0] ras0* cas2* md[31:16] vga dram cas1* cas3* a. 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4
p.14 2048k memory dram(s) config uration ras0* cas0* md[15:0] ras0* cas2* md[31:16] vga dram cas1* cas3* a. ras0* cas0* cas1* md[15:0] ras0* cas2* cas3* md[31:16] vga dram 512kx8 512kx8 cas2* cas3* md[31:16] vga dram 256kx16 b. c. ras0* cas0* cas1* md[15:0] 256kx16 ras1* 512kx8 512kx8 256kx16 256kx16 ras1* [sp508b06.ds4 84/05/23] 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4 256kx4
p15 v. pin descriptions sd[15:0] i/o 8mar sa[16:2] i (i/o) - sa[1:0] i la[23:22] i - a21 i (i/o) a20 i la[19:17] i (i/o) aen i - (i/o) ale i - sbhe* i - iord* i - (i/o) iowr* i - (i/o) memr* i - memw* i - iordy* ot 12mar iocs16* ot 12mar (i/o) memcs16* ot 12mar (i/o) reset* i/s - irq ot 8mar (i/o) ref* i - ows* ot 8mar (i/o) 33,34,35,36,37 38,40,41,44,45 46,47,48,49,50,51 195,194,193,192,191, 190,189,188,187,186, 185,183,182,180,179, 21,43 28,201,200,199,198, 197,196 31 22 32 27 25 11 23 24 18 19 207 30 10 20 true true true high high low low low low low low low low low low low low these signals provide 16 data bits transfer on isa bus with system microprocessor. address bit 16 through 0 are used to address frame buffer and i/o ports with TP6508. address bit 23 through 17 are used to address frame buffer and i/o ports with TP6508. in general ,these signals are not gated address la[19:17] a high active signal used to detect the TP6508 from the i/o channel to avoid a disturbance from the dma controller. this signal is used to latch those ungated ad- dress bus. it indicates and enables transfer of data on the high byte of data bus and is used with a0 to dis- tinguish between high and low byte. i/o read signal comes from a host micropro- cessor to read data from TP6508 control. i/o write signal comes from a host micropro- cessor to read data from TP6508 control regis- ters. memory read signal comes from a host microprocessor to read data from video memory. memory write signal comes from a host microprocessor to read data from video memory. this signal is driven low by TP6508 to lengthen the memory or i/o accessed cycle. this signal is driven low to indicate that the TP6508 can execute an i/o operation at the ad- dress currently on the 16-bit bus mode. this signal drives a 16-bit memory cycle for 16-bit bus data transfer. this pin is connected to the signal that was in- verted from the system board to reset the TP6508. the vertical retrace interrupt. this signal is driven by system mother board logic and is used to indicate a memory refresh cycle is in operation. this signal is driven by TP6508 to short the memory accessed cycle for improving system performance. * isa bus interface (54 pins) symble type drive pin number active function
p16 ad[31:0] i/o 8mar c/be[3:0]# i - par ot 4mar (i/o) frame# i - trdy# ot 12mar irdy# i - idsel i - reset# i/s - clk i - devsel# ot 12mar (i/o) stop# ot 4mar (i/o) perr# o/t 8mar (i/o) serr# o/t 8mar (i/o) 1,2,3,4,5, 6,7,8,13,14, 15,16,17,18,19,20, 33,34,35,36,37 38,40,41,44,45 46,47,48,49,50,51 10,21,32,43 31 22 24 23 11 207 201 25 27 29 30 true true true low low low high low true low low low low address and data are multiplexed on the same pci bus interface. a bus transaction consists of an address phase followed by one or more data phase. bus command and byte enable are multiplexed on the same pci bus interface. during the ad- dress phase of a transaction, they define the bus command. during the data phase , they are used as byte enable. parity is even part across ad[31:0] and c/be[3:0]#. parity generation is required by all pci agents. this input signal is used to indicate the beginning and duration of an access. this signal is driven to indicate TP6508's abil- ity to complete the current data phase. it is used in conjunction with irdy#. this input signal is to indicate bus master's abil- ity to complete the current data phase. it is used in conjunction with trdy#. this signal is used as a chip select during con- figuration read and write access. this signal is used to reset the TP6508 video device into initial state. this is the timing reference for TP6508 when connected to pci local bus. this signal is driven to indicate that TP6508 video device has been selected . so TP6508 has decoded its address as the target of the current access. this signal is output to indicate that TP6508 is requesting the master to stop the current trans- action. this signal is used for the reporting of data par- ity erros. perr# will be driven high for one clock before being tristated as with all sustained tristate signals. this signal is used for the reporting of system erros. * pci local bus interface ( 48 pins ) symble type drive pin number active function
p17 * display memory interface (82 pins) symble type drive pin number active function aa9 i/o 4mar aa[8:0] i/o/u 4mar ca[9:8] i/o 4mar ca[7:0] o 4mar mad[15:0] i/o/u 4mar mbd[15:0] i/o 4mar mcd[15:0] i/o 4mar rasa* o 4mar rasb* o 4mar rasc* i/o 4mar casal*/weal* o 4mar casah*/casa* o 4mar casbl*/webl* o 4mar casbh*/casb* o 4mar cascl*/weal*i/o 4mar casch*/casc* i/o 4mar wea*/weah* o 4mar web*/webh* o 4mar wec*/wech* o 4mar oeab* o 8mar oec* i/o 4mar true true true true true low low low low low low low low low low low low low low display memory address bit 9 to 0 for drams a and b. a pull-high mechanism gives a default high value in those configuration data. display memory address bit 9 to 0 for drams c. these pins are used to transfer data between the TP6508 and display memory, dram a. a pull- high mechanism gives a default high value in those configuration data. these pins are used to transfer data between the TP6508 and display memory, dram b. these pins are used to transfer data between the TP6508 and frame buffer memory, dram c. when a frame buffer dram isn't requireed, this bus may optionall be used to input up to 24 bits of rgb data from the external pc-video subsystem(device). row address strobe for latching 10-bit row ad- dress signal into display memory, dram a.. row address strobe for latching 10-bit row ad- dress signal into display memory, dram b.. row address strobe for latching 10-bit row ad- dress signal into display memory, dram c.. column address strobe for dram a lower byte in dual-cas application. in dual-we applica- tion, it is used as write enable signal for dram a lower byte. column address strobe for dram a upper bytein dual-cas application. column address strobe for dram b lower bytein dual-cas application. column address strobe for dram b upper byte.in dual-cas application. column address strobe for dram c lower bytein dual-cas application. column address strobe for dram c upper bytein dual-cas application. write enable signal for dram a in dual-cas application. in dual-we application, it is used as write enable signal for dram a upper byte. write enable signal for dram bin dual-cas application. write enable signal for dram cin dual-cas application. data output enable signal for dram a and dram b. data output enable signal for dram c. 154,153,152,151,150, 149,148,147,146,145 99,98,97,96,95, 94,93,92,91,90 177,176,175,174,173, 172,171,170,169,168, 167,166,165,164,163 162 144,143,141,140,138, 137,136,135,134,133, 132,131,130,129,128, 127 122,121,120,119,118, 117,116,115,114,113, 112,111,110,109,107, 106 156 123 101 160 159 126 125 104 103 157 124 102 155 100
p18 symble type drive pin number active function - - true true these three analog outputs are generated by TP6508's internal build-in dac and it supplies current corresponding to the red , green , blue value of pixel being displayed. this pin input is used as the internal build-in ramdac voltage reference. a setting resister is required between this pin and avss1 deter- mines the full-scale output of each dac. vertical retrace synchronization signal drives the crt monitor. horizontal retrace synchronization signal drives the crt monitor. 60 58 57 55 64 65 red analog output 20ma green analog output 20ma blue analog output 20ma rset analog output 10ma vsync o 12mar hsync o 12mar * crt output interface (6 pins) romcs* o 8mar (i/o) test i/o 4mar 29 178 low true vga bios rom enable signal for isa bus, it generated by hm86509 when the 32k-byte memory location from c0000 to c7fff or the 64k-byte memory domain setting by extended registers is selected. this pin is intended for testing. it can be rede- fined as other useful function pin at the combi- nation switch type of description in extended reg- ister hex cc . * misc. pins (2 pins) * clock input interface (4 pins) xtali i - exmclk i - osc i - xtalo o - exvclk i - (i/o) 32khz i - (i/o) 203 204 178 154 true true true true true true the pin serves as the crystal input. external memory clock input. it requires an input frequency of 14.318mhz with a duty cycle of 50+/-5%.this input pin sup- plies the reference frequency for the dual-fre- quency synthesizer . the pin serves as the crystal output . external video clock input it is a optional input from stanby pin. refresh clock input for drams under into off mode (vesa dpms).
p19 shfclk(cl2) o 12mar lp(cl1) ot 8mar phsync de flm ot 8mar pvsync m o 8mar de p[23:16] o 4mar p[15:0] o 8mar sld[7:0] o 8mar sud[7:0] o 8mar ld[3:0]/ed[3:0] o 8mar ud[3:0]/od[3:0] o 8mar 70 68 67 69 97,96,95,94,93, 92,91,90 88,87,86,85,84, 83,82,81,79,78, 76,75,74,73,72,71 75,76,78,79,85, 86,87,88 71,72,73,74,81, 82,83,84 75,76,78,79 71,72,73,74 true high true high high true true high true true true true true true true this signal is used to driver the flat panel shift clock . this signal is used to drive the flat panel line clock for lcd panels or the horizontal sync for plasma/el panels and some tft panels. it can also do as the display enable signal (de) for flat panel. this signal is used to start a new frame on flat panels for lcd panels or the vertical sync for plasma/el panels and some tft panels. this signal is used to provide the ac inversion for flat panels to prevent a chemical damage. it can also do as the display enable signal (de) for flat panel. these signals contain red/green/blue color data for 9/12/18/24 bit interface tft-color lcd panels. these signals contain the lower data for color stn lcd panels . these signals contain the upper data for color stn lcd panels . these signals contain the lower data for gray dual-scan lcd panels . these signals contain the even data for gray plasma/el panels . these signals contain the upper data for gray dual-scan lcd panels . these signals contain the odd data for gray plasma/el panels . * power management pins (5 pins) 53 62 61 54 178 high high high low high the acti output is an active high signal that is driven high every time a valid vga access (memory or i/o read/write). this signal is part of the flat panel power-down sequencing and should be connected to the flat panel logic power enable . ( default = 0 after reset-on) this signal is part of the flat panel power-down sequencing and should be connected to the flat panel bias power enable . ( default = 0 ) this signal is part of the flat panel power-down sequencing and should be connected to the flat panel backligh enable . ( default = 1 ) this input is used to force TP6508 into off mode enable . this pin can also redefined as an output to indicate the active status . it may be also configed as other function- by extended register. acti i - (i/o) fpvcc o 8mar fpvee o 8mar fpback o 8mar off i/o 4mar symble type drive pin number active function * flat panel interface (28 pins)
p20 flat panel interface table pin number pin name mono lcd color lcd color lcd* color lcd color lcd color lcd gray gray dual-scan stn single-scan stn dual-scan stn dual-scan stn tft tft plasm el 8-bit 16-bit 8-bit 16-bit 9/12/16-bit 18/24-bit 8-bit 8-bit 70 shfclk sclk cl2 cl2 cl2 dclk dclk clk vclk 68 lp lclk cl1 cl1 cl1 lp/hs lp/hs hsync hs 67 flm flm flm flm flm flm/vs flm/vs vsync vs 69 m mdl m m m de de disptmg de 71 p0 ud3 sud7 sud7 sud7 b0 b0 72 p1 ud2 sud6 sud6 sud6 b1 b1 73 p2 ud1 sud5 sud5 sud5 b2 b2 74 p3 ud0 sud4 sud4 sud4 b3 b3 75 p4 ld3 sud3 sud3 sld7 b4 b4 76 p5 ld2 sud2 sud2 sld6 g0 b5 78 p6 ld1 sud1 sud1 sld5 g1 b6 79 p7 ld0 sud0 sud0 sld4 g2 b7 81 p8 sld7 sud3 g3 g0 od3 od3 82 p9 sld6 sud2 g4 g1 od2 od2 83 p10 sld5 sud1 g5 g2 od1 od1 84 p11 sld4 sud0 r0 g3 od0 od0 85 p12 sld3 sld3 r1 g4 ed3 ed3 86 p13 sld2 sld2 r2 g5 ed2 ed2 87 p14 sld1 sld1 r3 g6 ed1 ed1 88 p15 sld0 sld0 r4 g7 ed0 ed0 90 p16 r0 91 p17 r1 92 p18 r2 93 p19 r3 94 p20 r4 95 p21 r5 96 p22 r6 97 p23 r7 * : color dual-scan stn lcd panel with external frame buffer [84.05.29 508pnl.tbl]
p21 symble type drive pin number active function * video interface (26 pins) vr[7:0] i/o 4mar vg[7:0] i/o 4mar vb[7:0] i/o 4mar key i/o 4mar pclk o 4mar vp[15:0] i/o 4mar vrdy i - grdy o 4mar evid# i - vclk i - 103,104,122,121,120, 119,100,154 118,117,116,115,114, 113,98,99 112,111,110,109,107, 106,54,53 101 102 103,104,122,121,120, 118,117,116,115,114, 113,112,111,110,109, 107 101 119 106 100 true true true true true true high high low true red data for the video-in input by external pc- video system. green data for the video-in input by external pc-video system. blue data for the video-in input by external pc- video system. color key signal for the video-in input by ex- ternal pc-video system. pixel clock input of the video-in interface by external pc-video system. vafc interface video pixel data output. vafc interface video system ready signal. vafc interface graphics system ready signal. vafc interface enable video signal. vafc interface video input clock. * power pins (25 pins) avdd1 avdd2 avdd3 bvdd[1:2] cvdd[1:2] dvdd mvdda mvddb mvddc avss1 avss2 avss3 bvss[1:4] cvss[1:2] dvss[1:2] mvssa mvssb mvssc 59 205 206 9,42 80,181 66 158 142 108 56 202 208 12,26,39,52 77,184 63,89 161 139 105 +5v +5v +5v +5v +5v +5v +5v +5v +5v ground ground ground ground ground ground ground ground ground internal dac analog power. internal mclk frequency synthesizer power. internal vclk frequency synthesizer power. host bus interface power. core logical power. digital pads output power. memory bus a interface power. memory bus b interface power. memory bus c interface power. internal dac analog ground. internal mclk frequency synthesizer analog ground. internal vclk frequency synthesizer analog ground. host bus interface ground. core logical ground. digital pads output ground. memory bus a interface ground. memory bus b interface ground. memory bus c interface ground. *** descript of type term o : output i : input i/o : birdirectional ot : output tri-state i/s : schmitt-trigger input u : internal passive pull-up
p22 * host bus interface table pin type pin number pin drive isa bus pci 32-bit local bus i/o - 8mar sd[15:0] ad[15:0] i/o 20 8mar ows ad16 i/o 19 8mar memcs16* ad17 i/o 18 8mar iocs16* ad18 i/o - 8mar ad[31:19] input 43 sa0 cbe0# input 32 sbhe* cbe1# input 21 sa1 cbe2# input 10 ref* cbe3# i/o - 4mar sa[19:2] roma[17:0] input - sa20 i/o - 4mar sa21 romoe* input 201 sa22 clk input 28 sa23 i/o 29 8mar romcs* perr# i/o 30 8mar irq serr# i/o 53 8mar (acti) (acti) i/o 54 8mar (fpback) (fpback) input 207 reset rst# input 22 ale frame# i/o 31 4mar aen par input 11 memr* idsel input 23 memw* irdy# ot 24 12mar iordy* trdy# i/o 25 12mar iowr* devsel# i/o 27 4mar iord* stop# [86.04.15 508bus.tbl]
p23 * pin list pin # pin drive pin type pin name other name(s) (isa bus) 1 8mar i/o ad31 2 8mar i/o ad30 3 8mar i/o ad29 4 8mar i/o ad28 5 8mar i/o ad27 6 8mar i/o ad26 7 8mar i/o ad25 8 8mar i/o ad24 9 power bvdd1 10 i cbe3# ref* 11 i idsel memr* 12 ground bvss1 13 8mar i/o ad23 14 8mar i/o ad22 15 8mar i/o ad21 16 8mar i/o ad20 17 8mar i/o ad19 18 8mar i/o ad18 iocs16* 19 8mar i/o ad17 memcs16* 20 8mar i/o ad16 ows 21 i cbe2# sa1 22 i frame# ale 23 i irdy# memw* 24 12mar ot trdy# iordy* 25 12mar i/o devsel iowr* 26 ground bvss2 27 12mar i/o stop iord* 28 i la23 29 8mar i/o perr# romcs* 30 8mar i/o serr# irq 31 4mar i/o par aen 32 i cbe1# sbhe* 33 8mar i/o ad15 sd15 34 8mar i/o ad14 sd14 35 8mar i/o ad13 sd13 36 8mar i/o ad12 sd1 37 8mar i/o ad11 sd11 38 8mar i/o ad10 sd10 39 ground bvss3 40 8mar i/o ad9 sd9 41 8mar i/o ad8 sd8 42 power bvdd2 43 i cbe0# sa0 44 8mar i/o ad7 sd7 45 8mar i/o ad6 sd6 46 8mar i/o ad5 sd5 47 8mar i/o ad4 sd4 48 8mar i/o ad3 sd3 49 8mar i/o ad2 sd2 50 8mar i/o ad1 sd1 51 8mar i/o ad0 sd0 52 ground bvss4 pin # pin drive pin type pin name other name(s) 53 8mar i/o acti vb0,sda,csync 54 8mar i/o fpback vb1,scl,csync 55 10ma analog output rset 56 ground avss1 57 20ma analog output blue 58 20ma analog output green 59 power avdd1 60 20ma analog output red 61 20ma o fpvee fpback 62 20ma o fpvcc 63 ground dvss1 64 12mar o vsync 65 12mar o hsync csync 66 power dvdd 67 8mar ot flm 68 8mar ot lp 69 8mar o m 70 12mar o shfclk 71 8mar o p0 72 8mar o p1 73 8mar o p2 74 8mar o p3 75 8mar o p4 76 8mar o p5 77 ground cvss1 78 8mar o p6 79 8mar o p7 80 power cvdd1 81 8mar o p8 82 8mar o p9 83 8mar o p10 84 8mar o p11 85 8mar o p12 86 8mar o p13 87 8mar o p14 88 8mar o p15 89 ground dvss2 90 4mar o p16 ca0 91 4mar o p17 ca1 92 4mar o p18 ca2 93 4mar o p19 ca3 94 4mar o p20 ca4 95 4mar o p21 ca5 96 4mar o p22 ca6 97 4mar o p23 ca7 98 4mar i/o vg1 ca8 99 4mar i/o vg0 ca9 100 4mar i/o vr1 vclk,oec* 101 4mar i/o key vrdy,rasc* 102 4mar o pclk wec*,wech* 103 4mar i/o vr7 vp15,cascl*,wecl* 104 4mar i/o vr6 vp15,casch*,casc*
p24 pin # pin drive pin type pin name other name(s) 105 ground mvssc 106 4mar i/o vb2 evid#,mcd0 107 4mar i/o vb3 vp0,mcd1 108 power mvddc 109 4mar i/o vb4 vp1,mcd2 110 4mar i/o vb5 vp2,mcd3 111 4mar i/o vb6 vp3,mcd4 112 4mar i/o vb7 vp4,mcd5 113 4mar i/o vg2 vp5,mcd6 114 4mar i/o vg3 vp6,mcd7 115 4mar i/o vg4 vp7,mcd8 116 4mar i/o vg5 vp8,mcd9 117 4mar i/o vg6 vp9,mcd10 118 4mar i/o vg7 vp10,mcd11 119 4mar i/o vr2 grdy,mcd12 120 4mar i/o vr3 vp11,mcd13 121 4mar i/o vr4 vp12,mcd14 122 4mar i/o vr5 vp13,mcd15 123 4mar o rasb* 124 4mar o web* webh*,aa9 125 4mar o casbh casb* 126 4mar o casbl* webl* 127 4mar i/o mbd0 128 4mar i/o mbd1 129 4mar i/o mbd2 130 4mar i/o mbd3 131 4mar i/o mbd4 132 4mar i/o mbd5 133 4mar i/o mbd6 134 4mar i/o mbd7 135 4mar i/o mbd8 136 4mar i/o mbd9 137 4mar i/o mbd10 138 4mar i/o mbd11 139 ground mvssb 140 4mar i/o mbd12 141 4mar i/o mbd13 142 power mvddb 143 4mar i/o mbd14 144 4mar i/o mbd15 145 4mar i/o/u aa0 cfg0 146 4mar i/o/u aa1 cfg1 147 4mar i/o/u aa2 cfg2 148 4mar i/o/u aa3 cfg3 149 4mar i/o/u aa4 cfg4 150 4mar i/o/u aa5 cfg5 151 4mar i/o/u aa6 cfg6 152 4mar i/o/u aa7 cfg7 153 4mar i/o/u aa8 cfg8 154 4mar i/o vr0 32khz 155 8mar o oeab* 156 4mar o rasa* pin # pin drive pin type pin name other name(s) 157 4mar o wea* weah* 158 power mvdda 159 4mar o casah* casa* 160 4mar o casal* weal* 161 ground mvssa 162 4mar i/o/u mad0 163 4mar i/o/u mad1 164 4mar i/o/u mad2 165 4mar i/o/u mad3 166 4mar i/o/u mad4 167 4mar i/o/u mad5 168 4mar i/o/u mad6 169 4mar i/o/u mad7 170 4mar i/o/u mad8 171 4mar i/o/u mad9 172 4mar i/o/u mad10 173 4mar i/o/u mad11 174 4mar i/o/u mad12 175 4mar i/o/u mad13 176 4mar i/o/u mad14 177 4mar i/o/u mad15 178 4mar i/o off exvclk 179 4mar i/o roma0 sa2 180 4mar i/o roma1 sa3 181 power cvdd2 182 4mar i/o roma2 sa4 183 4mar i/o roma3 ,sa5 184 ground cvss2 185 4mar i/o roma4 sa6 186 4mar i/o roma10 sa7 187 4mar i/o roma5 sa8 188 4mar i/o roma11 sa9 189 4mar i/o roma6 sa10 190 4mar i/o roma9 sa11 191 4mar i/o roma7 sa12 192 4mar i/o roma8 sa13 193 4mar i/o roma12 sa14 194 4mar i/o roma13 sa15 195 4mar i/o roma14 sa16 196 4mar i/o roma15 la17 197 4mar i/o roma16 la18 198 4mar i/o roma17 la19 199 i la20 200 4mar i/o romoe la21 201 i clk la22 202 ground avss2 203 i xtali exmclk,osc 204 - o xtalo 205 power avdd2 206 power avdd3 207 i/s rst# reset 208 ground avss3
p.26 vi. function descriptions the TP6508 contains seventeen major functional modules. there are; host bus interface , sequencer control , crt controller, attribute controller , graphics controller , address multiplexer , crt fifo , attribute fifo , write buffer , command fifo ,dual frequency synthesizer , true-color palette , graphics engine controller , pc video controller , lcd line buffer , panel controller , power management controller. the main difference between standard vga and TP6508 is graphics engine controller. we will introduce detail description on this part of the whole function. the following is an overview of the major elements of the TP6508. host bus interface in addition to an isa bus connection , it can be connected directly to pci standard local bus interface to provide additional graphics performance without any glue logic . * isa bus TP6508 supports 16-bit isa bus with a high integrated bus interface that no additional logical is require . the TP6508 executes either 8-bit or 16-bit i/o and memory accesses . * pci local bus TP6508 can directly connect to 32-bit pci local bus without any additional logic to support its multiplexed address and data pins, at speeds of up to 33mhz. the TP6508 sup- ports 32-bit data width accesses with memory burst mode , fast back-to-back , byte merge function . it also provides 256k bios rom support and transfers rom data through vga to pci bus . sequencer contr oller (seqc) the sequencer controller includes a timing generator. the timing generator produces the basic timing sequence control for the crtc , atc, gfxc. it manages the display memory and provides an arbitration for crt, cpu and refresh requests. with a deeper crt fifo design, the TP6508 performs fast-page mode to fetch display data quickly into crt fifo. when cpu accesses the frame memory, it inserts a cpu cycle via the arbitrating state machine to cpu access. cr t contr oller (cr tc) the crt controller includes a cursor control logic, a horizontal logic, a vertical control logic , and the compatible ibm crtc registers to generate horizontal synchronous and vertical synchronous signals for external raster-scan crt monitor. it also provides split-screen capability and smooth scrolling. it generates the blank signals that are sent to ramdac (true-color palette dac) to inhibit pixel display on the screen of monitor.
p.27 it provides a linear memory address logic and a raster address logic to produce memory address signals for fetching display informations from vga frame memory. attribute contr oller (a tc) the attribute controller provides flexible high-speed display shifting and attribute processing. it is designed for both text and graphics vga display applications. in text modes, the attribute controller takes in eight bits of character code data and eight bits of attribute data via the graphics controller. the character code is used to lookup into a character font table that is located in the map3 of the display memory. the character font data is loaded into a parallel-to-serial shift register. the serial output from the shift register is used to select a foreground or a background color that is assigned in the attribute data byte. text blinking, underline and cursor are also the responsibility of the attribute controller. in graphic mode, the display data are converted into pixel color data in groups of 16, 8, 2,or 1 adjacent bits, passed through an internal color palette table, and sent out serially to the ramdac. in the 256-color mode, the display data is latched twice to form an 8-bit pixel data. graphics contr oller (gfxc) the graphics controller is the interface between crt fifo and both the attribute controller during active display and the system microprocessor during display memory reads or writes. during display, memory data is latched from crt fifo and sent to the attribute controller. in graphic mode, the parallel memory data is converted to serial bit-plane data before being sent out. in text mode, the parallel attribute data is sent to attribute controller directly. during a system microprocessor writes or reads to display memory, the graphics controller can perform logical operations on the memory data before it reaches display memory or the system micro- processor data bus, respectively. these logical operations consisted of four logical write modes and two logical read modes. addr ess multiplexer (amux) the address multiplexer controls the address bus that is sent to the display memory. it includes ras* , cas* , we* , and oe* timing. during the crt cycle it sent the display memory address that comes from crt controller to the display memory for fetching the display information. when a system microprocessor writes or reads the display memory, the address multiplexer connects the system microprocessor address bus to the display memory. when the write buffer function is enabled, a system microprocessor write operation is done first to the write buffer logic, then the system address and data signals are latched in the logic. the sequencer controller inserts a cpu cycle to perform a write operation by a request coming from write buffer logic. at this time, the address multiplexer logic connects the address latched by write buffer to display memory.
p.28 cr t fifo (display fifo) the crt fifo logic is the interface between display memory and the graphics controller during the crt cycle. the sequencer controller takes an arbitration between crt, cpu and refresh cycle. because the crt cycle has the highest priority, the sequencer controller can perform a vast fast-page mode to fetch the display data and latch those data into the crt fifo. during display , the graphics controller takes the display data from the crt fifo by the display sequence. two threshold registers is defined as a high and a low indicator of the crt fifo. these regis- ters data are then compared with the number of available display data in the crt fifo. the compare outputs are sent to the sequencer controller for arbitrating operation. when the contents in the crt fifo are under the low threshold, the crt fifo issues a request to the sequencer controller for more crt cycles. when the contents in the crt fifo leaps over the high threshold or reaches full of the fifo, the cpu gains the highest priority. with this crt fifo logic, the TP6508 optimizes system performance. attribute fifo the dynamic memory cycle allocation architecture is used in TP6508. specially , in text mode we integrate 12 levels attribute fifo storing the attribute information latches the text attribute , ascii data and cursor state in order to improve performance. the attribute fifo logic is the interface between display memory and crt fifo during the crt attribute-accessed cycle in text mode. two threshold registers is defined as a high and a low indicator of the attribute fifo, these registers data compare with the number of available text attribute data in the attribute fifo. the content-data are sent to crt fifo for arbitrating operation. with the at- tribute fifo logic, the TP6508 optimizes system performance in text mode only . w rite buf fer when the write buffer function is enabled, a system microprocessor writes to the write buffer logic instead of writing directly to the display memory or accessing i/o-write command. a four-stage buffer latches the address, data and other status and maintains a zero wait state write cycle to improve the system performance. if the content of the buffer is not empty, the write buffer logic requests the sequencer controller to insert a cpu cycle. for compatibility issue, when the content of the buffer is not empty, the sequencer controller holds attempts to read display memory and write i/o register until the TP6508 completes processing all items in the write buffer logic. dual fr equency synthesizer the dual frequency synthesizer generates the memory clock (mclk) and the display clock (vclk) from a single reference frequency - 14.318mhz . . the frequency of each clock is programmable by setting divisor value in the extended regs. that contains field for pll (phase lock loop), voc (volt-
p.29 age controlled oscillator and post divide control. the pll parameters for dot /pixel clock (vclk) are programed vclk0 or vclk1 set regs. in sreg c3,c4,c5,c6 and for memory clock (mclk) are programmed mclk set regs. in sreg c9,ca. these registers uses to be in conjunction with denominator and post scalar value register, is used to determine the frequency of vga dot clock. these 7 bits numerator (n), 7 bits denominator (d), and 1 bit post scalar (p), for each clock (mclk or vclk) determines its frequency according to the follow- ing expression: osc x [n+1] x [2p+2] . mclk, vclk(mhz) = [d+1] osc = reference frequency / 14.318 mhz the reference frequency can be generated with an internal crystal controlled oscillator. alter- natively, it can be supplied from an external ttl source by xtal1 pin input. a optional feature is implemented that directs TP6508 to provide the memory clock and the display clock from mclk and vclk pin. t rue-color palette dac (tdac) the true-color palette dac block contains the true color palettes and three 6-bit or 8-bit digi- tal-to-analog converters. it contains three 256x8 color lut rams for all color mode with the capa- bility to display up to 16.8 million colors simultaneously in both rgb and bgr hicolor-24 tm formats. it also support both the popular hicolor-15 tm format which uses 5 bits/primary color and the hicolor-16 tm color format which uses 5 bits for red , 6 bits for the green , and 5 bit for the blue primary color. the total colors available using the hicolor-15 tm format are 32768 while the hicolor-16 tm format provides 65536 colors. when the true-color (16.8m) and hi-color (32k/64k) mode isn't activated , it behaves exactly as pseudo color format compatible ramdac. the color palette, with 256x18-bit entries, converts a color code that specifies the color of pixel into three 6-bit values, one each for red, green, and blue. it also provides a monitor sense logic to output a signal to input status #0 register for determin- ing the presence of the crt monitor. this output is a logical 0 if one or more of the red, green, blue outputs have exceeded the internal voltage reference level by being connected a loaded or unloaded rgb line. after the vga bios programed the palettes and determined the color/mono or no crt monitor, we can disable the monitor sense logic for saving power consumption. graphics engine contr oller (gec) the graphics engine controller generates the control signals for bitblt (screen-to-screen, host- to-screen) , color expansion (1-bit-per-pixel , font-painting) , line drawing , rectangular clipping , rectangular fill, pattern fill, transparence, and raster operations. they are specifically designed to speed up applications running under gui environments such as windows 3.x , windows applications , x-windows , autocad , and other cad/cam packages. it maintains memory address to locate data in display memory and combines the source data
p.30 ,destination data ,and pattern data to perform writing the result back to the destination area under the control of parameters programmed into the chip. the destination data and pattern data must reside in the display memory. the source data and color expansion pixel data may reside in display memory or be supplied by the cpu during a graphics accelerated operation. optionally, we support the base addressing and the memory map i/o addressing to access those gec. registers with 16-bit/32-bit data width. it is more convenient to implement the gui acceleration function in order to improve the software level performance. all of the accelerated functions are integrated by TP6508 for 8-bit , 16-bit , 24-bit color modes. the encoding of these 256 rops is 100% compatible with microsoft windows driver interface speci- fication. see appendix c for a list of raster operation. * line drawing the graphic engine implement line drawing function based on the bresenham's algo- rithm . it can draw solid line or dash line by programming the line drawing pattern registers . in the case of drawing dash line , there is one selection to determine whether to keep back- ground data unchanged (transparence) or using the color in "background color registers" as the background color . the pattern format are one pixel mapped to one bit and the first pixel mapped the msb of the join 32-bits pattern in registers . for the line drawing pattern , one selection is useful for actual screen display that is only used the lower 8-bits of line drawing pattern and one bit mapped four or three pixels . when we draw a more vertical line , the gec can produce three pixels per mapped bit . when we draw a more horizontal line , the gec can produce four pixels per mapped bit . another selection is to determine whether is to draw the last pixel of this drawing line or not . * bit block transfer bit block transfer can copy a rectangular image from a source region to a destination region on display memory with raster operation in 256 rops code described in appendix c. * color expansion color expansion function can expand monochrome image which one bit represent one pixel to two-color image . all the "1" bits in monochrome image expand to the color in foreground color registers . all the "0" bits expand to the color in background color regis- ters or keep the background data unchanged if 'background transparency enable' bit is en- abled . a useful case of color expansion is filling text in graphic mode . the monochrome data are the character font bitmap data and transfer to TP6508 by writing to "host to display data transfer register" . some additional notes for 'color expansion' need to care is described detail in that description of 'image write'.
p.31 * image write image write can transfer color image from host system memory to display memory . the color image data transfer to TP6508 by writing to "host to display data transfer register" . the display pixels order of color image is from left to right and from top to bottom if both 'x direction' bit and 'y direction' bit are programmed to "0" . some additional notes for 'image write' need to care in programming sequence . the first , if width-x isn't a double-word alignment number for 'image write', we muse add a , two or three dummy bytes to fill the last transfer to a double word at the end of each horizontal line . the second , we usually need to check the 'command fifo' status in "graphics com- mand fifo status register" at the start of any horizontal line . if one horizontal line needs 32 bytes or less to transfer , then the whole line can be written to TP6508 directly . if one horizontal line needs to transfer more than 32 bytes , it must be done after every 32 bytes have been written to TP6508 that we need to check the 'command fifo' status . * image read image read can transfer color image from display memory to host system memory . the color image data transfer from TP6508 by reading from "host to display data transfer reg- ister" . the display pixels order is as same as image write . also , for 'image read' the additional cares about 'image write' need to take care . * rectangular fill & pattern fill rectangular fill can fill a any size rectangular region on display memory using the color in "foreground color registers" . also, the pattern fill can use a 8-pixel by 8-pixel image that is storied on display memory as pattern source to fill a any size rectangular region on display memory if pattern is selected by 'raster operation'. * rectangular clipping rectangular clipping define a rectangular region where the image data can be written or cannot . if rectangular clipping is enabled , all the graphic engine functions including of 'line drawing' , 'bitblt' , 'color expansion' , 'image write' , 'image read' , and 'rectangular fill & pattern fill' can only write these pixels that inside the clipping region or on the boundary if the 'rectangular clipping polarity' bit is set to "0" . any pixel outside the rectangular region would not be changes . a another option , gec can write those pixels that outside clipping region (not includ- ing of on the boundary) if the 'rectangular clipping polarity' bit is set to "1" . * color transparency color transparency function can partition the destination pixels into two groups base on its color information . pixels transfer through gec with the same color as the "transparency color registers" can not be modified if 'transparency polarity' bit is "0" . pixels transfer
p.32 through gec with the different color as the "transparency color register" can not be modi- fied if 'transparency polarity' bit is "1" . in addition , there is a "transparency mask registers" . if the mask bit is "1" , then the color bit of destination pixel is not used in color compare and passes through . these is a example in enhanced 256 color mode . if "transparency color registers" is written hex 36 and "transparency mask registers" is written hex 28 and 'transparency polarity' bit is "0" , the destination pixels with color 16h , 36h , 1eh or 3eh would not be modified . command fifo when the graphics engine is in operation , we will transfer the necessary parameters ( x/y direction ,source/destination select, major movement , foreground/background color, ... etc..) to TP6508 by through the command fifo and write a graphics accelerate function command (bit block transfer , color expansion , line drawing , ... etc..) in the last. a eight-stage fifo latches the command data including of graphics accelerate function command and it's parameters and maintains a zero wait state write cycle to improve the system performance. if the content of the fifo is full , the command fifo logic requests the sequencer controller to assert the wait cycle until to the fifo isn't full. a better recommendation was to monitor the 'graphics command status register' in the group of graphics engine control register before you write graphics engine command to TP6508. hardwar e cursor contr oller the hardware cursor controller supports a 32x32 or 64x64 hardware cursor in 256-color,32k/ 64k-color and 16.8m-color graphics mode. it supports the two-bit plane cursor data structure which provides two colors plus transparent and inverted background color by following the microsoft win- dows driver interface specification. in addition, a auxiliary color data function can replace the in- verted background color function optionally . the pattern's data format of any pixel (two-bit) is : data bit-1 data bit-0 definition 0 0 hardware cursor primary color 0 1 hardware cursor secondary color 1 0 transparent 1 1 inversion or hardware cursor auxiliary color (decided by gareg 2a bit-15 selection) usually , the cursor pattern is stored in the off-screen display memory . the structure of cursor pattern is 16-bytes by 64-line . all the 16-bytes join together from low address to high address and from lsb to msb to form a 64x2-bit bit-string . the screen display order of cursor pattern from left to right is mapped to bit string from lsb to msb per two-bits . to write the cursor pattern to display memory can use image write or vga memory write access directly . the cursor pattern start must address at boundary of double-word . hardware cursor screen position, type, color selection, and pattern address of the cursor are to be controlled by programming these registers in the group of graphics engine control registers. the hardware cursor data are allowed of multiple patterns to be storied in display memory and rapidly to be selected one of the patterns as the active cursor's pattern by application program.
p.33 the hardware cursor replaces the software mouse cursor and eliminates to store and restore the screen data as changed the mouse position. typically, the application software initializes the cursor once and only needs to update the screen position by setting registers. so we can provide a smooth- moving mouse pointer by compared with a software mouse. pc v ideo contr oller TP6508 allows up to 24-bit of external rgb video data to be input and merged with the internal vga data stream. the TP6508 can support two forms of video window: 1) color key input and 2) x- y window keying. the x-y window key input can be used to position the live video window coordi- nates. lcd line buffer for dual-scan stn lcd panels, those panels require the upper and lower panels to refresh simultaneously so that we need additional buffer and logic to implement. the additional buffer is called "lcd frame buffer" storing the stn lcd's refresh data which are half of a whole lcd panel's. in TP6508 we have three frame-buffer technique; shadow frame buffer, external frame buffer, pseudo frame buffer, to accelerate lcd display refresh. for shadow frame buffer, we can share the off-screen display memory as the lcd frame buffer by programming the upper display memory region. TP6508 also implements a lcd line buffer to process and store a line of the lcd refresh data at the start of every crt horizontal raster. the operation sequence of lcd line buffer is executed by the following steps: 1. read a line of lcd frame data which are used for the present display frame from shadow frame buffer during the horizontal blank cycle. 2. write a line of lcd frame data which are used for the next display frame to shadow frame buffer by following the step-1 during the horizontal blank cycle. 3. output to panel controller from lcd line buffer, a set of frame information of pixels which are read from shadow frame buffer are used to display one of the half lcd panel. 4. generate and store into lcd line buffer from panel controller, a set of the frame information of pixels which will write to shadow frame buffer are used to display another of the half lcd panel for next frame. 5. continuously, process the step-3 and step-4 until ending a line of lcd frame data during the horizontal display period. 6. restart from step-1 for next horizontal raster display and repeat for whole frame display refresh. vga has the memory bandwidth limitation, but crt refresh rate higher than memory fetch speed. by external frame buffer technique, we can add another external 256kx16-bit dram-c as a lcd frame buffer. the video-in and pin[8:15] of panel is also by dram-c interface. in addition, the another solution for dual-scan stn lcd panel display is used the pseudo frame buffer technique. it is no additional memory required, but it gets rather lower lcd display contrast than others. it is designed to optimize cost and quality trade-off considerations.
p.34 panel contr oller the panel controller redefines data format from attribute controller in lcd/plasma/el dis- play modes. the TP6508 can directly drive various flat panels, including dual-scan/single-scan mono- chrome, color stn, and color tft. for monochrome lcd/plasma/el panels, it converts fp0-fp7 to gray level and goes through a special functional operation, sum_to_gray, which is called gray scaling. for color lcd panels, it converts fp0-fp23 to r.g.b. color level and goes through two special functional operation, which are called dithering and amplitude modulation . the vga standard defines how colors are mapped to 64 gray scale values on monochrome moni- tors. the mapping is based on the following weighting equation: i=0.30r+ 0.59g+ 0.11b this formula follows the ntsc conversion standard and is confirmed to display the original color information. basically, monochrome flat panels do not actually show shades of gray, but only black and white. to build a gray scale, some pixels stay white proportionally longer than they are dark, depending on the shade of gray being built up. gray scaling ( pattern modulation ) techniques determine which pixels are white or dark for corresponding gray level. if not done well, flicker and ripples will occur. others, the gray scaling techniques also can be using for color flat panel display. of course it will be occurred on color stn lcd panels that those problems are talking in previous paragraph. the TP6508 controller support both 8 and 16 bit interfaces to stn panels; 9-bit /12-bit/15-bit or 18-bit/ 24-bit interface tft color lcd panels. in addition, 65536 simultaneous colors are supported for color stn lcd panels, and up to 226,981 visual colors are supported by color dithering techniques. for color tft lcd panels, TP6508 can support 16.8m simultaneous colors on 24-bit interface. further more, 512 simultaneous colors are supported for 9-bit interface color tft lcd panels, and up to 185,193 visual colors are supported by amplitude modulation techniques. to avoid flicker and ripple phenomenon. there are three approaches: (1) increase frame rate: the higher the switching rate, the better the display quality. (2) adequate modulation sequences: spread pixels frame on time on continuous timing. (3) dispersion modulation: enhance modulation task from time spreading to spatial spreading each pixel on/off ratio does not change, but has time shift for neighboring pixels.
p.35 * gray scaling gray scaling is the continuous frame on/off ratio according to the corresponding gray level. we can do 2/4 gray level for pixels as follow: but notice how the dark pixels line up in diagonal columns. these rows of diagonal columns create regular striations marching across the gray region cycle by cycle. alternating the pixels other ways doesn't solve the problem but only creates vertical or other diagonal columns. if not designed correctly, a controller will exhibit diagonal columns jitter or scrambled movement across gray regions, greatly degrading display quality. how to eliminate the stripping wave become the key point of the panel vga design. basically, manufactures obey the following rules: (1) pixels on/off ratio are proportional to gray level. (2) the modulation sequence of neighboring pixels are uncorrelative to reduce stippling wave. frame 0 frame 1 frame 2 frame 3 s 0 3/8 s 1 3/8 s 2 3/8 s 3 3/8 frame seq. 0 1 2 3 4 5 6 7 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 s 0 3/8 s 1 3/8 s 2 3/8 s 3 3/8 note : 1 = on , 0 = off
p.36 p0-p7 fore back (g,r,b,i) (g,r,b,i) p/s cg sel gray pallete attribute remapping sync. delay m u x i0-i5 gray scaling to maximum contrast sp508b09.gem 85/02/12 l.r.y. 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 sp508b06.gem 85/02/12 l.r.y. we can see the following situation: according to the above rules, we can see the ambiguous stippling wave. it is clear that we find a method to eliminate wave phenomenon. but now another problem appear, how to find the best modula- tion sequence for all gray levels, so the adequate trade-off are needed. * maximum contrast and attribute emulation when color text converts to mono lcd panel mode, remapping gray levels between foreground and background are probably to the same gray level. it is difficult to recognize text forms on the screen. we provide user 'maximum contrast' option to enhance lcd display contrast. the operation as follow- ing: when foreground attribute (g0,r0,b0,i0) is larger than background attribute (g1,r1,b1,i1), we set (g0,r0,b0,i0) = (1,1,1,1) = 63 gray level, (g1,r1,b1,i1) = (0,0,0,0) = 0 gray level.when (g0,r0,b0,i0) = (g1,r1,b1,i1), we reverse the original attribute gray level. there is another option called attribute emulation. the user enable the 'attribute emulation' func- tion. attribute remapping does eight clear contrast automatically, so user can get the best looking in the text mode.
p.37 * frame buffer for dual-scan stn lcd panel , we must use "acceleration mode ". we can use the shadow frame buffer technique to fixed it . in the others, vga has the memory bandwidth limitation , but crt refresh rate higher than memory fetch speed. how to solve this series problem , we can add another external 256kx16-bit dram as a lcd frame buffer. when vga scans upper panel, frame buffer stores the pixel data of lower panel . every pixel needs only one bit to present on/off information . we provide following figures to show operating procedure: left diagram appears actual screen circumstance . a,b,c,d.. and 1,2,3,4 are the continuous pixels of upper/lower panel. right rectangles present the interior data of screen buffer . vga does read-modify-write to the frame buffer consecutively . upper buffer presents continuous process of scanning vga upper panel, so does lower panel . * color dithering for color stn lcd panel , TP6508 can add visual colors by color dithering techniques . the dithering technique uses a group of dithering pattern in 4 by 4 pixel-block and gray modulation to generate the gray shades for each of r,g,b . the dithering patterns for each shades is designed so that it creates minimum flicker and stripping wave on the panel screen. in the extended indexed register creg a9 , we can select the various dither algorithm and types to increase colors of the panels . * amplitude modulation for color tft lcd panel, TP6508 can add visual colors except the 24-bit true color panel by a b c d e... a b c d e... 1 2 3 4 5... 1 2 3 4 5... 1 2 3 4 5 a' 2 3 4 5 a' b' 3 4 5 ........ ........ ........ ........ a' b' c' d' e' a b c d e 1' b c d e 1' 2' c d e 1' 2' 3' 4' 5' start frame start frame r:1 w:a' r:2 w:b' end frame end frame r:a w:1' r:b w:2' screen sp508b08.gem 85/02/12 l.r.y. frame drams vga frame buffer drams buffer display buffer display buffer vga external frame buffer shadow frame buffer
p.38 color amplitude modulation techniques. the red, green, blue color data that directly come from the palette ram provide the code for each color. the amplitude modulation technique uses a group of weighting codes and frame (time) modulation to generate the shading information for each of r,g,b. in the extended indexed register creg a8 , we can select the various amplitude modulation types to increase colors of the panels . * display combination the new generation of lcd vga provides a simultaneous crt/lcd or crt/plasma display function . this adds a new dimension to the promotional application of portable computers by offering a more versatile visual demonstration . TP6508 also provides this function to extend added value to portable computer. in order to accommodate the limited minimum signal width of crt vga, the work- ing frequency of the lcd vga should at least be 6mhz . the TP6508 will provide a frame rate of about 120hz at this working frequency. in spite of the above, the crt vga still has its draw backs when used for commercial demon- stration because of its limited size . with the arrival of low priced tvs (60" to 120"), why not harness the big tv screen to reproduce the portable computer lcd display? to achieve this function, TP6508 has integrated the tv interface synchronization signal circuit . it needs only one analog ic to externally convert the rgb and synchronization signal to rs-170 standard signal for tv . the rs-170 signal is then transmitted through av terminal to tv . TP6508 has overcome the technical problem of interlaced scan on lcd . this makes the simultaneous display of tv/lcd come true. presently, TP6508 supports ntsc and pal tv standard. the secom standard support will be available in the future. * tv interface the simultaneous display on both tv and lcd panel is rather an unique design of TP6508. there are many add-on cards or devices on the market which can convert vga signal to tv display signal, but they can not accomplish a simultaneous display on lcd . the reason is that it is not as easy to perform a interlaced scan on lcd as on crt . this problem has to be resolved from the internal logic design of vga. on the other hand, TP6508 can generate synchronization signal that completely matches with the standard of rs-170. with an external ntsc encoder (a example , mc1377 , is set in application circuit chapter) , TP6508 can transmit image to tv through a/v terminal . in order to preclude flickering on tv display, TP6508 uses a non-interlaced scan to stabilize the frame rate at 60hz . under this frame rate, all display modes of ibm vga are supported. the optimum resolution is 640x480 with 256 colors. under tv display mode, the hsync signal which is originally sent to vga are converted to composite sync signal . this composite signal combines the horizontal sync, vertical sync and the equalization pulse . it is necessary of the 3.58 mhz crystal to generate a reference frequency for color burst signal. this frequency is used as the color calibration signal if adjusted by variable capacitor . due to the limitation of tvs resolution and frame rate, the displayed image may not be as good as that of vga display, but its display of big fonts and graphics as in a commercial demonstration and presentation, is distinctively sharp .
p.39 power management contr oller (p .m.c.) the TP6508 has a special function which is a power management unit to generate the power control signals for dual frequency synthesizer , ramdac, other block devices of TP6508, and montor output timing . it's implemented with the vesa dpms(display power management signaling) stan- dard and designed to provide power management for green pc systems . the TP6508 provides trigger pins and timers to determine when the system is idle . when idle, the TP6508 can remove power from unused internal block devices . the TP6508 also supports slow refresh dram for power saving. the TP6508 has four main operating modes: active mode, standby mode , suspend mode , and off mode. the i/o read/write ( register programming/keyboard request ) , external trigger pins, and the time-out control the transition between each mode . TP6508 supports one external trigger pins , off pin . dpms states: state hsync vsync crt flat panel power saving on(active) pulses pulses active active none standby no p ulses pulses blanked blanked minimal suspend pulses no pulses blanked blanked substantial off no pulses no pulses blanked blanked maximum cover-close pulses pulses active blanked minimal * dpms operating modes: 1. on(active) mode this is the start-up or wake-up mode of the system. the cpu is operating at maximum speed . fixed disks and floppy are working with normal situation and the vga is active normal . 2. standby mode standby mode is the first power saving mode . the standby mode is entered from the active mode when the time specified by the p.m.c. time-out register, or user i/o register programming . resume may be initiated by i/o register programming, or keyboard request . there are no crt cycle on in this mode and turns off internal dac . but video memory and register access allowed. 3. suspend mode suspend mode is the lower power saving mode . it is as same as the standby mode to TP6508's internal power saver except the output of hsync and vsync signal for various power saving mode monitor by vesa dmps standard. the different display sync output between standy mode and suspend mode is descripted on previous 'dmps states' table . suspend may be initiated by the p.m.c. time-out register, or user i/o register programming . resume may be initiated by i/o register programming , keyboard request. 4. off mode
p.40 1->2 * i/o register programming * standby timer time-out 2->1 * keyboard request * vga access 2->3 * i/o register programming * suspend timer time-out 3->1 * keyboard request * vga access 3->4 * i/o register programming * off timer time-out * off pin active 4->1 * keyboard request * vga access * off pin not active off mode is the lowest power mode . it may be initiated by the p.m.c. time-out register, user i/o register programming or off/suspend pin input . resume may be initiated by the off pin external trigger input. in this mode, system will turn off cpu cycle, crt cycle, screen buffer, display signal, internal dual frequency synthesizer and internal dac , meanwhile, does drams slow refresh. display memory and register accessing isn't allowed . 5. cover-close mode cover-close mode is the special power mode using for laptop pc. or notebook pc. system on closing the machine-cover . specially, this mode replace off mode when the user pro- grammed the extended register 3c4/3c5 index d2h bit 7 to logical 1 . it may be initiated by the off pin. resume may be initiated by external trigger input . in cover-close mode, system will turn off panel backlight, and down saving internal partial panel block device power . then the crt display is normal. 2 3 1 standby suspend on off 5 cover-close 4
p.41 * flat panel power sequencing the TP6508s power supply management design is very flexible . the following figure shows the timing diagram and the control signals related to power supply management . it is a very helpful reference for vga designing with portable or notebook computers . it is worth mentioning that the fpvcc, fpvee, and fpback signals can effectively resolve problems of lcd power sequencing . the fpvcc signal is used to turn on/off the digital power(+5 volt) for the digital logic of the lcd panel . the fpvee signal is sent to bias voltage generator of the lcd panel driver for control signal on/off application . the fpback signal can be sent to the back-light voltage generator to administer on/off control . there must be a 64ms skew between the fpvccs and fpvees timing during power on(into on mode) sequence and be a 16ms skew during power off (into standby/suspend/off/cover-close mode) sequence . the sequence is reversed between power on and power off. for the convenience of design, the length of skew is fixed and not adjustable, but topro is confident that this skew will satisfy the requirement of most panels . fpvcc signals lcd panel power sequencing [sp508b11.dsf] fpvee lcd driver power low skew 16 ms skew 16 ms on-mode panel-off panel-off panel-on power sequcnce panel-off power sequcnce skew 64 ms off-mode off-mode reset skew 64 ms vdd (+5v) lcd di g ital lo g ic power skew 64 ms low (flm / lp tri-state) fpback lcd backli g ht power
p.42 vii. registers description TP6508 contain seven groups of registers . these are ibm standard register backward compatible register , extended sequencer register , extended crtc register , panel control register , pci local bus configuration register, graphics engine register. ibm standard register there are five sets of registers in the video subsystem. all but the system microprocessor data latches and the attribute address flip-flop are readable. the following figure lists the registers and the i/o address where they are located. the figure also lists whether or not they are read/write, read-only, or write-only. * general registers misc. output register ( miscreg: r/3cch, w/3c2h ) d0 i/o address select ( 0/3bxh, 1/3dxh ) d1 enable video ram ( active high, no effect on display refresh ) d2 clock select 0 ( 00/25mhz, 01/28mhz ) d3 clock selcet 1 ( 10/auxi., 11/45mhz ) d4 reserved d5 odd/even page select ( for diagonostic use ) d6 horizontal sync. polarity select ( 0/positive, 1/negative) d7 vertical sync. polarity select ( 0/positive, 1/negative) input status register 0 ( instreg0 : r/3c2h ) d0-3 reserved d4 switch sense bit (match with clock select 0/1 ) d5-6 reserved (0) d7 crt interrupt ( 0/cleared, 1/pending ) input status register 1 ( instreg1 : r/3?ah ) d0 display enable ( active low ) d1-2 reserved d3 vertical retrace (vga) /cg out (herculus) d4 color plane register check 0 ( p0, p4, p1, p6 ) d5 color plane register check 1 ( p2, p5, p3, p7 ) d6-7 reserved feature control registe ( featreg: r/3cah, w/3?ah ) d0-7 reserved vga dac i/o ports 3c6h pixel mask register 3c7h dac state register ( read only, vga support d0-d1 ) 3c7h look-up table read index ( write only, ramdac support ) 3c8h look-up table write index 3c9h look-up table data register
p.43 * sequencer registers sequencer address register ( seqidreg : rw/3c4h ) d0-7 sequential address bits (00-ff) reset register ( sr00 : rw/3c5h ) d0 asynchrous reset ( active low ) d1 synchrous reset ( active low ) d2-7 reserved clocking mode register ( sr01 : rw/3c5h ) d0 8/9 dot clocks select ( 0/9, 1/8 ) d1 reserved d2 shift load ( 0/normal, 1/divide 2 ) d3 dot clock ( 0/normal, 1/divide 2 ) d4 shift 4 ( 0/d2, 1/divide 4 ) d5 screen off ( active high ) d6-7 reserved map mask register ( sr02 : rw/3c5h ) d0-3 enable map 0-3 ( active high ) d4-7 reserved character map select register ( sr03 : rw/3c5h ) d0 character generator table select b d1 character generator table select b d2 character generator table select a d3 character generator table select a d4 character generator table select b (msb) d5 character generator table select a (msb) d6 reserved memory mode register ( sr04 : rw/3c5h ) d0 reserved d1 extended memory ( 0/64k, 1/256k ) d2 odd/even ( active low ) d3 chain 4 ( 256 colors only, active high ) d4-7 reserved * crt registers crt address register ( crtidreg : rw/3?4h ) d0-4 sequential address bits d5-7 reserved horizontal total register ( cr00 : rw/3?5h ) d0-7 hori zontal total ( -5 ) horizontal display enable end register ( cr01 : rw/3?5h ) d0-7 horizontal display enable end ( -1 )
p.44 start horizontal blanking register ( cr02 : rw/3?5h ) d0-7 start horizontal blanking ( -1 ) end horizontal blanking register ( cr03 : rw/3?5h ) d0-4 end horizontal blanking bit 0-4 d5-6 display enable skew bit 0-1 d7 test (1) start horizontal retrace pulse register ( cr04 : rw/3?5h ) d0-7 start horizontal retrace pulse bit 0-7 end horizontal retrace register ( cr05 : rw/3?5h ) d0-4 end horizontal retrace bit 0-4 d5-6 horizontal retrace skew bit 0-1 d7 end horizontal blanking bit 5 vertecal total register ( cr06 : rw/3?5h ) d0-7 veratical total bit 0-7 ( -2 ) crtc overflow register ( cr07 : rw/3?5h ) d0 vertical total bit 8 d1 vertical display enable end bit 8 d2 vertical retrace start bit 8 d3 start vertical blank bit 8 d4 line compare bit 8 d5 vertical total bit 9 d6 vertical display enable end bit 9 d7 vertical retrace start bit 9 preset row scan register ( cr08 : rw/3?5h ) d0-4 preset row scan ( pexil scrolling ) d5-6 byte panning control bit 0-1 d7 reserved maximum scan line register ( cr09 : rw/3?5h ) d0-4 maximum scan line bit 0-4 d5 start vertical blank bit 9 d6 line compare bit 9 d7 200>400 line conversion cursor start register ( cr0a : rw/3?5h ) d0-4 row scan cursor start bit 0-4 d5 cursor off ( active high ) d6-7 reserved cursor end register ( cr0b : rw/3?5h) d0-4 row scan cursor end bit 0-4 d5-6 cursor skew bit 0-1 d7 reserved
p.45 start address high register ( cr0c : rw/3?5h ) d0-7 high order start address bit 0-7 start address low register ( cr0d : rw/3?5h ) d0-7 low order start address bit 0-7 cursor location high register ( cr0e : rw/3?5h ) d0-7 high order cursor location bit 0-7 cursor location low register ( cr0f : rw/3?5h ) d0-7 low order cursor location bit 0-7 vertical retrace start register ( cr10 : rw/3?5h ) d0-7 low order vertical start bit 0-7 ( 10 bits total ) vertical retrace end register ( cr11 : rw/3?5h ) d0-3 vert. retrace end bit 0-3 d4 clear vert. interrupt d5 enable vert. interrupt d6 select refresh cycles ( 0/3 cycle, 1/5 cycle ) d7 protect cr00-cr07 vertical display enable end register ( cr12 : rw/3?5h ) d0-7 low order vert. display enable end bit 0-7 ( -1 ) ( 10 bit total ) offset register ( cr13 : rw/3?5h ) d0-7 logical line width of the screen bit 0-7 underline location register (cr14 : rw/3?5h ) d0-4 underline location bit 0-4 d5 count by 4 d6 doubleword mode d7 reserved start vertical blanking register ( cr15 : rw/3?5h ) d0-7 low order vertical blanking bit 0-7 (-1) ( 10 bits total ) end vertical blanking register ( cr16 : rw/3?5h ) d0-7 end vertical blanking bit 0-7 crt mode control register ( cr17 : rw/3?5h ) d0 ra0 replace ma13 ( active low ) d1 ra1 replace ma14 ( active low ) d2 hor.retrace select ( 0/normal, 1/double scan ) d3 memory address count by 2 ( 0/byte refresh, 1/word refresh ) d4 reserved d5 address wrape ( 0/ma13:64k, 1/ma15: 256k ) d6 word/byte mode ( 0/normal, 1/ma13 or ma15 replace ma0 ) d7 hardware reset ( active low , reset vr and hr )
p.46 line compare register ( cr18 : rw/3?5h) d0-7 low order compare line number bit 0-7 ( 10 bits total ) * graphics registe graphics address register ( gfxidreg : rw/3ceh ) d0-4 graphics address bit 0-4 d5-7 reserved set/reset register ( gr00 : rw/3cfh ) d0-3 set/reset map bit 0-3 d4-7 reserved enable set/reset register ( gr01 : rw/3cfh ) d0-3 enable set/reset map bit 0-3 d4-7 reserved color compare register ( gr02 : rw/3cfh ) d0-3 colore compare map bit 0-3 d4-7 reserved data rotate register ( gr03 : rw/3cfh ) d0-2 rotate count bit 0-2 d3 function select bit 0 ( 00/unmodified, 01/anded ) d4 function select bit 1 ( 10/ored, 11/xored ) d5-7 reserved read map select register ( gr04 : rw/3cfh ) d0 map select bit 0 ( 00/map 0 , 01/map 1 ) d1 map select bit 1 ( 10/map 2 , 11/map 3 ) d2-7 reserved graphics mode register ( gr05 : rw/3cfh ) d0 write mode bit 0 ( 00/dirct write, 01/latch write ) d1 write mode bit 1 ( 10/packed write, 11/sr write ) d2 reserved d3 read type ( 0/map select read, 1/color compare read ) d4 odd/even ( active high, for text mode ) d5 shift register ode ( for cga mode 4,5 ) d6 256 color mode ( active high ) d7 reserved graphics misc. register ( gr06 : rw/3cfh ) d0 graphics enable ( active high ) d1 chain odd and even maps d2 memory address select ( 00/a0000-bffff, 01/a0000-affff ) d3 memory address select ( 10/b0000-b7fff, 11/b8000-bffff ) d4-7 reserved
p.47 color dont care register ( gr07 : rw/3cfh ) d0-3 plan 0-3 color dont care d4-7 reserved bit mask register ( gr08 : rw/3cfh ) d0-7 mask data bit 0-7 * attribute registers attribute address register ( atridreg : rw/3c0h ) d0-4 graphics address bit 0-4 d5 palette address source ( 0/cpu, 1/crtc ) d6-7 reserved pallete register ( ar00-ar0f : r/3c1h, w/3c0h ) d0-5 p0-5 d6-7 reserved attribute mode control register ( ar10 : r/3c1h, w/3c0h ) d0 graphics/text mode select ( 0/text, 1/graphics ) d1 color/mono emulation ( 0/color , 1/mono ) d2 enable line graphics characters ( acsii c0-df, active high ) d3 attribute code ( 0/select ackground, 1/enable blink ) d4 reserved d5 pel panning compatiblity with the line compare ( active high ) d6 pel width ( 0/normal, 1/256 colors ) d7 p5/p4 select source ( 0/normal, 1/color select reg. ) over-scan color register ( ar11 : r/3c1h, w/3c0h ) d0-7 over scan color bit 0-7 color plan enable register ( ar12 : r/3c1h, w/3c0h ) d0-3 enable plan 0-3 d4 video status mux bit 0 ( 00/p2-p0, 01/p5-p4 ) d5 videl status mux bit 1 ( 10/p3-p1, 11/p7-p6 ) d6-7 reserved horizontal pel panning register ( ar13 : r/3c1h, w/3c0h ) d0 horizontal pel panning bit 0-3 d4-7 reserved color select register ( ar14 : r/3c1h, w/3c0h ) d0-3 select color 4-7 d4-7 reserved
p.48 backward compatible register description the following registers are TP6508 backward compatible registers. these registers are accessed by first writing the index of the desired register to the sequencer index register, i.e. address hex 3c4 and then accessing the register using the address hex 3c5. specially , these are not protected by password/identification register (extended index register hex 05) . extended indexed register creg 05 : password/identification register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. write operation (=> hex 86) : d0-7 password read operation (=> hex 0b for correct password or hex f4 for incorrect passward): d0-4 identification code d5-7 chip version code with the password register, the TP6508 protects the extended register to avoid incorrectly application program- ming. when user wants to access the extended registers, he must first write hex 86 to this register to unlock the protection. when user reads the content of this register, he can get a value of hex 0b that is used to distinguish the TP6508. to enable the protection operation by writing other values into the register , and you can read back a value of hex f4. extended indexed register sreg 06 : extended memory bank misc. register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 enable bank c and bank d d1 disable dual bank (window) operation for bank c and d d2 enable read/write bank operation d3-7 reserved bit 0 for compatibility with the hm86305 that has only three bit bank select for up to 512k- byte display memory, a logical 0 directs the bank selection from bank a , bank b or both. when this bit is set to a logical 1, the TP6508 enables both bank c & d and bank a & b. bit 1 refer the sreg 09 bit 0-5 description. this bit is used to select the bank d location address from hex. a0000 to hex. affff or from hex b0000 to hex bffff . a logical 0 selects bank d addressing in hex. b0000 to hex. bffff. bit 2 a logical 1 forces bank c in write access operation and bank d in read access operation only. bank c & d are both location at address hex. a0000 to affff . a logical 0 doesn't enable it. bit-2 bit-1 bit-0 memory bank & segment selection 0 0 0 bank a&b r/w access by segment address a000&b000 0 0 1 bank c&d r/w access by segment address a000&b000 0 1 0 bank a r/w access by segment address a000 only 0 1 1 bank c r/w access by segment address a000 only 1 x x bank c write access & bank d read access by segment address a000 bit 3-7 reserved.
p.49 extended indexed register sreg 07 : cpu start address register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-3 cpu start address bit 0 to 3 d4-7 reserved bit 0-3 these bit are used to set the cpu start address that specifies the offset from original address point to the first byte of bank 0. it can solve the bank(window) boundary problem. the unit size of cpu start address is in 4 kb, so we can adjust the offset address domain from 0 to 60 kb. bit 4-7 reserved. extended indexed register sreg 08 : extended memory bank c select register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-4 memory bank c select bit 0 to 4 d5-7 reserved bit 0-4 when the TP6508 is configured with over 512k-byte display memory, a segment memory i.e. , 64k- byte, only access a small part of the display region. these bits help the user to access the remaining pixel data. when the user wants to move lots of pixel data from one bank to another, the microproces- sor suffers from executing i/o write to modify the content of the bank select register. with its dual and overlapping windowsarchitecture, operations performance has improved drastically.each window is associated with a four-bit bank select register. when the user wants to translate a good deal of pixel data from one bank to another, he can programs two bank registers before translation once instead of the modifying every pixel data movement. these bits are associated with the window down address region from hex a0000 to hex affff. bit 5-7 reserved. extended indexed register sreg 09 : extended memory bank d select register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-4 memory bank d select bit 0 to 4 d5-7 reserved bit 0-4 these bits perform the same function as with the previous register except that they are associated with the window down address region from hex b0000 to hex bffff under sreg 06 bit-1 being set to logical 0. when sreg 06 bit-1 is set to logical 1, they are associated with the same address region from hex a0000 to hex affff. bit 5-7 reserved. extended indexed register sreg e0,e1,e2 : scratched register 1,2,3 this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 reserved
p.50 extended indexed register sreg ee : memory bank select register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 dual window operation enable d1-3 select bank b bit 0 to 2 d4-6 select bank a bit 0 to 2 d7 reserved=1 vga subsystem enable register this is a read/write register. port address is hex 3c3 or hex 46e8 selected by vga subsystem enable port select control bit that comes from extended indexed reg. hex ce bit 4. default value after hardware reset is selected by extended indexed reg. hex ce bit 5. if this bit is a logical 1 , and then the value is hex 00 when the port address is hex 3c3 or is hex 00 when the port address is hex 46e8. if this bit is a logical 0 , and then the value is hex 01 when the port address is hex 3c3 or is hex 08 when the port address is hex 46e8. d0 vga subsystem enable ( for port hex 3c3) d1-2 reserved d3 vga subsystem enable ( for port hex 46e8) d4-7 reserved
p.51 extended sequencer register description the following registers are TP6508 extended sequencer registers. these registers are accessed by first writing the index of the desired register to the sequencer index register, i.e. address hex 3c4 and then accessing the register using the address hex 3c5. these regis- ters are protected by password/identification register (extended index register hex 05) . extended indexed register sreg c0: vga control register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 enable cpu write buffer d1 disable vga palette snooping for vesa local bus d2 enable linear addressing d3 enable memory map i/o d4 enable graphics engine read/write d5 graphics engine active enable d6 enable vafc interface d7 enable vafc pclk output divided by 2 bit 0 TP6508 support cpu write buffer to improve the performance when cpu writes a data into video memory . a logical 1 enables this function, a logical 0 disables it. bit 1 a logical 0 enables TP6508 snoops vga palette write for vesa local bus . a logical 0 disables it. bit 2 ibm compatible display address uses low base 1m address bit 0 to 19 and locates at hex a0000 to affff or hex b0000 to bffff . a logical 1 enables TP6508 to remape display memory in continu- ously linear address at over the base 1m-byte address . a logical 0 disables it and forces TP6508 in bank memory addressing on enhanced display mode. bit 3 by base addressing, we can used the reg. sreg f0 and sreg f1 to assign the base low address . (see the reg. description of sreg f0 and sreg f1) then TP6508 can access these registers with 16-bit data width by decoding at them, being conjunction with 'x..' and 'y..' , directly. by memory map i/o addressing forces TP6508 uses memory command accessing to access i/o command and remapes i/o command address on where are determined by memory mapping i/o command offset register ( see the reg. description of sreg d8). bit 3 addressing mode 0 base addressing 1 memory i/o addressing bit 4 a logical 1 enables to access the graphics engine control registers. bit 5 a logical 1 enables TP6508's graphics engine in operated mode. a logical 0 disables it . bit 6 a logical 1 enables TP6508 implement vafc interface. bit 7 a logical 1 forces TP6508 output pclk frequency divide by two for vafc. extended indexed register sreg c1 : extended mode select register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 enhanced 16 color mode enable d1 enhanced 256 color mode enable d2 enable 32k super-colors mode d3 enable 64k super-colors mode d4 enhanced 16.8m color enable
p.52 d5 enable 132 column text mode d6 enable interlace display d7 enable bank memory addressing on enhanced 16-color display bit 0 a logical 1 directs the TP6508 to work in the enhanced 16 color mode. bit 1 a logical 1 forces the TP6508 to display the 256 color except the mode 13. bit 2 when bit-1 was set to logical 1, we can force the build-in internal ramdac to support hicolor-15 tm compatible display mode architecture by setting this bit to logical 1. bit 3 when bit-1 was set to logical 1, we can force the build-in internal ramdac to support hicolor-16 tm compatible display mode architecture by setting this bit to logical 1. bit 4 when bit-1 was set to logical 1, we can force the build-in internal ramdac to support hicolor-24 tm compatible color display mode architecture by setting this bit to logical 1. bit 5 a logical 1 directs the TP6508 to display 132 columns text mode. bit 6 a logical 0 directs the TP6508 to perform a non-interlaced display mode. a logical 1 enables a interlaced display mode to fit the synchronous frequency of the monitor. bit 7 a logical 1 directs TP6508 to display enhanced 16-color mode by bank memory addressing. a logical 0 directs TP6508 to display enhanced 16-color mode by location continuous 128k-byte memory at a0000 to bffff. extended indexed register sreg c2: clock select register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-1 extended clock select bit 0 to 1 d2-3 reserved d4 enable extended clock select bit 0 and bit 1 d5 acti statue/data d6 acti pin(pin 53) output control d7 select 16.8m color mode in four-byte architecture bit 0-1 when the bit-4 was set to logical 1, these two bits replace the miscreg bit 2-3. the bit-0 or miscreg bit-2 is used to select the internal vclk clock synthesizer programming regs. set for deciding video clock frequency. miscreg bit-2 or sreg c2 bit-0 selected regs. group 0 : use the sreg c3,c5 1 : use the sreg c4,c6 bit 2-3 reserved. bit 4 a logical 1 directs previous two bits as the video clock select signals. a logical 0 inhibits the function of extended clock select bit 0 and 1. bit 5 this bit is reflected the acti pin status. when acti is redefined as user control output that is configured by bit 1, this bit determins the data output on acti pin. bit 6 when sreg d0 bit 6=1,sreg d9 bit 1-0=11, this bit can select acti pin(pin 53) output function as following: bit 6 acti pin function 0 acti output. acti responces high during vaild vga access operations. 1 user control output. output data from sreg c2 bit 5. bit 7 ture color(16.8m color) display mode memory access architecture selection: bit 7 16.8m color mode architecture selection 0 in three-byte memory architecture. 1 in four-byte memory architecture..
p.53 extended indexed register sreg c3 : vclk0 numerator value register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 9c. d0-6 vclk0 numerator bit 0 to 6 d7 vclk0 oscillation divider bit 0-6 this register,in conjunction with vclk0 denominator and post scalar value register, is used to determine the frequency of video clock. these 7 bits numerator (n), 7 bits denominator (d), and 1 bit post scalar (p), for each clock (vclk) determines its frequency according to the following expression: osc x [n+1] x [2p+2] vclk(mhz) = [d+1] , osc= 14.318 (mhz) bit 7 this bit is used to divide the internal generated oscillation frequency. a logical 0 indicates to do it divided by two. a logical 1 indicates to do it divided by four. normally, we set to logical 1 when vclk0 outputs frequency lower 50mhz. extended indexed register sreg c4 : vclk1 numerator value register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex a8. d0-6 vclk1 numerator bit 0 to 6 d7 vclk1 oscillation divider bit 0-6 this register,in conjunction with vclk1 denominator and post scalar value register, is used to determine the frequency of video clock . bit 7 this bit is used to divide the internal generated oscillation frequency. a logical 0 indicates to do it divided by two. a logical 1 indicates to do it divided by four . normally, we set to logical 1 when vclk1 outputs frequency lower 50mhz. extended indexed register sreg c5 : vclk0 denominator and post scalar value register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 83. d0 vclk0 post scalar d1-7 vclk0 denominator bit 0 to 6 bit 0-7 this register,in conjunction with vclk0 numerator value register, is used to determine the fre- quency of video clock. extended indexed register sreg c6 : vclk1 denominator and post scalar value register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex a3. d0 vclk1 post scalar d1-7 vclk1 denominator bit 0 to 6
p.54 bit 0-7 this register,in conjunction with vclk0 numerator value register, is used to determine the frequency of video clock. extended indexed register sreg c7 : crt fifo threshold register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-3 crt fifo threshold high bit 0 to 2 (default = 0, point to actual value 4) d4-7 crt fifo threshold low bit 0 to 2 (default = 0, point to actual value 3) bit 0-3 in the TP6508, memory cycle allocation is dynamic. when fifo accumulated data is larger than fifo threshold high value, cpu cycle can occur without any wait state. bit 4-7 when cpu access video memory, it must depend on remainder data of crt fifo . when the number of crt fifo data is less than the fifo threshold low value, the only one thing can do is crt access. threshold value affects the performance of TP6508. extended indexed register sreg c8 : attribute fifo threshold register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-2 a ttribute fifo threshold bit 0 to 2 (default = 0, point to actual value 1) d3-7 reserved bit 0-2 this dynamic memory cycle allocation architecture is used in TP6508 . specially, in text mode we integrate the attribute fifo storing attribute data in order to improve performance in text mode. bit 3-7 reserved extended indexed register sreg c9 : mclk numerator value register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex a1. d0-6 mclk numerator bit 0 to 6 d7 mclk oscillation divider bit 0-6 this register,in conjunction with mclk denominator and post scalar value register, is used to de- termine the frequency of video clock. these 7 bits numerator (n), 7 bits denominator (d), and 1 bit post scalar (p) for clock (mclk) determines its frequency according to the following expression: osc x [n+1] x [2p+2] mclk(mhz) = [d+1] , osc= 14.318 (mhz) bit 7 this bit is used to divide the internal generated oscillation frequency. a logical 0 indicates to do it divided by two. a logical 1 indicates to do it divided by four . normally, we set to logical 1 when mclk outputs frequency lower 50mhz. extended indexed register sreg ca : mclk denominator and post scalar value register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 4d. d0 mclk post scalar d1-7 mclk denominator bit 0 to 6
p.55 bit 0-7 this register,in conjunction with mclk numerator value register, is used to determine the frequency of memory clock. extended indexed register sreg cb: clock generator test register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-1 mclk/vclk signal output from off pin enable d2-3 vclk generated selection select mclk as vclk source d4 enable pixel clock divide by two for tv display d5 mclk frequency synthesizer off enable d6 vclk frequency synthesizer off enable d7 oscillator off enable bit 0-1 these bits are used to select mclk/vclk signal output from off pin. bit 1 bit 0 output signal from off pin 0 0 other signal 0 1 internal mclk signal 1 x internal vclk signal bit 2-3 these bits are used to select vclk clock source . bit 3 bit 2 vclk generated selection 0 0 from vclk frequency synthesizer 0 1 mclk synthesizer output dividing by 2 as the vclk 1 0 vclk synthesizer output dividing by 2 as the vclk 1 1 from mclk frequency synthesizer bit 4 a logical 1 forces TP6508 video clock frequency divide by two to generated the composite sync. signal for tv display . bit 5 a logical 1 forces TP6508 to power off mclk frequency synthesizer. bit 6 a logical 1 forces TP6508 to power off vclk frequency synthesizer. bit 7 a logical 1 forces TP6508 to power off oscillator. extended indexed register sreg cc: misc. control register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 dac monitor senser off enable d1 dac off enable d2 synchronous reset timing generator d3 vga palette off enable d4-5 host bus memory access data bus select d6 emulation 16-bit access disable for 16 color display modes d7 bypass internal pallete enable bit 0 a logical 1 forces TP6508 to power off monitor sense logical block. bit 1 a logical 1 forces TP6508 to power off dac block and disable crt display refresh. bit 2 when logical 1 we can used this bit to reset TP6508 timing generator and synchronize the internal state machine. bit 3 a logical 1 forces TP6508 vga palette power off. bit 4-5 these bits are used to set the host bus memory access data width.
p.56 bit 5 bit 4 data width 0 0 8-bit 0 1 16-bit 1 0 32-bit 1 1 32-bit or 16-bit bit 6 this bit is used to set the host-to-display memory bus width on 16 color modes. a logical 1 enables TP6508 to expand to 16-bit data bus access. a logical 0 forces TP6508 to access in 8-bit data bus. bit 7 a logical 1 forces the pixel data bypass the internal palette and transfer through a special logical block to do as internal palette. in high speed video clock mode , the lookup internal palette operation is critical . extended indexed register sreg cd: display memory register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-1 display memory configuration d2 asymmetical/symmetical address select for dram-a & b d3 dual-write/dual-cas select for dram-a & b d4 asymmetical/symmetical address select for dram-c d5 dual-write/dual-cas select for dram-c d6 enable 2m-byte display memory size d7 reserved bit 0-1 these bit are used to configure the drams interface. bit 1 bit 0 display memory bus width & configuration 0 0 32-bit, enable dram-a & dram-b interface 0 1 16-bit, enable dram-a only 1 0 32-bit, enable dram-a & dram-c interface * 1 1 reserved (*: dram-c isn't used as an external frame buffer with this setting, but does as display memory.) bit 2 a logical 0 indicates TP6508 to support symmetical dram memory addressing for dram-a & b. a logical 1 indicates TP6508 to support asymmetical dram memory addressing. bit 3 a logical 0 indicates TP6508 to support dual-cas dram memory addressing for dram-a & b. a logical 1 indicates TP6508 to support dual-write dram memory addressing. bit 4 a logical 0 indicates TP6508 to support symmetical dram memory addressing for dram-c. a logical 1 indicates TP6508 to support asymmetical dram memory addressing. bit 5 a logical 0 indicates TP6508 to support dual-cas dram memory addressing for dram-c. a logi- cal 1 indicates TP6508 to support dual-write dram memory addressing. bit 6 a logical 1 enables TP6508 is operated on 2m-byte size memory configuration . under the con- dition , TP6508 will adjust some of the counter length of the crtc and size again the domain of display memory address. bit 7 reserved. extended indexed register sreg ce: configuration register 1 this is a read only register. port address is hex 3c5. default value after hardware reset is hex ff. (chip internal pull high during power on reset) d0 enable bios romcs* signal output from off pin d1 enable 64k vga bios decoding d2 relocation vga bios address
p.57 d3 enable io 16 bit access d4 vga subsystem enable port address set to hex46e8(default 3c3) d5 select vga subsystem power-on in enable state d6 enable isa bus width 8 bit d7 select sa address decoder (these bits are latched from mad0 to mad7 at power on reset.) bit 0 when bus interface was selected vesa/cpu direct local bus connection , then this can set to logical 1 to enable bios romcs* signal output from off/eprom* pin(pin 178). bit 1 we can set this bit to logical 0 to enable TP6508 bios decoding to expansion to 64 kb address do- main. bit 2 when previous bit was set to logical 1, then this bit can be setting to relocate vga bios decoding address. bit 2 decoding address 0 hex e0000 to effff 1 hex c0000 to cffff bit 3 a logical 0 enables TP6508 io 16 bit access. bit 4 this bit selects the address of the video subsystem enable bit location. a logical 0 indicates the ad- dress of the video subsystem bit is hex 46e8 , a logical 1 indicates that it is located on the address hex 3c3. bit 5 a logical 0 indicates TP6508 power-on in the enable state that allows memory and io accessing . a logical 1 indicates TP6508 in the disable state at power-on. bit 6 a logical 0 forces TP6508 connects to 8 bit width host bus . a logical 1 forces TP6508 connects to 16 bit width host bus. bit 7 a logical 1 indicates TP6508 use ale signal to latch la address signal . a logical 0 indicates TP6508 directs to decode sa address by bus command signals (memw*,memr*,iow*,ior*) . extended indexed register sreg cf: configuration register 2 this is a read only register. port address is hex 3c5. default value after hardware reset is hex ff. (chip internal pull high during power on reset) d0-2 TP6508 into test mode selection bit (latched from md 4 to 5) d3 reserved d4-7 display type selection bits (these bits are latched from mad8 to mad15 at power on reset.) bit 0-2 these bit is used to enable TP6508 into test mode for the internal analog device blocks, including of the dual frequency synthesizer and ramdac . we can directly access the internal analog device blocks by TP6508's i/o pins. bit 2 bit 1 bit 0 test device 1 1 0 mclk analog device function test mode 1 0 1 vclk analog device function test mode 0 1 1 dac analog device function test mode bit 3 reserved. bit 4-7 these bits are used to read back for vga bios setting display type . bit-7 bit-6 bit-5 bit-4 display type 0 0 0 0 ntsc tv 0 0 0 1 lcd/ntsc tv 0 0 1 0 800x600 color tft 0 0 1 1 800x600 color dstn 0 1 0 0 crt-like tft 0 1 0 1 dual-scan stn lcd 0 1 1 0 800x600 color tft
p.58 0 1 1 1 800x600 color dstn 1 0 0 0 crt/plasma 1 0 0 1 crt/el 1 0 1 0 crt/line-clock tft 1 0 1 1 crt/crt-like tft 1 1 0 0 crt/single-scan stn lcd 1 1 0 1 crt/dual-scan stn lcd 1 1 1 0 crt/mono lcd 1 1 1 1 crt extended indexed register sreg d0: configuration register 3 this is a read only register. port address is hex 3c5. default value after hardware reset is hex ff. d0-2 host bus selection bit 0 to 2 (latched from aa0 to aa2) d3 disable a24 pin input data latch (latched from aa3) d4 disable internal dual frequency synthesizer (latched from aa4) d5 reserved (latched from aa5) d6 reserved=1 (latched from aa6) d7 disable pci bus command asserted on configuration registers accessing (latched (latched from aa7) bit 0-2 in addition to an isa bus connection, TP6508 can be connected directly to vesa local bus , pci local bus or 486dx/dx2 local bus to provide additional graphics performance. bit 2 bit 1 bit 0 host bus selection 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 reserved 1 0 1 isa bus 1 1 0 32-bit pci local bus 1 1 1 reserved bit 3 a logical 1 enables TP6508 to decode a24 pin input for linear address . this configuration bit must set to 1 for vesa/cpu local bus . bit 4 a logical 0 forces TP6508's internal dual frequency synthesizer not in operation. that make TP6508 to select the multiple pin off and xtali as vclk and mclk pin . the source of video clock and memory clock are come from external component by vclk and mclk pin . bit 5 reserved. bit 6 reserved. bit 7 we can set this bit to logical 0 to force TP6508 not to assert a vga access cycle on pci local bus interface under the configuration read or write command being happend.. extended indexed register sreg d1: gec. test register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 reserved bit 0-7 reserved.
p.59 extended indexed register sreg d2: power management control register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 reserved d1 select off pin as input pin d2 select off pin control as active high control signal d3 select standby timer as suspend timer d4 force into standby mode d5 force into suspend mode d6 force into off mode d7 select cover-close mode (crt display only this bit must =1) bit 0 reserved. bit 1 a logical 1 select off pin as input pin, and a logical 0 select it as output pin. bit 2 a logical 0 select off pin signal polarity as active low, and a logical 1 select off pin signal polarity as active high. bit 3 a logical 1 select standby timer as suspend timer, then we can program this timer to change state from active mode to suspend mode and not to standby mode. a logical 0 we can program this timer to change state from active mode to standby mode. bit 4 user can to change state from active mode to standby mode by software programming this bit to logical 1. bit 5 user can to change state to suspend mode by software programming this bit to logical 1. bit 6 user can to change state to off mode by software programming this bit to logical 1. bit 7 a logical 1 select into cover-close mode. cover-close mode is the special power mode using for laptop pc or notebook pc system on closing the machine-cover . specially, this mode replace off mode when the user programmed this bit to logical 1 . in cover-close mode, system will turn off panel backlight, and down saving internal partial panel block device power. then the crt display is normal. extended indexed register sreg d3: backlight and standby timer register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-3 timer for backlight control bit 0 to 3 (unit : 1 minute error -1/16 minute) d4-7 timer for standby/suspend control bit 0 to 3 (unit : 2 minute error -1/8 minute) (user can use the value of 00 to disable the timer for power management .) bit 0-3 these bits are used to program the time that panel's backlight turn off after active mode into standby mode . the timer clock base is 14.318mhz for internal c.g. or external osc. pin clock input divided by 4 . bit 4-7 these bits are used to program the time that active mode go into standby/suspend mode after the system was in the rest state. extended indexed register sreg d4 : activity monitoring register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 enable vga access to reset backlight timer d1 enable keyboard activity to reset backlight timer d2-3 reserved d4 enable vga access to reset standby/off timer
p.60 d5 enable keyboard activity to reset standby/off timer d6-7 reserved bit 0 a logical 1 enables TP6508 to reset backlight timer for flat panel by vga access. bit 1 a logical 1 enables TP6508 to reset backlight timer for flat panel by keyboard activity. bit 2-3 reserved bit 4 a logical 1 enables TP6508 to reset standby timer for flat panel by vga access. bit 5 a logical 1 enables TP6508 to reset standby timer for flat panel by keyboard activity. bit 6-7 reserved extended indexed register sreg d5 : off timer and slow refresh register this is a read only register. port address is hex 3c5. default value after hardware reset is hex 00. d0-3 timer for off control bit 0 to 3 (unit : 4 minute error -1/4 minute) d4 enable slow refresh in off mode d5-6 slow refresh rate selection bit 0 to 1 d7 select external 32khz clock as power management clock base bit 0-3 these bits are used to program the time that active mode go into off mode after the system was in the rest state. bit 4 a logical 1 enables TP6508 to slow down the refresh rate that specifies by next two bits in the off mode. bit 5-6 when TP6508 goes into off mode , it provide programmable refresh rate for power saving . bit 6 bit 5 refresh rate (khz) 0 0 no refresh 0 1 32 1 0 16 1 1 8 bit 7 user can use this bit to select the power management clock source. a logical 0 TP6508 selects the internal refresh clock base being divided the frequency of 14.318mhz clock source . and a logical 1 TP6508 switches the clock source to external 32khz clock input. extended indexed register sreg d6 : override and status control register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 fpback output override d1 fpback polarity d2 fpvcc/fpsig/fpvee output override d3 fpvcc status d4 fpsig output status d5 fpvee output status d6 panel control state machine test mode enable d7 fpvee pin(pin 61) output control bit 0 a logical 1 indicates TP6508 would override fpback standby mode. bit 1 if previous bit =1, then programming this bit would set the output state of fpback. if previous bit =0, then bit is used to invert the fpback output polarity. bit 2 a logical 1 indicates TP6508 would override fpvcc standby mode .
p.61 bit 3 if previous bit =1 , then programming this bit would set the output state of fpvcc. bit 4 if bit2 =1 , then programming this bit would set the output state of panel control signal (fpvdclk,mod,lfs,llclk,de*) and panel data bus. a logical 0 forces TP6508 set these output to logical 0 . a logical 1 indicates these signals output normal . bit 5 if bit2 =1 , then programming this bit would set the output state of fpvee. bit 6 the bit is used to enable the panel control state machine into test mode (short the power sequency cycle time) . it is to be enable for internal test only. bit 7 a logical 0 enables TP6508 output fpvee signal from pin 61. a logical 1 enables TP6508 output fpback signal from pin 61. extended indexed register sreg d7 : memory mapping i/o offset low register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 graphics engine memory mapping i/o command offset bit 0 to 7 bit 0-7 when memory map i/o was enabled (sreg bit-3=1), these bits would use to do as the segment ad- dress of i/o command for replacing the address a16 to a23. we can set these bits to relocate the i/ o port address of graphics engine registers. by memory map i/o addressing, these registers are accessed as memory command and located at memory address binary zzzz,zzzz,zzzz,xxxx,xxyy,yyyy,yy00. the address value - 'z..' is determined by this register and sreg d8. the low address value - 'y..' is determined by sreg f0. the address value - 'x..' is determined by the graphics engine control register indexed value. then TP6508 can access these registers with 16-bit data width by decoding at them, being conjunction with 'y..' and 'x..' , directly. extended indexed register sreg d8 : memory mapping i/o offset high register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-3 graphics engine memory mapping i/o command offset bit 8 to 11 d4-7 reserved bit 0-7 when memory map i/o was enabled, these bits would use to do as the segment address of i/o command for replacing the address a24 to a27. extended indexed register sreg d9 : pc video control register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0 enable pc video interface d1 select pc video width d2 enable pc video color key d3-7 reserved bit 0 a logical 1 enables pc video interface on dram-c pins that includes of rasc* ,casch* ,cascl* ,wec* , mcd[15:0]. a logical 0 disables it. bit 1 when previous bit is set to logical 1, this bit is used to select the pc video interface width. a logical 0 forces TP6508 inplements a 18-bit width pc video interface. a logical 1 enables TP6508 inplements a 24-bit width pc video interface and sets oec*,aa9,fpback,acti as video input. when this bit is set to logical 1, a 24-bit panel interface is also avilable by ca[7:0] being becomed p[23:16]. spe- cially, this bit shouldn't be set to 1 if the sreg d0 bit-6 is set to 1.
p.62 bit 2 if the previous bit-0 is set to logical 1 , then this bit is used to select the color key type for pc video overlay . a logical 1 forces TP6508 use external color key signals and enables pc video overlay on color key. a logical uses the following color compare registers to generate the color key . bit 3-7 reserved. extended indexed register sreg da : color key compare register 0 this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 color compare data bit 0 to 7 bit 0-7 these bits are compared to bit 0 to 7 of background video stream. they are in conjunction with color compare bit 8 to 15 and color compare bit 16 to 23 to compare with color key data. when all the enabled bits that are set by mask regs. sreg db/dc/dd matches the relation color key data bits and the key is enabled, external video sent to the screen. extended indexed register sreg db : color key compare register 1 this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 color compare data bit 8 to 15 bit 0-7 these bits are compared to bit 8 to 15 of background video stream. they are in conjunction with color compare bit 0 to 7 and color compare bit 16 to 23 to compare with color key data. when all the enabled bits that are set by mask regs. sreg db/dc/dd matches the relation color key data bits and the key is enabled, external video sent to the screen. extended indexed register sreg dc : color key compare register 2 this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 color compare data bit 16 to 23 bit 0-7 these bits are compared to bit 16 to 23 of background video stream. they are in conjunction with color compare bit 0 to 7 and color compare bit 8 to 15 to compare with color key data . when all the enabled bits that are set by mask regs. sreg db/dc/dd matches the relation color key data bits and the key is enabled, external video sent to the screen. extended indexed register sreg dd : color key mask register 0 this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 color compare mask bit 0 to 7 bit 0-7 these bits are used to select which bits of the background video data stream are used in the comparsion with the color compare data bit 0 to 23. this register control bits 0 to 7. the mask data bits format are as follow: 0: data does particpate in compare operation 1: data mask in compare operation
p.63 extended indexed register sreg de : color key mask register 1 this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 color compare mask bit 8 to 15 bit 0-7 these bits are used to select which bits of the background video data stream are used in the comparsion with the color compare data bit 0 to 23. this register control bits 8 to 15. extended indexed register sreg df : color key mask register 2 this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 color compare mask bit 16 to 23 bit 0-7 these bits are used to select which bits of the background video data stream are used in the comparsion with the color compare data bit 0 to 23. this register control bits 16 to 23. extended indexed register sreg f0 : graphics engine port address low register this is a read only register. port address is hex 3c5. default value after hardware reset is hex f1. d0-7 graphics engine port address bit 2 to 9 bit 0 -7 TP6508 graphics engine control registers are accessed at port binary address xxxx,xxyy,yyyy,yy00. these bits are used to determine the low address value - 'y..' and they are set default hex. f1. the high address value - 'x..' is determined by graphics engine control registers indexed value. for example, as default value hex. f1, bitblt source x offset reg. port address at hex. 07c4. extended indexed register sreg f1 : linear addressing register this is a read/write register. port address is hex 3c5. default value after hardware reset is hex 00. d0-7 base address bit 0 to 7 bit 0-7 when sreg c0 bit-2 was set to logical 1 , then these bits would use to do as la20 to la27. ibm compatible display address uses low base 1m address bit 0 to 19 and locates at hex a0000 to affff or hex b0000 to bffff. we can set these bits to relocate display address at upper high 255m memory address.
p.64 extended cr tc register description the following registers are TP6508 extended crtc registers. these registers are accessed by first writing the index of the desired register to the sequencer index register, i.e. address hex 3d4 and then accessing the register using the address hex 3d5. these registers are protected by password/ identification register (extended sequencer indexed register hex 05) . extended indexed register creg 20 : extended memory address offset register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended memory address offset bit 0 to 7 bit 0-7 in TP6508 interlace display design , you can use this register to program the memory address offset value as the memory length of one scan line to next scan line during odd or even filed for interlace display mode . the bit 8 are in the bit 4 of extended register creg 21. extended indexed register creg 21 : memory address offset high register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0 extended memory address offset bit 8 d1-3 reserved d4-5 ibm memory address offset bit 8,9 d6-7 reserved bit 0 extended memory address offset bit 8. bit 1-3 reserved. bit 4-5 memory address offset bit 8 to 9. bit 6-7 reserved. extended indexed register creg 22 : start address high register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 start address bit 16 to 19 d4-7 cursor address bit 16 to 19 bit 0-3 the most significant bit 16 and bit 19 of the start address register. bit 4-7 the most significant bit 16 and bit 19 of the cursor address register. extended indexed register creg 23 : reserved this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 reserved bit 0-7 reserved.
p.65 extended indexed register creg 24 : crt vertical high register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0 vertical total bit 10 d1 vertical display enable end bit 10 d2 vertical blank star bit 10 d3 vertical retrace start bit 10 d4 line compare bit 10 d5-7 reserved bit 0 bit 10 of the vertical total register. bit 1 bit 10 of the vertical display enable register. bit 2 bit 10 of the vertical blank start register. bit 3 bit 10 of the vertical retrace start register. bit 4 bit 10 of the line compare register. bit 5-7 reserved. extended indexed register creg 25 : half horizontal retrace start register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 half horizontal retrace start bit 0 to 7 bit 0-7 in interlace display mode , TP6508 need a count point that point at half of a scan-line to generate the interlace display timing sequence . and these bits are nice to program doing it , a real interlace display . extended indexed register creg 26 : tv leading horizontal retrace start register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 tv leading horizontal retrace start bit 0 to 7 bit 0-7 by tv display, it was designed to base on the interlace scan technique, TP6508 need two retrace signal(like vga retrace signal) on even field and odd field. tv composite sync. signal waveform in- clude two equalizing pulse interval, front and back the vertical sync. interval, those have three pulse individually. we need to define the intervals position in the tv composite sync. waveform. so we can use these bits to program the front equalizing pulse(front of horizontal sync. pulse interval ) start position. on even field and make it be able using in tv display mode. extended indexed register creg 27 : tv horizontal retrace end for equalizing pulse register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 tv horizontal retrace end bit 0 to 3 d4-7 reserved bit 0-3 these bits is used to program the back equalizing pulse(back of horizontal sync. pulse interval ) start position. on even field and make it be able using in tv display mode.
p.66 bit 4-7 reserved . extended indexed register creg 28 : tv leading half horizontal retrace start reg- ister this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 tv leading half horizontal retrace start bit 0 to 3 d4-7 reserved bit 0-3 by tv display, it was designed to base on the interlace scan technique, TP6508 need two retrace signal(like vga retrace signal) on even field and odd field. tv composite sync. signal waveform in- clude two equalizing pulse interval, front and back the vertical sync. interval, those have three pulse individually. we need to define the intervals position in the tv composite sync. waveform. so we can use these bits to program the front equalizing pulse(front of horizontal sync. pulse interval ) start position. on even field and make it be able using in tv display mode. bit 4-7 reserved . extended indexed register creg 29 : tv half horizontal retrace end for equaliz- ing pulse register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 tv leading half horizontal retrace end bit 0 to 3 d4-7 reserved bit 0-3 these bits is used to program the back equalizing pulse(back of horizontal sync. pulse interval ) start position. on odd field and make it be able using in tv display mode. bit 4-7 reserved .
p.67 panel contr ol register description the following registers are TP6508 panel control registers. these registers are accessed by first writing the index of the desired register to the sequencer index register, i.e. address hex 3d4 and then accessing the register using the address hex 3d5. these registers are protected by password/ identification register (extended index register hex 05) . extended indexed register creg a0 : panel miscellaneous control register 1 this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-2 flat panel type 0 to 2 d3 invert lp/phsync control d4 invert flm/pvsync control d5 invert fpvdclk/psclk d6 free run llclk d7 invert den control bit 0-2 these three bits select the type of flat panel connected. bit 2 bit 1 bit 0 panel type 0 0 0 dual-scan/dual-data monochrome lcd panels 0 0 1 gray scale plasma panels 0 1 0 single-scan stn color lcd panels 0 1 1 tft color lcd panels 1 0 0 reserved 1 0 1 gray scale el panels 1 1 0 dual-scan stn color lcd panels 1 1 1 reserved bit 3 a logical 1 would invert the llclk signal (normally active high). bit 4 a logical 1 would invert the lfs signal (normally active high). bit 5 a logical 1 would invert the fpvdclk signal (normally active high). bit 6 the last line of every frame may display longer and brighter than other lines. when this bit is a logical 1 , it forces TP6508 to generate a free-running llclk and eliminates the brighter line during crt blanking cycle. bit 7 a logical 1 would invert the den signal (normally active high) for plasma or tft panel display mode . extended indexed register creg a1 : panel miscellaneous control register 2 this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0 select 8 bits color stn interface d1 select enhance color stn timing d2 select crt-like lp and flm for tft lcd panel d3 disable crt display d4 enable flat panel interface d5 select 8 bit plasma panel interface
p.68 d6 select gray conversion type for mono flat panel display d7 enable tv display bit 0 a logical 1 TP6508 selects 8 bits color stn interface bit 1 a logical 1 TP6508 switches the panel display timing to enhance color stn timing. bit 2 a logical 1 TP6508 selects crt-like lp(hsync) and flm(vsync) for tft lcd panel. bit 3 a logical 1 disables the crt display , and a logical 0 enables it. bit 4 a logical 1 enables the flat panel display, and a logical 0 disables the flat panel display. bit 5 a logical 1 TP6508 selects 8 bits plasma interface . and a logical 0 TP6508 selects 4 bits plasma interface. bit 6 this bit is use to set the gray conversion type for mono flat panel display . a logical 1 enable it , a logical 0 disable it. bit 7 a logical 1 enables the tv display and we can output composite sync signal to hsync pin. extended indexed register creg a2 : panel miscellaneous control register 3 this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0 reverse panel video output for text mode d1 reverse panel video output for graphic mode d2-3 blinking rate selection bit 0 to 1 d4 select maximum contrast display for text mode d5 select attribute emulation display for text mode d6 select rgbi emulation display for 16 color graphic mode d7 enable full cursor display for text mode bit 0 a logical 1 reverses the pixel data that sends to the panel for text mode . bit 1 a logical 1 reverses the pixel data that sends to the panel for graphic mode . bit 2-3 lcd panel has low response time character, TP6508 provides flexible choice for blinking rate. bit 3 bit 2 blinking rate 0 0 1/16 0 1 1/32 1 0 1/64 1 1 1/128 bit 4 in panel text mode, when foreground rgb and background rgb mapping to the close gray level. it will produce ambiguous phenomenon. when this bit is a logical 1, TP6508 will compare foreground and background mapping gray level. if foreground gray level is larger than background gray level, TP6508 forces foreground to the maximum gray level , background to the minimum gray level . it will eliminate ambiguous situation. if the bit 6 of previous register set to logical 1 , then this bit is not valid . bit 5 when this bit is a logical 1, TP6508 provides 16 gray level without passing through gray palette for text mode . in this mode, red, green, blue, and intensity , four bits can make 16 gray level without losing color, mono mapping relation . bit 6 when this bit is a logical 1, TP6508 provides 16 gray level without passing through gray palette for 16 color graphic mode. bit 7 on lcd panel, a narrow cursor may difficult to observe. a logical 1 forces a full display cursor for easy find out and ignores the cursor sharp setting.
p.69 extended indexed register creg a3 : panel miscellaneous control register 4 this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0 enable vertical expansion for text mode d1 enable vertical expansion for graphic mode d2 force 8 dots character clock d3 enable shadow frame buffer with internal line buffer for mono dual-scan stn lcd d4 enable shadow frame buffer with internal line buffer for color dual-scan stn lcd d5 enable external frame buffer for color dual-scan stn lcd d6 enable extra llclk 244 d7 enable extra llclk 242 bit 0 a logical 1 forces TP6508 to fit the panel vertical resolution for text mode. bit 1 a logical 1 forces TP6508 to fit the panel vertical resolution for graphic mode. bit 2 in panel mode , lcd and plasma manufactures produce 640x480 pixel panel . some ibm standard modes define 9 dots per character , all characters cannot display 80 columns (720 dots) at the same time . when this bit is a logical 1, TP6508 force character width to be 8 dots. bit 3 in monochrome dual-scan stn lcd display,logical 1 enables shadow frame accelerate operation. at this time, TP6508 can gain better display quality and up to 64 gray level. other flat panel display modes this bit is invaild . bit 4 in color dual-scan stn lcd display,logical 1 enables shadow frame accelerate operation. at this time, TP6508 can gain better display quality and up to 64k color level . other flat panel display modes this bit is invaild . bit 5 in color dual-scan stn lcd display, logical 1 enables external frame accelerate operation to gain better display quality. at this time an extra dram(s) is necessary . a logical 0 disables the external frame buffer and TP6508 uses the pseudo frame buffer technique to implement the display mode . other display mode this bit is invaild . bit 6 a logical 1 enables one extra llclk for lcd monochrome panels that require 244 line clocks for the upper panel. bit 7 a logical 1 enables one extra llclk for lcd monochrome panels that require 242 line clocks for the upper panel. extended indexed register creg a4 : lcd ac modulation period register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 lcd ac modulation bit 0 to 7 bit 0-7 ac modulation lcd panel cannot be driven in the dc level. some lcd panel modules do not provide ac modulation signal, TP6508 offers this function to prevent lcd damage. these bits define the number of lp(hsync) between adjacent phase changes on mod output. as these bits are programmed to hex 00, then the mod signal phase changes every frame. extended indexed register creg a5 : panel miscellaneous control register 5 this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0 panel resolution selection
p.70 d1 select 600-line extended crt vertical group registers d2 enable horizontal expansion for text mode d3 enable horizontal expansion for graphic mode d4 enable tv equalizing pulse d5-7 reserved bit 0 this bit is used to select the flat panel resolution .(for vertical expansion and horizontal centering) 0 : 640x flat panel size 1 : 800x flat panel size bit 1 this bit is used to select the extended vertical timing set register group when the bit-1 of creg ac(enable extended vertical timing) was set to logical 1 and the bit-6,7 of miscreg were set to 1,1. the more description is in creg ac bit-1 description. 0 : use the 480-line vertical timing crt regs. creg b6-bc 1 : use the 600-line vertical timing crt regs. creg c7-cd bit 2 a logical 1 forces TP6508 to fit the panel horizontal resolution for text mode. bit 3 a logical 1 forces TP6508 to fit the panel horizontal resolution for graphic mode. bit 4 this bit is used to select the tv composit signal generated type. 0 : no equalizing pulse, it only composits horizontal and vertical sync. 1 : insert equalizing pulse bit 5-7 reserved. extended indexed register creg a6 : reserved this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 reserved extended indexed register creg a7:reserved this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 reserved extended indexed register creg a8 : x offset control register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-4 lcd panel gray modulation x offset bit 0 to 4 d5-6 tft lcd panel amplitude modulation bit 0 to 1 d7 reserved bit 0-4 TP6508 has a special function to eliminate stippling wave . you can program x-directional offset values for best looking. bit 5-6 user can use the amplitude modulation to smooth and get to colorfully by these two bits. bit 6 bit 5 description 0 0 disable amplitude modulation 0 1 select two bits and ground signal modulation (data bit 1 to 0) 1 0 select three bits modulation (data bit 2 to 0) 1 1 select three bits modulation (data bit 3 to 1) bit 7 reserved
p.71 extended indexed register creg a9 : y offset control register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-4 lcd panel gray modulation y offset bit 0 to 4 d5-6 flat panel dithering type bit 0 to 1 d7 dither algorithm selection bit 0-4 TP6508 has a special function to eliminate stippling wave . you can program y-directional offset values for best looking. bit 5-6 user can select the dithering type to smooth and get to colorfully by these two bits. bit 6 bit 5 description 0 0 disable dithering function 0 1 select two bits dithering (data bit 1 to 0) 1 0 select two bits dithering (data bit 2 to 1) 1 1 select two bits dithering (data bit 3 to 2) bit 7 this bit is used to select the dither algorithm method. a logical 0 select the color modulation bit to be the next bit of the two selected dithering bits in bit 5-6 of this register. a logical 1 select the color modulation bit to be the lsb of the color data. extended indexed register creg aa : frame buffer start address high register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 frame buffer start address bit 0 to 3 d4 reserved d5 m pin selection d6 lp pin selection d7 reserved bit 0-3 with integrated frame accelerator technology . TP6508 can use the video memory space as internal frame buffer to replace the external frame buffer . these bits is programming to set the internal frame buffer starting address of video memory. they replace and do as memory address ma14 to ma17. bit 4 reserved. bit 5 this bit is used to select the m pin(pin 69) output function. bit 5 output function 0 m signal output 1 de* signal output bit 6 this bit is used to select the lp pin(pin 68) output function. bit 6 output function 0 lp signal output 1 de* signal output bit 7 reserved. extended indexed register creg ab : line buffer terminal count register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-5 line buffer terminal count bit 0 to 5 (unit : 32 pixels) d6-7 reserved
p.72 bit 0-5 TP6508 has a internal line buffer to store pixel-data of a line for dual flat panel device. specially, the line buffer must work on the condition that TP6508 has turned on panel frame buffer and it do as a temp store of frame buffer. these bits can be programmed to set the line buffer length which base on flat panel horizontal resolution or do for simulation test only. bit 6-7 reserved. extended indexed register creg ac : extended crt control register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0 enable extended horizontal timing set d1 enable extended vertical timing set d2 ibm crt control registers lock d3 half panel timing source selection d4 text mode vertical expansion selection d5 enable 24-bit tft panel interface d6-7 reserved bit 0 a logical 1 forces TP6508 using the extended crt horizontal timing set registers to match or fit the flat panel resolution for lcd or lcd-crt display mode. a logical 0 set TP6508 working on using the ibm crt horizontal timing set registers. bit 1 a logical 0 set TP6508 working on using the ibm crt vertical timing set registers . a logical 1 forces TP6508 using the extended crt vertical timing set registers to match or fit the flat panel resolution for lcd or lcd-crt display mode. then, we can use the miscreg bit 6,7 to select the extended vertical timing set register group. the more description is in creg a5 bit-3 description. miscreg bit-7, bit-6 selected vertical crt register group 0 0 reserved 0 1 use the 400-line vertical timing crt regs. creg c7-cd 1 0 use the 350-line vertical timing crt regs. creg c7-cd 1 1 decided by creg a5 bit-3 bit 2 a logical 1 enables crtc lock to protect the parameter of ibm crt control register. bit 3 a logical 0 inducates TP6508 to generate the half panel timing by setting ext. reg. hex a5 for internal panel controller use . a logical 1 forces TP6508 use the half of vde signal as it by programming the crt reg. hex 12. bit 4 a logical 0 selects to insert a line by counting every 3 or 5 lines for x350 or x400 resolution text mode to fit the vertical resolution of flat panel . a logical 1 selects to insert 5 or 3 line into every character for x350 or x400 resolution text mode to fit the vertical resolution of flat panel . bit 5 a logical 1 enables TP6508 to implement 24-bit panel interface for 18-bit or 24-bit tft panel. a logical 0 forces TP6508 to implement 16-bit panel interface for 9/12/15/16-bit panel. bit 6-7 reserved extended indexed register creg ad : extended crt horizontal total register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt horizontal total bit 0 to 7 (-5 ) extended indexed register creg ae : extended crt horizontal display enable end register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00.
p.73 d0-7 extended crt horizontal display enable end bit 0 to 7 (-1) extended indexed register creg af : extended crt horizontal blanking start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt horizontal blanking start bit 0 to 7 (-1) extended indexed register creg b0 : extended crt horizontal blanking end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-5 extended crt horizontal blanking end bit 0 to 5 d6-7 reserved extended indexed register creg b1 : extended crt horizontal retrace start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt horizontal retrace start bit 0 to 7 extended indexed register creg b2 : extended crt horizontal retrace end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-4 extended crt horizontal retrace end bit 0 to 4 d5-7 reserved extended indexed register creg b3 : reserved this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 reserved extended indexed register creg b4 : extended crt horizontal retrace start for tft lcd panel this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt horizontal retrace start bit 0 to 7 for tft lcd panel extended indexed register creg b5 : extended crt horizontal retrace end for tft lcd panel this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-4 extended crt horizontal retrace end bit 0 to 4 for tft lcd panel d5-7 extended crt horizontal retrace skew bit 0 to 2 for tft lcd panel
p.74 extended indexed register creg b6 : 480-line extended crt vertical total register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt extended crt vertical total bit 0 to 7 (-2) extended indexed register creg b7 : 480-line extended crt vertical display enable end register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt extended crt vertical display enable end bit 0 to 7 (-1) extended indexed register creg b8 : 480-line extended crt vertical blank start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical blank start bit 0 to 7 (-1) extended indexed register creg b9 : 480-line extended crt vertical blank end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical blank end bit 0 to 7 extended indexed register creg ba : 480-line extended crt vertical retrace start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical retrace start bit 0 to 7 extended indexed register creg bb : 480-line extended crt vertical retrace end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 extended crt vertical retrace end bit 0 to 3 d4-7 reserved extended indexed register creg bc : 480-line extended crt vertical overflow this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-1 extended crt vertical total bit 8 to 9 d2-3 extended vertical display enable end bit 8 to 9 for vertical expansion mode d4-5 extended crt vertical blank start bit 8 to 9 d6-7 extended crt vertical retrace start bit 8 to 9
p.75 extended indexed register creg c0 : flat panel 350 scan line mode display center- ing control register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 lcd panel 350 scan line mode screen shift bit 0 to 7 bit 0-7 these bits are used to program the vertical screen shift length from the top or bottom of panel to actual display part on 350 scan line mode. and you can get through the screen display centering. extended indexed register creg c1: flat panel 400 scan line mode display centering control register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 lcd panel 400 scan line mode screen shift bit 0 to 7 bit 0-7 these bits are used to program the vertical screen shift length from the top or bottom of panel to actual display part on 400 scan line mode. and you can get through the screen display centering. extended indexed register creg c2: flat panel 480 scan line mode display centering control register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 lcd panel 480 scan line mode screen shift bit 0 to 7 bit 0-7 these bits are used to program the vertical screen shift length from the top or bottom of panel to actual display part on 480 scan line mode. and you can get through the screen display centering. extended indexed register cregc3 : half panel size low register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 half panel size bit 0 to 7 bit 0-7 these bits use to decide the half panel size (scan lines - 1 ) and make TP6508 generating accurate flat panel interface timing. extended indexed register creg c4 : half panel size high register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0 half panel size bit 8 d1-7 reserved bit 0 this bit is the high bit of half panel size register. bit 1-7 reserved.
p.76 extended indexed register creg c5: flat panel text mode display horizontal center- ing control register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 lcd panel horizontal screen shift bit 0 to 3 for text mode display (in character as unit) d4-7 reserved bit 0-3 these bits are used to program the horizontal screen shift length from the left or right of panel to actual display part. and you can get through the screen display centering . bit 4-7 reserved. extended indexed register creg c6: flat panel graphics mode display horizontal centering control register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 lcd panel horizontal screen shift bit 0 to 3 for graphics mode display ( in character as unit) d4-7 reserved bit 0-3 these bits are used to program the horizontal screen shift length from the left or right of panel to actual display part. and you can get through the screen display centering. bit 4-7 reserved. extended indexed register creg c7 : 600-line extended crt vertical total register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt extended crt vertical total bit 0 to 7 (-2) extended indexed register creg c8 : 600-line extended crt vertical display enable end register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt extended crt vertical display enable end bit 0 to 7 (-1) extended indexed register creg c9 : 600-line extended crt vertical blank start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical blank start bit 0 to 7 (-1) extended indexed register creg ca : 600-line extended crt vertical blank end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical blank end bit 0 to 7
p.77 extended indexed register creg cb : 600-line extended crt vertical retrace start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical retrace start bit 0 to 7 extended indexed register creg cc : 600-line extended crt vertical retrace end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 extended crt vertical retrace end bit 0 to 3 d4-7 reserved extended indexed register creg cd : 600-line extended crt vertical overflow this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-1 extended crt vertical total bit 8 to 9 d2-3 extended vertical display enable end bit 8 to 9 for vertical expansion mode d4-5 extended crt vertical blank start bit 8 to 9 d6-7 extended crt vertical retrace start bit 8 to 9 extended indexed register creg f0 : 400-line extended crt vertical total register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt extended crt vertical total bit 0 to 7 (-2) extended indexed register creg f1 : reserved this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 reserved extended indexed register creg f2 : 400-line extended crt vertical blank start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical blank start bit 0 to 7 (-1) extended indexed register creg f3 : 400-line extended crt vertical blank end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical blank end bit 0 to 7
p.78 extended indexed register creg f4 : 400-line extended crt vertical retrace start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical retrace start bit 0 to 7 extended indexed register creg f5 : 400-line extended crt vertical retrace end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 extended crt vertical retrace end bit 0 to 3 d4-7 reserved extended indexed register creg f6 : 400-line extended crt vertical overflow this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-1 extended crt vertical total bit 8 to 9 d2-3 reserved d4-5 extended crt vertical blank start bit 8 to 9 d6-7 extended crt vertical retrace start bit 8 to 9 extended indexed register creg f7 : 350-line extended crt vertical total register this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt extended crt vertical total bit 0 to 7 (-2) extended indexed register creg f8 : reserved this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 reserved extended indexed register creg f9 : 350-line extended crt vertical blank start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical blank start bit 0 to 7 (-1) extended indexed register creg fa : 350-line extended crt vertical blank end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical blank end bit 0 to 7
p.79 extended indexed register creg fb : 350-line extended crt vertical retrace start this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-7 extended crt vertical retrace start bit 0 to 7 extended indexed register creg fc : 350-line extended crt vertical retrace end this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-3 extended crt vertical retrace end bit 0 to 3 d4-7 reserved extended indexed register creg fd : 350-line extended crt vertical overflow this is a read/write register. port address is hex 3d5. default value after hardware reset is hex 00. d0-1 extended crt vertical total bit 8 to 9 d2-3 reserved d4-5 extended crt vertical blank start bit 8 to 9 d6-7 extended crt vertical retrace start bit 8 to 9
p.80 pci local bus configuration register description the following registers are TP6508 pci local bus configuration registers. these registers are accessed by first writing the index of the desired register to the index register, i.e. address hex cf8 and then accessing the register using the address hex cfc. read accesses to reserved (index hex 0c,0d,0f,18,1c,20,24,28,2c,30,34,38,3e,3f) or unimplemented (index hex 40 to ff) register can be completed normally and a data value of 0 returned. extended index register preg hex 00 : vendor id register this is a read only register. port address is hex cfc. default value after hardware reset is hex 10d4. d0-15 vendor id bit 0 to 15 bit 0-15 this field identifies the manufacturer of the device. extended index register preg hex 02 : device id register this is a read only register. port address is hex cfc. default value after hardware reset is hex 860b. d0-15 device id bit 0 to 15 bit 0-15 this field identifies the particular device. the bit 0 to 4 is as same as the bit of identification code in extended reg. sreg 05. extended index register preg hex 04 : command register this is a read/write register. port address is hex cfc. default value after hardware reset is hex 0000. d0 io space d1 memory space d2 bus master (reserved =0) d3 special cycle (reserved =0) d4 memory write and invalidate (reserved =0) d5 vga palette snoop d6 perr# enable d7 wait cycle control (reserved =0) d8 serr# enable d9 fast back-to-back enable (reserved =0) d10-15 reserved =0 bit 0 controls TP6508 response to i/o space accesses . a logical 0 disables the device response. a logical 1 allows the device to respond to i/o space accesses . bit 1 controls TP6508 response to memory space accesses . a logical 0 disables the device response. a logical 1 allows the device to respond to memory space accesses . bit 2 implemented by bus masters only. controls a device's ability to act as a master on pci bus. a logical 1 allows the device to behave as a bus master . a logical 0 disables it . bit 3 controls a device's action on special cycle operation . bit 4 this is an enable bit for using the memory write and invalidate command .
p.81 bit 5 when this bit is set to logical 1 , special palette snooping behavior is enabled . when this bit is reset to logical 0 , the device should treat palette accesses like all other accesses . bit 6 this bit controls the device's response to data parity errors. when this bit is set, the device must take its normal action when a parity error is detected. when this bit is reset, the device must ignore any parity error that it detects and continue normal operation. bit 7 this bit is used to control whether or not a device does address/data stepping. bit 8 this bit is an enable bit for the serr# driver. a logical 1 enables the serr# driver and report ad- dress parity error. a logical 0 disables the serr# driver. bit 9 implemented by bus masters only. bit 10-15 reserved. extended index register preg hex 06 : status register this is a read/write register. port address is hex cfc. default value after hardware reset is hex 0280. d0-4 reserved =0 d5 66 mhz capable (read only =0) d6 udf support (read only =0) d7 fast back-to-back capable (read only =1) d8 data parity error detected (reserved =0) d9-10 devsel# timing (read only =01) d11 signaled target abort d12 received target abort (reserved =0) d13 received master abort (reserved =0) d14 signaled system error d15 dected parity error (a write operation to this register can be reset, but not set.) bit 0-4 reserved. bit 5 a logical 1 indicates a device is capable of running at 66 mhz. a logical 0 indicates 33 mhz. bit 6 this optional bit indicates that this device supports user difinable features. bit 7 this optional bit indicates whether or not the target is capable of accepting fast back-to-back transac- tions when the transactions are not to the same agent. bit 8 implemented by bus masters only. bit 9-10 these bits encode timing of devsel#. there are three allowable timings for asserted of devesel# . they are encoded as binary value 00 for fast , 01 for medium , and 10 for slow . bit 11 this bit is set by TP6508 whenever its transaction is terminated with target-abort. bit 12 implemented by bus masters only. bit 13 implemented by bus masters only. bit 14 this bit must be set whenever the device asserts serr#. bit 15 this bit must be set by the device whenever it detects a parity error, even if parity error handing is disabled by bit 6 in the command register. extended index register preg hex 08 : revision id register this is a read only register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 revision id bit 0 to 7 bit 0-7 these bits specify TP6508 specific revision identifier. the bit 0 to 2 is as same as the bit of revision code of extended reg. sreg 05.
p.82 extended index register preg hex 09 : prog. class code register this is a read only register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 class code bit 0 to 7 bit 0-7 the class code register is broken into three byte-size field. the upper byte (at offset 0bh) is a base class code which broadly classifies the type of function the device performs. the middle byte (at offset 0ah ) is a sub-class code which identifies more specific the function of the device. the lower byte (at offset 09h) identifies a specific register-level programming interface so that device independent software can interact with the device. TP6508 sets the class code of hex 03,00,00 to mean that is a vga compatible controller . extended index register preg hex 0a : sub-class code register this is a read only register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 class code bit 8 to 15 extended index register preg hex 0b : base class code register this is a read only register. port address is hex cfc. default value after hardware reset is hex 03. d0-7 class code bit 16 to 23 extended index register preg hex 0c : reserved this is a read/write register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 reserved=0 extended index register preg hex 0d : reserved this is a read/write register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 reserved=0 extended index register preg hex 0e : header type register this is a read/write register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 header type bit 0 to 7 bit 0-7 these bits identify the layout of bytes index 10h through 3fh in configuration space . extended index register preg hex 0f : reserved this is a read/write register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 reserved =0
p.83 extended index register preg hex 10 : display memory base address register this is a read/write register. port address is hex cfc. default value after hardware reset is hex 0000,0000. d0 display memory space indicator (read-only =0) d1-2 type select bit 0 to 1 (read-only =00) d3 prefectchable bit (read-only =0) d4-20 base address bit 4 to 19 (read-only =0) d21 base address bit 21 (read-only =0; for 4m-byte display memory) d22-31 base address bit 22 to 31 (sreg f1 provides the same function for isa/local bus only.) bit 0 this bit is read-only and used to determine whether the register maps into memory or i/o space. base registers that map to memory space must return a 0 in bit 0 . base registers that map to i/o space must return a 1 in bit 0. then , TP6508 set this bit to logical 0 . bit 1-2 these bit is read-only . for memory base registers , bit 2 and 1 have an encoded meaning as shown in the following description . then , TP6508 set these bits to binary logical 00 . bit 2 bit 1 meaning 0 0 base register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space . 0 1 base register is 32 bits wide bust must be mapped below 1m in memory space. 1 0 base register is 64 bits wide and can be mapped anywhere in the 64-bit memory space . 1 1 reserved. bit 3 this bit is read-only . TP6508 set this bits to logical 1 and the data is perfectible . bit 4-21 there are 4m-byte display memory address space for TP6508 setting. the lower 2mb is for display memory and upper 2mb is for memory mapped io. power-up software can determine how much address space TP6508 required by writing a value of all 1's to the register and then reading the value back. when TP6508 has over 1m-byte display memory , it will return 0's in these don't care address bits. bit 22-31 by the description of previous bits , the bits 22 through 31 would implement on read and write opera- tion for power-up software determining 4m-byte address space. extended index register preg hex 14 : i/o command base address register this is a read/write register. port address is hex cfc. default value after hardware reset is hex 0000,0001. d0 i/o command space indicator (read-only =1) d1 reserved =0 d2-7 base address bit 2 to 7 (read-only =0) d8-31 base address bit 8 to 31 bit 0 this bit is read-only and used to determine whether the register maps into memory or i/o space. base registers that map to memory space must return a 0 in bit 0 . base registers that map to i/o space must return a 1 in bit 0. then , TP6508 set this bit to logical 1 . bit 1 this bit is reserved , and must return 0 on reads. bit 2-7 TP6508 has 256-byte i/o address space . power-up software can determine how much address space TP6508 required by writing a value of all 1's to the register and then reading the value back . TP6508 will return 0's in these don't care address bits . bit 8-31 by the description of previous bits , the bits 8 through 31 would implement on read and write opera- tion for power-up software determining 256-byte address space.
p.84 extended index register preg hex 18, 1c, 20, 24, 28, 2c, 30, 34, 38 : reserved this is a read/write register. port address is hex cfc. default value after hardware reset is hex 0000,0000. d0-31 reserved =0 extended index register preg hex 3c : interrupt line register this is a read/write register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 reserved =0 extended index register preg hex 3d : interrupt pin register this is a read/write register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 reserved =0 extended index register preg hex 3e : reserved this is a read/write register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 reserved =0 extended index register preg hex 3f : reserved this is a read/write register. port address is hex cfc. default value after hardware reset is hex 00. d0-7 reserved =0
p.85 graphics engine contr ol register description the following registers with 16-bit data width are topro vga graphics engine control regis- ters. there are two addressing types, base addressing, and memory map i/o addressing, to access these registers. by base addressing, these registers are accessed at port binary address xxxx,xxyy,yyyy,yy00. the address value - y.. is determined by graphics engine port address low register. they are set default hex. f1 and f3. the high address value - xx is determined by following graphics engine control register indexed value. then topro vga can access these registers with 16-bit data width by decoding at them, being conjunction with x.. and y.. , directly . by memory map i/o addressing, these registers are accessed as memory command and located at memory address binary zzzz,zzzz,xxxx,xxyy,yyyy,yy00. the y.. and x.. are as same as the decription of previours paragraph. the address value - z.. is determined by extended register- memory mapping i/o offset register and it is set default hex 00. for pci system access, the gec. regs. are addressed at by setting preg 14 and the pci port address low which is described in the following gec. register description. the pci configuration register preg 14 is used as the higher 8-bit port address and the pci port address low is defined as the lower 8-bit port address for pci local bus. gareg hex 01 : source x offset register this is a read/write register. default port address 07c4. pci port address low 04. default value after hardware reset is hex 00,00. d0-10 source x bit 0 to 10 d11-15 reserved bit 0-10 these bits would use to define source x screen position and transfer to memory address for bitblt operations. also, these bits are use to define starting x screen position for line drawing operations. bit 11-15 reserved . gareg hex 02 : source y offset register this is a read/write register. default port address 0bc4. pci port address low 08. default value after hardware reset is hex 00,00. d0-10 source y bit 0 to 10 d11-15 reserved bit 0-10 these bits would use to define source y screen position and transfer to memory address for bitblt operations. also, these bits are use to define starting y screen position for line drawing operations. bit 11-15 reserved . gareg hex 03 : pattern x offset register this is a read/write register. default port address 0fc4. pci port address low 0c. default value after hardware reset is hex 00,00. d0-15 line drawing pattern bit 0 to 15
p.86 d3-10 bitblt pattern x bit 3 to 10 bit 0-15 these bits would use to do as the pixel-pattern when topro vga is in line drawing command opera- tion. bit 3-10 these bits would use to define pattern x screen position and transfer to memory address for bitblt operations. gareg hex 04 : pattern y offset register this is a read/write register. default port address 13c4. pci port address low 10. default value after hardware reset is hex 00,00. d0-15 line drawing pattern bit 16 to 31 d3-10 bitblt pattern y bit 3 to 10 bit 0-15 these bits would use to do as the pixel-pattern when topro vga is in line drawing command opera- tion. bit 3-10 these bits would use to define pattern y screen position and transfer to memory address for bitblt operations. gareg hex 05 : destination x offset register this is a read/write register. default port address 17c4. pci port address low 14. default value after hardware reset is hex 00,00. d0-10 bitblt destination y bit 0 to 10 d11-15 reserved bit 0-10 these bits would use to define destination y screen position and transfer to memory address for bitblt operations. bit 11-15 reserved. gareg hex 06 : destination y offset register this is a read/write register. default port address 1bc4. pci port address low 18. default value after hardware reset is hex 00,00. d0-10 bitblt destination y bit 0 to 10 d11-15 reserved bit 0-10 these bits would use to define destination y screen position and transfer to memory address for bitblt operations. bit 11-15 reserved. gareg hex 07 : x width & max. term register this is a read/write register. default port address 1fc4. pci port address low 1c. default value after hardware reset is hex 00,00. d0-10 width x bit 0-10 for bitblt (number of bytes-1 per line) maxmum term for line drawing (m) d11-15 reserved bit 0-10 these bits would use to define the x direction width of the rectangular region to be copied for bitblt
p.87 operations , and as the value of the maximum term of the caculated equation for the line drawong operation. in bilblk operations, these bits define the x direction width using byte as unit . the caculated equation of the maximum term (m) is : m = max ( |x 2 -x 1 | , |y 2 -y 1 | ) bit 11-15 reserved . gareg hex 08 : y width & error term register this is a read/write register. default port address 23c4. pci port address low 20. default value after hardware reset is hex 00,00. d0-10 width y bit 0-10 for bitblt (number of line-1) d0-12 error term for line drawing (e) d13-15 reserved bit 0-10/12 these bits would use to define the y direction width of the rectangular region to be copied for bitblt operations , and as the value of the error term of the caculated equation for the line drawong opera- tion. in bilblk operations, these bits define the y direction width using line as unit . the caculated equation of the error term (e) is : e = 2 [ min ( |x 2 -x 1 | , |y 2 -y 1 | )-max ( |x 2 -x 1 | , |y 2 -y 1 | ) ] bit 13-15 reserved . gareg hex 09 : foreground color register 1 this is a read/write register. default port address 27c4. pci port address low 24. default value after hardware reset is hex 00,00. d0-15 foreground color bit 0 to 15 bit 0-15 these bits would use to define the foreground color for rectangular fill, color expansion, and line drawing. conjunction with foreground color bit 16 to 31,that descripts in gareg 0a, we must write with the same color data(byte) into bit 0-7, bit 8-15, bit 16-23, and bit 24-31 for 256-color mode. in different we must write with the same color data(word) into bit 0-15, and bit 16-31 for hi-color mode. another condiction we use bit 0-23 as color data and reserved bit 24-31 for ture-color m ode. gareg hex 0a : foreground color register 2 this is a read/write register. default port address 2bc4. pci port address low 28. default value after hardware reset is hex 00,00. d0-15 foreground color bit 16 to 31 bit 0-15 these bits would use to define the foreground color for rectangular fill, color expansion, and line drawing. gareg hex 0b : background color register 1 this is a read/write register. default port address 2fc4. pci port address low 2c. default value after hardware reset is hex 00,00. d0-15 background color bit 0 to 15
p.88 bit 0-15 these bits would use to define the background color for background fill, color expansion, and line drawing. conjunction with background color bit 16 to 31,that descripts in gareg 0c, we must write with the same color data(byte) into bit 0-7, bit 8-15, bit 16-23, and bit 24-31 for 256-color mode. in different we must write with the same color data(word) into bit 0-15, and bit 16-31 for hi-color mode. another condiction we use bit 0-23 as color data and reserved bit 24-31 for ture-color mode. gareg hex 0c : background color register 2 this is a read/write register. default port address 33c4. pci port address low 30. default value after hardware reset is hex 00,00. d0-15 background color bit 16 to 31 bit 0-15 these bits would use to define the background color for background, color expansion, and line drawing. gareg hex 0d : transparency color register 1 this is a read/write register. default port address 37c4. pci port address low 34. default value after hardware reset is hex 00,00. d0-15 transparency color bit 0 to 15 bit 0-15 these bits would use to define the transparency color for all graphics engine commands except image read. conjunction with transparency color bit 16 to 31,that descripts in gareg 0e, we must write with the same color data(byte) into bit 0-7, bit 8-15, bit 16-23, and bit 24-31 for 256-color mode. in different we must write with the same color data(word) into bit 0-15, and bit 16-31 for hi-color mode. another condiction we use bit 0-23 as color data and reserved bit 24-31 for ture-color m ode. gareg hex 0e : transparency color register 2 this is a read/write register. default port address 3bc4. pci port address low 38. default value after hardware reset is hex 00,00. d0-15 transparency color bit 16 to 31 bit 0-15 these bits would use to define the transparency color all graphics engine commands except image read if transparnecy enabled. gareg hex 0f : transparency mask register 1 this is a read/write register. default port address 3fc4. pci port address low 3c. default value after hardware reset is hex 00,00. d0-15 transparency mask bit 0 to 15 bit 0-15 these bits would use to define the transparency mask bits that are used to compare with the transpar- ency color all graphics engine commands except image read . conjunction with transparnecy color bit 16 to 31,that descripts in gareg 10, we must write with the same color data(byte) into bit 0-7, bit 8-15, bit 16-23, and bit 24-31 for 256-color mode. in different we must write with the same color data(word) into bit 0-15, and bit 16-31 for hi-color mode. another condiction we use bit 0-23 as color data and reserved bit 24-31 for ture-color mode. the pixels of the destination are compared against the transparency color under control of the transparency mask. eachbit of transparency mask
p.89 that is a logical 1 makes dont care for the corresponding bit of the transparency color . gareg hex 10 : transparency mask register 2 this is a read/write register. default port address 43c4. pci port address low 40. default value after hardware reset is hex 00,00. d0-15 transparency mask bit 16 to 31 bit 0-15 these bits would use to define the transparency mask bits that are used to compare with the transpar- ency color all graphics engine commands except image read. the pixels of the destination are com- pared against the transparency color under control of the transparency mask. each bit of transparency mask that is a logical 1 makes dont care for the corresponding bit of the transparency color . gareg hex 11 : top clipping position register this is a read/write register. default port address 47c4. pci port address low 44. default value after hardware reset is hex 00,00. d0-10 top clipping position bit 0-10 d11-15 reserved bit 0-10 these bits are conjunction with gareg 12,13,14 to define a rectangular area . any pixel inside and on the boundary of the rectangular area can be updated during a graphics command operation . bit 11-15 reserved gareg hex 12 : left clipping position register this is a read/write register. default port address 4bc4. pci port address low 48. default value after hardware reset is hex 00,00. d0-10 left clipping position bit 0-10 d11-15 reserved bit 0-10 these bits are conjunction with gareg 11,13,14 to define a rectangular area . any pixel inside and on the boundary of the rectangular area can be updated during a graphics command operation . bit 11-15 reserved gareg hex 13 : bottom clipping position register this is a read/write register. default port address 4fc4. pci port address low 4c. default value after hardware reset is hex 00,00. d0-10 bottom clipping position bit 0-10 of bit 0 to 10 d11-15 reserved bit 0-10 these bits are conjunction with gareg 11,12,14 to define a rectangular area . any pixel inside and on the boundary of the rectangular area can be updated during a graphics command operation . bit 11-15 reserved gareg hex 14 : right clipping position register this is a read/write register. default port address 53c4. pci port address low 50. default value after hardware reset is hex 00,00.
p.90 d0-10 right clipping position bit 0-10 of bit 0 to 10 d11-15 reserved bit 0-10 these bits are conjunction with gareg 11,12,13 to define a rectangular area . any pixel inside and on the boundary of the rectangular area can be updated during a graphics command operation . bit 11-15 reserved gareg hex 15 : raster operation register this is a read/write register. default port address 57c4. pci port address low 54. default value after hardware reset is hex 00,00. d0-7 raster operation code bit 0 to 7 d8-10 scan line width selection bits d11-15 reserved bit 0-7 raster operation as defined by microsoft windows.all logical operation of source,pattern, and destination data are supported. bit 8-10 these bit are used to set the scanline offset in pixel unit. bit-10 bit-9 bit-8 definition 0 0 0 1024 pixels per line 0 0 1 640 pixels per line 0 1 x 800 pixels per line 1 0 0 2048 pixels per line 1 0 1 1280 pixels per line 1 1 x 1600 pixels per line bit 11-15 reserved. gareg hex 16 : graphics engine control register this is a read/write register. default port address 5bc4. pci port address low 58. default value after hardware reset is hex 00,00. d0 x direction d1 y direction d2 source select/major movement d3 destination select/last pixel display enable d4 graphics function mode select d5 background transparency enable for color expansion and line drawing d6 transparency enable d7 rectangular clipping enable d8-9 source format d10 transparency polarity d11 rectangular clipping polarity d12 line drawing pattern width select d13-15 reserved bit 0 this bit is used to select the direction of x direction. a logical 0 indicates in the increasing direction , and a logical 1 indicates in the decreasing direction. bit 1 this bit is used to select the direction of y direction . a logical 0 indicates in the increasing direction , and a logical 1 indicates in the decreasing direction . bit 2 this bit selects the source as either the screen memory or the host cpu memory for bitblt opera-
p.91 tion. a logical 1 selects host cpu memory, and a logical 0 select screen memory. also, it is used to control whether the major movement is in the x or y direction for line drawing operation. a logical 0 indicates in the y direction (d y >d x) , and a logical 1 indicates in the x direction (d y d y, each bit represent 4 pixel. if d x < d y, each bit represent 3 pixel. 1 32 bit ; each bit represent 1 pixel. bit 13-15 reserved. gareg hex 20 : host to display data transfer register this is a read/write register. default port address 83c4. pci port address low 80. default value after hardware reset is hex 00,00,00,00. d0-31 data port for image read/write, color expansion
p.92 gareg hex 21 : hardware cursor pattern start address register this is a read/write register. default port address 87c4. pci port address low 84. default value after hardware reset is hex 00,00. d0-15 memory address a6 to a21 for hardware cursor pattern bit 0-15 these bits would use to define the location in the display memory where the cursor pattern is stored . the cursor pattern may be stored anywhere in the display memory but is generally stored in a non- visible location (off-screen memory ) . we can set the line offset of hardware cursor pattern in gareg 26 bit-14 . others , the start address of hardware cursor pattern has an address-alignment limit as follows : 1) if gareg 26 bit-14 = 0 ( line offset = 16 bytes ) , then the start address of hardware cursor pattern must be 1k-byte alignment . it is easy to fill hardware cursor pattern data contiuously . this register bit-mapping of memory address is : ( x : no used ) d0 ,d1 ,d2 ,d3 ,d4 ,d5 ,d6 ,d7 ,d8 ,d9 ,d10,d11,d12,d13,d14,d15 == x , x , x , x ,a10,a11,a12,a13,a14,a15,a16,a17,a18,a19,a20,a21 2) if gareg 26 bit-14 = 1 ( line offset = 2048 bytes ) , then the start address of hardware cursor pattern can be 64-byte alignment in the first 2048-byte memory address (a6-a10) of any 64x2048-byte memory segment (a17-a21) . it is useful for 1280x or 1600x display mode . this register bit-mapping of memory address is : ( x : no used ) d0 ,d1 ,d2 ,d3 ,d4 ,d5 ,d6 ,d7 ,d8 ,d9 ,d10,d11,d12,d13,d14,d15 == a6 ,a7 ,a8 ,a9 ,a10, x , x , x , x , x , x ,a17,a18,a19,a20,a21 gareg hex 22 : hardware cursor x&y origin register this is a read/write register. default port address 8bc4. pci port address low 88. default value after hardware reset is hex 00,00. d0-5 hardware cursor x-size xbit 0-5 d6-7 reserved d8-13 hardware cursor y-size ybit 0-5 d14-15 reserved bit 0-5 these bits would use to define the x offset in pixels from the left edge of the pattern which will be displayed at the cursor display position . d0 ,d1 ,d2 ,d3 ,d4 ,d5 ==xo0,xo1,xo2,xo3,xo4,xo5 bit 6-7 reserved bit 8-13 these bits would use to define the y offset in pixels from the top edge of the pattern which will be displayed at the cursor display position . d8 ,d9 , d10,d11 ,d12 ,d13 ==yo0,yo1,yo2,yo3,yo4,yo5 bit 14-15 reserved gareg hex 23 : hardware cursor x display position register this is a read/write register. default port address 8fc4. pci port address low 8c. default value after hardware reset is hex 00,00. d0-7 hardware cursor display x position bit 0-7 d8-10 hardware cursor display x position bit 8-10 d11-15 reserved
p.93 bit 0-10 these bits would use to define the x location on the screen at which the cursor origin is displayed . these values represent a position in pixels , referenced to the left edge of the screen . d0, d1, d2 , d3 ,d4 ,d5 ,d6 ,d7 ,d8 ,d9 ,d10 == xp0,xp1,xp2,xp3,xp4,xp5,xp6,xp7,xp8,xp9,xp10 bit 11-15 reserved gareg hex 24 : hardware cursor y display position register this is a read/write register. default port address 93c4. pci port address low 90. default value after hardware reset is hex 00,00. d0-7 hardware cursor display y position bit 0-7 d8-10 hardware cursor display y position bit 8-10 d11-15 reserved bit 0-10 these bits would use to define the y location on the screen at which the cursor origin is displayed . these values represent a position in pixels , referenced to the top edge of the screen . d0 ,d1 ,d2 ,d3 ,d4 ,d5 ,d6 ,d7 ,d8 ,d9 ,d10 == yp0,yp1,yp2,yp3,yp4,yp5,yp6,yp7,yp8,yp9,yp10 bit 11-15 reserved gareg hex 25 : hardware cursor primary color register 1 this is a read/write register. default port address 97c4. pci port address low 94. default value after hardware reset is hex 00,00. d0-7 hardware cursor primary color bit 0 to 7 for 8 bit color mode d8-15 hardware cursor primary color bit 8 to 15 for 16 bit color mode bit 0-7 these bits would use to define the primary color of hardware cursor for 8 bit color mode. bit 8-15 these bits would use to define the primary color of hardware cursor for 16 bit color mode. gareg hex 26 : hardware cursor primary color register 2 this is a read/write register. default port address 97c4. pci port address low 98. default value after hardware reset is hex 00,00. d0-7 hardware cursor primary color bit 16 to 23 for 24 bit color mode d8-13 reserved d14 hardware cursor pattern address line offset selection d15 enable hardware cursor bit 0-7 these bits would use to define the primary color of hardware cursor for 24 bit color mode. bit 8-13 reserved bit 14 this bit is used to select memory line offset of hardware cursor pattern. 0: 16-byte 1: 2048-byte bit 15 a logical 1 enables topro vgas hardware cursor function in operation . a logical 0 disables it. the data definition of hardware cursor pattern list in following description .
p.94 data bit-1 data bit-0 definition 0 0 hardware cursor primary color 0 1 hardware cursor secondary color 1 0 transparent 1 1 inversion or hardware cursor auxiliary color (decided by gareg 2a bit-15 selection) gareg hex 27 : hardware cursor secondary color register 1 this is a read/write register. default port address 9fc4. pci port address low 9c. default value after hardware reset is hex 00,00. d0-7 hardware cursor secondary color bit 0 to 7 for 8 bit color mode d8-15 hardware cursor secondary color bit 8 to 15 for 16 bit color mode bit 0-7 these bits would use to define the secondary color of hardware cursor for 8 bit color mode. bit 8-15 these bits would use to define the secondary color of hardware cursor for 16 bit color mode. gareg hex 28 : hardware cursor secondary color register 2 this is a read/write register. default port address a3c4. pci port address low a0. default value after hardware reset is hex 00,00. d0-7 hardware cursor secondary color bit 16 to 23 for 24 bit color mode d8-14 reserved d15 exchange primary color and secondary color bit 0-7 these bits would use to define the secondary color of hardware cursor for 24 bit color mode. bit 8-14 reserved. bit 15 a logical 1 forces the hardware cursor display color to be reverse . the hardware cursor primary color and secondary color are changed each other in the data definition description of gareg 26 by bit-15. a logical 0 disables it . gareg hex 29 : hardware cursor auxiliary color register 1 this is a read/write register. default port address a7c4. pci port address low a4. default value after hardware reset is hex 00,00. d0-7 hardware cursor auxiliary color bit 0 to 7 for 8 bit color mode d8-15 hardware cursor auxiliary color bit 8 to 15 for 16 bit color mode bit 0-7 these bits would use to define the auxiliary color of hardware cursor for 8 bit color mode. bit 8-15 these bits would use to define the auxiliary color of hardware cursor for 16 bit color mode. gareg hex 2a : hardware cursor auxiliary color register 2 this is a read/write register. default port address abc4. pci port address low a8. default value after hardware reset is hex 00,00. d0-7 har dware cursor auxiliary color bit 16 to 23 for 24 bit color mode d8-14 reserved d15 enable three color mode
p.95 bit 0-7 these bits would use to define the auxiliary color of hardware cursor for 24 bit color mode. bit 8-14 reserved bit 15 this bit is used to select hardware cursor display color mode . a logical 0 indicates topro vga is operated in two color mode . a logical 1 forces topro vga is operated in three color mode by using cursor auxiliary color to replace inversion destination data color. gareg hex 2b : graphics command fifo status register this is a read/write register. default port address afc4. pci port address low ac. default value after hardware reset is hex 00,00. d0 graphics command access status d1 host memory from display memory write status d2 host memory to display memory read status d3 command fifo empty status d4 command fifo full status d5-7 video line buffer valid status d8-15 command fifo valid status (*: write access operation will reset graphic engine) bit 0 this bit reflects the access status of graphics commands . a logical 1 indicates topro vga is excuting the graphics command in busy ststus now . a logical 0 indicates topro vga has excuted the graphics command. bit 1 this bit reflects the write access status of host memory to display memory . a logical 1 indicates topro vga is busy now . bit 2 this bit reflects the read access status of host memory from display memory . a logical 1 indicates topro vga is busy now . bit 3 this bit reflects the command fifo empty status . a logical 0 indicates the command fifo is empty now . a logical 1 indicates the command fifo isnt empty . bit 4 this bit reflects the command fifo full status . a logical 0 indicates the command fifo isnt full . a logical 1 indicates the command fifo is full now . bit 5-7 these bits reflects the video line buffer vaild status as following description . bit-7 bit-6 bit-5 status description 0 0 0 video line buffer empty blocks < 4 (32-bits data/1 block) 0 0 1 video line buffer empty blocks >= 4 0 1 1 video line buffer empty blocks >= 8 1 1 1 video line buffer empty blocks >= 16 bit 8-15 these bits reflects the command fifo vaild status as following description . bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit 8 status description 1 1 1 1 1 1 1 1 0 empty fifo is available (full) 0 1 1 1 1 1 1 1 1 empty fifo is available 0 0 1 1 1 1 1 1 2 empty fifo is available 0 0 0 1 1 1 1 1 3 empty fifo is available 0 0 0 0 1 1 1 1 4 empty fifo is available 0 0 0 0 0 1 1 1 5 empty fifo is available 0 0 0 0 0 0 1 1 6 empty fifo is available 0 0 0 0 0 0 0 1 7 empty fifo is available 0 0 0 0 0 0 0 0 8 empty fifo is available (empty)
p96 viii. absolute maximum rating storage temperature -40 to +125 degree c ambient temperature under bias 0 to +70 degree c voltage on any pin with respect to ground gnd-0.5 to vcc +0.5v active mode power dissipation 1.8 watts power supply voltage 7 v olts
p97 ix. dc electrical characteristic symbol parameter min typ max unit conditions vcc power supply (+5.0v) 4.75 5 5.25 v normal operation power supply (+3.3v) 3 3.3 3.6 v normal operation vil input low voltage -0.5 - 0.8 v vcc=5.0+-5% (a) vih input high voltage 2 - vcc+0.5 v vcc=5.0+-5% vt+ low to high threshold voltage - - 3.5 v schmitt trigger(preset) (h) vt- high to low threshold voltage 1.5 - - v schmitt trigger(preset) (h) vol output low voltaget (5.0v) - - 0.4 v iol=+12ma (b) output low voltage (3.3v) - - 0.4 v iol=+12ma (b) voh output high voltage (5.0v) 2.4 - - v ioh=-12ma (b) output high voltage (3.3v) 2.4 - - v ioh=-12ma (b) icc0 operating current (5.0v) - - 320 ma on power mode (c) icc1 operating current (3.3v) - - 150 ma on power mode (d) icc2 operating current - - 32 ma standby/suspend mode (e) icc3 operating current - - 18 ma off power mode (f) icc4 operating current (5.0v) - - 165 ma cover close mode (g) iil input leakage current -10 - 10 ua vss p98 dac characteristics dc drive characteristics symbol parameter min typ max unit conditions vo output voltage 1 v io< 20ma io output current 20 30 ma vo< 1.0v, 37.5ohm load dac resolution 8 bits full scale error +/-5 % dac to dac cross-talk tbd % dac linearity +/-2 lsb full scale settling time 15 ns output rise/fall time 6 ns 10% to 90% comparator sensitivity 50 mv operating voltage is 5.0v for 5v operation and 3.3v for 3.3v operation. [85.02.09 508dc3.tbl] symbol parameter output pins min unit conditions iol output low drive lrdy#,ldev#,hsync,vsync 12 ma output voltage=vol shfclk,fpvcc,fpvee,fpback d[31:0],a[27:24],oeab* 8 ma output voltage=vol lp,flm,m,p[23:0] all other output pins 4 ma output voltage=vol ioh output high drive lrdy#,ldev#,hsync,vsync 12 ma output voltage=voh shfclk,fpvcc,fpvee,fpback d[31:0],a[27:24],oeab* 8 ma output voltage=voh lp,flm,m,p[23:0] all other output pins 4 ma output voltage=voh operating voltage is 4.75v for 5v operation and 3.3v for 3.3v operation. [85.02.09 508dc2.tbl]
p99 x. ac electrical characteristic ac testing vih / vil : 5.0/0.0 volt voh / vol : 2.0/0.8 volt ( vclk = 28.322mhz / mclk = 55mhz ) " non-100% test " symbol parameter description min. max. units t1 sa0-19 setup time to smemr* 20 ns t2 sa0-19 hold time to smemr* 150 ns t3 smemr* pulse low width 150 ns t4 smemr* asserted to sd floated delay 20 ns t5 sd floated delay from smemr* negated 60 ns t6 delay time from smemr* low to romcs* low 40 ns t7 delay time from smemr* high to romcs* high 40 ns [84.06.26 sp508t01.tbl] bios rom interface timing spec.
p100 symbol parameter description min. max. units t1 sbhe*,sa[16:0] to c ommand ( smem r*, smemw*, iord*, iowr* ) low setup time 18 ns t2 sbhe*,sa[16:0] to command low hold time 10 ns t3 la[23:17] to comm and low setup time 20 ns t4 la[23:17] to com mand high hold time 10 ns t5 sd[15:0] write data to iowr*/memw* high setup time 20 ns t6 sd[15:0] read/write d ata/ to c ommand high hold time 10 ns t7 iord* pulse low width 70 ns t8 iowr* pulse low width 40 ns t9 sd[15:0] read data valid after iord* low 70 ns t10 iordy* high from smemr* low 10 2.45us ns t11 sd[15:0] read d ata valid from iordy* high 40 ns t12 ows low from iord* , smemr* low 15 ns t13 iordy* low from c ommand low 10 25 ns t14 sa[16:0] valid to iocs16* low 35 ns t15 iocs16* from iow* high hold time 20 ns t16 la[23:17] valid to memcs16* 41 ns t17 memcs16* tristate from the next active ale 39 ns t18 aen to iord* , iowr* low setup time 5 ns t19 aen from iord* , iowr* high setup time 5 ns t20 ref* to smemr* low setup time 20 ns t21 ref* from smemr* high hold time 0 ns [84.06.26 sp508t02.tbl] isa bus interface timing spec.
p101 symbol parameter description min. max. units t1 frame# setup time to clk high 5.1 ns t2 frame# hold time from clk high 3.7 ns t3 address setup time to clk high 4.9 ns t4 address hold time from clk high 1.6 ns t5 read data activ delay from clk high 25 ns t6 read data hold time from clk high 4.1 ns t7 command setup time to clk high 2 ns t8 command hold time from clk high 0.8 ns t9 be[3:0] setup time to clk high 1.3 ns t10 be[3:0] hold time from clk high 2 ns t11 irdy# setup time to clk high 3 ns t12 irdy# hold time from clk high 0.3 ns t13 devsel# low delay from clk high 14.4 ns t14 devsel# high delay from clk high 3.8 12.1 ns t15 devsel# tristate delay from clk high 3.5 11.5 ns t16 trdy# low delay from clk high 15.4 ns t17 trdy# high delay from clk high 4 12.7 ns t18 trdy# tristate delay from clk high 3.6 11 ns t19 stop# low delay from clk high 19.3 ns t20 stop# high delay from clk high 3.6 11.8 ns t21 stop# tristate delay from clk high 3.9 12.7 ns t22 par setup time to clk high 10.4 ns t23 par time from clk high 3.1 10.4 ns [84.06.26 sp508t12.tbl] pci local bus interface timing spec.
p102 mclk frequency = 56 mhz symbol parameter description min. max. units tm mclk period 17.86 ns th mclk high pulse 8.93+/-5% ns tl mclk low pulse 8.93+/-5% ns t1 ras precharge time (16-bit cpu/ gfx crt cycle) 3 tm t2 ras pulse width (16-bit cpu/gfx crt cycle) 6 tm t3 ras to cas delay time 3 tm t4 cas pluse width 1.5 tm t5 cas percharge time 0.5 tm t6 row address setup time 1 tm t7 row address hold time 2 tm t8 column address setup time 1 tm t9 column address hold time 1 tm t10 access time from ras 3.75 tm t11 random read/write cycle time 9 tm t12 fast page mode cycle time 2 tm t13 access time from oe* low 1.75 tm t14 output disable time after oe* low 0.75 tm t15 wite command setup time 1 tm t16 wite command hold time 1.5 tm t17 write command pulse width 4.5 tm t18 ras pulse width 4 tm t19 random read/write cycle time 7 tm [84.06.26 sp508t05.tbl] memory bus interface timing spec.
p103 memory interface timing spec. (continuance) symbol parameter description min. max. units t20 read-modify-write ras pulse width 12 tm t21 read-modify-write random read/write cycle time (16-bit) 15 tm t22 read-modify-write ras to cas delay time 3 tm t23 read-modify-write cas pluse width 1.5 tm t24 read-modify-write cas percharge time 0.5 1.5 tm t25 read-modify-write fast page mode cycle time 2 3 tm t26 read-modify-write column address hold time 4 tm t27 read-modify-write date-in setup time 0.5 tm t28 read-modify-write d ate-in hold time 1 tm t29 read-modify-write write command pulse width 2.5 tm t30 read-modify-write oe* command pulse width 2.5 tm t31 read-modify-write a ccess time from oe* low 1.25 tm t32 read-modify-write output disable time after oe* low 0.25 tm t33 read-modify-write ras pulse width 7 tm t34 read-modify-write random read/write cycle time (32-bit) 10 tm [84.06.26 sp508t14.tbl]
p104 symbol parameter description min. max. units tvclk vclk input frequency - 37.5 mhz t1 vclk input clock high time 10 - ns t2 vclk input clock low time 10 - ns t3 pc video input data to pclk setup time 12 - ns t4 pc video input data from pclk hold time 0 - ns t5 vafc input data to pclk setup time 10 - ns t6 vafc input data from pclk hold time 2 - ns [84.08.28 sp508t16.tbl] pclk frequency: 110 mhz symbol parameter description min. max. units t1 pixel clock c y cle time 9.1 ns t2 pixel clock p ulse width hi g h time 3.5 ns t3 pixel clock p ulse width low time 3.5 ns t4 vp[23:0],hsync,vsync,bl ank* setu p time 3 ns t5 vp[23:0],hsync,vsync,bl ank* hold time 3 ns t6 analo g out p ut dela y 30 ns t7 analo g out p ut skew 2 ns [84.06.26 sp508t13.tbl] color-key pc video & vafc interface timing ramdac & feature connector interface timing
p105 xi. timing diagrams (eprom *) sa[19:0] sm em r* sd[7:0] v alid a ddress sp508e01.drw 84/ 0 romcs* t1 t2 t3 t4 t5 t6 t7 bios rom read cycle
p106 ale la[23:17] t1 t2 sd[15:0] ows* iordy* iocs16* h i-z h i-z sa[16:0] sbhe* io rd * io w r* sm emr* sm emw* m emcs16* data v aild v aild t3 t4 t5 t6 t10 t11 t13 t14 t9 t12 t7 t8 t15 t16 t19 t17 t18 t20 t21 aen ref* v aild h i-z h i-z h i-z h i-z sp508e02.drw 84/ 0 isa bus interface timing
p107 a[31:0] d[31:0] b e[3:0]# cmd clk frame# ad[31:0] ad[31:0] c/be[3:0]# irdy# devsel# trdy# stop# par a[31:0] d[31:0] valid valid hi-z hi-z hi-z t1 t2 t3 t4 t6 t7 t8 t9 t10 t12 t14 t17 t18 t15 t13 t11 t20 t21 t23 t22 t5 t16 t19 hi-z hi-z hi-z [read] [w rite] sp508e05.dr w 84/06 / pci local bus interface timing (32-bit data bus)
p108 t2* t0* m clk rasa* ma qa0 w ea* s0 s1 s2 s0 s1 s0 s1 s0 row col asc atr m ap1 t0 state t1 casal* t0 m ap0 m ap2 m ad[7:0] oeab* s3 s3 s0 s2 s1 s0 t1 t2* cg col cg row asc atr cg row asclh atrlh rlh3-0 fifolh extfifolh s0 casah* cg cg' m ap3 m ad[15:8] cg' (casa*) (weal*,w eah*) sp508e06.drw 84/ 0 t1 t18 t19 t3 t4 t6 t7 t8 t9 t10 16-bit txt crt cycle
p109 rasa* ma qa0 wea* row col map0 map2 t0 state t1 casal* map0 mad[7:0] oeab* t2* t3* t0* map1 map3 map2 map3 col+1 mclk s0 s1 s2 s0 s1 s0 s1 s0 s3 s0 row fifolh cpulh [write cycle] map2 map3 map0 map1 wea* md[7:0] oeab* [read cycle] casah* map1 mad[15:8] md[15:8] (casa*) weal*,weah* (weal*,weah*) [sp508e07.drw 84/06/19 ] t17 t1 t2 t11 t3 t12 t5 t4 t6 t7 t8 t9 t10 t14 t13 t15 t16 16-bit cpu/gfx crt/shadow frame buffer cycle
p110 t2* t0* mclk rasa* ma wea* s0 s1 s2 s0 s1 s0 s1 s0 row col asc atr map1 t0 state t1 casal* t0 map0 mad[7:0] oeab* s3 s3 s0 s2 s1 s0 t1 t2* cg col cg row asc atr s0 casah* cg cg' mad[15:8] (casa*) (weal*,weah*) rasb* casbl* casbh* map2 mbd[7:0] cg map3 mbd[15:8] cg' web* (webl*,webh*) asc/atr [sp508e08.drw 84/06/19 (casb*) t1 t18 t19 t3 t4 t6 t7 t8 t9 t10 32-bit txt crt cycle
p111 t2* t0* mclk rasa* ma wea* s0 s1 s2 s0 s1 s0 s1 s0 row col map1 t0 state t1 casal* map0 mad[7:0] oeab* s3 s3 s0 s2 s1 s0 t1 t2* s0 casah* mad[15:8] (casa*) (weal*,weah*) rasb* casbl* casbh* mbd[7:0] mbd[15:8] web* (webl*,webh*) map0 map1 map2 map3 map3 map2 t0* [sp508e09.drw 84/06/19] (casb*) map1 map0 map3 map2 mad[7:0] mad[15:8] mbd[7:0] mbd[15:8] [read cycle] [write cycle] t1 t18 t19 t3 t4 t6 t7 t8 t9 t10 32-bit cpu/gfx crt/shadow frame buffer cycle
p112 rasa* mclk ma s0 s1 s2 s0 s1 s0 s4 s3 row col casal* map0/r mad[7:0] oeab* s3 s3 s0 s2 s1 s0 s2 casah* mad[15:8] casa* weal* weah* qa0 map0 map1 map2 map3 map2/r [sp508e10.drw 84/06/19] s4 t4 t5 t0* t0 t1 state wea* col+1 map0/w map0 map1 map2 map3 map2/w map1/r map3/r map1/w map3/w [dual-cas] [dual-we] t1 t20 t21 t22 t23 t6 t7 t8 t26 t10 t27 t28 t30 t31 t32 t29 t24 t25 16-bit read-modify-write cycle
p113 rasa* m clk ma s0 s1 s2 s0 s1 s0 s4 s3 row col casal* map0/r m ad[7:0] oeab* s3 s0 s2 casah* m ad[15:8] casa*/casb* w eal*/webl* w eah*/w ebh* m ap0 m ap1 m ap2 m ap3 map2/r sp508e11.drw 84/06 t4 t0* t0 t1 state w ea*/web* map0/w m ap0 m ap1 m ap2 m ap3 map2/w map1/r map3/r map1/w map3/w [dual-cas] [dual-we] m ad[7:0] m ad[15:8] casbl* casbh* t1 t33 t34 t22 t23 t6 t7 t8 t26 t10 t27 t28 t32 32-bit read-modify-write cycle
p114 mclk rasc* s0 s1 s2 s0 s0 s1 s0 t1 t18 t19 t0 state t2 t1 casal*,casah* wea*,web*,wec* oeab*,oec* t0* s3 [dual-cas] [dual-write] rasb* rasa* casbl*,casbh* cascl*,casch* casa*,casb*,casc* weal*,weah* webl*,webh* wecl*,wech* sp508e15.drw 84/ 0 refresh cycle cycle(cas before ras)
p115 rasc* m clk ca s0 s1 s2 s0 s4 s3 row col cascl* m cd[15:0] oec* casch* casc* w ecl* w ech* rgb sp508e16.drw 84/0 6 t2 t0 t1 state w ec* col+1 [dual-cas] [dual-we] s5 s6 s7 s8 s9 s0 s0 s10 s11 s12 s13 s14 s15 s0 s0 s1 t0* col+2 [read c y cle] rgb rgb m cd[15:0] [w rite c y cle] rgb rgb rgb t1 t3 t11 t12 t5 t6 t7 t8 t10 t9 t13 t14 t2 t4 external frame buffer interface timing (16-bit)
p116 pclk hsync vsync blank* pseudo color pixel 1 pixel 2 pixel 3 vp[7:0] blue red green [sp508e18.drw 84/06/2 24-bit color 16-bit color t4 t5 r[7:0],g[7:0],b[7:0] t1 t3 t2 t4 t5 t6 t7 ramdac & feature connector interface timing
p117 [sp508e17.drw 84/08/29] pclk out vclk in pixel 1 pixel 2 pixel 3 vp[15:0] vr[7:0],vg[7:0],vb[7:0] grdy vrdy high high (color-key pc video) (vafc interface) (color-key pc video) (vafc interface) envid# (vafc interface) (vafc interface) (vafc interface) t3 t4 t1 t2 t5 t6 color-key pc video & vafc interface timing
p118 xii. appendix a. monitor specification * super vga display monitor spec. mode vclk hsync vsync ibm 320x , 640x 25.175mhz 31.5khz 70hz ibm 360x , 720x 28.322mhz 31.5khz 70hz txt 132x25(font 8x16,8x14) 40mhz 31.5khz 60hz txt 132x44(font 8x8) 40mhz 31.5khz 70hz 640x400 25.175mhz 31.5khz 70hz 640x480 25.175mhz 31.5khz 60hz 800x600 36mhz 35.156khz 56.25hz 1024x768 /interlaced 44.9mhz 35.52khz 87hz 1024x768 /non-interlaced 65mhz 48.363khz 60hz 1280x1024 /interlaced 75mhz 46.875khz 87hz 1280x1024 /non-interlaced 102.4mhz 64khz 60hz 1600x1280 /interlaced 108mhz 57.447khz 87hz * vesa vga display monitor spec mode vclk hsync vsync ibm 320x , 640x 31.5mhz 37.86khz 84hz ibm 360x , 720x 31.5mhz 37.86khz 84hz 640x400 31.5mhz 37.86khz 84hz 640x480 31.5mhz 37.86khz 72.8hz 640x480 31.5mhz 37.5khz 75hz 800x600 40mhz 37.879khz 60.3hz 800x600 50mhz 48.077khz 72.2hz 800x600 49.5mhz 46.875khz 75hz 1024x768 /non-interlaced 65mhz 48.363khz 60hz 1024x768 /non-interlaced 75mhz 56.476khz 70hz 1024x768 /non-interlaced 78.75mhz 60.023khz 70hz 1280x1024 /non-interlaced 135mhz 79.976khz 75hz
p119 b. TP6508 vga modes TP6508 vga modes mode display size type colors /shades alpha format buff start box size vclk (mhz) hs y nc (khz) vs y nc (hz) min. memor y size max. pa g e 0 / 1 320x200 a/n 16/256k 40x25 b80 8x8 25.17 31.5 70 256kb 8 0*/1* 320x350 a/n 16/256k 40x25 b80 8x14 25.17 31.5 70 256kb 8 0+/1 360x400 a/n 16/256k 40x25 b80 9x16 28.32 31.5 70 256kb 8 2 / 3 640x200 a/n 16/256k 80x25 b80 8x8 25.17 31.5 70 256kb 8 2*/3* 640x350 a/n 16/256k 80x25 b80 8x14 25.17 31.5 70 256kb 8 2+/3 720x400 a/n 16/256k 80x25 b80 9x16 28.32 31.5 70 256kb 8 4 / 5 320x200 apa 4/256k 40x25 b80 8x8 25.17 31.5 70 256kb 1 6 640x200 apa 2/256k 80x25 b80 8x8 25.17 31.5 70 256kb 1 7 720x350 a/n mono 80x25 b00 9x14 28.32 31.5 70 256kb 8 7+ 720x400 a/n mono 80x25 b00 9x16 28.32 31.5 70 256kb 8 d 320x200 apa 16/256k 40x25 a00 8x8 25.17 31.5 70 256kb 8 e 640x200 apa 16/256k 80x25 a00 8x8 25.17 31.5 70 256kb 4 f 640x350 apa mono 80x25 a00 8x14 25.17 31.5 70 256kb 2 10 640x350 apa 16/256k 80x25 a00 8x14 25.17 31.5 70 256kb 2 11 640x480 apa 2/256k 80x30 a00 8x16 25.17 31.5 60 256kb 1 12 640x480 apa 16/256k 80x30 a00 8x16 25.17 31.5 60 256kb 1 13 320x200 apa 256/256 40x25 a00 8x8 25.17 31.5 70 256kb 1 20 1056x400 a/n 16/256k 132x25 b80 8x16 40 30.9 60 256kb 4 21 1056x396 a/n 16/256k 132x44 b80 8x8 40 30.9 70 256kb 2 22 1056x400 a/n 16/256k 132x25 b80 8x14 40 30.9 70 256kb 4 23 1600x1280/i apa 256/256 200x80 a00 8x16 108 57.44 87 2mb 1 24 1600x1280/ apa 256/256 200x80 a00 8x16 166.6 79.2 60 2mb 1 25 1600x1280/i apa 65536 200x80 a00 8x16 108 57.44 87 4mb 1 26 1600x1280/ apa 65536 200x80 a00 8x16 166.6 79.2 60 4mb 1 27 1600x1280/ apa 16/256k 200x80 a00 8x16 166.6 79.2 60 1mb 1 28 800x600 apa 16/256k 100x37 a00 8x16 36 35.5 57 256kb 1 29 1024x768/i apa 16/256k 128x48 a00 8x16 44.9 35.5 87 512kb 1 2a 1024x768/n apa 16/256k 128x48 a00 8x16 65 48.36 60 512kb 1 2b 640x200 apa 256/256 80x25 a00 8x16 25.17 31.5 70 512kb 1 2c 640x400 apa 256/256 80x25 a00 8x16 25.17 31.5 70 512kb 1 2d 640x480 apa 256/256 80x30 a00 8x16 25.17 31.5 60 512kb 1 2e 800x600 apa 256/256 100x37 a00 8x16 36 35.5 57 512kb 1 2f 1024x768/i apa 256/256 128x48 a00 8x16 44.9 35.5 87 1mb 1 30 1024x768/n apa 256/256 128x48 a00 8x16 65 48.36 60 1mb 1 [88.04.12 tpmode1.tbl]
p120 : TP6508 don't support mode 23 , 24 , 25 , 26 , 27 , 3e , 3f , 40 , 41 . TP6508 vga modes (continuous) mode display size typ colors /shades alpha format buff start box size vclk (mhz) hsync (khz) vsync (hz) min. memory size max. page 31 1280x1024/i apa 1677721 160x64 a00 8x16 75 46.87 87 4mb 1 32 1280x1024/ apa 1677721 160x64 a00 8x16 102.4 64 60 4mb 1 33 1280x1024/i apa 16/256k 160x64 a00 8x16 75 46.87 87 1mb 1 34 1280x1024/ apa 16/256k 160x64 a00 8x16 135 79.97 75 1mb 1 35 1280x1024/i apa 256/256 160x64 a00 8x16 75 46.87 87 2mb 1 36 1280x1024/ apa 256/256 160x64 a00 8x16 102.4 64 60 2mb 1 37 1600x1280/i apa 16/256k 200x80 a00 8x16 129.4 64.7 96 1mb 1 38 640x480 apa 65536 80x30 a00 8x16 25.17 31.5 60 1mb 1 39 800x600 apa 65536 100x37 a00 8x16 36 35.5 56.25 1mb 1 3a 640x480 apa 1677721 80x30 a00 8x16 25.17 31.5 60 1mb 1 3b 800x600 apa 1677721 100x37 a00 8x16 36 35.5 56.25 2mb 1 3c 1024x768/i apa 65536 128x48 a00 8x16 44.9 35.5 87 2mb 1 3d 1024x768/n apa 65536 128x48 a00 8x16 65 48.36 60 2mb 1 3e 1024x768/i apa 1677721 128x48 a00 8x16 44.9 35.5 87 4mb 1 3f 1024x768/n apa 1677721 128x48 a00 8x16 65 48.36 60 4mb 1 40 1280x1024/i apa 65536 160x64 a00 8x16 75 46.87 87 4mb 1 41 1280x1024/ apa 65536 160x64 a00 8x16 102.4 64 60 4mb 1 [88.04.12 tpvgam2.tbl]
p121 c. rast operation code list operation : a : and objects : d : destination o : or p : pattern x : xor s : source n : not boolean function : in hex 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 in r polish 0 dpsoon dpsona pson sdpona dpon pdsxnon pdsaon sdpnaa pdsxon dpna psdnaon spna pdsnaon pdsonon pn pdsona dson sdpxnon sdpaon dpsxnon dpsaon psdpsanaxx sspxdsxaxn spxpdxa sdpsanaxn pdspaox sdpsxaxn psdpaox dspdxaxn pdsox pdsoan dpsnaa sdpxon dsna spdnaon spxdsxa in hex ff fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 ef ee ed ec eb ea e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 df de dd dc db in r polish 1 dpsoo psdnoo pso dpsnoo dpo pdsxno pdsao pdsano pdsxo pdno psdnao psno pdsnao pdsono p sdpnoo dso sdpxno sdpao dpsxno dpsao dspdsanaxxn sspxdsxax spxpdxan sdpsanax pdspaoxn sdpsxax psdpaoxn dspdxax pdsoxn pdsoa sdpano sdpxo sdno spdnao spxdsxan
p122 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 pdspanax sdpsaoxn sdpsxax dpsxan psdpsaoxx dpsanan sspxpdxax spdsoaxn pdsnax psdpxoxn psdnoa spno sdpnao sdpono s spdsaoxn dpsdxax spdoxn sdpoa psdpoaxn sdpnax spdsxoxn spdnoa psxn spdsonoxn spdsnaoxn psa dpsano dpsxo sdxpdxan spdsanax dsno dpsnao dspdaoxn psdpxax sdpxan pdspdoaxx dpsdoaxn psdnax sdpanan sspxdsxox pdspxoxn pdsnoa dpno dspnao dpsdaoxn pdspanaxn sdpsaoxxn sdpsxnox dpsxa psdpsaoxxn dpsana sspxpdxaxn spdsoax psdnox psdpxox psdnoan psna sdpnaon sdpsoox sn spdsaox spdsxnox sdpox sdpoan psdpoax spdnox spdsxox spdnoan psx spdsonox spdsnaox psan psdnaa dpsxon sdxpdxa spdsanaxn sdna dpsnaon dspdaox psdpxaxn sdpxa pdspdoaxxn dpsdoax pdsnox sdpana sspxdsxoxn pdspxox pdsnoan pdna dspnaon dpsdaox da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 bf be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 af ae ad
p123 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f spdsxax dpsono d dpsoxn dpsoa pdspoaxn dspnax dpxn dpsdonoxn dpsdxoxn dpsnoa dpsdnaoxn dpa pdsxan dspdsaoxx dspdoaxn spdnax sdpsoaxn dpsnax dsxn sdpsonoxn dspdsonoxx pdsxx dpsaxn psdpsoaxx sdpaxn pdspdoaxx sdpsnoaxn pdsxna pdsanan ssdxpdxax sdpsxoxn sdpnoa dspdxoxn dspnoa sdpsnaoxn dsa pdsaxn dspdsoaxx dpsdnoaxn sdpxna spdsnoaxn dpsxna spxdsxon dpsaa spdsxaxn dpsonon dn dpsox dpsoan pdspoax dpsnox dpx dpsdonox dpsdxox dpsnoan dpsdnaox dpan pdsxa dspdsaoxxn dspdoax sdpnox sdpsoax dspnox dsx sdpsonox dspdsonoxxn pdsxxn dpsax psdpsoaxxn sdpax pdspdoaxxn sdpsnoax pdsxnan pdsana ssdxpdxaxn sdpsxox sdpnoan dspdxox dspnoan sdpsnaox dsan pdsax dspdsoaxxn dpsdnoax sdpxnan spdsnoax dpsxnan spxdsxo dpsaan ac ab aa a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 9f 9e 9d 9c 9b 9a 99 98 97 96 95 94 93 92 91 90 8f 8e 8d 8c 8b 8a 89 88 87 86 85 84 83 82 81 80
p124 d. memor y addr ess t able cpu address multiplexing - symmetry addressing vga mode enhance 16 color mode enhance 256/hi-/ture color enhance text mode 16-bit / 32-bit 16-bit / 32-bit//* 16-bit / 32-bit 16-bit / 32-bit cas-a0 qa0/bank0 qa0/bank0//bank qa0/ba3 qa0/bank0 cas-a1 pg sa0 ba0 sa5 cas-a2 ch sa1 ba1 sa6 cas-a3 sa2 sa2 sa2 sa7 cas-a4 sa3 sa3 sa3 sa8 cas-a5 sa4 sa4 sa4 sa9 cas-a6 sa5 sa5 sa5 sa10 cas-a7 sa6 sa6 sa6 sa11 cas-a8 0 sa169/sa169//ban ba2 0 ras-a0 sa7 sa7 sa7 sa0 ras-a1 sa8 sa8 sa8 sa1 ras-a2 sa9 sa9 sa9 sa2 ras-a3 sa10 sa10 sa10 sa3 ras-a4 sa11 sa11 sa11 sa4 ras-a5 sa12 sa12 sa12 sa12 ras-a6 sa13 sa13 sa13 sa13 ras-a7 sa14 sa14 sa14 sa14 ras-a8 sa159 sa15 sa159 sa159 * : bank addressing for enhanced 16-color display mode [84.06.12 sp508t06.tbl]
p125 cpu address multiplexing - asymmetry addressing vga mode enhance 16 color mode enhance 256/hi-/ture color enhance text mode 16-bit / 32-bit 16-bit / 32-bit//* 16-bit / 32-bit 16-bit / 32-bit cas-a0 qa0/bank0 qa0/bank0//bank qa0/ba3 qa0/bank0 cas-a1 pg sa0 ba0 sa5 cas-a2 ch sa1 ba1 sa6 cas-a3 sa2 sa2 sa2 sa7 cas-a4 sa3 sa3 sa3 sa8 cas-a5 sa4 sa4 sa4 sa9 cas-a6 sa5 sa5 sa5 sa10 cas-a7 sa6 sa6 sa6 sa11 cas-a8 0 0 ba2 0 ras-a0 sa7 sa7 sa7 sa0 ras-a1 sa8 sa8 sa8 sa1 ras-a2 sa9 sa9 sa9 sa2 ras-a3 sa10 sa10 sa10 sa3 ras-a4 sa11 sa11 sa11 sa4 ras-a5 sa12 sa12 sa12 sa12 ras-a6 sa13 sa13 sa13 sa13 ras-a7 sa14 sa14 sa14 sa14 ras-a8 sa159 sa15 sa159 sa159 ras-a9 0 sa169/sa169//ban ba2 0 * : bank addressing for enhanced 16-color display mode [84.06.12 sp508t07.tbl]
p126 crt address multiplexing - symmetry addressing b y te mode word mode double word mode ibm text mode enhance text mode 16-bit / 32-bit 16-bit / 32-bit 16-bit / 32-bit 16-bit / 32-bit 16-bit / 32-bit cas-a0 qa0/ma17 qa1/ma17 qa0/ma17 qa1/ma17 qa1/asc7 cas-a1 ma0 ma15/ma13 ma14 ra0 asc0 cas-a2 ma1 ma0 ma15 ra1 asc1 cas-a3 ma2 ma1 ma0 ra2 asc2 cas-a4 ma3 ma2 ma1 ra3 asc3 cas-a5 ma4 ma3 ma2 ra4 asc4 cas-a6 ma5 ma4 ma3 asc0 asc5 cas-a7 ma6 ma5 ma4 asc1 asc6 cas-a8 ma16 ma16 ma16 0 0 ras-a0 ma7 ma6 ma5 asc2 ra0 ras-a1 ma8 ma7 ma6 asc3 ra1 ras-a2 ma9 ma8 ma7 asc4 ra2 ras-a3 ma10 ma9 ma8 asc5 ra3 ras-a4 ma11 ma10 ma9 asc6 ra4 ras-a5 ma12 ma11 ma10 asc7 0 ras-a6 ma13/ra0 ma12/ra0 ma11/ra0 chhap2 chhap2 ras-a7 ma14/ra1 ma13/ra1 ma12/ra1 chhap0 chhap0 ras-a8 ma15 ma14 ma13 chhap1 chhap1 [84.06.13 sp508t08.tbl]
p127 crt address multiplexing - asymmetry addressing b y te mode word mode double word mode ibm text mode enhance text mode 16-bit / 32-bit 16-bit / 32-bit//* 16-bit / 32-bit 16-bit / 32-bit 16-bit / 32-bit cas-a0 qa0/ma17 qa1/ma17 qa0/ma17 qa1/ma17 qa1/asc7 cas-a1 ma0 ma15/ma13 ma14 ra0 asc0 cas-a2 ma1 ma0 ma15 ra1 asc1 cas-a3 ma2 ma1 ma0 ra2 asc2 cas-a4 ma3 ma2 ma1 ra3 asc3 cas-a5 ma4 ma3 ma2 ra4 asc4 cas-a6 ma5 ma4 ma3 asc0 asc5 cas-a7 ma6 ma5 ma4 asc1 asc6 cas-a8 0 0 0 0 0 ras-a0 ma7 ma6 ma5 asc2 ra0 ras-a1 ma8 ma7 ma6 asc3 ra1 ras-a2 ma9 ma8 ma7 asc4 ra2 ras-a3 ma10 ma9 ma8 asc5 ra3 ras-a4 ma11 ma10 ma9 asc6 ra4 ras-a5 ma12 ma11 ma10 asc7 0 ras-a6 ma13/ra0 ma12/ra0 ma11/ra0 chhap2 chhap2 ras-a7 ma14/ra1 ma13/ra1 ma12/ra1 chhap0 chhap0 ras-a8 ma15 ma14 ma13 chhap1 chhap1 ras-a9 ma16 ma16 ma16 0 0 [84.06.13 sp508t09.tbl]
p128 ba0 to ba4 selection table bank addressing mode linear addressing mode ba0 bank0 sa16 ba1 bank1 sa17 ba2 bank2 sa18 ba3 bank3 sa19 ba4 bank4 sa20 [84.06.26 sp508t10.tbl] pg*,ch*,saa* table extmem odd/even ega/128k vga chain4 pg* ch* saa* x 0 x 0 sa0 - - 0 1 0 0 sa14 - - 1 1 1 0 sa16 - - 1 1 0 0 /pagbit - - x x x 1 0 - - byte mode ba2/ba3** - - - - - 0 - sa1 - - - - 1 - 0 - word mode ba2/ba3** - - - sa2 dword mode - - ba2/ba3** extmem : sequencer register indexed hex 04 bit 1 odd/even : graphics control register indexed hex 06 bit 1 vga chain4 : sequencer register indexed hex 04 bit 3 ega128k : 1- graphics control register indexed hex 06 bit 2=0 and bit 3=0 0- graphics control register indexed hex 06 bit 2=1 and bit 3=1 pagbit : miscellaneousn output register bit 5 ** : 256k 64-bit bus--ba2 , 512k 64-bit bus--ba3 [84.09.08 sp508t11.tbl]
p129 e. mclk & vclk fr equency pr ogramming t able TP6508 vga vclk synthesizer parameter table vclk spec. vclk frequenc o n d p reg. 22/c3h 23/c4h reg. 24/c5h 25/c6h hm8694-304 25.175 25.165 1 1c 41 1 9c 83 00,00 0 25.267 25.2671 1 e 10 0 8e 20 28.322 28.2991 1 29 54 1 a9 a9 00,01 1 28.636 28.636 1 14 29 1 94 53 00,01 1 31.5 31.4996 1 a 9 1 8a 12 10,10 a 32.514 32.5188 1 42 3a 0 c2 74 00,10 2 34 33.8425 1 0c a 0 8c 14 35 34.9996 1 0a 8 0 8a 10 36 35.9995 1 e b 0 8e 16 00,11 3 40 39.9823 1 f 16 1 8f 2d 01,00 4 44.9 44.9065 1 a 6 0 8a 0c 01,01 5 49.5 49.5325 1 12 a 0 92 14 50 50.3299 1 39 20 0 b9 40 01,10 6 56.644 56.5982 0 53 54 1 53 a9 11,00 c 57.272 57.272 0 47 47 1 47 8f 58.8 58.7993 0 4c 4a 1 4c 95 10,11 b 65 65.0115 0 18 15 1 18 2b 01,11 7 70 69.9991 0 2b 23 1 2b 47 75 75.0461 0 10 c 1 10 19 11,01 d 78.75 78.749 0 a 3 0 0a 06 85 84.8853 0 52 37 1 52 6f 11,10 e 90 89.9989 0 4c 30 1 4c 61 94.5 94.4988 0 41 27 1 41 4f 100 99.9214 0 51 2e 1 51 5d 102.4 102.3954 0 18 6 1 18 0c 108 107.9986 0 10 8 1 10 11 110 110.023 0 48 25 1 48 4b 115 114.544 0 11 8 1 11 11 120 119.7985 0 2b 14 1 2b 29 129.4 129.3923 0 2a 12 1 2a 25 135 134.998 0 20 6 0 20 0c [88.04.12 tpvgav2.tbl]
p130 TP6508 vga mclk synthesizer parameter table mclk spec. mclk fre q uenc o n d p reg. 26/c9h reg. 27/cah 30mhz 29.9996 1 24 3e 1 a0 7d 33mhz 33.0042 1 21 3a 1 a1 75 36mhz 36.0259 1 26 3d 1 a6 7b 40mhz 39.9823 1 24 34 1 a4 69 45mhz 44.9994 1 20 29 1 a0 53 50mhz 49.9294 1 21 26 1 a1 4d 55mhz 54.9993 0 78 3e 0 78 7c 60mhz 59.9992 0 41 3e 1 41 7d 65mhz 64.9817 0 3a 33 1 3a 67 68mhz 68.0105 0 38 2f 1 38 5f 69mhz 69.9867 0 34 2b 1 34 57 70mhz 69.9991 0 41 35 1 41 6b 71mhz 70.9675 0 38 2d 1 38 5b 72mhz 72.0519 0 4d 3d 1 4d 7b 73mhz 72.9937 0 40 32 1 40 65 74mhz 74.0345 0 34 28 1 34 51 75mhz 74.9743 0 47 36 1 47 6d 78mhz 77.9874 0 3f 2e 0 3f 5d 80mhz 80.034 0 6c 26 0 6c 4c 82mhz 82.0383 0 34 34 1 34 49 85mhz 85.0898 0 33 22 1 33 45 88mhz 88.0033 0 3e 28 1 3e 51 90mhz 89.9989 0 36 22 1 36 45 95mhz 94.9877 0 43 28 1 43 51 100mhz 99.893 0 4a 2a 1 4a 55 [88.04.12 tpvgam2.tbl]
p131 f . pins selection configuration *1. disable internal dual frequency synthesizer ( sreg d0 d4 = 0 ) pin name pin number selected multipelx function off 178 exvclk ~ external vclk input xtal1 203 exmclk ~ external mclk input *2. vga bios rom interface ( sreg d0 d2-0 = 101 ) ~ isa bus pin name pin number selected multipelx function romcs* 29 bios rom chip_select signal output *3. off pin control selection (pin number =178 ) ( if sreg ce d0 = 1 & if *1 isn't true ) ~ sreg cb d1-0 = selection bits d1 d0 selected multipelx function 0 0 vesa dpms off mode pin trigger input/output pin 0 1 output internal mclk frequency signal 1 x output internal vclk frequency signal *4. 24-bit tft panel interface selection ( creg ac d5 = 1 ) pin name pin number selected multipelx function ca[7:0] 97-90 p[23:16] ~ flat panel data signals *5. video interface selection [a]. ( sreg d9 d1-0 = 01 ) ~ 18-bit video port interface pin name : rasc* , wec*, casch*, cascl* , mcd[15:0] selected multipelx function : key , pclk , vr[7:2] ,vg[7:2] , vb[7:2] [b]. ( sreg d9 d1-0 = 11 , sreg d0 d6 = 1 ) ~ 24-bit video port interface pin name : rasc* , casch*, cascl* , wec*, mcd[15:0] , oec* , 32khz , ca8 , ca9 , a27 , a26 selected multipelx function : key , pclk , vr[7:2] ,vg[7:2] , vb[7:2] , vr[1,0] , vg[1,0] , vb[1:0] [c]. ( sreg d9 d0 = 0 , sreg d0 d6 = 1 , sreg c0 d6=1) ~ vafc interface pin name : rasc* , casch*, cascl* , wec*, mcd[15:0] , oec* , 32khz , ca8 , ca9 , a27 , a26 selected multipelx function : vrdy , pclk , grdy , evid# , vp[15:0] , vclk , blank* *6. external lcd frame buffer interface selection ( if *4,*5 isn't true) pin name : rasc* , casch*, cascl* , wec*, mcd[15:0] , oec* , ca[9:0] selected multipelx function : external lcd frame buffer dram interface *7. acti & fpback output selection ( creg d0 d6 = 1 , & if *5 [b] ) pin name pin number selected multipelx function a26 53 acti ~ responses high during valid vga access a27 54 fpback ~ flat panel power control signal output *8. pin-61 output control ( sreg d1 d4 = selection bit ) d7 selected multipelx function 0 fpvee ~ flat panel power control signal output 1 fpback ~ flat panel power control signal output

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