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1/24 february 2003 m24c64 m24c32 64kbit and 32kbit serial i2c bus eeprom features summary n two wire i 2 c serial interface supports 400 khz protocol n single supply voltage: C 4.5v to 5.5v for m24cxx C 2.5v to 5.5v for m24cxx-w C 1.8v to 5.5v for m24cxx-r n write control input n byte and page write (up to 32 bytes) n random and sequential read modes n self-timed programming cycle n automatic address incrementing n enhanced esd/latch-up behavior n more than 1 million erase/write cycles n more than 40 year data retention figure 1. packages pdip8 (bn) 8 1 so8 (mn) 150 mil width 8 1 tssop8 (dw) 169 mil width tssop8 (ds) 3x3mm2 body size (msop)
m24c64, m24c32 2/24 summary description these i 2 c-compatible electrically erasable programmable memory (eeprom) devices are organized as 8192 x 8 bits (m24c64) and 4096 x 8 bits (m24c32). figure 2. logic diagram these devices are compatible with the i 2 c memo- ry protocol. this is a two wire serial interface that uses a bi-directional data bus and serial clock. the devices carry a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus defini- tion. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiat- ed by a start condition, generated by the bus mas- ter. the start condition is followed by a device select code and rw bit (as described in table 2), terminated by an acknowledge bit. when writing data to the memory, the device in- serts an acknowledge bit during the 9 th bit time, following the bus masters 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. table 1. signal names power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power-up, a power on reset (por) circuit is included. the internal reset is held active until v cc has reached the por threshold value, and all operations are disabled C the device will not respond to any command. in the same way, when v cc drops from the operating voltage, below the por threshold value, all oper- ations are disabled and the device will not respond to any command. a stable and valid v cc must be applied before applying any logic signal. figure 3. dip, so and tssop connections note: 1. see page 18 (onwards) for package dimensions, and how to identify pin-1. ai01844b 3 e0-e2 sda v cc m24c64 m24c32 wc scl v ss e0, e1, e2 chip enable sda serial data scl serial clock wc write control v cc supply voltage v ss ground sda v ss scl wc e1 e0 v cc e2 ai01845c m24c64 m24c32 1 2 3 4 8 7 6 5
3/24 m24c64, m24c32 signal description serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be con- nected from serial clock (scl) to v cc . (figure 4 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. serial data (sda) this bi-directional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-ored with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . (fig- ure 4 indicates how the value of the pull-up resistor can be calculated). chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code. write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write op- erations. write operations are disabled to the en- tire memory array when write control (wc ) is driven high. when unconnected, the signal is in- ternally read as v il , and write operations are al- lowed. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. figure 4. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k w ) 10 1000 fc = 400khz fc = 100khz
m24c64, m24c32 4/24 figure 5. i 2 c bus protocol table 2. device select code note: 1. the most significant bit, b7, is sent first. 2. e0, e1 and e2 are compared against the respective external pins on the memory device. table 3. most significant byte table 4. least significant byte device type identifier 1 chip enable address 2 rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1 0 1 0 e2 e1 e0 rw scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
5/24 m24c64, m24c32 device operation the device supports the i 2 c protocol. this is sum- marized in figure 5. any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. the m24cxx device is always a slave in all communication. start condition start is identified by a falling edge of serial data (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not respond unless one is given. stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driv- en high. a stop condition terminates communica- tion between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the stand-by mode. a stop condition at the end of a write command triggers the internal ee- prom write cycle. acknowledge bit (ack) the acknowledge bit is used to indicate a success- ful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driv- en low. memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. following this, the bus master sends the device select code, shown in table 2 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable address (e2, e1, e0). to address the memory array, the 4- bit device type identifier is 1010b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received on seri- al data (sda), the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into stand- by mode. table 5. operating modes note: 1. x = v ih or v il . mode rw bit wc 1 bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 3 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 32 start, device select, rw = 0
m24c64, m24c32 6/24 figure 6. write mode sequences with wc =1 (data write inhibited) write operations following a start condition the bus master sends a device select code with the rw bit reset to 0. the device acknowledges this, as shown in figure 7, and waits for two address bytes. the device re- sponds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if write control (wc ) is driven high. any write instruction with write control (wc ) driven high (during a pe- riod of time from the start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 6. each data byte in the memory has a 16-bit (two byte wide) address. the most significant byte (ta- ble 3) is sent first, followed by the least significant byte (table 4). bits b15 to b0 form the address of the byte in memory. when the bus master generates a stop condition immediately after the ack bit (in the 10 th bit time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) is disabled internally, and the device does not re- spond to any requests. byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, in- stead, the addressed location is not write-protect- ed, the device replies with ack. the bus master terminates the transfer by generating a stop con- dition, as shown in figure 7. page write the page write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same row in the memory: that is, the most significant memory address bits stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120c page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
7/24 m24c64, m24c32 (b12-b5 for m24c64, and b12-b5 for m24c32) are the same. if more bytes are sent than will fit up to the end of the row, a condition known as roll-over occurs. this should be avoided, as data starts to become overwritten in an implementation depen- dent way. the bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory loca- tion are not modified, and each data byte is fol- lowed by a noack. after each byte is transferred, the internal byte address counter (the 5 least sig- nificant address bits only) is incremented. the transfer is terminated by the bus master generat- ing a stop condition. figure 7. write mode sequences with w c =0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106c page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack
m24c64, m24c32 8/24 figure 8. write cycle polling flowchart using ack minimizing system delays by polling on ack during the internal write cycle, the device discon- nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in tables 17 and 18, but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 8, is: C initial condition: a write cycle is in progress. C step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). C step 2: if the device is busy with the internal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
9/24 m24c64, m24c32 figure 9. read mode sequences note: 1. the seven most significant bits of the device select code of a random read (in the 1 st and 4 th bytes) must be identical. read operations read operations are performed independently of the state of the write control (wc ) signal. random address read a dummy write is performed to load the address into the address counter (as shown in figure 9) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the rw bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. current address read the device has an internal address counter which is incremented each time a byte is read. for the current address read operation, following a start condition, the bus master only sends a device se- lect code with the rw bit set to 1. the device ac- knowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 9, without acknowledging the byte. sequential read this operation can be used after a current ad- dress read or a random address read. the bus start dev sel * byte addr byte addr start dev sel data out 1 ai01105c data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
m24c64, m24c32 10/24 master does acknowledge the data byte output, and sends additional clock pulses so that the de- vice continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 9. the output data comes from consecutive address- es, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter rolls-over, and the device continues to output data from memory address 00h. acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device termi- nates the data transfer and switches to its stand- by mode.
11/24 m24c64, m24c32 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 6. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter min. max. unit t stg storage temperature C65 150 c t lead lead temperature during soldering pdip: 10 seconds so: 20 seconds (max) 1 tssop: 20 seconds (max) 1 260 235 235 c v io input or output range C0.6 6.5 v v cc supply voltage C0.3 6.5 v v esd electrostatic discharge voltage (human body model) 2 C4000 4000 v
m24c64, m24c32 12/24 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 7. operating conditions (m24cxx) table 8. operating conditions (m24cxx-w) table 9. operating conditions (m24cxx-r) symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature C40 85 c symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature C40 85 c symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature C40 85 c
13/24 m24c64, m24c32 table 10. ac measurement conditions figure 10. ac measurement i/o waveform table 11. input parameters note: 1. t a = 25 c, f = 400 khz 2. sampled only, not 100% tested. symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v symbol parameter 1,2 test condition min . max . unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z wcl wc input impedance v in < 0.5 v 5 20 k w z wch wc input impedance v in > 0.7v cc 500 k w t ns pulse width ignored (input filter on scl and sda) single glitch 100 ns ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
m24c64, m24c32 14/24 table 12. dc characteristics (m24cxx) table 13. dc characteristics (m24cxx-w) symbol parameter test condition (in addition to those in table 7) min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in stand-by mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 2ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 5 v 10 a v il input low voltage (e2, e1, e0, scl, sda) C0.3 0.3v cc v input low voltage (wc ) C0.3 0.5 v v ih input high voltage (e2, e1, e0, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 3 ma, v cc = 5 v 0.4 v symbol parameter test condition (in addition to those in table 8) min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in stand-by mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =2.5v, f c =400khz (rise/fall time < 30ns) 1ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 2.5 v 2a v il input low voltage (e2, e1, e0, scl, sda) C0.3 0.3v cc v input low voltage (wc ) C0.3 0.5 v v ih input high voltage (e2, e1, e0, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v 0.4 v
15/24 m24c64, m24c32 table 14. dc characteristics (m24cxx-r) symbol parameter test condition (in addition to those in table 9) min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in stand-by mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =1.8v, f c =100khz (rise/fall time < 30ns) 0.8 ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 1.8 v 0.2 a v il input low voltage (e2, e1, e0, scl, sda) C 0.3 0.3 v cc v input low voltage (wc ) C0.3 0.5 v v ih input high voltage (e2, e1, e0, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 0.7 ma, v cc = 1.8 v 0.2 v
m24c64, m24c32 16/24 table 15. ac characteristics (m24cxx, m24cxx-w) note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. 4. the write time of 5 ms only applies to devices b earing the process letter b in the package marking (on the top side of the pack- age), otherwise (for devices bearing the process letter n) the write time is 10 ms. for further details, please contact your nearest st sales office, and ask for a copy of the product change notice pcee0036. table 16. ac characteristics (m24cxx-r) note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. test conditions specified in table 10 and table 7 or 8 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 2 t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv 3 t aa clock low to next data valid (access time) 200 900 ns t chdx 1 t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 5 or 4 10 ms test conditions specified in table 10 and table 9 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 2 t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv 3 t aa clock low to next data valid (access time) 200 900 ns t chdx 1 t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 10 ms
17/24 m24c64, m24c32 figure 11. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795c start condition
m24c64, m24c32 18/24 package mechanical pdip8 C 8 pin plastic dip, 0.25mm lead frame, package outline notes: 1. drawing is not to scale. pdip8 C 8 pin plastic dip, 0.25mm lead frame, package mechanical data pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 C C 0.100 C C ea 7.62 C C 0.300 C C eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150
19/24 m24c64, m24c32 so8 narrow C 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. so8 narrow C 8 lead plastic small outline, 150 mils body width, package mechanical data so-a e n cp b e a d c l a1 a 1 h h x 45? symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004
m24c64, m24c32 20/24 tssop8 C 8 lead thin shrink small outline, package outline notes: 1. drawing is not to scale. tssop8 C 8 lead thin shrink small outline, package mechanical data tssop8am 1 8 cp c l e e1 d a2 a a e b 4 5 a1 l1 symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 C C 0.0256 C C e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 a 0 8 0 8
21/24 m24c64, m24c32 tssop8 3x3mm2 C 8 lead thin shrink small outline, 3x3mm2 body size, package outline notes: 1. drawing is not to scale. tssop8 3x3mm2 C 8 lead thin shrink small outline, 3x3mm2 body size, package mechanical data tssop8bm 1 8 cp c l e e1 d a2 a a e b 4 5 a1 l1 symbol mm inches typ. min. max. typ. min. max. a 1.100 0.0433 a1 0.050 0.150 0.0020 0.0059 a2 0.850 0.750 0.950 0.0335 0.0295 0.0374 b 0.250 0.400 0.0098 0.0157 c 0.130 0.230 0.0051 0.0091 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 4.900 4.650 5.150 0.1929 0.1831 0.2028 e1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 C C 0.0256 C C cp 0.100 0.0039 l 0.550 0.400 0.700 0.0217 0.0157 0.0276 l1 0.950 0.0374 a 0 6 0 6
m24c64, m24c32 22/24 part numbering table 17. ordering information scheme note: 1. available for m24c32 only. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: m24c64 Cwmn6t device type m24 = i 2 c serial access eeprom device function 64 = 64 kbit (8192 x 8) 32 = 32 kbit (4096 x 8) operating voltage blank = v cc = 4.5 to 5.5v w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v package bn = pdip8 mn = so8 (150 mil width) dw = tssop8 (169 mil width) ds 1 = tssop8 (3x3mm2 body size, msop8) temperature range 6 = C40 to 85 c option t = tape & reel packing
23/24 m24c64, m24c32 revision history table 18. document revision history date rev. description of revision 22-dec-1999 2.3 tssop8 package in place of tssop14 (pp 1, 2, orderinginfo, packagemechdata). 28-jun-2000 2.4 tssop8 package data corrected 31-oct-2000 2.5 references to temperature range 3 removed from ordering information voltage range -s added, and range -r removed from text and tables throughout. 20-apr-2001 2.6 lead soldering temperature in the absolute maximum ratings table amended write cycle polling flow chart using ack illustration updated references to psdip changed to pdip and package mechanical data updated 16-jan-2002 2.7 test condition for i li made more precise, and value of i li for e2-e0 and wc added -r voltage range added 02-aug-2002 2.8 document reformated using new template. tssop8 (3x3mm2 body size) package (msop8) added. 5ms write time offered for 5v and 2.5v devices 06-feb-2003 2.9 so8w package removed. -s voltage range removed
m24c64, m24c32 24/24 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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