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a sharc ? dsp microcomputer information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o.box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 world wide web site: http://www.analog.com fax:781/326-8703 ? analog devices, inc., 2001 rev. 0 sharc is a registered trademark of analog devices, inc. adsp-21160m summary high-performance 32-bit dsp?applications in audio, medical, military, graphics, imaging, and communication super harvard architecture?four independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead i/o backwards-compatible?assembly source level compatible with code for adsp-2106x dsps single-instruction-multiple-data (simd) computational architecture?two 32-bit ieee floating-point computation units, each with a multiplier, alu, shifter, and register file integrated peripherals?integrated i/o processor, 4 m bit on-chip dual-ported sram, glueless multiprocessing features, and ports (serial, link, external bus, and jtag) key features 80 mhz (12.5 ns) core instruction rate single-cycle instruction execution, including simd operations in both computational units 480 mflops peak and 320 mflops sustained performance (based on fir) dual data address generators (dags) with modulo and bit-reverse addressing zero-overhead looping and single-cycle loop setup, providing efficient program sequencing ieee 1149.1 jtag standard test access port and on-chip emulation 400-ball 27 27 mm metric pbga package functional block diagram ! " 6 # $ # % % % "%""$" %"" & adsp-21160m ?2? rev. 0 features (continued) single instruction multiple data (simd) architecture provides: two computational processing elements concurrent execution ? each processing element executes the same instruction, but operates on different data code compatibility ? at assembly level, uses the same instruction set as the adsp-2106x sharc dsps parallelism in buses and computational units allows: single-cycle execution (with or without simd) of: a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle accelerated fft butterfly computation through a multiply with add and subtract 4m bit on-chip dual-ported sram for independent access by core processor, host, and dma dma controller supports: 14 zero-overhead dma channels for transfers between adsp-21160m internal memory and external memory, external peripherals, host processor, serial ports, or link ports 64-bit background dma transfers at core clock speed, in parallel with full-speed processor execution 560m bytes/s transfer rate over iop bus host processor interface to 16- and 32-bit microprocessors 4g word address range for off-chip memory memory interface supports programmable wait state generation and page-mode for off-chip memory multiprocessing support provides: glueless connection for scalable dsp multiprocessing architecture distributed on-chip bus arbitration for parallel bus connect of up to six adsp-21160ms plus host six link ports for point-to-point connectivity and array multiprocessing serial ports provide: two 40m bit/s synchronous serial ports with companding hardware independent transmit and receive functions tdm support for t1 and e1 interfaces 64-bit wide synchronous external port provides: glueless connection to asynchronous and sbsram external memories up to 40 mhz operation general description the adsp-21160m sharc dsp is the first processor in a new family featuring analog devices? super harvard architecture. easing portability, the adsp- 21160m is application source code compatible with first generation adsp-2106x sharc dsps in sisd (single instruction, single data) mode. to take advantage of the processor?s simd (single instruction, multiple data) capability, some code changes are needed. like other sharcs, the adsp-21160m is a 32-bit processor that is optimized for high performance dsp applications. the adsp-21160m includes an 80 mhz core, a dual-ported on-chip sram, an integrated i/o processor with multiprocessing support, and multiple internal buses to eliminate i/o bottlenecks. the adsp-21160m introduces single-instruction, multiple-data (simd) processing. using two computa- tional units (adsp-2106x sharc dsps have one), the adsp-21160m can double performance versus the adsp-2106x on a range of dsp algorithms. fabricated in a state of the art, high speed, low power cmos process, the adsp-21160m has a 12.5 ns instruc- tion cycle time. with its simd computational hardware running at 80 mhz, the adsp-21160m can perform 480 million math operations per second. table 1 shows performance benchmarks for the adsp-21160m. these benchmarks provide single-channel extrapolations of measured dual-channel processing performance. for more information on benchmarking and optimizing dsp code for single- and dual-channel processing, see analog devices?s website. the adsp-21160m continues sharc?s industry-leading standards of integration for dsps, combining a high-performance 32-bit dsp core with integrated, on-chip system features. these features include a 4m bit dual ported sram memory, host processor interface, i/o processor that supports 14 dma channels, two serial ports, six link ports, external parallel bus, and glueless multiprocessing. table 1. adsp-21160m benchmarks benchmark algorithm speed 1024 point complex fft (radix 4, with reversal) 115 s fir filter (per tap) 6.25 ns iir filter (per biquad) 25 ns matrix multiply (pipelined) [3 3] [3 1] 56.25 ns matrix multiply (pipelined) [4 4] [4 1] 100 ns divide (y/x) 37.5 ns inverse square root 56.25 ns dma transfer rate 560m bytes/s ? 3 ? rev. 0 adsp-21160m the functional block diagram on page 1 shows a block diagram of the adsp-21160m, illustrating the following architectural features: two processing elements, each made up of an alu, mul- tiplier, shifter, and data register file data address generators (dag1, dag2) program sequencer with instruction cache pm and dm buses capable of supporting four 32-bit data transfers between memory and the core every core processor cycle interval timer on-chip sram (4 mbit) external port that supports: interfacing to off-chip memory peripherals glueless multiprocessing support for six adsp-21160m sharcs host port dma controller serial ports and link ports jtag test access port figure 1 shows a typical single-processor system. a multi- processing system appears in figure 4 . adsp-21160m family core architecture the adsp-21160m includes the following archi- tectural features of the adsp-2116x family core. the adsp-21160m is code compatible at the assembly level with the adsp-21060, adsp-21061, and adsp-21062. simd computational engine the adsp-21160m contains two computational process- ing elements that operate as a single instruction multiple data (simd) engine. the processing elements are referred to as pex and pey, and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. this architecture is efficient at executing math-intensive dsp algorithms. entering simd mode also has an effect on the way data is transferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the processing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arith- metic/logic unit (alu), multiplier, and shifter. these units perform single-cycle instructions. the three units within each processing element are arranged in parallel, maximiz- ing computational throughput. single multifunction instructions execute parallel alu and multiplier opera- tions. in simd mode, the parallel alu and multiplier operations occur in both processing elements. these com- putation units support ieee 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is contained in each processing element. the register files transfer data between the computation units and the data buses, and store inter- mediate results. these 10-port, 32-register (16 primary, 16 secondary) register files, combined with the adsp-2116x enhanced harvard architecture, allow unconstrained data flow between computation units and internal memory. the registers in pex are referred to as r0 ? r15 and in pey as s0 ? s15. single-cycle fetch of instruction and four operands the adsp-21160m features an enhanced harvard archi- tecture in which the data memory (dm) bus transfers data, and the program memory (pm) bus transfers both instruc- tions and data (see the functional block diagram on page 1 ). figure 1. single-processor system ! " # $ $ %$ &" $ " $ '$ " " " " $ ! ! $ $ ( $ ( $ " adsp-21160m ? 4 ? rev. 0 with the adsp-21160m ? s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands and an instruction (from the cache), all in a single cycle. instruction cache the adsp-21160m includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. the cache is selective ? only the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed execution of core, providing looped operations such as digital filter multiply- accumulates and fft butterfly processing. data address generators with hardware circular buffers the adsp-21160m ? s two data address generators (dags) are used for indirect addressing and provide for implement- ing circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data struc- tures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the adsp-21160m contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags auto- matically handle address pointer wraparound, reducing overhead, increasing performance, and simplifying imple- mentation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise programming. for example, the adsp-21160m can conditionally execute a multiply, an add, and subtract, in both processing elements, while branching, all in a single instruction. adsp-21160m memory and i/o interface features augmenting the adsp-2116x family core, the adsp-21160m adds the following architectural features: dual-ported on-chip memory the adsp-21160m contains four megabits of on-chip sram, organized as two blocks of 2 mbits each, which can be configured for different combinations of code and data storage. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o proces- sor. the dual-ported memory in combination with three separate on-chip buses allows two data transfers from the core and one from i/o processor, in a single cycle. on the adsp-21160m, the memory can be configured as a maximum of 128k words of 32-bit data, 256k words of 16-bit data, 85k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the dm bus for transfers, and the other block stores instructions and data, using the pm bus for transfers. using the dm bus and pm bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data trans- fers. in this case, the instruction must be available in the cache. off-chip memory and peripherals interface the adsp-21160m ? s external port provides the proces- sor ? s interface to off-chip memory and peripherals. the 4g word off-chip address space is included in the adsp-21160m ? s unified address space. the separate on-chip buses ? for pm addresses, pm data, dm addresses, dm data, i/o addresses, and i/o data ? are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 64-bit data bus. the lower 32 bits of the external data bus connect to even addresses and the upper 32 bits of the 64 connect to odd addresses. every access to external memory is based on an address that fetches a 32-bit word, and with the 64-bit bus, two address locations can be accessed at once. when fetching an instruction from external memory, two 32-bit data locations are being accessed (16 bits are unused). figure 3 shows the alignment of various accesses to external memory. the external port supports asynchronous, synchronous, and synchronous burst accesses. zbt synchronous burst sram can be interfaced gluelessly. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. separate control lines are also generated for simpli- fied addressing of page-mode dram. the adsp-21160m provides programmable memory wait states and external memory acknowledge controls to allow interfacing to dram and peripherals with variable access, hold, and disable time requirements. dma controller the adsp-21160m ? s on-chip dma controller allows zero-overhead data transfers without processor interven- tion. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between the adsp-21160m ? s internal memory and external memory, external peripherals, or a host processor. dma transfers can also occur between the adsp-21160m ? s internal memory and its serial ports or link ports. external bus packing to 16-, 32-, 48-, or 64-bit words is performed during dma transfers. fourteen channels of dma are available on the adsp-21160m ? six via the link ports, four via the serial ports, and four via the processor ? s external port (for either ? 5 ? rev. 0 adsp-21160m host processor, other adsp-21160ms, memory or i/o transfers). programs can be downloaded to the adsp-21160m using dma transfers. asynchronous off-chip peripherals can control two dma channels using dma request/grant lines (dmar1 ? 2 , dmag1 ? 2 ). other dma features include interrupt generation upon completion of dma transfers, two-dimensional dma, and dma chaining for automatic linked dma transfers. multiprocessing the adsp-21160m offers powerful features tailored to multiprocessing dsp systems as shown in figure 4 . the external port and link ports provide integrated glueless mul- tiprocessing support. the external port supports a unified address space (see figure 2 ) that allows direct interprocessor accesses of each adsp-21160m ? s internal memory. distributed bus arbitra- tion logic is included on-chip for simple, glueless connection of systems containing up to six adsp-21160ms and a host processor. master processor changeover incurs only one cycle of overhead. bus arbitration is selectable as either fixed or rotating priority. bus lock allows indivisible read-mod- ify-write sequences for semaphores. a vector interrupt is provided for interprocessor commands. maximum throughput for interprocessor data transfer is 320m bytes/s over the external port. broadcast writes allow simultaneous transmission of data to all adsp-21160ms and can be used to implement reflective semaphores. six link ports provide for a second method of multiprocess- ing communications. each link port can support communications to another adsp-21160m. using the links, a large multiprocessor system can be constructed in a 2d or 3d fashion. systems can use the link ports and cluster multiprocessing concurrently or independently. link ports the adsp-21160m features six 8-bit link ports that provide additional i/o capabilities. with the capability of running at 80 mhz rates, each link port can support 80m bytes/s. link port i/o is especially useful for point-to-point interprocessor communication in multiprocessing systems. the link ports can operate independently and simulta- neously. link port data is packed into 48- or 32-bit words, and can be directly read by the core processor or dma-transferred to on-chip memory. each link port has its own double-buffered input and output registers. clock/acknowledge handshaking controls link port trans- fers. transfers are programmable as either transmit or receive. for data throughput information, see link port timing details in table 18 on page 34 . serial ports the adsp-21160m features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. the serial ports can operate up to half the clock rate of the core, providing each with a maximum data rate of 40m bit/s. independent figure 2. adsp-21160m memory map ) * ' '""""" ) """""""" +,-.+/0 -12.3 4/5- ,-.+/0 -12.3 4/5- -678 2+6(2.9 2.1/0(2.9 :2.,(2.9 +,-.+/0 4/5- +,-.+/0 4/5- +,-.+/0 4/5- +,-.+/0 4/5- +,-.+/0 4/5- +,-.+/0 4/5- .2/95/8, 00 8 /+; /+; /+; /+; 2++;-9 -12.3 = = -12.3 = -12.3 -12.3 = (.>,-,2 = -12.3 = -12.3 = figure 3. adsp-21160m external data alignment options ! " ### " $% & $ & ' ' adsp-21160m ? 6 ? rev. 0 transmit and receive functions provide greater flexibility for serial communications. serial port data can be automati- cally transferred to and from on-chip memory via a dedicated dma. each of the serial ports offers a tdm multichannel mode. the serial ports can operate with lit- tle-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. they offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be internally or externally generated. host processor interface the adsp-21160m host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. the host interface is accessed through the adsp-21160m ? s external port and is memory-mapped into the unified address space. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor communicates with the adsp-21160m ? s external bus with host bus request (hbr ), host but grant (hbg ), ready (redy), acknowledge (ack), and chip select (cs) signals. the host can directly read and write the internal memory of the adsp-21160m, and can access the dma channel setup and mailbox regis- ters. vector interrupt support provides efficient execution of host commands. program booting the internal memory of the adsp-21160m can be booted at system power-up from an 8-bit eprom, a host proces- sor, or through one of the link ports. selection of the boot source is controlled by the bms (boot memory select), eboot (eprom boot), and lboot (link/host boot) pins. 32-bit and 16-bit host processors can be used for booting. phased locked loop the adsp-21160m uses an on-chip pll to generate the internal clock for the core. ratios of 2:1, 3:1, and 4:1 between the core and clkin are supported. the clk_cfg pins are used to select the ratio. the clkin rate is the rate at which the synchronous external port operates. power supplies the adsp-21160m has separate power supply connections for the internal (v ddint ), external (v ddext ), and analog (av dd /agnd) power supplies. the internal and analog supplies must meet the 2.5 v requirement. the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same supply. note that the analog supply (av dd ) powers the adsp-21160m ? s clock generator pll. to produce a stable clock, the system must provide an external circuit to filter the power input to the av dd pin. place the filter as close as possible to the pin. for an example circuit, see figure 5 . to prevent noise coupling, use a wide trace for the analog ground (agnd) signal and install a decoupling capacitor as close as possible to the pin. figure 4. shared memory multiprocessing system $ $ ? * @ $ ? $ $ $@ $ ? * $ $ $ ? ?* ? ! " ! $ # $ $ $ ! ! ( ( * ? 7 ? rev. 0 adsp-21160m development tools the adsp-21160m is supported with a complete set of software and hardware development tools, including analog devices ? emulators and visualdsp++ 1 development envi- ronment. the same emulator hardware that supports other adsp-2116x dsps, also fully emulates the adsp-21160m. the visualdsp++ project management environment lets programmers develop and debug an application. this envi- ronment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simula- tor, a c/c++ compiler, and a c/c++ run-time library that includes dsp and mathematical functions. two key points for these tools are: compiled adsp-2116x c/c++ code efficiency ? the compiler has been developed for efficient translation of c/c++ code to adsp-2116x assembly. the dsp has architectural features that improve the efficiency of compiled c/c++ code. adsp-2106x family code compatib ility ? the assembler has legacy features to ease the conversion of existing adsp-2106x applications to the adsp-2116x. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: view mixed c/c++ and assembly code (interleaved source and object information) insert break points set conditional breakpoints on registers, memory, and stacks trace instruction execution perform linear or statistical profiling of program execution fill, dump, and graphically plot the contents of memory source level debugging create custom debugger windows the visualdsp++ ide lets programmers define and manage dsp software development. its dialog boxes and property pages let programmers configure and manage all of the adsp-2116x development tools, including the syntax highlighting in the visualdsp++ editor. this capability permits: control how the development tools process inputs and generate outputs. maintain a one-to-one correspondence with the tool ? s command line switches. analog devices ? dsp emulators use the ieee 1149.1 jtag test access port of the adsp-21160m processor to monitor and control the target board processor during emulation. the emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. nonintrusive in-circuit emulation is assured by the use of the processor ? s jtag interface ? the emulator does not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the adsp-2116x processor family. hardware tools include adsp-2116x pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the white mountain dsp (product line of analog devices, inc.) family of emulators are tools that every dsp developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halted to send data and commands, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the target ? s design must include the interface between an analog devices ? jtag dsp and the emulation header on a custom dsp target board. target board header the emulator interface to an analog devices ? jtag dsp is a 14-pin header, as shown in figure 6 . the customer must supply this header on the target board in order to commu- nicate with the emulator. the interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1" spacing, with a minimum post length of 0.235". pin 3 is the key position used to prevent the pod from being inserted backwards. this pin must be clipped on the target board. figure 5. analog power (av dd ) filter circuit 1 visualdsp++ is a registered trademark of analog devices, inc. adsp-21160m ? 8 ? rev. 0 also, the clearance (length, width, and height) around the header must be considered. leave a clearance of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector. as can be seen in figure 6 , there are two sets of signals on the header. there are the standard jtag signals tms, tck, tdi, tdo, trst , and emu used for emulation purposes (via an emulator). there are also secondary jtag signals btms, btck, btdi, and btrst that are option- ally used for board-level (boundary scan) testing. when the emulator is not connected to this header, place jumpers across btms, btck, btrst , and btdi as shown in figure 7 . this holds the jtag signals in the correct state to allow the dsp to run free. remove all the jumpers when connecting the emulator to the jtag header. jtag emulator pod connector figure 8 details the dimensions of the jtag pod connector at the 14-pin target end. figure 9 displays the keep-out area for a target board header. the keep-out area allows the pod connector to properly seat onto the target board header. this board area should contain no components (chips, resistors, capacitors, etc.). the dimensions are referenced to the center of the 0.25" square post pin. design-for-emulation circuit information for details on target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ? use site search on ? ee-68 ? (www.analog.com). this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a general overview of the adsp-21160m architecture and functionality. for detailed information on the adsp-2116x family core architecture and instruction set, refer to the adsp-2116x sharc dsp hardware reference . pin function descriptions adsp-21160m pin definitions are listed below. inputs identified as synchronous (s) must meet timing require- ments with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). figure 6. jtag target board connector for jtag equipped analog devices dsp (jumpers in place) figure 9. jtag pod connector keep-out area ( a a ') * # bc b*c figure 7. jtag target board connector with no local boundary scan figure 8. jtag pod connector dimensions ( a a ') * # b c b))c b c ? 9 ? rev. 0 adsp-21160m unused inputs should be tied or pulled to vdd or gnd, except for addr31 ? 0, data63 ? 0, flag3 ? 0, and inputs that have internal pull-up or pull-down resistors (pa , ack, brst , page, clkout, ms 3 ? 0, rdx , wrx , dmarx , dmagx , dtx, drx, tclkx, rclkx, lxdat7 ? 0, lxclk, lxack, tms, trst and tdi) ? these pins can be left floating. these pins have a logic-level hold circuit (only enabled on the adsp-21160m with id2 ? 0 = 00x) that prevents input from floating internally. the following symbols appear in the type column of table 2 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d)=active drive, (o/d)=open drain, and t = three-state (when sbts is asserted, or when the adsp-21160m is a bus slave). table 2. pin function descriptions pin type function addr31 ? 0 i/o/t external bus address. the adsp-21160m outputs addresses for external memory and peripherals on these pins. in a multiprocessor system, the bus master outputs addresses for read/writes of the internal memory or iop registers of other adsp-21160ms. the adsp-21160m inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or iop registers. a keeper latch on the dsp ? s addr31 ? 0 pins maintains the input at the level it was last driven (only enabled on the adsp-21160m with id2 ? 0 = 00x). data63 ? 0 i/o/t external bus data. the adsp-21160m inputs and outputs data and instructions on these pins. pull-up resistors on unused data pins are not necessary. a keeper latch on the dsp ? s data63-0 pins maintains the input at the level it was last driven (only enabled on the adsp-21160m with id2 ? 0 = 00x). ms3 ? 0 o/t memory select lines. these outputs are asserted (low) as chip selects for the corre- sponding banks of external memory. memory bank size must be defined in the syscon control register. the ms3 ? 0 outputs are decoded memory address lines. in asyn- chronous access mode, the ms3 ? 0 outputs transition with the other address outputs. in synchronous access modes, the ms3 ? 0 outputs assert with the other address lines; however, they de-assert after the first clkin cycle in which ack is sampled asserted. rdl i/o/t memory read low strobe. rdl is asserted whenever adsp-21160m reads from the low word of external memory or from the internal memory of other adsp-21160ms. external devices, including other adsp-21160ms, must assert rdl for reading from the low word of adsp-21160m internal memory. in a multiprocessing system, rdl is driven by the bus master. rdh i/o/t memory read high strobe. rdh is asserted whenever adsp-21160m reads from the high word of external memory or from the internal memory of other adsp-21160ms. external devices, including other adsp-21160ms, must assert rdh for reading from the high word of adsp-21160m internal memory. in a multiprocessing system, rdh is driven by the bus master. wrl i/o/t memory write low strobe. wrl is asserted when adsp-21160m writes to the low word of external memory or internal memory of other adsp-21160ms. external devices must assert wrl for writing to adsp-21160m ? s low word of internal memory. in a multiprocessing system, wrl is driven by the bus master. wrh i/o/t memory write high strobe. wrh is asserted when adsp-21160m writes to the high word of external memory or internal memory of other adsp-21160ms. external devices must assert wrh for writing to adsp-21160m ? s high word of internal memory. in a multiprocessing system, wrh is driven by the bus master. page o/t dram page boundary. the adsp-21160m asserts this pin to signal that an external dram page boundary has been crossed. dram page size must be defined in the adsp-21160m ? s memory control register (wait). dram can only be implemented in external memor y bank 0; the page signal can only be activated for bank 0 accesses. in a multiprocessing system page is output by the bus master. a keeper latch on the dsp ? s page pin maintains the output at the level it was last driven (only enabled on the adsp-21160m with id2 ? 0 = 00x). adsp-21160m ? 10 ? rev. 0 brst i/o/t sequential burst access. brst is asserted by adsp-21160m or a host to indicate that data associated with consecutive addresses is being read or written. a slave device samples the initial address and increments an internal address counter after each transfer. the incremented address is not pipelined on the bus. if the burst access is a read from host to adsp-21160m, adsp-21160m automatically increments the address as long as brst is asserted. brst is asserted after the initial access of a burst transfer. it is asserted for every cycle after that, except for the last data request cycle (denoted by rdx or wrx asserted and brst negated). a keeper latch on the dsp ? s brst pin maintains the input at the level it was last driven (only enabled on the adsp-21160m with id2 ? 0 = 00x). ack i/o/s memor y acknowledge. external devices can de-assert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. the adsp-21160m deasserts ack as an output to add wait states to a synchronous access of its internal memory. a keeper latch on the dsp ? s ack pin maintains the input at the level it was last driven (only enabled on the adsp-21160m with id2 ? 0 = 00x). sbts i/s suspend bus and three-state. external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. if the adsp-21160m attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is deasserted. sbts should only be used to recover from host processor and/or adsp-21160m deadlock or used with a dram controller. irq2 ? 0 i/a interrupt request lines. these are sampled on the rising edge of clkin and may be either edge-triggered or level-sensitive. flag3 ? 0 i/o/a flag pins. each is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. timexp o timer expired. asserted for four clkin cycles when the timer is enabled and tcount decrements to zero. hbr i/a host bus request. must be asserted by a host processor to request control of the adsp-21160m ? s external bus. when hbr is asserted in a multiprocessing system, the adsp-21160m that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the adsp-21160m places the address, data, select, and strobe lines in a high impedance state. hbr has priority over all adsp-21160m bus requests (br6 ? 1 ) in a multiprocessing system. hbg i/o host bus grant. acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the adsp-21160m until hbr is released. in a multiprocessing system, hbg is output by the adsp-21160m bus master and is monitored by all others. cs i/a chip select. asserted by host processor to select the adsp-21160m. redy o (o/d) host bus acknowledge. the adsp-21160m deasserts redy (low) to add waitstates to a host access when cs and hbr inputs are asserted. dmar1 i/a dma request 1 (dma channel 11). asserted by external port devices to request dma services. dmar2 i/a dma request 2 (dma channel 12). asserted by external port devices to request dma services. id2 ? 0 i multiprocessing id. determines which multiprocessing bus request (br1 ? br6 ) is used by adsp-21160m. id = 001 corresponds to br1 , id = 010 corresponds to br2 , and so on. use id = 000 or id = 001 in single-processor systems. these lines are a system configuration selection which should be hardwired or only changed at reset. dmag1 o/t dma grant 1 (dma channel 11). asserted by adsp-21160m to indicate that the requested dma starts on the next cycle. driven by bus master only. table 2. pin function descriptions (continued) pin type function ? 11 ? rev. 0 adsp-21160m dmag2 o/t dma grant 2 (dma channel 12). asserted by adsp-21160m to indicate that the requested dma starts on the next cycle. driven by bus master only. br6 ? 1 i/o/s multiprocessing bus requests. used by multiprocessing adsp-21160ms to arbitrate for bus mastership. an adsp-21160m only drives its own brx line (corresponding to the value of its id2 ? 0 inputs) and monitors all others. in a multiprocessor system with less than six adsp-21160ms, the unused brx pins should be pulled high; the processor ? s own brx line must not be pulled high or low because it is an output. rpba i/s rotating priority bus arbitration select. when rpba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system configuration selection which must be set to the same value on every adsp-21160m. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-21160m. pa i/o/t priority access. asserting its pa pin allows an adsp-21160m bus slave to interrupt background dma transfers and gain access to the external bus. pa is connected to all adsp-21160ms in the system. if access priority is not required in a system, the pa pin should be left unconnected. dtx o data transmit (serial ports 0, 1). each dt pin has a 50 k ? internal pull-up resistor. drx i data receive (serial ports 0, 1). each dr pin has a 50 k ? internal pull-up resistor. tclkx i/o transmit clock (serial ports 0, 1). each tclk pin has a 50 k ? internal pull-up resistor. rclkx i/o receive clock (serial ports 0, 1). each rclk pin has a 50 k ? internal pull-up resistor. tfsx i/o transmit frame sync (serial ports 0, 1). rfsx i/o receive frame sync (serial ports 0, 1). lxdat7 ? 0 i/o link port data (link ports 0 ? 5). each lxdat pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lctl0 ? 1 register. lxclk i/o link port clock (link ports 0 ? 5). each lxclk pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lctl0 ? 1register. lxack i/o link port acknowledge (link ports 0 ? 5). each lxack pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register. eboot i eprom boot select. for a description of how this pin operates, see table 3 . this signal is a system configuration selection that should be hardwired. lboot i link boot. for a description of how this pin operates, see table 3 . this signal is a system configuration selection that should be hardwired. bms i/o/t boot memory select. serves as an output or input as selected with the eboot and lboot pins; see table 3 . this input is a system configuration selection that should be hardwired. clkin i local clock in. clkin is the adsp-21160m clock input. the adsp-21160m external port cycles at the frequency of clkin. the instruction cycle rate is a multiple of the clkin frequency; it is programmable at power-up. clkin may not be halted, changed, or operated below the specified frequency. clk_cfg3 ? 0 i core/clkin ratio control. adsp-21160m core clock (instruction cycle) rate is equal to n clkin where n is user-selectable to 2, 3, or 4, using the clk_cfg3 ? 0 inputs. for clock configuration definitions, see the reset & clkin section of the system design chapter of the adsp-21160 sharc dsp hardware reference manual. clkout o/t local clock out. clkout is driven at the clkin frequency by the current bus master. this output is three-stated when the adsp-21160m is not the bus master, or when the host controls the bus (hbg asserted). a keeper latch on the dsp ? s clkout pin maintains the output at the level it was last driven (only enabled on the adsp-21160m with id2 ? 0 = 00x). reset i/a processor reset. resets the adsp-21160m to a known state and begins execution at the program memory location specified by the hardware reset vector address. the reset input must be asserted (low) at power-up. table 2. pin function descriptions (continued) pin type function adsp-21160m ? 12 ? rev. 0 tck i test clock (jtag). provides a clock for jtag boundary scan. tms i/s test mode select (jtag). used to control the test state machine. tms has a 20 k ? internal pull-up resistor. tdi i/s test data input (jtag). provides serial data for the boundary scan logic. tdi has a 20 k ? internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan path. trst i/a test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21160m. trst has a 20 k ? internal pull-up resistor. emu o (o/d) emulation status. must be connected to the adsp-21160m emulator target board connector only. emu has a 50 k ? internal pull-up resistor. cif o/t core instruction fetch. signal is active low when an external instruction fetch is performed. driven by bus master only. three-state when host is bus master. v ddint p core power supply. nominally 2.5 v dc and supplies the dsp ? s core processor (40 pins). v ddext p i/o power supply. nominally 3.3 v dc (46 pins). av dd p analog power supply. nominally 2.5 v dc and supplies the dsp ? s internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitry is required. for more information, see power supplies on page 6. agnd g analog power supply return. gnd g power supply return. (83 pins) nc do not connect. reserved pins that must be left open and unconnected (5 pins). table 3. boot mode selection eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select.) 001 (input)host processor 0 1 1 (input) link port 0 0 0 (input) no booting. processor executes from external memory. 010 (input)reserved 1 1 x (input) reserved table 2. pin function descriptions (continued) pin type function ? 13 ? rev. 0 adsp-21160m adsp-21160m specifications recommended operating conditions signal k grade parameter 1 min max unit v ddint internal (core) supply voltage 2.37 2.63 v av dd analog (pll) supply voltage 2.37 2.63 v v ddext external (i/o) supply voltage 3.13 3.47 v v ih1 high level input voltage 2 , @ v ddext =max 2.2 v ddext +0.5 v v ih2 high level input voltage 3 , @ v ddext =max 2.3 v ddext +0.5 v v il low level input voltage 2,3 , @ v ddext =min ? 0.5 0.8 v t case case operating temperature 4 085 o c 1 specifications subject to change without notice. 2 applies to input and bidirectional pins: data63 ? 0, addr31 ? 0, rdx , wrx , ack, sbts , irq2 ? 0 , flag3 ? 0, hbg , cs , dmar1 , dmar2 , br6 ? 1 , id2 ? 0, rpba, pa , brst , tfs0, tfs1, rfs0, rfs1, lxdat3 ? 0, lxclk, lxack, eboot, lboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, rclk1. 3 applies to input pins: clkin, reset , trst . 4 see environmental conditions on page 45 for information on thermal specifications. electrical characteristics parameter 1 test conditions min max unit v oh high level output voltage 2 @ v ddext =min, i oh = ? 2.0 ma 3 2.4 v v ol low level output voltage 2 @ v ddext =min, i ol =4.0 ma 3 0.4 v i ih high level input current 4,5,6 @ v ddext =max, v in =v dd max 10 a i il low level input current 4 @ v ddext =max, v in =0 v 10 a i ilpu1 low level input current pull-up1 5 @ v ddext =max, v in =0 v 250 a i ilpu2 low level input current pull-up2 6 @ v ddext =max, v in =0 v 500 a i ozh three-state leakage current 7,8,9,10 @ v ddext =max, v in =v dd max 10 a i ozl three-state leakage current 7 @ v ddext =max, v in =0 v 10 a i ozhpd three-state leakage current pull-down 10 @ v ddext =max, v in =v dd max 250 a i ozlpu1 three-state leakage current pull-up1 8 @ v ddext =max, v in =0 v 250 a i ozlpu2 three-state leakage current pull-up2 9 @ v ddext =max, v in =0 v 500 a i ozha three-state leakage current 11 @ v ddext =max, v in =v dd max 25 a i ozla three-state leakage current 11 @ v ddext =max, v in =0 v 4 ma i dd-inpeak supply current (internal) 12 t cclk =12.5 ns, v ddint =max 1400 ma i dd-inhigh supply current (internal) 13 t cclk =12.5 ns, v ddint =max 875 ma i dd-inlow supply current (internal) 14 t cclk =12.5 ns, v ddint =max 625 ma i dd-idle supply current (idle) 15 t cclk =12.5 ns, v ddint =max 80 ma ai dd supply current (analog) 16 @av dd =max 10 ma c in input capacitance 17,18 f in =1 mhz, t case =25 c, v in =2.5 v 4.7 pf 1 specifications subject to change without notice. 2 applies to output and bidirectional pins: data63 ? 0, addr31 ? 0, ms3 ? 0 , rdx , wrx , page, clkout, ack, flag3 ? 0, timexp, hbg , redy, dmag1 , dmag2 , br6 ? 1 , pa , brst , cif , dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat3 ? 0, lxclk, lxack, bms , tdo, emu . 3 see output drive currents on page 42 for typical drive current capabilities. 4 applies to input pins: ack, sbts , irq2 ? 0 , hbr , cs , id2 ? 0, rpba, eboot, lboot, clkin, reset , tck, clk_cfg3-0. adsp-21160m ? 14 ? rev. 0 absolute maximum ratings esd sensitivity 5 applies to input pins with internal pull-ups: dr0, dr1. 6 applies to input pins with internal pull-ups: dmarx , tms, tdi, trst . 7 applies to three-statable pins: data63 ? 0, addr31 ? 0, page, clkout, ack, flag3 ? 0, redy, hbg , bms , br6 ? 1 , tfsx, rfsx, tdo. 8 applies to three-statable pins with internal pull-ups: dtx, tclkx, rclkx, emu. 9 applies to three-statable pins with internal pull-ups: ms3 ? 0 , rdx , wrx , dmagx , pa , cif . 10 applies to three-statable pins with internal pull-downs: lxdat7 ? 0, lxclk, lxack. 11 applies to ack pulled up internally with 2 k ? during reset or id2 ? 0= 00x. 12 the test program used to measure i dd-inpeak represents worst case processor operation and is not sustainable under normal application conditions. actual internal power measurements made using typical applications are less than specified. for more information, see power dissipation on page 42. 13 i ddinhigh is a composite average based on a range of high activity code. for more information, see power dissipation on page 42. 14 i ddinlow is a composite average based on a range of low activity code. for more information, see power dissipation on page 42. 15 idle denotes adsp-21160m state during execution of idle instruction. for more information, see power dissipation on page 42. 16 characterized, but not tested. 17 applies to all signal pins. 18 guaranteed, but not tested. internal (core) supply voltage (v ddint ) 1 . . . ? 0.3 v to +3.0 v analog (pll) supply voltage (a vdd ) . . . . . ? 0.3 v to +3.0 v external (i/o) supply voltage (v ddext ) . . . . ? 0.3 v to +4.6 v input voltage . . . . . . . . . . . . . . . . . . ? 0.5 v to v ddext +0.5 v output voltage swing . . . . . . . . . . . ? 0.5 v to v ddext +0.5 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf storage temperature range . . . . . . . . . . . ? 65 o c to +150 o c lead temperature (5 seconds) . . . . . . . . . . . . . . . . . 185 o c 1 stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution: esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-21160m features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electro- static discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ? 15 ? rev. 0 adsp-21160m timing specifications the adsp-21160m ? s internal clock switches at higher fre- quencies than the system input clock (clkin). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsp ? s internal clock (the clock source for the external port logic and i/o pads). the adsp-21160m ? s internal clock (a multiple of clkin) provides the clock signal for timing internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchronous access mode). during reset, program the ratio between the dsp ? s internal clock frequency and external (clkin) clock frequency with the clk_cfg3 ? 0 pins. even though the internal clock is the clock source for the external port, the external port clock always switches at the clkin fre- quency. to determine switching frequencies for the serial and link ports, divide down the internal clock, using the programmable divider control of each port (tdivx/rdivx for the serial ports and lxclkd1 ? 0 for the link ports). note the following definitions of various clock periods that are a function of clkin and the appropriate ratio control: t cclk = (t ck ) / cr t lclk = (t cclk ) lr t sclk = (t cclk ) sr where: lclk = link port clock sclk = serial port clock t ck = clkin clock period t cclk = (processor) core clock period t lclk = link port clock period t sclk = serial port clock period cr = core/clkin ratio (2, 3, or 4:1, determined by clk_cfg3 ? 0 at reset) lr = link port/core clock ratio (1, 2, 3, or 4:1, determined by lxclkd) sr = serial port/core clock ratio (wide range, determined by clkdiv) use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaning- ful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. con- sequently, it is not meaningful to add parameters to derive longer times. see figure 32 under test conditions for voltage reference levels. switching characteristics specify how the processor changes its signals. circuitry external to the processor must be designed for compatibility with these signal characteris- tics. switching characteristics describe what the processor will do in a given circumstance. use switching characteris- tics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. adsp-21160m ? 16 ? rev. 0 clock input reset table 4. clock input parameter 80 mhz unit min max timing requirements: t ck clkin period 25 80 ns t ckl clkin width low 10.5 40 ns t ckh clkin width high 10.5 40 ns t ckrf clkin rise/fall (0.4v ? 2.0v) 3 ns figure 10. clock input table 5. reset parameter min max unit timing requirements: t wrst reset pulsewidth low 1 1 applies after the power-up sequence is complete. at power-up, the processor ? s internal phase-locked loop requires no more than 100 ms while reset is low, assuming stable vdd and clkin (not including start-up time of external clock oscillator). 4t ck ns t srst reset setup before clkin high 2 2 only required if multiple adsp-21160ms must come out of reset synchronous to clkin with program counters (pc) equal. not requir ed for multiple adsp-21160ms communicating over the shared bus (through the external port), because the bus arbitration logic automatically syn chronizes itself after reset. 8ns figure 11. reset , ! , , , ( , ? 17 ? rev. 0 adsp-21160m interrupts timer table 6. interrupts parameter min max unit timing requirements: t sir irq2 ? 0 setup before clkin high 1 6ns t hir irq2 ? 0 hold after clkin high 1 0ns t ipw irq2 ? 0 pulsewidth 2 2+t ck ns 1 only required for irqx recognition in the following cycle. 2 applies only if t sir and t hir requirements are not met. figure 12. interrupts %$ , ( , , ! table 7. timer parameter min max unit switching characteristic: t dtex clkin high to timexp 1 7 ns figure 13. timer , , adsp-21160m ? 18 ? rev. 0 flags table 8. flags parameter min max unit timing requirements: t sfi flag3 ? 0 in setup before clkin high 1 1 flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cycl e n+2. 4ns t hfi flag3 ? 0 in hold after clkin high 1 1ns t dwrfi flag3 ? 0 in delay after rdx /wrx low 1 12 ns t hfiwr flag3 ? 0 in hold after rdx /wrx deasserted 1 0ns switching characteristics: t dfo flag3 ? 0 out delay after clkin high 9 ns t hfo flag3 ? 0 out hold after clkin high 1 ns t dfoe clkin high to flag3 ? 0 out enable 1 ns t dfod clkin high to flag3 ? 0 out disable 5 ns figure 14. flags " $ # "## @ ( "# " $ , " , !" , " , " , " , " , !" , !"( , ( " ? 19 ? rev. 0 adsp-21160m memory read?bus master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkin. these specifications apply when the adsp-21160m is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only applies to asynchronous access mode. table 9. memory read?bus master parameter min max unit timing requirements: t dad address, cif , selects delay to data valid 1,2 t ck ? 0.25t cclk ? 11+w ns t drld rdx low to data valid 1,3 0.75t ck ? 11+w ns t hda data hold from address, selects 4 0ns t sds data setup to rdx high 1 8ns t hdrh data hold from rdx high 3,4 1ns t daak ack delay from address, selects 2,5 t ck ? 0.5t cclk ? 12+w ns t dsak ack delay from rdx low 3,5 t ck ? 0.75t cclk ? 11+w ns t sakc ack setup to clkin 3,5 0.5t cclk +3 ns t hakc ack hold after clkin 3 1ns switching characteristics: t drha address, cif , selects hold after rdx high 3 0.25t cclk ? 1+h ns t darl address, cif , selects to rdx low 2 0.25t cclk ? 3ns t rw rdx pulse width 3 t ck ? 0.5t cclk ? 1+w ns t rwr rdx high to wrx , rdx , dmagx low 3 0.5t cclk ? 1+hi ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0). 1 data delay/setup: user must meet t dad , t drld , or t sds. 2 the falling edge of msx , bms is referenced. 3 note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only applies to asynchronous access mode. 4 data hold: user must meet t hda or t hdrh in asynchronous access mode. see example system hold time calculation on page 44 for the calculation of hold times given capacitive and dc loads. 5 ack delay/setup: user must meet t daak , t dsak , or t sakc for deassertion of ack (low), all three specifications must be met for assertion of ack (high). figure 15. memory read?bus master (@ @" , , ( , , , !! , ! , ( , , ! , , , , ! adsp-21160m ? 20 ? rev. 0 memory write ? bus master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkin. these specifications apply when the adsp-21160m is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only applies to asynchronous access mode. table 10. memory write ? bus master parameter min max unit timing requirements: t daak ack delay from address, selects 1,2 t ck ? 0.5t cclk ? 12+w ns t dsak ack delay from wrx low 1,3 t ck ? 0.75t cclk ? 11+w ns t sakc ack setup to clkin 1,3 0.5t cclk +3 ns t hakc ack hold after clkin 1,3 1ns switching characteristics: t dawh address, cif , selects to wrx deasserted 2,3 t ck ? 0.25t cclk ? 3+w ns t dawl address, cif , selects to wrx low 2 0.25t cclk ? 3ns t ww wrx pulse width 3 t ck ? 0.5t cclk ? 1+w ns t ddwh data setup before wrx high 3 t ck ? 0.25t cclk ? 12.5+w ns t dwha address hold after wrx deasserted 3 0.25t cclk ? 1+h ns t dwhd data hold after wrx deasserted 3 0.25t cclk ? 1+h ns t datrwh data disable after wrx deasserted 3,4 0.25t cclk ? 2+h 0.25t cclk +2+h ns t wwr wrx high to wrx , rdx , dmagx low 3 0.5t cclk ? 1+hi ns t ddwr data disable before wrx or rdx low 0.25t cclk ? 1+i ns t wde wrx low to data enabled ? 0.25t cclk ? 1ns w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). 1 ack delay/setup: user must meet t daak or t dsak or t sakc for deassertion of ack (low), all three specifications must be met for assertion of ack (high). 2 the falling edge of msx , bms is referenced. 3 note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only applies to asynchronous access mode. 4 see example system hold time calculation on page 44 for calculation of hold times given capacitive and dc loads. ? 21 ? rev. 0 adsp-21160m figure 16. memory write ? bus master , (! @ ( @ @ " , ( , (( , , (( , ( , ( , (! , (! , , (! , (! , , ! adsp-21160m ? 22 ? rev. 0 synchronous read/write ? bus master use these specifications for interfacing to external memory systems that require clkin ? relative timing or for accessing a slave adsp-21160m (in multiprocessor memory space). these synchronous switching characteris- tics are also valid during asynchronous memory reads and writes except where noted (see memory read ? bus master on page 19 and memory write ? bus master on page 20 ). when accessing a slave adsp-21160m, these switching characteristics must meet the slave ? s timing requirements for synchronous read/writes (see synchronous read/write ? bus slave on page 24 ). the slave adsp-21160m must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. table 11. synchronous read/write ? bus master parameter min max unit timing requirements: t ssdati data setup before clkin 1 5.5 ns t hsdati data hold after clkin 1 1ns t sackc ack setup before clkin 1 0.5t cclk +3 ns t hackc ack hold after clkin 1 1ns switching characteristics: t daddo address, ms x, bms , brst , cif delay after clkin 10 ns t haddo address, ms x, bms , brst , cif hold after clkin 1.5 ns t dpgo page delay after clkin 1. 5 11 ns t drdo rdx high delay after clkin 1 0.25t cclk ? 1 0.25t cclk +9 ns t dwro wrx high delay after clkin 1 0.25t cclk ? 1 0.25t cclk +9 ns t drwl rdx /wrx low delay after clkin 0.25t cclk ? 1 0.25t cclk +9 ns t ddato data delay after clkin 12.5 ns t hdato data hold after clkin 1.5 ns t dackmo ack delay after clkin 2 0.25t cclk +3 0.25t cclk +9 ns t ackmtr ack disable before clkin 2 0.25t cclk ? 3ns t dckoo clkout delay after clkin 25ns t ckop clkout period t ck ? 1t ck 3 +1 ns t ckwh clkout width high t ck /2 ? 2t ck /2+2 3 ns t ckwl clkout width low t ck /2 ? 2t ck /2+2 3 ns 1 note that timing for ack, data, rdx , wrx , and dmag strobe timing parameters only applies to synchronous access mode. 2 applies to broadcast write, master precharge of ack. 3 applies only when the dsp drives a bus operation; clkout held inactive or three-state otherwise, for more information, see the system design chapter in the adsp-2116x sharc dsp hardware reference . ? 23 ? rev. 0 adsp-21160m figure 17. synchronous read/write ? bus master # @ @ " # ( ( , ( , ! , , , ( , ! , , ( , , , ( , ! , , , ! , , ( ! # , , adsp-21160m ? 24 ? rev. 0 synchronous read/write ? bus slave use these specifications for adsp-21160m bus master accesses of a slave ? s iop registers or internal memory (in multiprocessor memory space). the bus master must meet these (bus slave) timing requirements. table 12. synchronous read/write ? bus slave parameter min max unit timing requirements: t saddi address, brst setup before clkin 5 ns t haddi address, brst hold after clkin 1 ns t srwi rdx /wrx setup before clkin 5ns t hrwi rdx /wrx hold after clkin 1ns t ssdati data setup before clkin 5.5 ns t hsdati data hold after clkin 1 ns switching characteristics: t ddato data delay after clkin 12.5 ns t hdato data hold after clkin 1.5 ns t dackc ack delay after clkin 10 ns t hacko ack hold after clkin 1.5 ns ? 25 ? rev. 0 adsp-21160m figure 18. synchronous read/write ? bus slave # ( ( , , ! , , ! , !( , ( , , ! , ( , !( , ! , adsp-21160m ? 26 ? rev. 0 multiprocessor bus request and host bus request use these specifications for passing of bus mastership between multiprocessing adsp-21160ms (brx ) or a host processor (hbr , hbg ). table 13. multiprocessor bus request and host bus request parameter min max unit timing requirements: t hbgrcsv hbg low to rdx /wrx /cs valid 19 ns t shbri hbr setup before clkin 1 6ns t hhbri hbr hold after clkin 1 1ns t shbgi hbg setup before clk/= ? ]in 6ns t hhbgi hbg hold after clkin high 1ns t sbri brx , pa setup before clkin 9ns t hbri brx , pa hold after clkin high 1ns t spai pa setup before clkin 9ns t hpai pa hold after clkin high 1ns t srpbai rpba setup before clkin 6 ns t hrpbai rpba hold after clkin 2 ns switching characteristics: t dhbgo hbg delay after clkin 7ns t hhbgo hbg hold after clkin 2ns t dbro brx delay after clkin 8ns t hbro brx hold after clkin 1.5 ns t dpaso pa delay after clkin, slave 8ns t trpas pa disable after clkin, slave 1.5 ns t dpamo pa delay after clkin, master 0.25t cclk +9 ns t patr pa disable before clkin, master 0.25t cclk ? 5ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 2 0.5t ck ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 2 t ck +25 ns t ardytr redy (a/d) disable from cs or hbr high 2 11 ns 1 only required for recognition in the current cycle. 2 (o/d) = open drain, (a/d) = active drive. ? 27 ? rev. 0 adsp-21160m figure 19. multiprocessor bus request and host bus request ! !# ( =@ = , ! ! !# # # , !! , ! , # , , ! , ! , , ! , , ! , !! , , , , ! , !! , ! , , ! , ! , adsp-21160m ? 28 ? rev. 0 asynchronous read/write ? host to adsp-21160m use these specifications ( table 14 and table 15 ) for asyn- chronous host processor accesses of an adsp-21160m, after the host has asserted cs and hbr (low). after hbg is returned by the adsp-21160m, the host can drive the rdx and wrx pins to access the adsp-21160m ? s internal memory or iop registers. hbr and hbg are assumed low for this timing table 14. read cycle parameter min max unit timing requirements: t sadrdl address setup/cs low before rdx low 0 ns t hadrdh address hold/cs hold low after rdx 2ns t wrwh rdx /wrx high width 5ns t drdhrdy rdx high delay after redy (o/d) disable 0ns t drdhrdy rdx high delay after redy (a/d) disable 0ns switching characteristics: t sdatrdy data valid before redy disable from low 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rdx low 10 ns t rdyprd redy (o/d) or (a/d) low pulsewidth for read t ck ns t hdarwh data disable after rdx high 26ns figure 20. read cycle (asynchronous read ? host to adsp-21160m) # , , , ((! , !! , !(! , , ! , ? 29 ? rev. 0 adsp-21160m table 15. write cycle parameter min max unit timing requirements: t scswrl cs low setup before wrx low 0ns t hcswrh cs low hold after wrx high 0ns t sadwrh address setup before wrx high 6 ns t hadwrh address hold after wrx high 2 ns t wwrl wrx low width 7ns t wrwh rdx /wrx high width 5ns t dwrhrdy wrx high delay after redy (o/d) or (a/d) disable 0ns t sdatwh data setup before wrx high 5 ns t hdatwh data hold after wrx high 4 ns switching characteristics: t drdywrl redy (o/d) or (a/d) low delay after wrx /cs low 11 ns t rdypwr redy (o/d) or (a/d) low pulsewidth for write 12 ns figure 21. write cycle (asynchronous write ? host to adsp-21160m) =@ = ( ( , (! , !(! , (( , ( , ((! , !(! , ( , (! , (! , ( , ! (! adsp-21160m ? 30 ? rev. 0 three-state timing ? bus master and bus slave these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin and the sbts pin. this timing is appli- cable to bus master transition cycles (btc) and host transition cycles (htc) as well as the sbts pin. table 16. three-state timing ? bus slave, hbr , sbts parameter min max unit timing requirements: t stsck sbts setup before clkin 6ns t htsck sbts hold after clkin 1ns switching characteristics: t miena address/select enable after clkin 1.5 9 ns t miens strobes enable after clkin 1 1.5 9 ns t mienhg hbg enable after clkin 1.5 9 ns t mitra address/select disable after clkin 0.25t cclk ? 1 0.25t cclk +4 ns t mitrs strobes disable after clkin 1 0.25t cclk ? 4 0.25t cclk ns t mitrhg hbg disable after clkin 3.5 8 ns t daten data enable after clkin 2 1.5 10 ns t dattr data disable after clkin 2 1.5 5 ns t acken ack enable after clkin 2 1.5 9 ns t acktr ack disable after clkin 2 1.5 5 ns t cdcen clkout enable after clkin 1.5 9 ns t cdctr clkout disable after clkin t cclk ? 3t cclk +1 ns t mtrhbg memory interface disable before hbg low 3 t ck ? 6t ck +2 ns t menhbg memory interface enable after hbg high 3 t ck ? 5t ck +5 ns 1 strobes = rdx , wrx , dmag x. 2 in addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 3 memory interface = address, rdx , wrx , msx , page, dmagx , and bms (in eprom boot mode). ? 31 ? rev. 0 adsp-21160m figure 22. three-state timing ? bus slave, hbr , sbts " , ! ! "= @@(@ @"@!@@b # " , ! , @ , @ , ! , , ! , , , , , , , @ , @ , ! adsp-21160m ? 32 ? rev. 0 dma handshake these specifications describe the three dma handshake modes. in all three modes dmar is used to initiate trans- fers. for handshake mode, dmag controls the latching or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr31 ? 0, rdx , wrx , page, ms3 ? 0 , ack, and dmag signals. for paced master mode, the data transfer is controlled by addr31 ? 0, rdx , wrx , ms3 ? 0 , and ack (not dmag ). for paced master mode, the memory read-bus master, memory write-bus master, and synchronous read/write-bus master timing specifications for addr31 ? 0, rdx , wrx , ms3 ? 0 , page, data63 ? 0, and ack also apply. table 17. dma handshake parameter min max unit timing requirements: t sdrc dmarx setup before clkin 1 3ns t wdr dmarx width low (nonsynchronous) 2 t cclk +4.5 ns t sdatdgl data setup after dmagx low 3 0.75t ck ? 7ns t hdatidg data hold after dmagx high 2 ns t datdrh data valid after dmarx high 3 t ck +10 ns t dmarll dmarx low edge to low edge 4 t ck ns t dmarh dmarx width high 2 t cclk +4.5 ns switching characteristics: t ddgl dmagx low delay after clkin 0.25t cclk +1 0.25t cclk +9 ns t wdgh dmagx high width 0.5t cclk ? 1+hi ns t wdgl dmagx low width t ck ? 0.5t cclk ? 1ns t hdgc dmagx high delay after clkin t ck ? 0.25t cclk +1.5 t ck ? 0.25t cclk +9 ns t vdatdgh data valid before dmagx high 5 t ck ? 0.25t cclk ? 8t ck ? 0.25t cclk +5 ns t datrdgh data disable after dmagx high 6 0.25t cclk ? 3 0.25t cclk +1.5 ns t dgwrl wrx low before dmagx low ? 1.5 2 ns t dgwrh dmag x low before wrx high t ck ? 0.5t cclk ? 2+w ns t dgwrr wrx high before dmagx high 7 ? 1.5 2 ns t dgrdl rdx low before dmagx low ? 1.5 2 ns t drdgh rdx low before dmagx high t ck ? 0.5t cclk ? 2+w ns t dgrdr rdx high before dmagx high 7 ? 1.5 2 ns t dgwr dmagx high to wrx , rdx , dmagx low 0.5t cclk ? 2+hi ns t dadgh address/select valid to dmagx high 18 ns t ddgha address/select hold after dmagx high 1 ns w = (number of wait states specified in wait register) t ck . hi = t ck (if data bus idle cycle occurs, as specified in wait register; otherwise hi = 0). 1 only required for recognition in the current cycle. 2 maximum throughput using dmarx/dmagx handshaking equals t wdr + t dmarh = (t cclk +4.5) + (t cclk +4.5)=34ns (29.4 mhz). this throughput limit applies to non-synchronous access mode only. 3 t sdatdgl is the data setup requirement if dmarx is not being used to hold off completion of a write. otherwise, if dmarx low holds off completion of the write, the data can be driven t datdrh after dmarx is brought high. 4 use t dmarll if dmarx transitions synchronous with clkin. otherwise, use t wdr and t dmarh . 5 t vdatdgh is valid if dmarx is not being used to hold off completion of a read. if dmarx is used to prolong the read, then t vdatdgh =t ck ? .25t cclk ? 8+(n t ck ) where n equals the number of extra cycles that the access is prolonged. 6 see example system hold time calculation on page 44 for calculation of hold times given capacitive and dc loads. 7 this parameter applies for synchronous access mode only. ? 33 ? rev. 0 adsp-21160m figure 23. dma handshake timing , ( , ( , , ! , , ! , (! , , ! , ! , ! , ! , ( , (! , ( , , ! , , d# @(# @ !# (# " " $@@( @ $ !b " ( " ( d ! ! , ! , ! , ( " " adsp-21160m ? 34 ? rev. 0 link ports calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata relative to lclk (setup skew = t lclktwh min ? t dldch ? t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata (hold skew = t lclktwl min ? t hldch ? t hldcl ). calcu- lations made directly from speed specifications will result in unrealistically small skew times because they include multiple tester guardbands. note that there is a two-cycle effect latency between the link port enable instruction and the dsp enabling the link port. maximum throughput varies across link port trans- mit/receive pairs. table 18 shows maximum throughput for all transmit/receive pairs based on setup skew of 0.5 ns (setup skew=t lclktwh min ? t dldch ? t sldcl = 0 . 5 n s ) . ho l d s k e w results indicate 80 mhz operation across all link ports. all hold time skews are equal to 0.5 ns or greater for all link port transmit/receive pairs at 80 mhz. based upon these values, all link port transmit/receive pairs can be operated at maximum throughput for lxclk:cclk ratios of 2:1, 3:1, and 4:1 at 80 mhz cclk. to operate all link port transmit/receive pairs at lxclk:cclk ratio of 1:1, the core clock frequency must be no greater than 62.5 mhz. maximum data throughput values are based upon the reset value of the lar link port assignment register (link buffer 0 assigned to link port 0, link buffer 1 assigned to link port 1, etc.). throughputs are not guaranteed for lar settings other than the reset lar value. for additional details on lar, refer to the adsp-21160 dsp hardware reference manual. table 18. link port ? maximum data throughput for transmit/receive pairs transmit link port receive link port maximum operating frequency (mhz) 0 0 71.43 1 74.07 2 71.43 380 480 5 76.92 1 0 68.97 1 71.43 2 68.97 380 4 76.92 5 74.07 2 0 68.97 1 71.43 2 71.43 380 4 76.92 5 74.07 3 0 64.52 1 66.67 2 66.67 3 71.43 4 71.43 5 71.43 4 0 64.52 1 66.67 2 66.67 3 74.07 4 74.07 5 71.43 5 0 62.5 1 66.67 2 64.52 3 71.43 4 71.43 5 71.43 table 18. link port ? maximum data throughput for transmit/receive pairs (continued) transmit link port receive link port maximum operating frequency (mhz) ? 35 ? rev. 0 adsp-21160m table 19. link ports ? receive parameter min max unit timing requirements: t sldcl data setup before lclk low 2.5 ns t hldcl data hold after lclk low 2.5 ns t lclkiw lclk period t lclk ns t lclkrwl lclk width low 6.0 ns t lclkrwh lclk width high 6.0 ns switching characteristics: t dlalc lack low delay after lclk high 1 12 17 ns 1 lack goes low with t dlalc relative to rise of lclk after first nibble, but doesn ? t go low if the receiver ? s link buffer is not about to fill. figure 24. link ports ? receive 'e # , , ! , (! , , ( , ( adsp-21160m ? 36 ? rev. 0 table 20. link ports ? transmit parameter min max unit timing requirements: t slach lack setup before lclk high 14 ns t hlach lack hold after lclk high ? 2ns switching characteristics: t dldch data delay after lclk high 6.0 ns t hldch data hold after lclk high ? 2ns t lclktwl lclk width low 0.5t lclk ? 1.5 0.5t lclk +1.5 ns t lclktwh lclk width high 0.5t lclk ? 1.5 0.5t lclk +1.5 ns t dlaclk lclk low delay after lack high 0.5t lclk +5 3t lclk +11 ns figure 25. link ports ? transmit 'e ! , ! %# ! ""!" b " !! # , ! , !! , ( ! , ( , ! , !! , ? 37 ? rev. 0 adsp-21160m serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. table 21. serial ports ? external clock parameter min max unit timing requirements: t sfse tfs/rfs setup before tclk/rclk 1 3.5 ns t hfse tfs/rfs hold after tclk/rclk 1,2 4ns t sdre receive data setup before rclk 1 1.5 ns t hdre receive data hold after rclk 1 4ns t sclkw tclk/rclk width 14 ns t sclk tclk/rclk period 2t cclk ns 1 referenced to sample edge. 2 rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck for late external tfs is 0 ns mini mum from drive edge. table 22. serial ports ? internal clock parameter min max unit timing requirements: t sfsi tfs setup before tclk 1 ; rfs setup before rclk 1 8ns t hfsi tfs/rfs hold after tclk/rclk 1,2 1ns t sdri receive data setup before rclk 1 6.5 ns t hdri receive data hold after rclk 1 3ns 1 referenced to sample edge. 2 rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck for late external tfs is 0 ns mini mum from drive edge. table 23. serial ports ? external or internal clock parameter min max unit switching characteristics: t dfse rfs delay after rclk (internally generated rfs) 1 13 ns t hofse rfs hold after rclk (internally generated rfs) 1 3ns 1 referenced to drive edge. table 24. serial ports ? external clock parameter min max unit switching characteristics: t dfse tfs delay after tclk (internally generated tfs) 1 13 ns t hofse tfs hold after tclk (internally generated tfs) 1 3ns t ddte transmit data delay after tclk 1 16 ns t hdte transmit data hold after tclk 1 0ns 1 referenced to drive edge. table 25. serial ports ? internal clock parameter min max unit switching characteristics: t dfsi tfs delay after tclk (internally generated tfs) 1 4.5 ns t hofsi tfs hold after tclk (internally generated tfs) 1 ? 1.5 ns adsp-21160m ? 38 ? rev. 0 t ddti transmit data delay after tclk 1 7.5 ns t hdti transmit data hold after tclk 1 0ns t sclkiw tclk/rclk width 0.5t sclk ? 2.5 0.5t sclk +2 ns 1 referenced to drive edge. table 26. serial ports ? enable and three-state parameter min max unit switching characteristics: t ddten data enable from external tclk 1 4ns t ddtte data disable from external tclk 1 10 ns t ddtin data enable from internal tclk 1 0ns t ddtti data disable from internal tclk 1 3ns 1 referenced to drive edge. table 25. serial ports ? internal clock (continued) parameter min max unit ? 39 ? rev. 0 adsp-21160m figure 26. serial ports " f f " e!! ""@# ! b " " f f e!! ""@# ! b , , , , , , ! , " , !" , " , !" , ( , , ! , " , !" , " , ( , !" , , ! , " , !" , ( , " , !" , , ! , " , !" , " , ( , !" adsp-21160m ? 40 ? rev. 0 table 27. serial ports ? external late frame sync parameter min max unit switching characteristics: t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 1 1 mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs . 13 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 1 1.0 ns figure 27. external late frame sync " " " ( !=@"= " , !" , " , , " , " , ! , !" , " , , " , " , ! ? 41 ? rev. 0 adsp-21160m jtag test access port and emulation table 28. jtag test access port and emulation parameter min max unit timing requirements: t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck low 1 1 system inputs = data63 ? 0, addr31 ? 0, rdx , wrx , ack, sbts , hbr , hbg , cs , dmar1 , dmar2 , br6 ? 1 , id2 ? 0, rpba, irq2 ? 0 , flag3 ? 0, pa , brst , dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7 ? 0, lxclk, lxack, eboot, lboot, bms , clkin, reset . 7ns t hsys system inputs hold after tck low 1 18 ns t trstw trst pulsewidth 4t ck ns switching characteristics: t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 2 2 system outputs = data63 ? 0, addr31 ? 0, ms3 ? 0 , rdx , wrx , ack, page, clkout, hbg , redy, dmag1 , dmag2 , br6 ? 1 , pa , brst , cif , flag3 ? 0, timexp, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7 ? 0, lxclk, lxack, bms . 30 ns figure 28. ieee 11499.1 jtag test access port # ## , , , ! , , , ! , adsp-21160m ? 42 ? rev. 0 output drive currents figure 29 shows typical i ? v characteristics for the output drivers of the adsp-21160m. the curves represent the current drive capability of the output drivers as a function of output voltage. power dissipation total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execution sequence and the data operands involved. using the current specifications (i ddinpeak , i ddinhigh , i ddinlow , i ddidle ) from electrical characteristics on page 13 and the current-ver- sus-operation information in table 29 , engineers can estimate the adsp-21160m ? s internal power supply (v ddint ) input current for a specific application, according to the following formula: the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: the number of output pins that switch during each cycle (o) the maximum frequency at which they can switch (f) their load capacitance (c) their voltage swing (vdd) and is calculated by: p ext = o c v dd 2 f figure 29. adsp-21160m typical drive currents # $ $ b* b* b* b* # # $ 1 $ $) $ $ $ ) = b '@g = b @*g = b @)*g = b ' @g = b @*g = b @)*g % peak i ddinpeak % high i ddinhigh % low i ddinlow + % idle i ddidle i ddint ------------------------------------------------- - ? 43 ? rev. 0 adsp-21160m the load capacitance should include the processor ? s package capacitance (c in ). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. table 29. adsp-21160m operation types vs. input current operation peak activity 1 high activity 1 low activity 1 instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 2 per t ck cycle (dm 64 and pm 64) 1 per t ck cycle (dm 64) none internal memory dma 1 per 2 t cclk cycles 1 per 2 t cclk cycles none external memory dma 1 per external port cycle ( 64) 1 per external port cycle ( 64) none data bit pattern for core memory access and dma wo r s t c a s e r a n d o m n / a 1 peak activity=i ddinpeak , high activity=i ddinhigh , and low activity=i ddinlow . the state of the peyen bit (simd versus sisd mode) does not influence these calculations. 2 these assume a 2:1 core clock ratio. for more information on ratios and clocks (t ck and t cclk ), see the timing ratio definitions on page 15 . adsp-21160m ? 44 ? rev. 0 example: estimate p ext with the following assumptions: a system with one bank of external data memory ? asyn- chronous ram (64-bit) four 64k 16 ram chips are used, each with a load of 10 pf external data memory writes occur every other cycle, a rate of 1/(4 t ck ), with 50% of the pins switching the bus cycle time is 40 mhz (t ck = 25 ns). the p ext equation is calculated for each class of pins that can drive: a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + p int + p pll where: p ext is from table 30 p int is i ddint 2.5v, using the calculation i ddint listed in power dissipation on page 42 p pll is ai dd 2.5v, using the value for ai dd listed in absolute maximum ratings on page 14 note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. te s t c o n d i t i o n s the test conditions for timing parameters appearing in adsp-21160m specifications on page 13 include output disable time, output enable time, and capacitive loading. output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capac- itive load, c l and the load current, i l . this decay time can be approximated by the following equation: t decay = ( c l ? v )/ i l the output disable time t dis is the difference between t measured and t decay as shown in figure 30 . the time t measured is the interval from when the reference signal switches to when the output voltage decays ? v from the measured output high or output low voltage. t decay is calculated with test loads c l and i l , and with ? v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 30 ). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the adsp-21160m ? s output voltage and the input threshold for the device requiring the hold time. a typical ? v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). table 30. external power calculations (3.3 v device) pin type # of pins % switching c f vdd 2 = p ext address 15 50 44.7 pf 12.5 mhz 10.9 v = 0.046 w ms0 1 0 44.7 pf 12.5 mhz 10.9 v = 0.000 w wrx 2 ? 44.7 pf 25 mhz 10.9 v = 0.024 w data 64 50 14.7 pf 12.5 mhz 10.9 v = 0.064 w clkout 1 ? 4.7 pf 25 mhz 10.9 v = 0.001 w p ext = 0.135 w figure 30. output enable/disable reference signal t dis output starts driving v oh (measured) ? dv v ol (measured) + dv t measured v oh (measured) v ol (measured) 2.0v 1.0v high-impedance state. test conditions cause thisvoltage to be approximately 1.5v output stops driving t decay t ena ? 45 ? rev. 0 adsp-21160m capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 31 ). the delay and hold specifications given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figure 33 and figure 34 show how output rise time varies with capacitance. figure 35 graphically shows how output delays and holds vary with load capacitance. (note that this graph or derating does not apply to output disable delays; see output disable time on page 44 .) the graphs of figure 33 , figure 34 , and figure 35 may not be linear outside the ranges shown. environmental conditions the adsp-21160m is tested for performance over the commercial temperature range, 0 c to 85 c. thermal characteristics the adsp-21160m is packaged in a 400-ball plastic ball grid array (pbga). the adsp-21160m is specified for a case temperature (t case ). to ensure t hat t he t case data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. use the center block of ground pins (pbga balls: h8 ? 13, j8 ? 13, k8 ? 13, l8 ? 13, m8 ? 13, and n8 ? 13) to provide thermal pathways to the printed circuit board ? s ground plane. a heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. figure 31. equivalent device loading for ac measurements (includes all fixtures) figure 32. voltage reference levels for ac measurements (except output enable/disable) figure 33. typical output rise time (10% ? 90%, v ddext = max) vs. load capacitance b* *4" ## ! # ## b* b* $4" b b * * * b b *b *b *b " $ +8 " =b'')hbaa =b))'hb) figure 34. typical output rise time (10% ? 90%, v ddext = min) vs. load capacitance figure 35. typical output delay or hold vs. load capacitance (at max case temperature) $4" b b * * * b *b *b *b " $ +8 " =b' hb* =b)ahb $4" *b b * * * *b $*b b b ## ! $ +8 =b)**$ b)' adsp-21160m ? 46 ? rev. 0 t case = case temperature (measured on top surface of package) pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown under power dissipation). ca = value from table 31 . jb = 6.46 c/w 400-ball metric pbga pin configurations table 32 lists the pin assignments for the pbga package, and the pin configurations diagram on page 51 shows the pin assignment summary. table 31. airflow over package versus ca airflow (linear ft./min.) 0 200 400 ca ( c/w) 1 1 jc = 3.6 c/w. 12.13 9.86 8.7 t case t amb pd ca () + = ? 47 ? rev. 0 adsp-21160m table 32. 400-ball metric pbga pin assignments pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin# data[14] a01 data[22] b01 data[24] c01 data[28] d01 data[13] a02 data[16] b02 data[18] c02 data[25] d02 data[10] a03 data[15] b03 data[17] c03 data[20] d03 data[8] a04 data[9] b04 data[11] c04 data[19] d04 data[4] a05 data[6] b05 data[7] c05 data[12] d05 data[2] a06 data[3] b06 data[5] c06 v ddext d06 tdi a07 data[0] b07 data[1] c07 v ddint d07 trst a08 tck b08 tms c08 v ddext d08 reset a09 emu b09 td0 c09 v ddext d09 rpba a10 irq2 b10 irq1 c10 v ddext d10 irq0 a11 flag3 b11 flag2 c11 v ddext d11 flag1 a12 flag0 b12 v ddext c12 v ddext d12 timexp a13 v ddext b13 nc c13 v ddint d13 v ddext a14 nc b14 tclk1 c14 v ddext d14 nc a15 dt1 b15 dr1 c15 tfs0 d15 tfs1 a16 rclk1 b16 dr0 c16 l1dat[7] d16 rfs1 a17 rfs0 b17 l0dat[7] c17 l0clk d17 rclk0 a18 tclk0 b18 l0dat[6] c18 l0dat[3] d18 dt0 a19 l0dat[5] b19 l0ack c19 l0dat[1] d19 l0dat[4] a20 l0dat[2] b20 l0dat[0] c20 l1clk d20 data[30] e01 data[34] f01 data[38] g01 data[40] h01 data[29] e02 data[33] f02 data[35] g02 data[39] h02 data[23] e03 data[27] f03 data[32] g03 data[37] h03 data[21] e04 data[26] f04 data[31] g04 data[36] h04 v ddext e05 v ddext f05 v ddext g05 v ddext h05 v ddint e06 v ddint f06 v ddint g06 v ddint h06 v ddint e07 gnd f07 gnd g07 gnd h07 v ddint e08 gnd f08 gnd g08 gnd h08 v ddint e09 gnd f09 gnd g09 gnd h09 v ddint e10 gnd f10 gnd g10 gnd h10 gnd e11 gnd f11 gnd g11 gnd h11 v ddint e12 gnd f12 gnd g12 gnd h12 v ddint e13 gnd f13 gnd g13 gnd h13 v ddint e14 gnd f14 gnd g14 gnd h14 v ddint e15 v ddint f15 v ddint g15 v ddint h15 v ddext e16 v ddext f16 v ddext g16 v ddext h16 l1dat[6] e17 l1dat[4] f17 l1dat[2] g17 l2dat[5] h17 l1dat[5] e18 l1dat[3] f18 l2dat[6] g18 l2ack h18 l1ack e19 l1dat[0] f19 l2dat[4] g19 l2dat[3] h19 l1dat[1] e20 l2dat[7] f20 l2clk g20 l2dat[1] h20 adsp-21160m ? 48 ? rev. 0 data[44] j01 clk_cfg_0 k01 clkin l01 av dd m01 data[43] j02 data[46] k02 clk_cfg_1 l02 clk_cfg_3 m02 data[42] j03 data[45] k03 agnd l03 clkout m03 data[41] j04 data[47] k04 clk_cfg_2 l04 gnd m04 v ddext j05 v ddext k05 v ddext l05 v ddext m05 v ddint j06 v ddint k06 v ddint l06 v ddint m06 gnd j07 gnd k07 gnd l07 gnd m07 gnd j08 gnd k08 gnd l08 gnd m08 gnd j09 gnd k09 gnd l09 gnd m09 gnd j10 gnd k10 gnd l10 gnd m10 gnd j11 gnd k11 gnd l11 gnd m11 gnd j12 gnd k12 gnd l12 gnd m12 gnd j13 gnd k13 gnd l13 gnd m13 gnd j14 gnd k14 gnd l14 gnd m14 v ddint j15 v ddint k15 v ddint l15 v ddint m15 v ddext j16 v ddext k16 v ddext l16 v ddext m16 l2dat[2] j17 br6 k17 br2 l17 page m17 l2dat[0] j18 br5 k18 br1 l18 sbts m18 hbg j19 br4 k19 ack l19 pa m19 hbr j20 br3 k20 redy l20 l3dat[7] m20 nc n01 data[49] p01 data[53] r01 data[56] t01 nc n02 data[50] p02 data[54] r02 data[58] t02 data[48] n03 data[52] p03 data[57] r03 data[59] t03 data[51] n04 data[55] p04 data[60] r04 data[63] t04 v ddext n05 v ddext p05 v ddext r05 v ddext t05 v ddint n06 v ddint p06 v ddint r06 v ddint t06 gnd n07 gnd p07 gnd r07 v ddint t07 gnd n08 gnd p08 gnd r08 v ddint t08 gnd n09 gnd p09 gnd r09 v ddint t09 gnd n10 gnd p10 gnd r10 v ddint t10 gnd n11 gnd p11 gnd r11 v ddint t11 gnd n12 gnd p12 gnd r12 v ddint t12 gnd n13 gnd p13 gnd r13 v ddint t13 gnd n14 gnd p14 gnd r14 v ddint t14 v ddint n15 v ddint p15 gnd r15 v ddint t15 v ddext n16 v ddext p16 v ddext r16 v ddext t16 l3dat[5] n17 l3dat[2] p17 l4dat[5] r17 l4dat[3] t17 l3dat[6] n18 l3dat[1] p18 l4dat[6] r18 l4ack t18 l3dat[4] n19 l3dat[3] p19 l4dat[7] r19 l4clk t19 l3clk n20 l3ack p20 l3dat[0] r20 l4dat[4] t20 table 32. 400-ball metric pbga pin assignments (continued) pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin# ? 49 ? rev. 0 adsp-21160m data[61] u01 addr[4] v01 addr[5] w01 addr[8] y01 data[62] u02 addr[6] v02 addr[9] w02 addr[11] y02 addr[3] u03 addr[7] v03 addr[12] w03 addr[13] y03 addr[2] u04 addr[10] v04 addr[15] w04 addr[16] y04 v ddext u05 addr[14] v05 addr[17] w05 addr[19] y05 v ddext u06 addr[18] v06 addr[20] w06 addr[21] y06 v ddext u07 addr[22] v07 addr[23] w07 addr[24] y07 v ddext u08 addr[25] v08 addr[26] w08 addr[27] y08 v ddext u09 addr[28] v09 addr[29] w09 addr[30] y09 v ddext u10 id0 v10 id1 w10 addr[31] y10 v ddext u11 addr[1] v11 addr[0] w11 id2 y11 v ddext u12 ms1 v12 bms w12 brst y12 v ddext u13 cs v13 ms2 w13 ms0 y13 v ddext u14 rdl v14 cif w14 ms3 y14 v ddext u15 dmar2 v15 rdh w15 wrh y15 v ddext u16 l5dat[0] v16 dmag2 w16 wrl y16 l5dat[7] u17 l5dat[2] v17 lboot w17 dmag1 y17 l4dat[0] u18 l5ack v18 l5dat[1] w18 dmar1 y18 l4dat[1] u19 l5dat[4] v19 l5dat[3] w19 eboot y19 l4dat[2] u20 l5dat[6] v20 l5dat[5] w20 l5clk y20 table 32. 400-ball metric pbga pin assignments (continued) pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin# adsp-21160m ? 50 ? rev. 0 400-ball metric pbga pin configurations (bottom view, summary) d e d # !"# e !)$ @)$ @)$ @)$ @)$ @)$ !!( ##7 #b * ' ) a * ' a ) ! " ( # ? 51 ? rev. 0 adsp-21160m outline dimensions the adsp-21160m comes in a 27mm 27mm, 400-ball metric pbga package with 20 rows of balls. 400-ball metric pbga (b-400) ba b'* b b' b b* b b** b* b a b b* * ' ) a * ' a ) ! " ( # b b b ba % ( e b @b* ! ! b b"# b b!# "! (!b " ! b b!# "! ( !b" !b ba b' b* b 'b 'b b) % % b'b* ! ( adsp-21160m ? 52 ? rev. 0 p ri n t e d in u . s . a . c 0 242 6 ?2 . 5 ? 4 / 0 1 ( 0 ) ordering guide part number 1, 2 1 b = plastic ball grid array (pbga) package. 2 see adsp-21160n data sheet for ordering information for higher-performance derivative. case temperature range instruction rate on-chip sram operating voltage ADSP-21160MKB-80 0 c to 85 c 80 mhz 4 mbit 2.5 int/3.3 ext v |
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