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this document is a general product description and is subjec t to change without notice. hynix electronics does not assume any responsibility for use of circuits de scribed. no patent licenses are implied. rev 0.2 / apr. 2004 1 hy5ps1g431(l)f hy5ps1g831(l)f 1gb ddr2 sdram hy5ps1g431(l)f hy5ps1g831(l)f
rev 0.2 / apr. 2004 2 hy5ps1g431(l)f hy5ps1g831(l)f revision details revision no. history draft date remark 0.1 preliminary feb.2004 initial release 0.2 corrected typos of pin description & trfc spec. , added idd spec. apr.2004
3 rev 0.1 / feb. 2004 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f contents 1. description 1.1 device features and ordering information 1.1.1 key feaures 1.1.2 ordering information 1.1.3 ordering frequency 1.2 pin configuration 1.2.1 256m 4 ddr2 pin configuration 1.2.2 128m 8 ddr2 pin configuration 1.3 pin description 2. functioanal description 2.1 simplified state diagram 2.2 functional block diagram 2.2.1 functional block diagram(256m 4) 2.2.2 functional block diagram(128m 8) 2.3 basic function & operation of ddr2 sdram 2.3.1 power up and initialization 2.3.2 programming the mode and extended mode registers 2.3.2.1 ddr2 sdram mode register set(mrs) 2.3.2.2 ddr2 sdram extended mode register set 2.3.2.3 off-chip driver(ocd) impedance adjustment 2.3.2.4 odt(on die termination) 2.4 bank activate command 2.5 read and write command 2.5.1 posted cas 2.5.2 burst mode operation 2.5.3 burst read command 2.5.4 burst write operation 2.5.5 write data mask 2.6 precharge operation 2.7 auto precharge operation 2.8 refresh commands 2.8.1 auto refresh command 2.8.2 self refresh command 2.9 power down 2.10 asynchronous cke low event 2.11 no operation command 2.12 deselect command 3. truth tables 3.1 command truth table 3.2 clock enable(cke) truth table for synchronous transistors 3.3 data mask truth table 4. operating conditions 4.1 absolute maximum dc ratings 4.2 operating temperature condition
4 rev 0.1 / feb. 2004 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 5. ac & dc oper ating conditions 5.1 dc operation conditions 5.1.1 recommended dc operating conditions(sstl_1.8) 5.1.2 odt dc electri cal characteristics 5.2 dc & ac logic input levels 5.2.1 input dc logic level 5.2.2 input ac logic level 5.2.3 ac input test conditions 5.2.4 differential input ac logic level 5.2.5 differential ac output parameters 5.2.6 overshoot / undershoot specification 5.3 output buffer levels 5.3.1 output ac test conditions 5.3.2 output dc current drive 5.3.3 ocd default chracteristics 5.4 default output v-i characteristics 5.4.1 full strength default pulldown driver characteristics 5.4.2 full strength default pullup driver chracteristics 5.4.3 calibrated output driver v-i characteristics 5.5 input/output capacitance 6. idd specifications & measurement conditions 7 . ac timing specifications 7.1 timing parameters by speed grade 7.2 general notes for all ac parameters 7.3 specific notes for dedicated ac parameters. 8 package dimensions 8.1 package dimension (x4 , x8)
rev 0.2 / apr. 2004 5 hy5ps1g431(l)f hy5ps1g831(l)f 1.1 device features & ordering information 1.1.1 key features ? vdd=1.8v ? vddq=1.8v +/- 0.1v ? all inputs and outputs are compatible with sstl_18 interface ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous-data transaction aligne d to bidirectional da ta strobe (dqs, dqs ) ? differential data strobe (dqs, dqs ) ? data outputs on dqs, dqs edges when read (edged dq) ? data inputs on dqs centers when write(centered dq) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm mask write data-in at the both risi ng and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and da ta masks latched on the rising edges of the clock ? programmable cas latency 3, 4, 5 and 6 supported ? programmable additive latency 0, 1, 2, 3, 4 and 5 supported ? programmable burst length 4/8 with both nibble sequential and interleave mode ? internal 8 bank operatio ns with single pulsed ras ? auto refresh and self refresh supported ? tras lockout supported ? 8k refresh cycles /64ms ? jedec standard 60ball fbga(x4/x8) ? full strength driver option controlled by emrs ? on die termination supported ? off chip driver impedance adjustment supported ? read data strobe suupported (x8 only) ? self-refresh high temperature entry ordering information part no. configuration package hy5ps1g431(l)f-x* 256mx4 68ball hy5ps1g831(l)f-x* 128mx8 operating frequency grade tck(ns) cl trcd trp unit -e3 5333 clk -e4 5444 clk -c4 3.75 4 4 4 clk -c5 3.75 5 5 5 clk -y5 3555 clk -y6 3666 clk note: -x* is the speed bin, refer to the operation frequency table for complete part no. 1. description
6 rev 0.1 / feb. 2004 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 1.2 pin configuration 1.2.1 256mx4 ddr2 pin configuration vss dm vddq dq3 vss we ba1 a1 a5 a9 nc nc vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 vdd nc vddq nc vddl ba2 vss vdd e f g h j k l m n p vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 vddq nc vddq nc vdd odt vdd vss nc nc a b c d r t u v w nc nc nc nc nc nc 3 2 1 78 9 row and column address table items 256mx4 # of bank 8 bank address ba0,ba1,ba2 auto precharge flag a10/ap row address a0 - a13 column address a0-a9, a11 page size 1 kb
rev 0.2 / apr. 2004 7 hy5ps1g431(l)f hy5ps1g831(l)f 1.2.2 128mx8 ddr2 pin configuration vss dm/rdqs vddq dq3 vss we ba1 a1 a5 a9 nc nu/rdqs vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 vdd dq6 vddq dq4 vddl ba2 vss vdd e f g h j k l m n p vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 vddq dq7 vddq dq5 vdd odt vdd vss nc nc a b c d r t u v w nc nc nc nc nc nc 3 2 1 78 9 row and column address table items 128mx8 # of bank 8 bank address ba0, ba1, ba2 auto precharge flag a10/ap row address a0 - a13 column address a0-a9 page size 1 kb
rev 0.2 / apr. 2004 8 hy5ps1g431(l)f hy5ps1g831(l)f 1.3 pin description pin type description ck, ck input clock: ck and ck are differential clock inputs. all ad dress and control input signals are sam- pled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivate s internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all banks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchro nous for self refresh exit, and for output disable. cke must be maintained high th roughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power down. input buffers, excluding cke are dis- abled during self refresh. cke is an sstl_18 input, but will detect an lvcmos low level after vdd is applied. cs input chip select : enables or disables all inputs except ck, ck , cke, dqs and dm. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. odt input on die termination control : odt enables on die termination resistan ce internal to the ddr2 sdram. when enabled, on die termin ation is only applied to dq, dqs, dqs , rdqs, rdqs , and dm. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm (ldm, udm) input input data mask : dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a wr ite access. dm is sampled on both edges of dqs, although dm pins are in put only, the dm loading matches the dq and dqs loading. for x8 device, the function of dm or rdqs/ rdqs is enabled by emrs com- mand. ba0 ~ ba2 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 ~ a13 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to deter- mine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op code during mode register set commands. dq input/output data input / output : bi-directional data bus dqs, (dqs) (rdqs),(rdqs ) input/output data strobe : output with read data, input wi th write data. edge aligned with read data, centered in write data. for the x8, an rdqs option using dm pin can be enabled via the emrs(1) to simplify read timi ng. the data strobes dqs, ldqs, udqs, and rdqs may be used in single ended mode or paired with optional complementary signals dqs, ldqs,udqs and rdqs to provide differential pair signalin g to the system during both reads and wirtes. an emrs(1) control bit enables or disables all complementary data strobe signals. nc no connect : no internal elec trical connection is present. v ddq supply dq ground v ddl supply dll power supply : 1.8v +/- 0.1v v ssdl supply dll ground vdd supply power supply : 1.8v +/- 0.1v v ss supply ground v ref supply reference voltage for inputs for sstl interface.
rev 0.2 / apr. 2004 9 hy5ps1g431(l)f hy5ps1g831(l)f -continue- pin type description vdd supply power supply : 1.8v +/- 0.1v v ss supply ground v ref supply reference voltage for inputs for sstl interface. in this data sheet, "differential dqs signals" refers to any of the following with a10 = 0 of emrs(1) x4 dqs/dqs x8 dqs/dqs if emrs(1)[a11] = 0 x8 dqs/dqs , rdqs/rdqs , if emrs(1)[a11] = 1 "single-ended dqs signals" refers to any of the following with a10 = 1 of emrs(1) x4 dqs x8 dqs if emrs(1)[a11] = 0 x8 dqs, rdqs, if emrs(1)[a11] = 1
rev 0.2 / apr. 2004 10 hy5ps1g431(l)f hy5ps1g831(l)f self idle setting emrs bank precharging power writing act rda read srf ref ckel mrs ckeh ckeh ckel write automatic sequence command sequence rda wra read pr, pra pr refreshing refreshing down power down active with rda reading with wra active precharge reading writing pr(a) = precharge (all) mrs = (extended) mode register set srf = enter self refresh ref = refresh ckel = cke low, enter power down ckeh = cke high, exit power down, exit self refresh act = activate wr(a) = write (with autoprecharge) rd(a) = read (with autoprecharge) note: use caution with this diagram. it is indented to provide a floorplan of the possible state transitions 2.1 simplified state diagram all banks precharged activating ckeh read write ckel mrs ckel sequence initialization ocd calibration ckel ckel ckel autoprecharge autoprecharge pr, pra pr, pra and the commands to control them, not all details. in particular situations involving more than one bank, enabling/disabling on-die termination, power down en ty/exit - among other things - are not captured in full detail. 2. functional description
rev 0.2 / apr. 2004 11 hy5ps1g431(l)f hy5ps1g831(l)f 2.2 functional block diagram 2.2.1 functional block diagram(256mx4) 8 banks x 32mbit x 4 i/o ddr2 sdram input buffers & state machine row pre decoders column pre decoders self refresh logic & timer internal row counter 32mx4 bank3 32mx4 bank2 32mx4 bank1 32mx4 bank0 column decoders memory cell array refresh column active clk clk cke cs ras cas we dm address registers column add counter&latch mode register address buffers a0 a1 a13 ba2 ba1 row active bank select sense amp & i/o gate 4bit pre-fetch read data register 4bit pre-fetch write data register column active latch additive latency output buffers & odt refresh input buffers dll clk ocd control dqs i/o buffer dqs dqs dll clk ds ds dq 0~3 16 4 4 odt dll clk ocd control odt control odt control row decoders 32mx4 bank4 32mx4 bank5 32mx4 bank6 32mx4 bank7 ba0
rev 0.2 / apr. 2004 12 hy5ps1g431(l)f hy5ps1g831(l)f 2.2.2 functional block diagram(128mx8) 8 banks x 16mbit x 8 i/o ddr2 sdram input buffers & state machine row pre decoders column pre decoders self refresh logic & timer internal row counter 16mx8 bank3 16mx8 bank2 16mx8 bank1 16mx8 bank0 column decoders memory cell array refresh column active clk clk cke cs ras cas we dm address registers column add counter&latch mode register address buffers a0 a1 a13 ba2 ba1 row active bank select sense amp & i/o gate 4bit pre-fetch read data register 4bit pre-fetch write data register column active latch additive latency output buffers & odt refresh input buffers dll clk ocd control dqs i/o buffer dqs dqs dll clk ds ds dq 0~7 32 8 8 odt dll clk ocd control odt control odt control row decoders 16mx8 bank4 16mx8 bank5 16mx8 bank6 16mx8 bank7 ba0
rev 0.2 / apr. 2004 13 hy5ps1g431(l)f hy5ps1g831(l)f 2.3 basic function & op eration of ddr2 sdram read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a prog rammed sequence. accesses be gin with the registration of an active command, which is then followed by a read or write command. the address bits registered coinci- dent with the active command are used to select the bank and row to be accessed (ba0-ba2 select the bank; a0-a15 select the row). the address bits registered coincident with the read or write command are used to select the starting co lumn location for the burst access and to determine if the auto precharge command is to be issued. prior to normal operation, the ddr2 sdram must be in itialized. the following secti ons provide detailed infor- mation covering device initialization, register defi nition, command descriptions and device operation. 2.3.1 power up and initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may resu lt in undefined operation. power-up and initialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2*vddq and odt *1 at a low state (all other inputs may be undefined.) - vdd, vddl and vddq are driven from a single power converter output, and - vtt is limited to 0.95 v max, and - vref tracks vddq/2. or - apply vdd before or at the same time as vddl. - apply vddl before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. for the minimum of 200 us after stable power and clock(ck, ck ), then apply nop or deselect & take cke high. 4. wait minimum of 400ns then issue precharge a ll command. nop or deselect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs(2) command, provide ?low? to ba0 and ba2, ?high? to ba1.) *2 6. issue emrs(3) command. (to issue emrs(3) command, provide ?low? to ba2, ?high? to ba0 and ba1.) *2 7. issue emrs to enable dll. (to issue "dll enable " command, provide "low" to a0, "high" to ba0 and "low" to ba1-2 and a13~a15.) 8. issue a mode register set command for ?dll reset?. (to issue dll reset command, provide "high" to a8 and "low" to ba0-2, and a13~15.) 9. issue precharge all command. 10. issue 2 or more auto-refresh commands. 11. issue a mode register set command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll.) 12. at least 200 clocks after step 8, execute ocd ca libration ( off chip driv er impedance adjustment ).
rev 0.2 / apr. 2004 14 hy5ps1g431(l)f hy5ps1g831(l)f 1. if ocd calibration is not used, emrs ocd defa ult command (a9=a8= a7=1) followed by emrs ocd calibration mode exit command (a9=a8=a7=0) must be issued with other operating parameters of emrs. 2. the ddr2 sdram is now ready for normal operation. *1) to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. *2) sequence 5 and 6 may be performed between 8 and 9. 2.3.2 programming the mode and extended mode registers for application flexibility, bu rst length, bu rst type, cas latency, dll reset function, write recovery time(twr) are user defined variables and must be programmed with a mode register set (mrs) command. addition- ally, dll disable function, driver impedance, additive cas latency, od t(on die termination), single-ended strobe, and ocd(off chip driver impedance adjustment) are also user defined variables and must be pro- grammed with an extended mode register set (emrs) command. contents of the mode register(mr) or extended mode registers(emr(#)) can be altered by re-executing the mrs and emrs commands. if the user chooses to modify only a subset of the mrs or emrs variables, all variab les must be redefined when the mrs or emrs commands are issued. mrs, emrs and reset dll do not affect array contents , which means reinitializati on including those can be executed any time after power-up without affecting array contents. initialization sequence after power up /ck ck cke command pre all pre all emrs mrs ref ref mrs emrs emrs any cmd dll enable dll reset ocd default ocd cal. mode exit follow ocd flowchart 400ns trfc trfc trp trp tmrd tmrd tmrd toit min. 200 cycle nop odt tcl tch tis
rev 0.2 / apr. 2004 15 hy5ps1g431(l)f hy5ps1g831(l)f 2.3.2.1 ddr2 sdra m mode register set (mrs) the mode register stores the data for controlling the variou s operating modes of ddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, twr and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba0 and ba1, while controlling the state of address pins a0 ~ a15. the ddr2 sdram should be in all bank precharge with cke already high pr ior to writing in to the mode reg- ister. the mode register set command cycle time (tmrd) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all ba nks are in the precharge st ate. the mode register is divided into various fields depending on functionality. burst length is de fined by a0 ~ a2 with options of 4 and 8 bit burst lengths. the burst length decodes are comp atible with ddr sdram. burst address sequence type is defined by a3, cas latency is defined by a4 ~ a6. the ddr2 doesn?t support half clock latency mode. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal mrs operation. write recov- ery time twr is defined by a9 ~ a11. refer to the table for specific codes. address field cas latency a 6 a 5 a 4 latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2(optional) 011 3 100 4 101 5 110 6 1 1 1 reserved a 7 mode 0normal 1test a 3 burst type 0 sequential 1 interleave a 8 dll reset 0no 1yes mode register ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 tm cas latency bt dll 0* 1 wr write recovery for autoprecharge a 11 a 10 a 9 wr(cycles) 0 0 0 reserved 001 2 010 3 011 4 100 5 101 6 1 1 0 reserved 1 1 1 reserved a 15 ~ a 13 0 burst length burst length a 2 a 1 a 0 bl 0104 0118 *1 : ba2 and a13~a15 are reserved for future use and must be programmed to 0 when setting the mode register. * 2: wr(write recovery for autoprecha rge) min is determined by tck max and wr max is determined by tck min. wr in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer (wr[cycles] = twr(ns)/tck(ns)). the mode register must be programmed to this value. this is also used with trp to determine tdal. ba 2 0* 1 ba1 ba0 mrs mode 00 mrs 01 emrs(1) 1 0 emrs(2): reserved 1 1 emrs(3): reserved ddr400 ddr533 ddr667 ddr800 *2 a 12 pd a 12 active power down exit time 0 fast exit(use t xard ) 1 slow exit(use t xards )
rev 0.2 / apr. 2004 16 hy5ps1g431(l)f hy5ps1g831(l)f 2.3.2.2 ddr2 sdram extende d mode register set emrs(1) the extended mode register(1) stor es the data for enabling or disabling the d ll, output driver strength, additive latency, odt, dqs disable, ocd program, rdqs enable. the default valu e of the extended mode r egister(1) is not defined, therefore the extended mode register(1) must be written after power-up for pr oper operation. the extended mode regis- ter(1) is written by asserting low on cs , ras , cas , we , high on ba0 and low on ba1, while controlling the states of address pins a0 ~ a15. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register(1). the mode register set command cycle time (tmrd) must be satisfied to complete the write operation to the extended mode register(1). mode register contents can be cha nged using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength output driver . a3~a5 determines the additive latency, a7~a9 are used for ocd control, a10 is used for dqs disable and a11 is used for rdqs enable. a2 and a6 are used for odt setting. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re-e nabled upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the exte rnal clock. failing to wait for syn- chronization to occur may result in a vi olation of the tac or tdqsck parameters.
rev 0.2 / apr. 2004 17 hy5ps1g431(l)f hy5ps1g831(l)f address field rdqs extended mode register dll 0* 1 d.i.c ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 0 dll enable 0 enable 1 disable additive latency a 5 a 4 a 3 additive latency 000 0 001 1 010 2 011 3 100 4 101 5 1 1 0 reserved 1 1 1 reserved a: when adjust mode is issued, al from previously set value must be applied. b: after setting to default, ocd mode needs to be exited by setting a9-a7 to 000. refer to the following 2.2.2.3 section for detailed information a9 a8 a7 ocd calibration program 0 0 0 ocd calibration mode ex it; maintain setting 0 0 1 drive(1) 0 1 0 drive(0) 100 adjust mode a 111 ocd calibration default b ocd program 1 dqs rtt rtt a1 output driver impedence control driver size 0 normal 100% 1 half 60% a10 dqs 0 enable 1 disable * if rdqs is enabled, the dm function is disabled. rdqs is active for reads and don?t care for writes. a11 rdqs enable 0 disable 1 enable *1 : ba2 and a13~a15 are reserved for future use and must be programmed to 0 when setting the mode register. ba 1 0 a6 a2 r tt ( nominal ) 0 0 odt disabled 0 1 75 ohm 1 0 150 ohm 11 reserved ba1 ba0 mrs mode 00 mrs 01 emrs(1) 1 0 emrs(2): reserved 1 1 emrs(3): reserved ba 2 0* 1 emrs(1) programming qoff a 12 a 12 qoff (optional) a a. outputs disabled - dqs, dqss, dqs s, rdqs, rdqs . this feature is used in conjunction with dimm idd meaurements when iddq is not desired to be included. 0 output buffer enabled 1 output buffer disabled a11 (rdqs enable) a10 (dqs disable) strobe function matrix rdqs/dm rdqs dqs dqs 0 (disable) 0 (enable) dm hi-z dqs dqs 0 (disable) 1 (disable) dm hi-z dqs hi-z 1 (enable) 0 (enable) rdqs rdqs dqs dqs 1 (enable) 1 (disable) rdqs hi-z dqs hi-z
rev 0.2 / apr. 2004 18 hy5ps1g431(l)f hy5ps1g831(l)f emrs(2) the extended mode register(2) controls refresh related features. the default value of the extended mode reg- ister(2) is not defined, therefore the extended mode register(2) must be written after power-up for proper operation. the extended mode regi ster(2) is written by asserting lo w on /cs,/ras,/cas,/we, high on ba1 and low on ba0, while controling the states of addr ess pins a0~a15. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register(2). mode register contents can be changed using the same command and clock cycle re quirements during normal operation as long as all bank are in the precharge state. emrs(2) programming: *1 : the rest bits in emrs(2) is reserved for future use and all bits except a7, ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. due to the migration natural, user needs to ensure the dram part supports higher than 85 tcase tempera- ture self-refresh entry. jedec standard ddr2 sdram module us er can look at ddr2 sdram module spd fileld byte 49 bit[0]. if the high temperature self-refre sh mode is supported then controller can set the emrs2 [a7] bit to enable the self-refresh rate in case of higher than 85 temperature self-refresh operation. for the lose part user, please refer to the hynix web site(www .hynix.com) to check the high temperature self-refresh rate availability. emrs(3) programming: reserved * 1 *1 : emrs(3) is reserved for future use and all bits e xcept ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. address field extended mode 0* 1 ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 ba 1 1 ba 2 0* 1 a 12 srf 0* 1 register(2) 0* 1 ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 ba 1 1 ba 2 0* 1 a 12 ba1 ba0 mrs mode 00 mrs 01 emrs(1) 10 emrs(2) 1 1 emrs(3):reserved a7 hign temp self-refresh rate enable 0 disable 1 enable
rev 0.2 / apr. 2004 19 hy5ps1g431(l)f hy5ps1g831(l)f 2.3.2.3 off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd imped ance adjustment and odt (on die termian- tion) should be carefully controlled depending on system environment. start emrs: drive(1) dq & dqs high; dqs low test emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: drive(0) dq & dqs low; dqs high test emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit end all ok all ok need calibration need calibration emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit mrs shoud be set before entering ocd impedance adjustment and odt should be carefully controlled depending on system environment
rev 0.2 / apr. 2004 20 hy5ps1g431(l)f hy5ps1g831(l)f extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs mode. in drive mode all outputs are driven out by ddr2 sdram and drive of rdqs is de pedent on emrs bit enabling rdqs operation. in drive(1) mode, all dq, dqs (and rdqs) signals are driven high and all dqs signals are driven low. in drive(0) mode, all dq, dqs (and rdqs) signals are driven low and all dqs signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver charac- teristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. output driver characteristics for ocd calibration default are specified in table x. ocd applies only to normal full strength output drive setting defined by emrs(1) an d if half strength is set, ocd default output driver characteristics are not applicable. when ocd calibrati on adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibration is completed or driver strength is set to default, subsequent emrs commands not intended to adjust o cd characteristics must specify a9-a7 as '000' in order to maintain the def ault or calibrated value. off- chip-driver program ocd impedance adjust to adjust output driver impedanc e, controllers must issue the adju st emrs command along with a 4bit burst code to ddr2 sdram as in table x. for this o peration, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must driv e this burst code to all dqs at the same time. dt0 in table x means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output impedance is adjusted for all ddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the 16 step range. when adjust mode command is issued, al from previously set value must be applied table x : off- chip-driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, (rdqs) high and dqs low 0 1 0 drive(0) dq, dqs, (rdqs) low and dqs high 1 0 0 adjust mode 1 1 1 ocd calibration default 4bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 0000 nop (no operation) nop (no operation) 0 0 0 1 increase by 1 step nop 0010 decrease by 1 step nop 0100 nop increase by 1 step 1000 nop decrease by 1 step 0101 increase by 1 step increase by 1 step 0110 decrease by 1 step increase by 1 step 1001 increase by 1 step decrease by 1 step 1010 decrease by 1 step decrease by 1 step other combinat ions reserved
rev 0.2 / apr. 2004 21 hy5ps1g431(l)f hy5ps1g831(l)f for proper operation of adjust mode, wl = rl - 1 = al + cl - 1 clocks and tds/tdh should be met as the fol- lowing timing diagram. for input data pattern for adjustment, dt0 - dt3 is a fixed order and "not affected by mrs addressing mode (ie. sequential or interleave). drive mode drive mode, both drive(1) and drive(0), is used for controllers to measure ddr2 sdram driver impedance. in this mode, all outputs are driven out toit after ?e nter drive mode? command and all output drivers are turned-off toit after ?ocd ca libration mode exit? command as the following timing diagram. nop nop nop nop emrs d t0 cmd ck dqs_in dq_in tds tdh wl ocd adjust mode ocd calibration mode exit d t1 d t2 d t3 wr emrs nop nop ck dqs dm emrs nop nop nop emrs cmd ck dqs dq enter drive mode ocd calibration mode exit toit hi-z dqs high for drive(1) dqs high & dqs low for drive(1), dqs low & dqs high for drive(0) hi-z dqs low for drive(0) toit ck dqs
rev 0.2 / apr. 2004 22 hy5ps1g431(l)f hy5ps1g831(l)f 2.3.2.4 odt (on die termination) on die termination (odt) is a feature that allows a dram to turn on/off termination resistance for each dq, dqs/dqs , rdqs/rdqs , and dm signal for x4x8 configurations vi a the odt control pin. for x16 configura- tion odt is applied to each dq, udqs/udqs , ldqs/ldqs , udm, and ldm signal via the odt control pin. the odt feature is designed to improve signal integr ity of the memory channel by allowing the dram con- troller to independently turn on/off termination resistance for any or all dram devices. the odt function is supported for active and stand by modes. odt is turned off and not supported in self refresh mode. functional represen tation of odt input pin input buffer dram v ss qv ss q v dd qv dd q rval2 rval2 rval1 rval1 sw1 sw1 sw2 sw2 selection between sw1 or sw2 is determined by ?rtt (nominal)? in emrs termination included on all dqs, dm, dqs, dqs , rdqs, and rdqs pins. switch sw1 or sw2 is enabled by odt pin. target rtt (ohm) = (rval1) / 2 or (rval2) / 2
rev 0.2 / apr. 2004 23 hy5ps1g431(l)f hy5ps1g831(l)f odt timing for active/standby mode odt timing for powerdown mode t0 t1 t2 t3 t4 t5 t aond ck ck cke odt internal te r m r e s . t6 t aofd t is t is t aon,min t aon,max t aof,min t aof,max r tt t0 t1 t2 t3 t4 t5 ck ck cke odt internal te r m r e s . t6 t is t is t aonpd,min t aofpd,max t aonpd,max t aofpd,min r tt
rev 0.2 / apr. 2004 24 hy5ps1g431(l)f hy5ps1g831(l)f odt timing mode switch at entering power down mode t-5 t-4 t-3 t-2 t-1 t0 ck ck t1 cke odt internal term res. t is t aofd rtt t is rtt t2 t3 t4 odt internal te r m r e s . active & standby mode timings to be applied. power down mode timings to be applied. t aofpdmax t is odt internal te r m r e s . t is t aond rtt t is rtt odt internal te r m r e s . active & standby mode timings to be applied. power down mode timings to be applied. t aonpdmax t anpd entering slow exit ac tive power down mode or precharge power down mode.
rev 0.2 / apr. 2004 25 hy5ps1g431(l)f hy5ps1g831(l)f odt timing mode switch at exiting power down mode t0 t1 t4 t5 t6 t7 ck ck t8 cke odt internal te r m r e s . t is t aofpdmax rtt t is t is rtt t9 t10 t11 odt internal te r m r e s . t axpd active & standby mode timings to be applied. power down mode timings to be applied. exiting from slow active power down mode or precharge power down mode. t aofd internal te r m r e s . t is rtt odt active & standby mode timings to be applied. t aond internal te r m r e s . rtt odt t aonpdmax t is power down mode timings to be applied.
rev 0.2 / apr. 2004 26 hy5ps1g431(l)f hy5ps1g831(l)f 2.4 bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank addresses ba0 ~ ba2 are us ed to select the desired bank. the row address a0 through a15 is used to determine which row to activa te in the selected bank. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the trcdmin specific ation, then additive latency must be programmed into the device to delay when the r/w comman d is internally issued to the device. the additive latency value must be chosen to assu re trcdmin is satisfied. additive latencies of 0, 1, 2, 3 and 4 are sup- ported. once a bank has been activated it must be pr echarged before another bank activate command can be applied to the same bank. the bank active and pr echarge times are defined as tras and trp, respec- tively. the minimum time interval between successive bank activate commands to the same bank is deter- mined by the ras cycle time of the device (t rc ). the minimum time interval between bank activate commands is t rrd . inorder to ensure that 8 bank devices do not ex eed the instaneous current supplying capab ility of 4 bank devices, certain restrictions on oper ation of the 8 bank devic es must be observed. there are two rules, one for restricting the number of sequential act commands that can be issued and another for allowing more time for ras precharge for a precharge all command. the rules are as follows: 1. 8 bank device sequential bank activation restrictio n: no more than 4 banks may be activated in a rolling 4 * trrd + 2 * tck window. trrd must be conver ted to clocks prior to multiplying by 4 and prior to adding 2* tck. converting to clocks is done by dividing trrd(ns) by tck( ns) and rounding up to next integer value. 2. 8 bank device precharge all allo wance: trp for a precharge all command for an 8 bank device will equal to trp + 1*tck, where trp is th e value for a single bank pre-charge. bank activate command cycle: trcd = 3, al = 2, trp = 3, trrd = 2, tccd = 2 address ck / ck t0 t2 t1 t3 tn tn+1 tn+2 tn+3 command bank a row addr. bank a activate bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internal ras -cas delay (>= t rcdmin ) : ?h? or ?l? ras cycle time ( >= t rc ) additive latency delay ( al ) read bank b row addr. bank b activate bank b col. addr. bank a bank a precharge bank b addr. bank b precharge bank a row addr. activate bank a ras - ras delay time ( >= t rrd ) read begins trcd =1 addr. bank active (>= t ras ) bank precharge time ( >= t rp ) cas -cas delay time ( t ccd ) bank a post cas read bank b post cas
rev 0.2 / apr. 2004 29 hy5ps1g431(l)f hy5ps1g831(l)f 2.5 read and wr ite access modes after a bank has been activated, a read or write cycl e can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defined at this time to determine whether the access cycle is a read operation (we high) or a write operation (we low). the ddr2 sdram provides a fast co lumn access operation. a single read or write command will initiate a serial read or write operation on successive clock cycles . the boundary of the burst cycle is strictly restricted to specific segments of the page length. for example, the 32mbit x 4 i/o x 4 bank chip has a page length of 2048 bits (defined by ca0-ca9, ca11). the page length of 2048 is divided into 512 or 256 uniquely addres- sable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. a 4- bit or 8 bit burst operation will occur entirely within one of the 512 or 256 group s beginning with the column address supplied to the device during the read or write command (ca0-ca9, ca11). the second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. a new burst access must not interrupt the previous 4 bi t burst operation in case of bl = 4 setting. however, in case of bl = 8 setting, two case s of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry respectively . the minimum cas to cas delay is defined by tccd, and is a mini mum of 2 clocks for read or write cycles.
rev 0.2 / apr. 2004 30 hy5ps1g431(l)f hy5ps1g831(l)f 2.5.1 posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a cas read or write command to be issued immediately after the ras bank activate command (or any time during the ras -cas -delay time, trcd, period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the cas latency (cl). therefore if a user chooses to i ssue a r/w command before th e trcdmin, then al (greater than 0) must be written into the emrs(1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). read or write operations using al allow seamless bursts (refer to semaless operation timing di agram examples in read burst and wirte burst section) examples of posted cas operation example 1 read followed by a write to the same bank [al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl - 1) = 4, bl = 4] example 2 read followed by a write to the same bank [al = 0 and cl = 3, rl = (al + cl) = 3, wl = (rl - 1) = 2, bl = 4] 0123456789101112 active a-bank read a-bank write a-bank dout0 dout1 dout2 dout3 din0 din1 din2 din3 ck/ck cmd dqs/dqs dq al = 2 -1 > = trcd cl = 3 > = trac wl = rl -1 = 4 rl = al + cl = 5 active a-bank read a-bank write a-bank dout0 dout1 dout2 dout3 din0 din1 din2 din3 al = 0 > = trcd cl = 3 > = trac wl = rl -1 = 2 rl = al + cl = 3 0 1 2 3 4 5 6 7 8 9 10 11 12 -1 ck/ck cmd dqs/dqs dq
rev 0.2 / apr. 2004 31 hy5ps1g431(l)f hy5ps1g831(l)f 2.5.2 burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). th e parameters that define how the burst mode will op erate are burst sequence and burst length. ddr2 sdram supports 4 bi t burst and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, ho wever, sequential address ordering is nibble based for ease of implementation. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs, which is similar to th e ddr sdram operation. seam less burst read or write operations are su pported. unlike ddr devices, interruption of a burst read or write cycle during bl = 4 mode operation is prohibited. however in ca se of bl = 8 mode, interruption of a burst read or write operation is lim- ited to two cases, reads interrupted by a read, or writ es interrupted by a write. therefore the burst stop com- mand is not supported on ddr2 sdram devices. burst length and sequence note: page length is a function of i/o organization and column addressing burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 0 0 0 0, 1, 2, 3 0, 1, 2, 3 0 0 1 1, 2, 3, 0 1, 0, 3, 2 0 1 0 2, 3, 0, 1 2, 3, 0, 1 0 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
rev 0.2 / apr. 2004 32 hy5ps1g431(l)f hy5ps1g831(l)f 2.5.3 burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column addres s for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low 1 clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchroniz ed with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs), similar to the existing sdr and ddr sdrams. the al is defined by the extended mode register set (1)(emrs(1)). ddr2 sdram pin timings are specifi ed for either single ended mode or differential mode depending on the setting of the emrs(1) ?enable dqs? mode bit; timing advantages of differential mode are realized in sys- tem design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to t he rising or falling edges of dqs crossing at v ref . in differential mode, these timing re lationships are measured relative to the crosspoint of dqs and its com- plement, dqs . this distinction in timing methods is guarante ed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 kohm resistor to insure proper operation. t ch t cl ck ck ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax figure yy-- data output (read) timing q qq burst read operation: rl = 5 (al = 2, cl = 3, bl = 4) cmd nop nop nop nop nop nop nop dqs nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a posted cas al = 2 cl =3 rl = 5 dqs/dqs =< t dqsck t0 t2 t1 t3 t4 t5 t6 t7 t8
rev 0.2 / apr. 2004 33 hy5ps1g431(l)f hy5ps1g831(l)f burst read operation: rl = 3 (al = 0 and cl = 3, bl = 8) burst read followed by burst write: rl = 5, wl = (rl-1) = 4, bl = 4 the minimum time from the burst read command to th e burst write command is defined by a read-to-write- turn-around-time, which is 4 clocks in case of bl = 4 operation, 6 clocks in ca se of bl = 8 operation. cmd nop nop nop nop nop nop nop dqs nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a cl =3 rl = 3 dqs/dqs =< t dqsck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 4 dout a 5 dout a 6 dout a 7 cmd post cas nop nop nop nop nop dq?s nop ck/ck t0 tn-1 t1 tn tn+1 tn+2 tn+3 tn+4 tn+5 dout a 0 dout a 1 dout a 2 dout a 3 dqs/dqs din a 0 din a 1 din a 2 din a 3 read a wl = rl - 1 = 4 rl =5 post cas write a t rtw (read to write turn around time) nop
rev 0.2 / apr. 2004 34 hy5ps1g431(l)f hy5ps1g831(l)f seamless burst read operation: rl = 5, al = 2, and cl = 3, bl = 4 the seamless burst read operation is supported by enab ling a read command at every other clock for bl = 4 operation, and every 4 clock for bl = 8 operation. this operation is allowed regardless of same or different banks as long as the banks are activated. cmd nop nop nop nop nop nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 2 cl =3 rl = 5 dqs/dqs dout b 0 dout b 1 dout b 2 read b post cas
rev 0.2 / apr. 2004 35 hy5ps1g431(l)f hy5ps1g831(l)f reads interrupted by a read burst read can only be interrupted by another read with 4 bit burst boundary. any other case of read interrupt is not allowed. read burst interrupt timing exam ple: (cl=3, al=0, rl=3, bl=8) note 1. read burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. 2. read burst of 8 can only be interrupted by anothe r read command. read burst interruption by write command or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after previous read command. any other read burst interrupt timings are prohibited. 4. read burst interruption is allowed to any bank inside dram. 5. read burst with auto precharge enabled is not allowed to interrupt. 6. read burst interruption is allowed by another read with auto precharge command. 7. all command timings are referenced to burst length set in the mode register. they are not referenced to actual burst. for example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). ck/ck cmd dqs/dqs dqs read b read a nop nop nop nop nop nop nop nop a0 a1 a2 a3 b0 b1 b2 b3 b4 b5 b6 b7
rev 0.2 / apr. 2004 36 hy5ps1g431(l)f hy5ps1g831(l)f 2.5.4 burst write operation the burst write command is initiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the st arting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl -1). a data strobe signal (dqs) should be driven low (preamble) one clock prior to the wl. the first da ta bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble . the tdqss specification mu st be satisfied for write cycles. the subsequent burst bit data are issued on su ccessive edges of the dqs until the burst length is completed, which is 4 or 8 bit burst. when the burst ha s finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operat ion is complete. the time from the com- pletion of the burst write to bank prec harge is the write recovery time (wr). ddr2 sdram pin timings are specified for either singl e ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing ad vantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measur ed is mode depe ndent. in single ended mode, timing relationships are measured relative to t he rising or falling edges of dqs crossing at v ref . in differential mode, these timing re lationships are measured relative to the crosspoint of dqs and its com- plement, dqs . this distinction in timing methods is guarante ed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 kohm resistor to insure proper operation. burst write operation: rl = 5, wl = 4, twr = 3 (al=2, cl=3), bl = 4 t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh data input (write) timing dmin dmin dmin d d d dqs cmd nop nop nop nop nop nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 tn write a posted cas wl = rl - 1 = 4 dqs/dqs < = t dqss > = wr din a 0 din a 1 din a 2 din a 3 precharge completion of the burst write
rev 0.2 / apr. 2004 37 hy5ps1g431(l)f hy5ps1g831(l)f burst write operation: rl = 3, wl = 2, twr = 2 (al=0, cl=3), bl = 4 burst write followed by burst read: rl = 5 (al=2, cl=3), wl = 4, twtr = 2, bl = 4 the minimum number of clock from the burst write comm and to the burst read command is [cl - 1 + bl/2 + twtr]. this twtr is not a write recovery time (twr) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array. twtr is defined in ac spec table of this data sheet. cmd nop nop nop nop precharge nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 tn write a wl = rl - 1 = 2 dqs/ < = t dqss > = wr din a 0 din a 1 din a 2 din a 3 bank a completion of the burst write activate > = trp dqs cmd nop nop nop nop dq ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 din a 0 din a 1 din a 2 din a 3 nop dqs/ dout a 0 wl = rl - 1 = 4 post cas read a nop rl =5 al = 2 cl = 3 nop nop write to read = cl - 1 + bl/2 + twtr > = twtr t9 dqs dqs dqs
rev 0.2 / apr. 2004 38 hy5ps1g431(l)f hy5ps1g831(l)f seamless burst write operation: rl = 5, wl = 4, bl = 4 the seamless burst write operation is supported by enabling a write command every other clock for bl = 4 operation, every four clocks for bl = 8 operation. this operation is allowed regardless of same or different banks as long as the banks are activated cmd nop nop nop nop nop nop dq?s nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 din a 0 din a 1 din a 2 din a 3 write a post cas wl = rl - 1 = 4 dqs/ write b post cas din b 0 din b 1 din b 2 din b 3 dqs dqs dqs
rev 0.2 / apr. 2004 39 hy5ps1g431(l)f hy5ps1g831(l)f writes interrupted by a write burst write can only be interrupted by another write with 4 bit burst boundary. any other case of write interrupt is not allowed. write burst interrupt timing exampl e: (cl=3, al=0, rl=3, wl=2, bl=8) notes: 1. write burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. 2. write burst of 8 can only be interrupted by anothe r write command. write burst interruption by read command or precharge command is prohibited. 3. write burst interrupt must occur exactly two clocks after previous write command. any other write burst interrupt timings are prohibited. 4. write burst interruption is allowed to any bank inside dram. 5. write burst with auto precharge en abled is not allo wed to interrupt. 6. write burst interruption is allowed by another write with auto precharge command. 7. all command timings are referenced to burst length set in the mode register. they are not referenced to actual burst. for example, minimum write to prec harge timing is wl+bl/2+twr where twr starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end. ck/ck cmd dqs/dqs dqs nop nop nop nop nop nop nop nop a0 a1 a2 a3 b0 b1 b2 b3 b5 b6 b7 write b write a b4
rev 0.2 / apr. 2004 40 hy5ps1g431(l)f hy5ps1g831(l)f 2.5.5 write data mask one write data mask (dm) pin for each 8 data bits (dq) will be supported on ddr2 sdrams, consistent with the implementation on ddr sdrams. it ha s identical timings on write operations as th e data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. dm of x4 and x16 bit organization is not used during read cycles. however dm of x8 bit organization can be used as rdqs during read cycles by emrs(1) settng. data mask timing dqs/ dq dm t ds t dh t ds t dh write ck ck command dqs/dqs dq dm case 2 : max t dqss dqs/dqs dq dm t dqss t dqss t wr data mask function, wl=3, al=0, bl = 4 shown case 1 : min t dqss dqs
rev 0.2 / apr. 2004 41 hy5ps1g431(l)f hy5ps1g831(l)f 2.6 precharge operation the precharge command is used to precharge or close a bank that has been activated. the precharge com- mand is triggered when cs , ras and we are low and cas is high at the rising ed ge of the clock. the pre- charge command can be used to precharge each bank independently or all banks simultaneously. four address bits a10, ba0 ~ba2 for 1gb are used to define which bank to precharge when the command is issued. bank selection for prech arge by address bits burst read operation followed by precharge minium read to precharge command spacing to the same bank = al + bl/2 clocks for the earliest possible precharge, the precharge command may be issued on the rising edge which is ?additive latency(al) + bl/2 clocks? after a read command. a new bank ac tive (command) may be issued to the same bank after the ras precharge time (t rp ). a precharge command cannot be issued until t ras is sat- isfied. the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock egde that initiates the last 4-bit prefetch of a re ad to precharge command. this time is called trtp (r ead t o p recharge). for bl = 4 this is the time from the actu al read (al after the read command) to precharge com- mand. for bl = 8 this is the time from al + 2 clocks after the read to the precharge command. a10 ba2 ba1 ba0 precharged bank(s) remarks low low low low bank 0 only low low low high bank 1 only low low high low bank 2 only low low high high bank 3 only low high low low bank 4 only low high low high bank 5 only low high high low bank 6 only low high high high bank 7 only high don?t care don?t ca re don?t care all banks
rev 0.2 / apr. 2004 42 hy5ps1g431(l)f hy5ps1g831(l)f example 1: burst read operat ion followed by precharge: rl = 4, al = 1, cl = 3, bl = 4, t rtp <= 2 clocks example 2: burst read operat ion followed by precharge: rl = 4, al = 1, cl = 3, bl = 8, t rtp <= 2 clocks cmd nop nop precharge a nop dq?s nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas rl =4 dqs/dqs active bank a > = t rp nop cl =3 nop > = t ras t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks al = 1 cl = 3 > = t rtp cmd nop nop nop nop dq?s nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas rl =4 dqs/dqs precharge a nop t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks al = 1 cl = 3 > = t rtp dout a 4 dout a 5 dout a 6 dout a 7 first 4-bit prefetch second 4-bit prefetch nop
rev 0.2 / apr. 2004 43 hy5ps1g431(l)f hy5ps1g831(l)f example 3: burst read operat ion followed by precharge: rl = 5, al = 2, cl = 3, bl = 4, t rtp <= 2 clocks example 4: burst read operat ion followed by precharge: rl = 6, al = 2, cl = 4, bl = 4, t rtp <= 2 clocks cmd nop nop nop nop dq?s precharge a ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a posted cas al = 2 cl =3 rl =5 dqs/dqs activate bank a > = t rp nop cl =3 nop > = t ras t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks > = t rtp cmd nop nop nop nop dq?s precharge a ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 2 cl =4 rl = 6 dqs/dqs activate bank a > = t rp nop cl =4 nop > = t ras t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks > = t rtp
rev 0.2 / apr. 2004 44 hy5ps1g431(l)f hy5ps1g831(l)f example 5: burst read operat ion followed by precharge: rl = 4, al = 0, cl = 4, bl = 8, t rtp > 2 clocks cmd nop nop nop nop dq?s precharge a ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 0 cl =4 rl = 4 dqs/dqs activate bank a > = t rp nop nop > = t ras t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + 2 clks + max{trtp;2 tck}* * : rounded to next interger dout a 4 dout a 5 dout a 6 dout a 7 first 4-bit prefetch second 4-bit prefetch > = t rtp
rev 0.2 / apr. 2004 45 hy5ps1g431(l)f hy5ps1g831(l)f burst write followed by precharge minium write to precharge command spacing to the same bank = wl + bl/2 clks + twr for write cycles, a delay must be satisfied from the comp letion of the last burst wr ite cycle until the precharge command can be issued. this delay is known as a write recovery time (twr) referenced from the completion of the burst write to the precharge command. no prechar ge command should be issued prior to the twr delay. example 1: burst writ e followed by prechar ge: wl = (rl-1) =3 example 2: burst writ e followed by prechar ge: wl = (rl-1) = 4 cmd nop nop nop nop nop nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t 8 din a 0 din a 1 din a 2 din a 3 write a posted cas wl = 3 dqs/dqs > = wr precharge a completion of the burst write cmd nop nop nop nop nop nop dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t 9 din a 0 din a 1 din a 2 din a 3 write a posted cas wl = 4 dqs/dqs > = t wr precharge a completion of the burst write
rev 0.2 / apr. 2004 46 hy5ps1g431(l)f hy5ps1g831(l)f 2.7 auto precharge operation before a new row in an active bank can be opened, the active bank must be precha rged using either the pre- charge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column ad dress a10, to allow the active bank to auto- matically begin precharge at the earliest possible mom ent during the burst read or write cycle. if a10 is low when the read or write command is issued, then nor mal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write com- mand is issued, then the auto-prec harge function is enga ged. during auto-prec harge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is cas latency (cl) clock cycles befo re the end of the read burst. auto-precharge is also implemented during write co mmands. the precharge operation engaged by the auto precharge command will not begin until the last data of the burst write se quence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for ran dom data access. the ras lock- out circuit internally delays the precharge operation until the array restore operation has been completed (tras satisfied) so that the auto precharge comma nd may be issued with any read or write command. burst read with auto precharge if a10 is high when a read command is issued, the read with auto-precharge function is engaged. the ddr2 sdram starts an auto precharge operation on the rising edge which is (al + bl/2) cycles later than the read with ap command if tras(min) and trtp are satisfied. if tras(min) is not satisfied at t he edge, the start point of auto-prechar ge operation will be delayed until tras(min) is satisfied. if trtp(min) is not satisfied at the edge, the start po int of auto-precharge oper ation will be delayed until trtp(min) is satisfied. in case the internal precharge is pushed out by trtp, trp starts at the point where the internal precharge happens (not at the next rising clock edge after this ev ent). so for bl = 4 the minimum time from read_ap to the next activate command becomes al + (trtp + trp)* (see example 2) for bl = 8 the time from read_ap to the next activate is al + 2 + (trtp + trp)*, where ?* ? means: ?rounded up to the next integer?. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank activate (command) may be issued to the sa me bank if the following two conditions are satisfied simultaneously. (1) the ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. (2) the ras cycle time (trc) from the previous bank activation has been satisfied.
rev 0.2 / apr. 2004 47 hy5ps1g431(l)f hy5ps1g831(l)f example 1: burst read oper ation with auto precharge: rl = 4, al = 1, cl = 3, bl = 8, t rtp <= 2 clocks example 2: burst read oper ation with auto precharge: rl = 4, al = 1, cl = 3, bl = 4, t rtp > 2 clocks cmd nop nop nop nop dq?s nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas rl =4 dqs/dqs t0 t2 t1 t3 t4 t5 t6 t7 t 8 al + bl/2 clks al = 1 cl = 3 > = t rtp dout a 4 dout a 5 dout a 6 dout a 7 first 4-bit prefetch second 4-bit prefetch nop t rtp nop precharge begins here activate bank a > = t rp autoprecharge cmd nop nop nop nop dq?s nop ck/ck dout a 0 dout a 1 dout a 2 dout a 3 read a post cas rl =4 dqs/dqs t0 t2 t1 t3 t4 t5 t6 t7 t 8 > = al + trtp + trp al = 1 cl = 3 4-bit prefetch nop t rtp nop precharge begins here activate bank a autoprecharge t rp
rev 0.2 / apr. 2004 48 hy5ps1g431(l)f hy5ps1g831(l)f example 3: burst read with auto precharge followed by an activation to the same bank(trc limit): rl = 5 (al = 2, cl = 3, inte rnal trcd = 3, bl = 4, t rtp <= 2 clocks) example 4: burst read with auto precharge followed by an activation to the same bank(trp limit): rl = 5 (al = 2, cl = 3, inte rnal trcd = 3, bl = 4, t rtp <= 2 clocks) cmd nop nop nop nop nop dq?s nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 2 cl =3 rl = 5 dqs/dqs activate bank a > = t rp a10 = 1 auto precharge begins cl =3 > = t rc nop > = tras(min) cmd nop nop nop nop nop dq?s nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 read a post cas al = 2 cl =3 rl = 5 dqs/dqs activate bank a > = t rp a10 = 1 auto precharge begins cl =3 > = t rc nop > = tras(min)
rev 0.2 / apr. 2004 49 hy5ps1g431(l)f hy5ps1g831(l)f burst write with auto-precharge if a10 is high when a write command is issued, the wr ite with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge operation af ter the completion of the burst write plus write recovery time (twr). the bank undergoing auto-prec harge from the completion of the write burst may be reactivated if the following tw o conditions are satisfied. (1) the data-in to bank activate dela y time (wr + trp) has been satisfied. (2) the ras cycle time (trc) from the previous bank activation has been satisfied. burst write with auto-precharge (trc li mit): wl = 2, twr =2, bl = 4, trp=3 burst write with auto-precharge (twr + trp): wl = 4, twr =2, bl = 4, trp=3 cmd nop nop nop nop nop bank a dqs nop ck/ck t0 t2 t1 t3 t4 t5 t6 t7 tm din a 0 din a 1 din a 2 din a 3 wra banka post cas wl =rl - 1 = 2 dqs/dqs a10 = 1 auto precharge begins nop > = wr completion of the burst write active > = t rp > = t rc cmd nop nop nop nop nop bank a dqs nop ck/ck t0 t4 t3 t5 t6 t7 t8 t9 t12 din a 0 din a 1 din a 2 din a 3 wra bank a post cas wl =rl - 1 = 4 dqs/dqs a10 = 1 auto precharge begins nop > = wr completion of the burst write active > = t rp > = t rc
rev 0.2 / apr. 2004 50 hy5ps1g431(l)f hy5ps1g831(l)f 2.8 refresh commands ddr2 sdrams require a refresh of all rows in any rollin g 64 ms interval. each refresh is generated in one of two ways: by an explicit auto-refresh command, or by an internally timed event in self refresh mode. dividing the number of device rows into the rolling 64ms interval, trefi, whic h is a guideline to controllers for distributed refresh timing. for example, a 512mb ddr2 sdram has 8192 rows resulting in a trefi of 7.8 ? . to avoid excessive interruptions to the memory cont roller, higher density dd r2 sdrams maintain 7.8 ? average refresh time and perform multiple internal refr esh bursts. in these cases, the refresh recovery times, trfc an txsnr are extended to accomodate these internal operations. 2.8.1 auto refresh command auto refresh is used during normal operation of t he ddr2 sdram. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don ?t care? during an auto refresh command. when cs, ras and cas are held low and we high at the rising edge of the clock, the chip enters the refresh mode (ref). all banks of the ddr2 sdram must be precharged and idle for a minimum of the pre- charge time (trp) before the refresh command (ref) can be applied. an address counter, internal to the device, supplies the bank address during the refresh cycle . no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the ddr2 sdram will be in the prec harged (idle) state. a delay between the refresh command (ref) and the next activate command or subsequent refresh com- mand must be greater than or equal to the refresh cycle time (trfc). to allow for improved efficiency in scheduling andswitching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any refresh command and the next refresh command is 9 * trefi. 2.8.2 self refresh operation the self refresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mod, the dd r2 sdram retains data wi thout external clocking. the ddr2 sdram device has a built-in timer to acco mmodate self refresh operation. the self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. odt must be turned off before issuin g self refresh command, by either driving odt pin low or using emrs command. once the command is registered, cke must be held low to keep the dev ice in self refresh mode. the dll is automatically disabled upon entering self re fresh and is automatically enabled upon existing self refresh. when the ddr2 sdram has entered self refresh mode all of the external signals except cke, are ?don?t care?. the dram initiates a minimum of one au to refresh command interna lly within tcke period once it enters self refresh mode.the clock is internally di sabled during self refresh operation to save power. the minimum time that the ddr2 sdram mu st remain in self refresh mode is tcke. the user may change the external clock frequency or halt the external clock one clock after self-refresh entr y is registered, however, the clock must be restarted and stable before the device can exit self refresh operation. cmd nop ref ref nop any ck/ck t0 t2 t1 t3 tm tn tn + 1 precharge cke nop > = t rp > = t rfc > = t rfc high
rev 0.2 / apr. 2004 51 hy5ps1g431(l)f hy5ps1g831(l)f the procedure for existing self refresh requires a se quence of commands. first, the clock must be stable prior to cke going back high. once self refresh exit command is registered, a delay equal or longer than the txsnr or txsrd must be satisfied before a va lid command can be issued to the device. cke must remain high for the entire self refresh exit period txsrd for proper operation. upon exit from self refresh, the ddr2 sdram can be put back in to self refresh mode after txsrd expires.nop or deselect commands must be registered on each positive clock edge during the self refresh exit inte rval. odt should also be turned off during txsrd. the use of self refresh mode introd uce the possibility that an internally time d refresh event can be missed when cke is raised for exit from se lf refresh mode. upon exit from se lf refresh, the ddr2 sdram requires a minimum of one extra auto refresh command bef ore it is put back into self refresh mode. - device must be in the ?all banks idle? state prior to entering self refresh mode. - odt must be turned off taofd before entering self refresh mode, and can be turned on again when txsrd timing is satisfied. - txsrd is applied for a read or a read with autoprecharge command - txsnr is applied for any command except a read or a read with autoprecharge command. cmd ck t0 t2 t1 tm tn cke t3 t4 t5 odt self refresh t6 nop taofd ck > = txsnr > = txsrd trp* valid tck tch tcl tis tis tis tis tih nop nop
rev 0.2 / apr. 2004 52 hy5ps1g431(l)f hy5ps1g831(l)f 2.9 power-down power-down is synchronously entered when cke is regist ered low (along with nop or deselect command). cke is not allowed to go low while mode register or exten ded mode register command time, or read or write operation is in progress. cke is allowed to go low while any of other operations such as row activation, precharge or auto- precharge, or auto -refresh is in progress, but power-down idd spec will not be applied until finishing those opera- tions. timing diagrams are shown in the followin g pages with details for entry into power down. the dll should be in a locked state when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power- down deactivates the input and output buffers, excluding ck, ck , odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active powe r-down, but the dll is kept enabled during fast exit active power-down. in power-down mode, cke low and a stab le clock signal must be maintained at the inputs of the ddr2 sdram, and odt should be in a valid state but all other input signals are ?don?t care?. cke low must be maintained until tcke has been satisfied. power-down duration is limited by 9 times trefi of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect com- mand). cke high must be maintained until tcke has been sa tisfied. a valid, executable command can be applied with power-down exit latency, txp, txar d, or txards, after cke goes high. power-down exit latency is defined at ac spec table of this data sheet. basic power down entry and exit timing diagram t is t is ck/ck cke c ommand valid nop valid don?t care nop t xp, t xard, enter power-down mode t cke t ih t ih t cke t xards valid t ih exit power-down mode t is t ih t cke t ih valid t is
rev 0.2 / apr. 2004 53 hy5ps1g431(l)f hy5ps1g831(l)f ck cmd cke dq dqs cmd cke dq dqs cmd cke dq dqs cmd cke dq dqs rda rda bl=8 pre pre al + bl/2 with trtp = 7.5ns & tras min satisfied al + bl/2 with trtp = 7.5ns & tras min satisfied read to power down entry read with autoprecharge to power down entry ck ck ck start internal precharge al + cl al + cl cke should be kept high until the end of burst operation. al + cl bl=4 cke should be kept high cke should be kept high until the end of burst operation. al + cl t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 q q q q q q q q q q q q cke should be kept high until the end of burst operation. until the end of burst operation. q q q q q q q q rd bl=4 rd bl=8 read operation starts with a read command and q q q q t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 dqs dqs dqs dqs
rev 0.2 / apr. 2004 54 hy5ps1g431(l)f hy5ps1g831(l)f cmd cke dq dqs cmd cke dq dqs t0 tm+1 tm+3 tx tx+1 tx+2 ty t1 tm tm+2 ty+1 ty+2 ty+3 wr wr bl=8 cmd cke dq dqs cmd cke dq dqs t0 tm+1 tm+3 tx tx+1 tx+2 tx+3 t1 tm tm+2 tx+4 tx+5 tx+6 wra wra bl=8 pre pre d d d d d d d d d d d d twtr twtr wr*1 d d d d d d d d d d d d wr*1 write to power down entry write with autoprecharge to power down entry ck ck ck ck wl bl=4 bl=4 wl wl wl t0 tm+1 tm+3 tm+4 tm+5 tx tx+1 t1 tm tm+2 tx+2 tx+3 tx+4 ck ck * 1: wr is programmed through mrs t0 tm+1 tm+3 tm+4 tm+5 tx tx+1 t1 tm tm+2 tx+2 tx+3 tx+4 dqs dqs dqs dqs
rev 0.2 / apr. 2004 55 hy5ps1g431(l)f hy5ps1g831(l)f cmd cke cmd cke t0 t3 t5 t6 t7 t8 t9 t1 t2 t4 t10 cmd cke cmd cke cke can go to low one clock after an active command pr or mrs or pra emrs ref act tmrd refresh command to power down entry active command to power down entry precharge/precharge all command to power down entry mrs/emrs command to power down entry ck ck cke can go to low one clock after a precharge or precharge all command cke can go to low one clock after an auto-refresh command t11
rev 0.2 / apr. 2004 56 hy5ps1g431(l)f hy5ps1g831(l)f 2.10 asynchronous cke low event dram requires cke to be maintained ?high? for all valid operations as defined in this data sheet. if cke asyn- chronously drops ?low? during any valid operation dram is not guaranteed to preserve the contents of array. if this event occurs, memory co ntroller must satisfy dram timing specific ation tdelay before turning off the clocks. stable clocks must exist at the input of dram before cke is raised ?high? again. dram must be fully re-initial- ized (steps 4 thru 13) as described in initializaliation sequence . dram is ready for normal operation after the ini- tialization sequence. see ac timing par ametric table for tdelay specification tck ck ck# tdelay cke cke asynchronously drops low clocks can be turned off after this point stable clocks
rev 0.2 / apr. 2004 57 hy5ps1g431(l)f hy5ps1g831(l)f input clock frequency change during precharge power down ddr2 sdram input clock frequency can be changed under following condition: ddr2 sdram is in precharged power down mode. odt must be turned off and cke must be at logic low level. a minimum of 2 clocks must be waited after cke goes low before clock frequency may change. sdram input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. during input clock frequency c hange, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new cl ocks must be provided to dram before precharge power down may be exited and dll must be reset via emrs after precharge power down exit. depending on new clock frequency an additional mrs command may need to be issued to appropriately set the wr, cl etc.. during dll re-lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency. ck cke t0 t4 tx+1 ty ty+1 ty+2 t1 t2 tx ck valid dll nop 200 clocks frequency change ty+3 tz nop nop nop nop reset trp clock frequency change in precharge power down mode txp occurs here taofd stable new clock before power down exit odt is off during dll reset minmum 2 clocks required before changing frequency odt cmd ty+4
rev 0.2 / apr. 2004 58 hy5ps1g431(l)f hy5ps1g831(l)f 2.11 no operation command the no operation command should be used in cases wh en the ddr2 sdram is in an idle or a wait state. the purpose of the no o peration command (nop) is to prevent the ddr2 sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, su ch as a burst read or write cycle. 2.12 deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high at the rising edge of the clock, the ras , cas , and we signals become don?t cares.
rev 0.2 / apr. 2004 59 hy5ps1g431(l)f hy5ps1g831(l)f 3. truth tables 3.1 command truth table. function cke cs ras cas we ba0 ba1 ba2 a15-a11 a10 a9 - a0 notes previous cycle current cycle (extended) mode register set h h l l l l ba op code 1,2 refresh (ref) h h l l l h x x x x 1 self refresh entry h l l l l h x x x x 1 self refresh exit l h hxxx xxxx1,7 lhhh single bank precharge h h l l h l ba x l x 1,2 precharge all banks h h l l h l x x h x 1 bank activate h h l l h h ba row address 1,2 write h h l h l l ba column l column 1,2,3, write with auto precharge h h l h l l ba column h column 1,2,3, read h h l h l h ba column l column 1,2,3 read with auto-precharge h h l h l h ba column h column 1,2,3 no operation h x l h h h x x x x 1 device deselect h x h x x x x x x x 1 power down entry h l hxxx xxxx1,4 lhhh power down exit l h hxxx xxxx1,4 lhhh 1. all ddr2 sdram commands are defined by states of cs , ras , cas , we and cke at the rising edge of the clock. 2. bank addesses ba0, ba1, ba2 (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 3. burst reads or writes at bl=4 cannot be terminated or inte rrupted. see sections "reads interrupted by a read" and "writes in ter- rupted by a write" in section 2.2.4 for details. 4. the power down mode does not perform any refresh operations. th e duration of power down is therefore limited by the refresh requirements outlined in section 2.2.7. 5. the state of odt does not affect the states described in this table. the odt function is not av ailable during self refresh. s ee section 2.2.2.4. 6. ?x? means ?h or l (but a defined logic level)?. 7. self refresh exit is asynchronous.
rev 0.2 / apr. 2004 60 hy5ps1g431(l)f hy5ps1g831(l)f 3.2 clock enable (cke) truth ta ble for synchronous transitions current state 2 cke command (n) 3 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power down l l x maintain power-down 11, 13, 15 l h deselect or nop power down exit 4, 8, 11,13 self refresh l l x maintain self refresh 11, 15 l h deselect or nop self refresh exit 4, 5,9 bank(s) active h l deselect or nop act ive power down entry 4,8,10,11,13 all banks idle h l deselect or nop precharge power down entry 4, 8, 10,11,13 h l refresh self refresh entry 6, 9, 11,13 h h refer to the command truth table 7 notes: 1. cke (n) is the logic state of cke at clock edge n; cke (n?1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock e dge n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or reserved unless explicitel y described elsewhere in this document. 5. on self refresh exit deselect or nop commands mu st be issued on every cloc k edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselect only. 10. power down and self refresh can not be entered while read or write operations, (extended) m ode register set operations or precharge operations are in progress. see section 2.2.9 "power down" and 2.2.8 "self refresh command" for a detailed list of restrictions. 11. minimum cke high time is three clocks .; minimum cke low time is three clocks. 12. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. see section 2.2.2.4. 13. the power down does not perform any refresh operations. the dur ation of power down mode is therefore limited by the refresh requirements outlined in section 2.2.7. 14. cke must be maintained high while the sdram is in ocd calibration mode . 15. ?x? means ?don?t care (including floating around vref)? in se lf refresh and power down. however odt must be driven high or low in power down if the odt fucntion is enabled (bit a2 or a6 set to ?1? in emrs(1) ). 3.3 dm truth table name (functional) dm dqs note write enable lvalid1 write inhibit hx1 1. used to mask write data, provided coinsident with the corresponding data
rev 0.2 / apr. 2004 61 hy5ps1g431(l)f hy5ps1g831(l)f 4.1 absolute maximum dc ratings 4.2 operating temperature condition symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1 vddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1 vddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1 v in , v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damag e to the device. this is a stress rating only and functional operation of the device at thes e or any other conditions above those indicated in the operati onal sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. symbol parameter rating units notes toper operating temperature 0 to 85 c 1,2 1. operating temperature is the case surface temperature on th e center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 2. the operatin temperature range are the temperature where all dr am specification will be support ed. outside of this temperatur e rang, even it is still within the limit of stress condition, some deviation on porti on of operation specification may be requir ed. during operation, the dram case temperature must be maintained betw een 0 ~ 85c under all other specification parameters. however, in some applications, it is desirable to operate the dram up to 95c case temperature. therefore 2 spec options may exist. 1) supporting 0 - 85 c with full jedec ac & dc specifications. this is the minimum requirements for all oprating tempera- ture options. 2) supporting 0 - 85c and being able to extend to 95c wi th doubling auto-refresh commands in frequency to a 32 ms period(trfi=3.9us). note; self-refresh period within the above dram is hard coded at 64ms(trefi= 7.8us). therfore, it is imperative that the sys- tem ensures the dram is at or below 85c case temperature before initiating self-refresh operation. 4. operating conditions
rev 0.2 / apr. 2004 62 hy5ps1g431(l)f hy5ps1g831(l)f 5.1 dc operation conditions 5.1.1 recommended dc operating conditions (sstl_1.8) 5.1.2 odt dc electrical characteristics note 1: test condition for rtt measurements measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately , then measure current i(v ih (ac)) and i( v il (ac)) respectively. v ih (ac), v il (ac), and vddq values defined in sstl_18 measurement definition for vm : measurement voltage at test pin(mid point) with no load. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v vddl supply voltage for dll 1.7 1.8 1.9 v 4 vddq supply voltage for output 1.7 1.8 1.9 v 4 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 1, 2 vtt termination voltage v ref -0.04 v ref v ref +0.04 v 3 there is no specific device vdd supply voltage requirement fo r sstl-1.8 compliance. however under all conditions vddq must be less than or equal to vdd. 1. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track variations in vddq. 2. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 3. vtt of transmitting device must track vref of receiving device. 4. vddq tracks with vdd, vddl tracks with vdd. ac para meters are measured with vdd, vddq and vdddl tied together parameter/condition symbol min nom max units notes rtt effective impedance value for emrs(a 6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6, a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 deviation of v m with respect to vddq/2 delta vm -3.75 +3.75 % 1 delta vm = 2 x vm vddq x 100% - 1 rtt(eff) = v ih (ac) - v il (ac) i( v ih (ac) ) - i( v il (ac) ) 5. ac & dc operating conditons
rev 0.2 / apr. 2004 63 hy5ps1g431(l)f hy5ps1g831(l)f 5.2.1 input dc logic leve l 5.2.2 input ac logic level 5.2.3 ac input test conditions notes: 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v il(dc) max to v ih(ac) min for rising edges and the range from v ih(dc) min to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching fr om vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter min. max. units notes v ih (ac) ac input logic high v ref + 0.250 - v v il (ac) ac input logic low -v ref - 0.250 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss < figure : ac input test signal waveform > v swing(max) delta tr delta tf start of falling edge input timing start of rising edge input timing v ih (dc) min - v il (ac) max delta tf falling slew = rising slew = v ih(ac) min - v il(dc) max delta tr 5.2 dc & ac logic input levels
rev 0.2 / apr. 2004 64 hy5ps1g431(l)f hy5ps1g831(l)f 5.2.4 differential input ac logic level 1. v in(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id(dc ) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih(dc) - v il(dc) . notes: 1. v id(ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih(ac) - v il(ac) . 2. the typical value of v ix(ac) is expected to be about 0.5 * vddq of the transmitting device and v ix(ac) is expected to track variations in vddq . v ix(ac) indicates the voltage at whitch differential input signals must cross. 5.2.5 differential ac output parameters notes: 1. the typical value of v ox(ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox(ac ) is expected to track variations in vddq . v ox(ac) indicates the voltage at whitch differential output signals must cross. symbol parameter min. max. units notes v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 symbol parameter min. max. units notes v ox (ac) ac differential cross point voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev 0.2 / apr. 2004 65 hy5ps1g431(l)f hy5ps1g831(l)f 5.2.6 overshoot/unders hoot specification ac overshoot/undershoot specification for address and control pins a0-a15, ba0-ba2, cs , ras , cas , we , cke, odt parameter specification ddr2-400 ddr2-533 ddr2-667 maximum peak amplitude allowed for overshoot area (see figure 1): 0.9v 0.9v 0.9v maximum peak amplitude allowed for undershoot area (see figure 1): 0.9v 0.9v 0.9v maximum overshoot area above vdd (see figure1). 0.75 v-ns 0.56 v-ns 0.45 v-ns maximum undershoot area below vss (see figure 1). 0.75 v-ns 0.56 v-ns 0.45 v-ns ac overshoot/undershoot specification for clock, data, strobe, and mask pins dq, dqs, dm, ck, ck parameter specification ddr2-400 ddr2-533 ddr2-667 maximum peak amplitude allowed for overshoot area (see figure 2): 0.9v 0.9v 0.9v maximum peak amplitude allowed for undershoot area (see figure 2): 0.9v 0.9v 0.9v maximum overshoot area above vddq (see figure 2). 0.38 v-ns 0.28 v-ns 0.23 v-ns maximum undershoot area below vssq (see figure 2). 0.38 v-ns 0.28 v-ns 0.23 v-ns overshoot area maximum amplitude v dd undershoot area maximum amplitude v ss volts (v) figure 1: ac overshoot and undershoot definition for address and control pins time (ns) overshoot area maximum amplitude v ddq undershoot area maximum amplitude v ssq volts (v) figure 2: ac overshoot and undershoot defini tion for clock, data, strobe, and mask pins time (ns)
rev 0.2 / apr. 2004 66 hy5ps1g431(l)f hy5ps1g831(l)f power and ground clamps are required on the following input only pins: 1. ba0-ba2 2. a0-a15 3. ras 4. cas 5. we 6. cs 7. odt 8. cke v-i characteristics table for input only pins with clamps voltage across clamp(v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0
rev 0.2 / apr. 2004 67 hy5ps1g431(l)f hy5ps1g831(l)f 5.3 output buffer levels 5.3.1 output ac t est conditions 5.3.2 output dc current drive 5.3.3 ocd defalut characteristics note 1: absolute sp ecifications (0c t case +95c; vdd = +1.8v 0.1 v, vddq = +1.8v 0.1v) note 2: impedance measurement condition for output source dc current: vddq = 1.7v; vout = 1420mv; (vout-vddq)/ioh must be less than 23.4 ohms fo r values of vout between vddq and vddq-280mv. impedance measurement condition for output sink dc current: vddq = 1.7v; vout = 280mv; vout/iol must be less than 23.4 ohms for values of vout between 0v and 280mv. note 3: mismatch is absolute value between pull-up an d pull-dn, both are measured at same temperature and voltage. note 4: slew rate measured from vil(ac) to vih(ac). note 5: the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. note 6: dram output slew rate specification table. note 7: dram output slew rate specificat ion applies to 400mt/s & 533mt/s speed bins. symbol parameter sstl_18 class ii units notes v oh minimum required output pull-up under ac test load v tt + 0.603 v v ol maximum required output pull-down under ac test load v tt - 0.603 v v otr output timing measurement reference level 0.5 * v ddq v1 1. the vddq of the device under test is referenced. symbol parameter sstl_18 class ii units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh(dc) and i ol(dc) are based on the conditions given in notes 1 a nd 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shi fting the desired driver operating point (see se ction 3.3) along a 21 ohm load line to define a convenient driver current for measurement. description parameter min nom max unit notes output impedance 12.6 18 23.4 ohms 1,2 pull-up and pull- down mismatch 0 4 ohms 1,2,3 output slew rate sout 1.5 - 5 v/ns 1,4,5,6,7
rev 0.2 / apr. 2004 68 hy5ps1g431(l)f hy5ps1g831(l)f 5.4 default output v-i characteristics ddr2 sdram output driver characteri stics are defined for full strength default operation as selected by the emrs1 bits a7-a9 = ?111?. the above figures show the dr iver characteristics graphically, and tables show the same data in tabular format suitabl e for input into simulation tools. 5.4.1 full strength default pu lldown driver characteristics pulldow n current (ma) voltage (v) minimum (23.4 ohms) nominal default low (18 ohms) nominal default high (18 ohms) maximum (12.6 ohms) 0.2 8.5 11.3 11.8 15.9 0.3 12.1 16.5 16.8 23.8 0.4 14.7 21.2 22.1 31.8 0.5 16.4 25.0 27.6 39.7 0.6 17.8 28.3 32.4 47.7 0.7 18.6 30.9 36.9 55.0 0.8 19.0 33.0 40.9 62.3 0.9 19.3 34.5 44.6 69.4 1.0 19.7 35.5 47.7 75.3 1.1 19.9 36.1 50.4 80.5 1.2 20.0 36.6 52.6 84.6 1.3 20.1 36.9 54.2 87.7 1.4 20.2 37.1 55.9 90.8 1.5 20.3 37.4 57.1 92.9 1.6 20.4 37.6 58.4 94.9 1.7 20.6 37.7 59.6 97.0 1.8 37.9 60.9 99.1 1.9 101.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 vout to vssq (v) 0 20 40 60 80 100 120 pulldown current (ma) maximum nominal default high nominal default low minimum
rev 0.2 / apr. 2004 69 hy5ps1g431(l)f hy5ps1g831(l)f 5.4.2 full strength default pullu p driver characteristics ddr2 default pullup char acteristics for full st rength output driver pullup current (ma) voltage (v) minimum (23.4 ohms) nominal default low (18 ohms) nominal default high (18 ohms) maximum (12.6 ohms) 0.2 -8.5 -11.1 -11.8 -15.9 0.3 -12.1 -16.0 -17.0 -23.8 0.4 -14.7 -20.3 -22.2 -31.8 0.5 -16.4 -24.0 -27.5 -39.7 0.6 -17.8 -27.2 -32.4 -47.7 0.7 -18.6 -29.8 -36.9 -55.0 0.8 -19.0 -31.9 -40.8 -62.3 0.9 -19.3 -33.4 -44.5 -69.4 1.0 -19.7 -34.6 -47.7 -75.3 1.1 -19.9 -35.5 -50.4 -80.5 1.2 -20.0 -36.2 -52.5 -84.6 1.3 -20.1 -36.8 -54.2 -87.7 1.4 -20.2 -37.2 -55.9 -90.8 1.5 -20.3 -37.7 -57.1 -92.9 1.6 -20.4 -38.0 -58.4 -94.9 1.7 -20.6 -38.4 -59.6 -97.0 1.8 -38.6 -60.8 -99.1 1.9 -101.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 vddq to vout (v) -120 -100 -80 -60 -40 -20 0 pullup current (ma) minimum nominal default low nominal default high maximum
rev 0.2 / apr. 2004 70 hy5ps1g431(l)f hy5ps1g831(l)f 5.4.3 calibrated output dr iver v-i characteristics ddr2 sdram output driver characteri stics are defined for full strength calibrated operation as selected by the procedure in ocd impedance adjustment. the below tables show the data in tabular format suitable for input into simulation tools. the nominal points repres ent a device at exactly 18 ohms. the nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohm step size with no calibration error at the exact nomina l conditions only (i.e. perfect calib ration procedure, 1.5 ohm maximum step size guaranteed by specification). real system calibration error needs to be added to these values. it must be understood that these v-i curves as represented here or in supplier ibis models need to be adjusted to a wider range as a result of any system ca libration error. since this is a system specific phe- nomena, it cannot be quantified here. the values in the calibrated tables represent just the dram portion of uncertainty while looking at one dq only. if the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figures. in such a situ- ation, the timing parameters in the specification cannot be guaranteed. it is solely up to the system applica- tion to ensure that the device is calibrated between the minimum and maximum default values at all times. if this can?t be guaranteed by the system calibration pr ocedure, re-calibration po licy, and uncertainty with dq to dq variation, then it is recommended that on ly the default values be used. the nominal maximum and minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. if calibrated at an extreme condition, the amount of variation co uld be as much as from the nominal minimum to the nominal maximum or vice versa. the driv er characteristics evaluation conditions are: nominal 25 o c (t case), vddq = 1.8 v, typical process nominal low and nominal high 25 o c (t case), vddq = 1.8 v, any process nominal minimum tbd o c (t case), vddq = 1.7 v, any process nominal maximum 0 o c (t case), vddq = 1.9 v, any process full strength calibrated pulldow n driver characteristics full strength calibrated pu llup driver characteristics calibrated pulldow n current (ma) voltage (v) nominal minimum (21 ohms) nominal low (18.75 ohms) nominal (18 ohms) nominal high (17.25 ohms) nominal maximum (1 5 ohms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 calibrated pullup current (ma) voltage (v) nominal minimum (21 ohms) nominal low (18.75 ohms) nominal (18 ohms) nominal high (17.25 ohms) nominal maximum (1 5 ohms) 0.2 -9.5 -10.7 -11.4 -11.8 -13.3 0.3 -14.3 -16.0 -16.5 -17.4 -20.0 0.4 -18.7 -21.0 -21.2 -23.0 -27.0
rev 0.2 / apr. 2004 71 hy5ps1g431(l)f hy5ps1g831(l)f 5.5 input/output capacitance parameter symbol ddr2 400 ddr2 533 ddr2 667 ddr2 800 units min max min max input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 2.0 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 pf
rev 0.2 / apr. 2004 72 hy5ps1g431(l)f hy5ps1g831(l)f 6.1 idd specifications symbol e3 ddr2 400 c4 ddr2 533 y5 ddr2 667 units x4 x8 x4 x8 x4 x8 idd0 100 100 110 110 110 110 ma idd1 110 110 120 120 130 130 ma idd2p 556677 ma idd2q 40 40 50 50 60 60 ma idd2n 45 45 55 55 65 65 ma idd3p f 25 25 30 30 35 35 ma s 778899 ma idd3n 60 60 70 70 80 80 ma idd4w 140 140 180 180 240 240 ma idd4r 130 130 170 170 230 230 ma idd5 270 270 270 270 270 270 ma idd6 normal 777777 ma low power 555555 ma idd7 240 240 300 300 330 330 ma 6. idd specifications & measurement conditions
73 rev 0.1 / feb. 2004 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 6.2 idd meauarement conditions note: 1. idd specifications are tested afte r the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are s pecified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs, udqs, and udqs . idd values must be met with all combina- tions of emrs bits 10 and 11. 5. definitions for idd low is defined as vin vilac(max) high is defined as vin vihac(min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and low ever y other data transfer (once per clock) for dq signals not incl uding masks or strobes . symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras- min(idd);cke is high, cs is high between valid commands;addres s bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge curren ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are sw itching ; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other contro l and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and addre ss bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pat- tern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev 0.2 / apr. 2004 74 hy5ps1g431(l)f hy5ps1g831(l)f for purposes of idd testing, the following parameters are to be utilized detailed idd7 the detailed timings are shown below for i dd7. changes will be required if timing parame ter changes are made to the specificati on. legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all bank interleave read operation all banks are being interleaved at minimum t rc(idd) without violating t rrd(idd) using a burst length of 4. control and address bus inputs are stable during deselects. iout = 0ma timing patterns for 4 bank devices x4/ x8 -ddr2-400 4/4/4: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d d -ddr2-400 3/3/3: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d -ddr2-533 5/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -ddr2-533 4/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d ddr2-667 ddr2-533 ddr2-400 parameter 5-5-5 6-6-6 4-4-4 5-5-5 3-3-3 4-4-4 units cl(idd) 564534tck t rcd(idd) 15 18 15 18.75 15 20 ns t rc(idd) 60 63 60 63.75 55 65 ns t rrd(idd)-x4/x8 7.5 7.5 7.5 7.5 7.5 7.5 ns t ck(idd) 3 3 3.75 3.75 5 5 ns t rasmin(idd) 45 45 45 45 40 45 ns t rasmax(idd) 70000 70000 70000 70000 70000 70000 ns t rp(idd) 15 18 15 18.75 15 20 ns t rfc(idd)-1gb 127.5 127.5 127.5 127.5 127.5 127.5 ns
rev 0.2 / apr. 2004 75 hy5ps1g431(l)f hy5ps1g831(l)f 7.1 timing parameters by speed grade parameter symbol ddr2-400 3-3-3 ddr2-533 4-4-4 ddr2-667 5-5-5 unit note min max min max min max dq output access time from ck/ck tac -600 +600 -500 +500 -450 +450 ps dqs output access time from ck/ck tdqsck -500 +500 -450 +450 -400 +400 ps ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) - min(tcl, tch) - min(tcl, tch) - ps 11,12 clock cycle time, cl=x tck 5000 8000 3750800030008000 ps 15 dq and dm input hold time tdh 400 - 350 - 300 - ps 6,7,8 dq and dm input setup time tds 400 - 350 - 300 - ps 6,7,8 control & address input pulse width for each input tipw 0.6 - 0.6 -0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - 0.35 -0.35 - tck data-out high-impedance time from ck/ck thz - tac max - tac max -tac max ps dqs low-impedance time from ck/ck tlz (dqs) tac min tac max tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz (dq) 2*tac min tac max 2*tac min tac max 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 350 - 300 - tbd ps 13 dq hold skew factor tqhs - 450 - 400 - tbd ps 12 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - thp - tqhs - ps write command to first dqs latching transition tdqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - 2 - tck 7. ac timing specifications
rev 0.2 / apr. 2004 76 hy5ps1g431(l)f hy5ps1g831(l)f parameter symbol ddr2-400 3-3-3 ddr2-533 4-4-4 ddr2-667 5-5-5 unit note min max min max min max write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 10 write preamble twpre 0.25 - 0.25 - tbd - tck address and control input hold time tih 600 - 500 -tbd - ps 5,7,9 address and control input setup time tis 600 - 500 -tbd - ps 5,7,9 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck active to precharge command tras 40* 70000 45 70000 45 70000 ns 3 active to read or write (with and without auto- precharge) delay trcd 15 - 15 - 15 - ns auto-refresh to active/auto-refresh command period trfc 127.5 - 127.5 - 127.5 - ns precharge command period trp 15 - 15 - 15 - ns active to active/auto- refresh command period trc 55* - 60 - 60 - ns active to active command period for 1kb page size(x4,x8) trrd 7.5 -7.5 -7.5 - ns 4 cas to cas command delay tccd 2 2 2 tck write recovery time twr 15 -15 -15 - ns auto precharge write recovery + precharge time tdal wr+trp - wr+trp - wr+trp - tck 14 internal write to read command delay twtr 2 -2 - 2 - tck internal read to precharge command delay trtp 7.5 7.5 7.5 ns 3 exit self refresh to a non- read command txsnr trfc + 10 trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - 2 - tck
rev 0.2 / apr. 2004 77 hy5ps1g431(l)f hy5ps1g831(l)f parameter symbol ddr2-400 3-3-3 ddr2-533 4-4-4 ddr2-667 5-5-5 unit note min max min max min max exit active power down to read command txard 2 2 2 tck 1 exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al 6 - al tck 1, 2 cke minimum pulse width (high and low pulse width) t cke 3 3 3 tck average periodic refresh interval trefi 7.8 7.8 7.8 us odt turn-on delay t aond 2 2 2222tck odt turn-on t aon tac(min) tac(max) +1 tac(min) tac(ma x)+1 tac(min) tac(ma x)+0.7 ns 16 odt turn-on(power-down mode) t aonpd tac(min) +2 2tck+ta c(max) +1 tac(min) +2 2tck+ta c(max) +1 tac(min) +2 2tck+ta c(max) +1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max) + 0.6 tac(min) tac(ma x)+ 0.6 tac(min) tac(ma x)+ 0.6 ns 17 odt turn-off (power-down mode) t aofpd tac(min) +2 2.5tck+t ac(max) +1 tac(min) +2 2.5tck+ tac(ma x)+1 tac(min) +2 2.5tck+ tac(ma x)+1 ns odt to power down entry latency tanpd 3 3 3 tck odt power down exit latency taxpd 8 8 8 tck ocd drive mode output delay toit 0 12 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+ tih tis+tck+ tih tis+tck+ tih ns 15 * : tras(min) , trc(min) specification for ddr2-400 4-4-4 is 45ns, 60ns respectively.
rev 0.2 / apr. 2004 78 hy5ps1g431(l)f hy5ps1g831(l)f 7.2 general notes, which may apply for all ac parameters 1. slew rate measurement levels a. output slew rate for falling a nd rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = -500 mv and dqs - dqs = +500mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b. input slew rate for single ended signals is measur ed from dc-level to ac-level: from vref - 125 mv to vref + 250 mv for rising edges and from vref + 125 mv and vref - 250 mv for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck - ck = +500 mv (250mv to -5 00 mv for falling egdes). c. vid is the magnitude of the difference between the input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 2. ddr2 sdram ac timing reference load the following fiture represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise repr esentation of the typical syst em environment nor a depic- tion of the actual load pr esented by a production tester. system de signers will use ibis or other simulation tools to correlate the timing referenc e load to a system environment. manu facturers will correlate to their pro- duction test conditions (generally a coaxial transmi ssion line terminated at the tester electronics). the output timing reference voltage level for single en ded signals is the crosspoint with vtt. the output tim- ing reference voltage level for different ial signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs) signal. 3. ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as shown below. 4. differential data strobe ddr2 sdram pin timings are specified for either singl e ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing ad vantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measur ed is mode depe ndent. in single vddq dut dq dqs dqs rdqs rdqs output v tt = v ddq /2 25 ? timing reference point ac timing reference load vddq dut dq dqs, dqs rdqs, rdqs output v tt = v ddq /2 25 ? test point slew rate test load
rev 0.2 / apr. 2004 79 hy5ps1g431(l)f hy5ps1g831(l)f vref. in differential mode, these timing relationships ar e measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is guarant eed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 k ohm resistor to insure proper operation. 5. ac timings are for linear signal transitions. see system derating for other signal transitions. 6. these parameters guarantee device behavior, but t hey are not necessarily test ed on each device. they may be guaranteed by device design or tester correlation. 7. all voltages referenced to vss. 8. tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal refer- ence/supply voltage levels, but the rela ted specifications and device operat ion are guaranteed for the full volt- age range specified. t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh figure -- data input (write) timing dmin dmin dmin d d d dqs t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax figure -- data output (read) timing q qq
rev 0.2 / apr. 2004 80 hy5ps1g431(l)f hy5ps1g831(l)f 7.3 specific notes for dedicated ac parameters 1. user can choose which active po wer down exit timing to use via mr s(bit 12). txard is expected to be used for fast active power down exit timing. txards is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. al = additive latency 3. this is a minimum requirement. minimum read to pr echarge timing is al + bl/2 providing the trtp and tras(min) have been satisfied. 4. a minimum of two clocks (2 * tck) is required irrespective of operating frequency 5. timings are guaranteed with command/address input slew rate of 1.0 v/ns. see system derating for other slew rate values. 6. timings are guaranteed with data, mask, and (dqs/rdqs in singled ended mode) input slew rate of 1.0 v/ns. see system derating for other slew rate values. 7. timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns . timings are guaranteed for dqs sig- nals with a differential slew rate of 2. 0 v/ns in differential strobe mode and a slew rate of 1v/ns in single ended mode. see system derating for other slew rate values. 8. tds and tdh (data setup and hold) derating tbd 9. tis and tih (input setup and hold) derating tbd 10. the maximum limit for this parame ter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnarou nd) will degrade accordingly. 11. min ( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time as pro- vided to the device (i.e. this value can be greater than the minimum specification lim its for t cl and t ch). for example, t cl and t ch are = 50% of the period, less the half period jitter ( t jit(hp )) of the clock source, and less the half period jitter due to crosstalk ( t jit(crosstalk)) into the clock traces. 12. t qh = t hp ? t qhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low ( tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers. 13. tdqsq: consists of data pin skew and output patter n effects, and p-channel to n-channel variation of the output drivers for any given cycle. 14. t dal = (nwr) + ( trp/tck): for each of the terms above, if not already an integer, round to the nex t highest integer. tck refers to the application clock period. nwr refers to the t wr parameter stored in the mrs. example: for ddr533 at t ck = 3.75 ns with t wr pr ogrammed to 4 clocks. tdal = 4 + (15 ns / 3.75 ns) clocks =4 +(4) clocks=8clocks.
81 rev 0.1 / feb. 2004 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 15. the clock frequency is allowed to change during self?refresh mode or precharge power-down mode. in case of clock frequency change during precharge power- down, a specific procedure is required as described in section 2.9. 16. odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond. 17. odt turn off time min is when the de vice starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd.
rev 0.2 / apr. 2004 82 hy5ps1g431(l)f hy5ps1g831(l)f 8. package dimensions 8.1 package dimension(x4,x8) 68ball fine pitch ball grid array outline < bottom view> 0.80 0.80 x 18 = 14.40 a1 ball mark 0.80 1 2 3 4 5 0.80 x 8 = 6.40 6 84 - .50 e f g h j k l m n p r a b c d t u v w note: all dimension un its are millimeters. 1.20 max. 0.34 +/- 0.10 < top view> 11.9 +/- 0.10 20.9 +/-0.10 a1 ball mark

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