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  april 1999 f dn 359a n n-channel logic level powertrench tm mosfet general description features absolute maximum ratings t a = 25 o c unless other wise noted symbol parameter ratings units v dss drain-source voltage 30 v v gss gate-source voltage 20 v i d maximum drain current - continuous (note 1a) 2.7 a - pulsed 15 p d maximum power dissipation (note 1a ) 0.5 w (note 1 b) 0.46 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 250 c/w r q jc thermal resistance, junction-to-case (note 1) 75 c/w fdn 359a n rev.c 2.7 a, 3 0 v. r ds(on ) = 0.046 w @ v gs = 10 v r ds(on ) = 0.060 w @ v gs = 4.5 v . very fast switching . low gate charge ( 5nc typical ). high power version of industry s tandard sot-23 package. identical pin out to sot-23 with 30% higher power handling capability. this n-channel logic level mosfet is produced using fairchild semiconductor 's advanced powertrench process that has been especially tailored to minimize on-state resistance and yet maintain superior switching performance . these devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. sot-23 supersot t m -8 soic-16 so-8 sot-223 supersot t m -6 g d s supersot -3 tm 359a d s g ? 1999 fairchild semiconductor corporation
electrical characteristics (t a = 25 o c unless otherwise noted ) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c 23 mv/ o c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a t j = 5 5c 10 a i gssf gate - body leakage, forward v gs = 20 v,v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = - 20 v , v ds = 0 v -100 na on characteristics (note ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 1 1.6 3 v d v gs(th) / d t j gate threshold voltage temp. coefficient i d = 250 a , referenced to 25 o c -4 mv/ o c r ds(on) static drain-source on-resistance v gs = 10 v, i d = 2.7 a 0.037 0.046 w t j =12 5c 0.055 0.075 v gs = 4 .5 v, i d = 2.4 a 0.049 0.06 i d(on) on-state drain current v gs = 10 v, v ds = 5 v 15 a g fs forward transconductance v ds = 5 v, i d = 2.7 a 9.5 s dynamic characteristics c iss input capacitance v ds = 10 v, v gs = 0 v, f = 1.0 mhz 480 pf c oss output capacitance 120 pf c rss reverse transfer capacitance 45 pf switching ch aracteristics (note) t d(on ) turn - on delay time v dd = 5 v, i d = 1 a, v gs = 4.5 v, r gen = 6 w 6 12 ns t r turn - on rise time 13 24 ns t d(off) turn - off delay time 15 27 ns t f turn - off fall time 4 10 ns q g total gate charge v ds = 10 v, i d = 2.7 a, v gs = 5 v 5 7 nc q gs gate-source charge 1.4 nc q gd gate-drain charge 1.6 nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current 0.42 a v sd drain-source diode forward voltage v gs = 0 v, i s = 0.42 a (note ) 0.65 1.2 v note: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. typical r q ja using the board layouts shown below on fr-4 pcb in a still air environment : scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. fdn 359a n rev.c a. 250 o c/w when mounted on a 0.0 2 in 2 pad of 2oz cu. b. 270 o c/w when mounted on a minimum pad.
fdn 359a n rev.c 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 v , drain-source voltage (v) i , drain-source current (a) v =10v gs 3.5v 3.0v 2.5v 6.0v 4.5v ds d 0 2 4 6 8 10 12 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance v = 3.0v gs 3.5v 6.0v 4.5v d 10v 4.0v r , normalized ds(on) typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = 10 v gs i = 2.7 a d r , normalized ds(on) figure 3. on-resistance variation with temperature . 1 2 3 4 5 0 3 6 9 12 v , gate to source voltage (v) i , drain current (a) gs 25c 125c v = 5v ds d t = -55c a figure 5 . transfer characteristics. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.0001 0.001 0.01 0.1 1 15 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c a 25c -55c v = 0v gs sd s 0 2 4 6 8 10 0 0.03 0.06 0.09 0.12 0.15 v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) t = 25c a i = 1.3a d t = 125c a figure 6 . body diode forward voltage varia tion with source current and temperature. figure 4 . on-resistance variation with gate-to -source voltage.
fdn 359a n rev.c 0 2 4 6 8 10 0 2 4 6 8 10 q , gate charge (nc) v , gate-source voltage (v) g gs i = 2.7a d 10v 15v v = 5v ds 0.1 0.2 0.5 1 2 5 10 20 30 50 0.01 0.03 0.1 0.3 1 3 10 30 v , drain-source voltage (v) i , drain current (a) ds d rds(on) limit v = 10v single pulse r =270c/w t = 25c gs a q ja dc 1s 10ms 100ms 10s 1ms 0.0001 0.001 0.01 0.1 1 10 100 300 0 10 20 30 40 50 single pulse time (sec) power (w) single pulse r =270 c/w t = 25c q ja a figure 10 . single pulse maximum power dissipation. 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r (t) = r(t) * r r = 270 c/w duty cycle, d = t /t 1 2 q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 figure 11 . transient thermal response curve . thermal characterization performed using the conditions described in note 1b . transient thermal response will change depending on the circuit board design. 0.1 0.2 0.5 1 2 5 10 30 20 50 100 200 500 1000 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. typical electrical characteristics
ssot-3 std unit orientation conductive embossed carrier tape customize label antistatic cover tape ssot-3 packaging configuration: figure 1.0 components leader tape 390mm minimum trailer tape 160mm minimum ssot-23 tape leader and trailer configuration: figure 2.0 cover tape carrier pin 1 tape note/comments packaging option ssot-3 std packaging information standard (no flow code) d87z packaging type reel size tnr 7?dia tnr 13 qty per reel/tube/bag 3,000 10,000 box dimension (mm) 187x107x183 343x343x64 max qty per box 9,000 20,000 weight per unit (gm) 0.0097 0.0097 weight per reel (kg) 0.1230 0.4150 human readable label human readable label sample 343mm x 342mm x 64mm intermediate box for d87z option human readable label 187mm x 107mm x 183mm intermediate box for standard option 3p 3p 3p 3p human readable label supersot tm -3 tape and reel data and package dimensions december 1998, rev. b
dimensions are in millimeter pkg type a0 b0 w d0 d1 e1 e2 f p1 p0 k0 t wc tc ssot-3 (8mm) 3.15 +/-0.10 2.77 +/-0.10 8.0 +/-0.3 1.55 +/-0.05 1.00 +/-0.125 1.75 +/-0.10 6.25 min 3.50 +/-0.05 4.0 +/-0.1 4.0 +/-0.1 1.30 +/-0.10 0.228 +/-0.013 5.2 +/-0.3 0.06 +/-02 p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 8mm 7?dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 ?0.429 7.9 ?10.9 8mm 13?dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 4.00 100 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 ?0.429 7.9 ?10.9 see detail aa dim a max 13?diameter option 7 diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed ssot-3 embossed carrier tape configuration: figure 3.0 ssot-3 reel configuration: figure 4.0 supersot tm -3 tape and reel data and package dimensions, continued december 1998, rev. b
supersot ? -3 (fs pkg code 32) 1 : 1 scale 1:1 on letter size paper di mensions shown below are in: inches [mil limeters] part weight per unit (gram): 0.0097 supersot tm -3 tape and reel data and package dimensions, continued september 1998, rev. a
trademarks acex? coolfet? crossvo l t? e 2 cmos tm f act? f act quiet series? f ast ? f as t r? g t o? hisec? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy f airchilds products are not authorized for use as critical components in life suppo r t devices or systems without the express written appro v al of f airchild semiconduc t or corpor a tion. as used herein: isoplanar? microwire? pop? power t rench? qs? quiet series? supersot?-3 supersot?-6 supersot?-8 t inylogic? 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the bod y , or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the use r . 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to a f fect its safety or e f fectiveness. product s t a tus definitions definition of t erms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconducto r . the datasheet is printed for reference information onl y . formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein to improve reliabilit y , function or design. fairchild does not assume any liability arising out of the applic a tion or use of any product or circuit described herein; neither does it convey any license under its pa tent rights, nor the rights of others.


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