View CXD2464R_1372741.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

timing generator for lcd panels description the CXD2464R is a timing signal generator for driving the lcx026, lcx016 and lcx012bl lcd panels. this chip has a built-in serial interface circuit which supports various xga, svga and vga signals, and (double speed) ntsc and pal signals through external control from a microcomputer, etc. features ? generates the lcx026/lcx016/lcx012bl drive pulse. ? supports various svga (horizontal scanning frequency: 35 to 54khz, vertical scanning frequency: 56 to 86hz) and vga (horizontal scanning frequency: 31 to 38khz, vertical scanning frequency: 59 to 75hz) signals. ? supports simple (skip scan) display of xga signals (1024 768 dots, horizontal scanning frequency: 57khz, vertical scanning frequency: 71hz or less, clock frequency: 62.5mhz or less). ? supports simple ( skip scan) display of svga signals (800 600 dots). ? supports macintosh16 signals (lcx016) ? supports pc-98 signals (640 400 dots, horizontal scanning frequency: 24 to 38khz, vertical scanning frequency: 56 to 86hz). ? supports ntsc and pal signals ? line double-speed display realized with a built-in double-speed controller (clock frequency: 33.3mhz or less) (line memory pd485505: nec) ? allows control of sample-and-hold position of cxa2112r sample-and-hold driver. ? supports up/down inversion and/or right/left inversion. ? supports line inversion and field inversion ? ac drive of lcd panels during no signal note) supported signals vary according to lcd panel. applications lcd projectors, etc. structure silicon gate cmos ic absolute maximum ratings (ta = 25c, v ss = 0v) ? supply voltage v dd v ss C 0.5 to +7.0 v ? input voltage v i v ss C 0.5 to v dd + 0.5 v ? output voltage v o v ss C 0.5 to v dd + 0.5 v ? operating temperature topr C20 to +75 c ? storage temperature tstg C55 to +150 c recommended operating conditions ? supply voltage v dd 4.5 to 5.5 v ? operating temperature topr C20 to +75 c C 1 C e98327-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2464R 64 pin lqfp (plastic) note) "macintosh" is a registered trademark of apple computer inc.. "pc-98" is a registered trademark of nec. "vga" is a registered trademark of ibm corp.. other company names and product names, etc. contained in these materials are trademarks or registered trademarks of the respective companies.
C 2 C CXD2464R block diagram 1 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 8 2 3 2 4 3 5 4 0 5 5 5 6 s e r i a l d a t a i / f 5 0 5 1 5 2 5 3 3 8 5 4 5 7 5 8 5 9 6 3 2 0 2 1 2 2 2 5 2 6 3 7 4 5 4 6 4 7 4 8 4 9 6 0 6 1 6 2 3 3 3 4 4 1 4 3 4 4 2 7 2 8 2 9 3 0 3 1 3 2 3 6 3 9 4 2 4 1 1 9 1 7 6 4 v d d v s s v s y n c h s y n c v c k v s t f l d o f r p x f r p s c t r s c l k s d a t x c l r c k i 1 c k i 2 h d r s t r r c k r s t w w c k h d n h s t h c k 1 h c k 2 b l k c l r e n b p c g c l p 1 c l p 2 p r g x v s x h s i r a c t o r a c t t e s t m o d e 3 m o d e 2 m o d e 1 r g t x r g t d w n s h p a s h p b s h p c s h p d i n v s y s t e m c l e a r v - s y n c s e p a r a t o r v - r e s e t p u l s e g e n e r a t o r v - c o n t r o l c o u n t e r h - s y n c d e t e c t o r v - p o s i t i o n c o u n t e r v p o s i t i o n d e c o d e r v - t i m i n g p u l s e g e n e r a t o r f i e l d & l i n e c o n t r o l l e r a u x . v - c o u n t e r d e c o d e r h - t i m i n g p u l s e g e n e r a t o r a d d i t i o n a l p u l s e g e n e r a t o r p u l s e e l i m i n a t o r h - p o s i t i o n d e c o d e r h - p o s i t i o n c o u n t e r p l l p h a s e c o m p a r a t o r p l l c o u n t e r p l l d e c o d e r a u x . p l l c o u n t e r a u x . p l l d e c o d e r m a s t e r c l o c k 2 3 n o t e ) c l p 2 a n d f l d o p u l s e s s h a r e t h e s a m e p i n s .
C 3 C CXD2464R pin description pin no. symbol i/o description input pin for open status 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 hsync vsync tst0 tst1 tst2 tst3 tst4 v ss 0 tst5 tst6 tst7 tst8 tst9 tst10 tst11 tst12 cki2 tst13 xclr mode3 mode2 mode1 v ss 1 v dd 0 rgt xrgt hst hck1 hck2 blk clr enb vck i i i i i o o o o o o o o o o o o horizontal sync signal input pin vertical sync signal input pin test pin (connect to gnd.) test pin (connect to v dd .) test pin (not connected.) test pin (connect to gnd.) test pin (not connected.) gnd test pin (connect to gnd.) test pin (connect to v dd .) test pin (not connected.) test pin (not connected.) test pin (not connected.) test pin (not connected.) test pin (not connected.) test pin (connect to gnd.) clock 2 input pin (for scan converter) test pin (not connected.) system clear pin (set to l: svga (vesa 72hz)) mode switching pin 3 output mode switching pin 2 output mode switching pin 1 output gnd v dd right/left inversion discrimination signal output (h output: normal, l output: reverse) right/left inversion discrimination signal output (h output: reverse, l output: normal) hst pulse output hck 1 pulse output hck 2 pulse output blk pulse output clr pulse output enb pulse output vck pulse output h
C 4 C CXD2464R pin no. i/o description input pin for open status 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 vst tst14 pcg dwn hd clp1 v ss 2 clp2/fldo prg frp xfrp shpa shpb shpc shpd inv xvs xhs iract oract rstr v ss 3 v dd 1 rck rstw wck sctr sclk sdat hdn cki1 o o o o o o o o o o o o o o o o o o o o o o i i i o i vst pulse output test pin (not connected.) pcg pulse output up/down inversion discrimination signal output (h output: down, l output: up) hd pulse output pedestal clamp pulse 1 output gnd pedestal clamp pulse 2 output/fldo pulse output precharge signal pulse output ac drive inversion timing output ac drive inversion timing output (reverse polarity of frp) external sample-and-hold driver control signal (for cxa2112r) external sample-and-hold driver control signal (for cxa2112r) external sample-and-hold driver control signal (for cxa2112r) external sample-and-hold driver control signal (for cxa2112r) external sample-and-hold driver control signal (for cxa2112r) auxiliary pulse output for cxd2449q auxiliary pulse output for cxd2449q auxiliary pulse output for scan converter auxiliary pulse output for scan converter reset read output (for high-speed line buffer) gnd v dd read clock output (for high-speed line buffer) reset write output (for high-speed line buffer) write clock output (for high-speed line buffer) chip select input pin (serial transfer block) serial clock input pin (serial transfer block) serial data input pin (serial transfer block) phase comparator pulse output clock 1 input pin * h: pull up, l: pull down symbol
C 5 C CXD2464R electrical characteristics 1. dc characteristics (v dd = 5.0 0.5v, v ss = 0v, topr = C20 to +75 c) item symbol min. typ. max. unit conditions v dd v i , vo v ih v il vt + vt C vt + C vt C v oh v ol v oh v ol i i i il i oz i dd cmos input i oh = C2ma i ol = 4ma i oh = C4ma i ol = 8ma * 3 * 5 * 6 * 8 4.5 v ss 0.7v dd 2.2 v dd C 0.8 v dd C 0.8 C10 C40 C40 5.0 0.4 C100 5.5 v dd 0.3v dd 0.8 0.4 0.4 10 C240 40 56 v v v v v v a a ma applicable pins xclr cki1, cki2 hsync vsync sctr, sclk sdat * 1 * 2 * 4 xclr * 7 at a 30pf load * 1 inv, shpa, shpb, shpc, shpd, mode1, mode2, mode3, hd, hdn, clr, enb, prg, pcg, clp1, clp2/fldo, vst, blk, frp, xfrp, vck, dwn, rgt, xrgt, iract, oract, xhs, xvs * 2 rstr, rstw, rck, wck, hck1, hck2, hst * 3 normal input pins (v in = v ss or v dd ) * 4 hsync, vsync, sclk, sdat, sctr, cki1, cki2 * 5 pins with pull-up resistors (v in = v ss ) * 6 at high impedance (v in = v ss or v dd ) * 7 shpa, shpc * 8 fclk = 62.5mhz, v dd = 5.0v supply voltage input, output voltages input voltage 1 input voltage 2 output voltage 1 output voltage 2 input leak current output leak current current consumption ttl schmitt trigger input
C 6 C CXD2464R 2. ac characteristics (v dd = 5.0 0.5v, v ss = 0v, topr = C20 to +75 c) item min. typ. max. unit conditions clock input cycle output rise time output fall time cross-point time difference output rise delay time output fall delay time hck1 duty hck2 duty t r t f d t t pr t pf t h /( t h + t l ) t l /( t h + t l ) cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf 16.0 20.0 30.0 C10 48 48 20 20 10 15 15 52 52 ns symbol cki1, 2 all outputs all outputs hck1, 2 all outputs all outputs hck1 hck2 note) the minimum value for the clock input cycle (cki1) when using the built-in double-speed controller is 30.0ns. note) during external clock input, set serial data hr to l. the pulse synchronized with the horizontal sync signal is generated by detecting the front edge of horizontal sync signal and then resetting internal pll counter. note) consider the frequency at free run (no signal). when the above characteristic specification is not satisfied at free run, operating guarantee is not performed as serial transfer. % applicable pins 3. serial transfer ac characteristics (v dd = 5.0 0.5v, vss = 0v, topr =C20 to +75 c) item min. typ. max. t s0 t s1 t h0 t h1 t w1l t w1h t w2 t w3 sctr setup time with respect to rise of sclk sdat setup time with respect to rise of sclk sctr hold time with respect to rise of sclk sdat hold time with respect to rise of sclk sclk l level pulse width sclk h level pulse width 4tns 2tns 4tns 2tns 2tns 2tns 5tns 5tns symbol t: master clock cycle (ns) 4. external clock input ac characteristics (v dd = 5.0 0.5v, vss = 0v, topr = C20 to +75 c) item min. typ. max. t s0 t h0 t wl t wh hsync setup time with respect to rise of cki1/2 hsync hold time with respect to rise of cki1/2 cki1/2 l level pulse width cki1/2 h level pulse width 2ns 6ns 6ns 6ns t/2ns t/2ns symbol t: master clock cycle (ns) xga, mac16 svga vga
C 7 C CXD2464R 9 0 % 1 0 % n o t e ) h c k 2 i s t h e r e v e r s e p h a s e o f h c k 1 . c k i 1 / 2 o u t p u t 1 0 0 % t p r 1 0 % 9 0 % t r t f t p f v d d 0 v v d d 0 v v d d 0 v o u t p u t d t 5 0 % h c k 1 h c k 2 5 0 % 5 0 % 5 0 % v d d 0 v v d d 0 v 5 0 % 5 0 % 5 0 % h c k 1 t h t l d t 5. timing definitions ac characteristics serial transfer ac characteristics external clock input ac characteristics d 7 d 9 d 1 4 s c l k s d a t 5 0 % 5 0 % 5 0 % s c t r t s 0 t h 0 t w 1 l t w 1 h t s 1 t h 1 5 0 % 5 0 % t w 2 t w 3 d 1 5 n o t e ) s e e " s e r i a l t r a n s f e r t i m i n g " f o r t h e t i m i n g r e l a t i o n s h i p b e t w e e n d 1 5 t o d 0 a n d e a c h p u l s e . t s 1 t h 1 d 0 d 8 d 1 5 c k i 2 5 0 % h s y n c ( n e g a t i v e p o l a r i t y ) t h 0 t s 0 t s 0 t h 0 5 0 % 5 0 % 5 0 % t w l t w h 5 0 % 5 0 %
C 8 C CXD2464R 6 d o t s 8 1 6 d o t s 6 d o t s 6 0 6 d o t s 1 d o t 1 d o t 8 0 4 d o t s 6 0 4 d o t s g a t e s w g a t e s w g a t e s w d i s p l a y a r e a p h o t o - s h i e l d i n g a r e a pixel arrangement the lcd panels supported by the CXD2464R are the lcx026, the lcx016 and the lcx012bl. the pixel arrangement is a square arrangement for both panels. the shaded region in the diagram is not displayed, however, for the lcx026 and the lcx016, since the CXD2464R has a built-in display area variable circuit, the display area dots varies according to the mode * 1 to match the various signal protocols. lcx026 pixel arrangement mode1 mode2 mode3 display mode number of horizontal display dots number of vertical display dots number of display dots l l l h l h h l l h l svga pal vga/ntsc pc-98 804 762 644 644 604 572 484 404 485,616 435,864 311,696 260,176 * 1 see the description of serial data specifications for details. unit: dot : don't care
C 9 C CXD2464R lcx016 pixel arrangement 4 d o t s 8 4 0 d o t s 4 d o t s 6 2 6 d o t s 1 d o t 1 d o t 8 3 2 d o t s 6 2 4 d o t s g a t e s w g a t e s w g a t e s w d i s p l a y a r e a p h o t o - s h i e l d i n g a r e a mode1 mode2 mode3 l l l l h h l l h h l l l h l h l h macintosh16 svga pal vga/ntsc pc-98 wide 832 800 762 640 640 832 624 600 572 480 400 480 519,168 480,000 435,864 307,200 256,000 399,360 unit: dot display mode number of horizontal display dots number of vertical display dots number of display dots
C 10 C CXD2464R lcx012bl pixel arrangement 5 d o t s 6 5 4 d o t s 5 d o t s 4 8 6 d o t s 1 d o t 1 d o t 6 4 4 d o t s 4 8 4 d o t s g a t e s w g a t e s w g a t e s w d i s p l a y a r e a p h o t o - s h i e l d i n g a r e a number of horizontal display dots 644 number of vertical display dots 484 number of display dots 311,696 unit: dot
C 11 C CXD2464R input signal protocol 1. horizontal sync signal a) a standard signal (hsync) should be input for the following display modes. lcx026 : svga (800 600), vga/ntsc (640 480), pc-98 (640 400), pal (762 572) lcx016 : macintosh16 (832 624), svga (800 600), vga/ntsc (640 480), pc-98 (640 400), pal (762 572), wide (832 480) lcx012b l : vga/ntsc/pal (640 480), pc-98 (640 400) however, since the CXD2464R requires a double speed signal as input during ntsc/pal double- speed display when not using the built-in double-speed controller, a simply double-speeded, 1/2 cycle, 1/2 width horizontal sync signal (hsync) should be input at that time. b) the input sync signal polarity is not fixed, and is set by the serial data (hpol). 2. vertical sync signal a) a sync-separated, normal-speed vsync should be input as the vertical sync signal. b) the input sync signal polarity is not fixed, and is set by the serial data (vpol). c) the phase relationship between hsync and vsync is specified as follows for the CXD2464R. (1) svga, vga, pc-98 (lcx026)/macintosh16, svga, vga, pc-98 (lcx016)/vga, pc-98 (lcx012bl) (2) double-speed ntsc (lcx026/lcx016/lcx012bl) (3) double-speed pal (lcx026/lcx016/lcx012bl) h s y n c v s y n c s y n c s i g n a l p h a s e r e f e r e n c e d o u b l e - s p e e d h s y n c v s y n c s y n c s i g n a l p h a s e r e f e r e n c e v s y n c d o u b l e - s p e e d h s y n c s y n c s i g n a l p h a s e r e f e r e n c e
C 12 C CXD2464R (4) ntsc (lcx026/lcx016/lcx012bl) o d d f i e l d e v e n f i e l d v s y n c h s y n c s y n c s i g n a l p h a s e r e f e r e n c e (5) pal (lcx026/lcx016/lcx012bl) o d d f i e l d e v e n f i e l d v s y n c h s y n c s y n c s i g n a l p h a s e r e f e r e n c e note) (2) and (3) show the timing when supporting input of double-speed signals (4) and (5) show the timing when using the built-in double-speed controller (CXD2464R) and a line memory ( pd485505: nec)
C 13 C CXD2464R description of operation sync signal input the hsync and vsync input pins support separate sync only. when using a composite sync input, use a separate ic for sync separation, etc. clock input (1) cki1 pin cki1 is the clock input pin from an external pll ic. a 1/n frequency divider output for pll ic is output from the hdn pin. hdn polarity at this time is set by serial data hdnpol. (2) cki2 pin cki2 is a clock input pin when using a scan converter that operates with synchronous input signals and asynchronous clock in the system. since two types of clocks are input in this case, the circuit that basically operates with the respective clocks of cki1 and cki2 is asynchronous. for details, refer to the explanation of pulse setting for the scan converter in this specification (starting on page 37). ac driving of lcd panels for no signal the following measures have been adopted to allow ac driving of lcd panels even when there is no signal. horizontal direction pulse the pll is set to free running status. therefore, the frequency of the horizontal direction pulse is dependent on the pll free running frequency. vertical direction pulse the number of lines is counted by an internal counter (aux-vd counter) and the vertical direction pulses (vst, frp) are output at a specified cycle. for the CXD2464R, no signal (free running) status is judged if there is no vsync input for longer than the following periods (free running detection timing). mode double-speed ntsc double-speed pal other v cycle for no signal 263h 313h 650h free running detection 468h 900h note) the double-speed ntsc and pal modes are the modes when using the built-in double-speed controller.
C 14 C CXD2464R xclr pin the CXD2464R should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits. serial transfer operation 1. control method the CXD2464R operation timing is controlled by serial data. the control data is comprised of an 8-bit address and 8-bit data, and the individual data is loaded at the rise of sclk. this load operation starts from the fall of sctr and is completed at the next rise of sctr. serial transfer timing s c t r s c l k s d a t a d d r e s s d a t a d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 d 1 4 d 1 5
C 15 C CXD2464R 2. control data when using the CXD2464R, set the control data corresponding to each signal source according to the formats in the table below. d1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 pllp7 hp7 vp7 vgav ird7 iru7 orrs3 orp7 ord7 oru7 hprs7 pllp6 hp6 vp6 hr ird6 iru6 orrs2 orp6 ord6 oru6 hprs6 pllp5 hp5 vp5 cktst0 vpol mode021 dwn ird5 iru5 orrs1 orp5 ord5 oru5 hprs5 pllp4 hp4 vp4 pcgp4 prgp4 inv fld hpol mbkb modeb rgt sllap ird4 iru4 orrs0 orp4 ord4 oru4 hprs4 pllp3 hp3 vp3 hstp3 pcgp3 prgp3 shp3 frp1 hdnpol mbka modea hst ird3 iru3 orp3 ord3 oru3 hprs3 pllp10 pllp2 hp2 vp2 hstp2 pcgp2 prgp2 shp2 frp0 clppol mbk2 mode3 pcg ird10 ird2 iru10 iru2 orp10 orp2 ord10 ord2 oru10 oru2 hprs10 hprs2 pllp9 pllp1 hp1 vp1 hstp1 pcgp1 prgp1 clpp1 shp1 cktst1 pcgpol mbk1 mode2 dsp ird9 ird1 iru9 iru1 orp9 orp1 ord9 ord1 oru9 oru1 hprs9 hprs1 pllp8 pllp0 hp0 vp0 hstp0 pcgp0 prgp0 clpp0 shp0 rck prgpol mbk0 mode1 pc98 ird8 ird0 iru8 iru0 orp8 orp0 ord8 ord0 oru8 oru0 hprs8 hprs0 pre d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 note) pllp0, hp0, vp0, hstp0, pcgp0, prgp0, clpp0, shp0, ird0, iru0, orrs0, orp0, ord0, oru0, hprs0: lsb address data function settings other than those above are invalid (a) pll frequency division ratio (1/n) (b) h-position (c) v-position (d) hst-position (e) pcg-position (e) prg-position (f) clp-position (g) s/h control for cxd2112r (h) mode settings (i) iract fall position (i) iract rise position (j) oract reset cycle oract frequency (k) oract fall position (k) oract rise position (l) h position counter reset position (m) preset
C 16 C CXD2464R each control data is described in detail below. (a) to (m) (a) pllp10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 these bits set the frequency division ratio (master clock) of the internal 1/n frequency divider for the pll. the data is 11 bits and the frequency division ratio can be set up to 2048. the actual frequency division ratio should be set as follows. number of clk for the horizontal period C 2 = actual number of dots set examples of settings for major modes are shown below. examples using the lcx026 1) svga (800 600) pllp setting value = 1040 (horizontal period) C 2 ? 1038 (hllllllhhhl: lsb) 2) vga (640 480) pllp setting value = 832 (horizontal period) C 2 ? 830 (lhhllhhhhhl: lsb) 3) pc-98 (640 400) pllp setting value = 848 (horizontal period) C 2 ? 846 (lhhlhllhhhl: lsb) 4) ntsc (640 480) pllp setting value = 1560 (horizontal period) C 2 ? 1558 (hhllllhlhhl: lsb) 5) pal (762 572) pllp setting value = 1880 (horizontal period) C 2 ? 1878 (hhhlhlhlhhl: lsb) pllp 10 9 8 7 6 5 4 3 2 1 0 setting data h l l l l l l h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data l h h l l h h h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data l h h l h l l h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data h h l l l l h l h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data h h h l h l h l h h l * vesa vga72 * vesa svga72
C 17 C CXD2464R examples using the lcx016 1) macintosh16 (832 624) pllp setting value = 1152 (horizontal period) C 2 ? 1150 (hlllhhhhhhl: lsb) 2) svga (800 600) pllp setting value = 1040 (horizontal period) C 2 ? 1038 (hllllllhhhl: lsb) 3) vga (640 480) pllp setting value = 832 (horizontal period) C 2 ? 830 (lhhllhhhhhl: lsb) 4) pc-98 (640 400) pllp setting value = 848 (horizontal period) C 2 ? 846 (lhhlhllhhhl: lsb) 5) ntsc wide (832 480) pllp setting value = 1014 (horizontal period) C 2 ? 1012 (lhhhhhhlhll: lsb) 6) ntsc (640 480) pllp setting value = 1560 (horizontal period) C 2 ? 1558 (hhllllhlhhl: lsb) 7) pal (762 572) pllp setting value = 1880 (horizontal period) C 2 ? 1878 (hhhlhlhlhhl: lsb) pllp 10 9 8 7 6 5 4 3 2 1 0 setting data h l l l h h h h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data h l l l l l l h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data l h h l l h h h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data l h h l h l l h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data l h h h h h h l h l l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data h h l l l l h l h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data h h h l h l h l h h l * vesa svga72 * vesa vga72
C 18 C CXD2464R examples using the lcx012bl 1) vga (640 480) pllp setting value = 896 (horizontal period) C 2 ? 894 (lhhlhhhhhhl: lsb) 2) pc-98 (640 400) pllp setting value = 848 (horizontal period) C 2 ? 846 (lhhlhllhhhl: lsb) 3) ntsc, pal (640 480) pllp setting value = 1560 (horizontal period) C 2 ? 1558 (hhllllhlhhl: lsb) pllp 10 9 8 7 6 5 4 3 2 1 0 setting data l h h l h h h h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data l h h l h l l h h h l pllp 10 9 8 7 6 5 4 3 2 1 0 setting data h h l l l l h l h h l * vesa vga72
C 19 C CXD2464R (b) hp7, 6, 5, 4, 3, 2, 1, 0 these bits set the horizontal display start position. the minimum adjustment width is 1 dot, and adjustment of up to 256 clk with 8 bits is possible using the front edge of hsync as the reference. t h p h s y n c i m a g e d i s p l a y p e r i o d t h p : t i m i n g f r o m t h e e d g e o f h s y n c t o t h e s t a r t o f i m a g e d i s p l a y minimum and maximum thp setting values for each mode lcx026 lcx016 lcx012bl hp 7 6 5 4 3 2 1 0 800 600 762 572 640 480 640 400 min. max. h l l l l l l l l 416 clk 370 clk h h h h h h h 161 clk 115 clk hp 7 6 5 4 3 2 1 0 832 624 800 600 762 572 640 480 640 400 832 480 min. max. h l l l l l l l l 440 clk 410 clk 364 clk h h h h h h h 185 clk 155 clk 109 clk hp 7 6 5 4 3 2 1 0 644 484 min. max. h l l l l l l l l 367 clk h h h h h h h 112 clk
C 20 C CXD2464R (c) vp7, 6, 5, 4, 3, 2, 1, 0 these bits set the vertical display start position. the minimum adjustment width is 1h, and adjustment of up to 256h with 8 bits is possible using the following references. progressive signal input ? front edge of vsync interlace signal input ? first 1h of vsync here, the interlace signal input indicates ntsc or pal display (using the built-in double-speed controller). in this case, the image is raised or lowered by two lines on the panel side with respect to a 1h adjustment. (1) progressive minimum and maximum tvp setting values lcx026 lcx016/lcx012bl t v p v s y n c h s y n c i m a g e d i s p l a y p e r i o d t v p : t i m i n g f r o m t h e e d g e o f v s y n c t o t h e s t a r t o f i m a g e d i s p l a y vp 7 6 5 4 3 2 1 0 min. max. l h h h h h h h h 264h l l l l l l l 9h vp 7 6 5 4 3 2 1 0 min. max. l h h h h h h h h 262h l l l l l l l 7h
C 21 C CXD2464R (2) interlace (a) ntsc t v p v s y n c h s y n c ( o d d f i e l d ) h s y n c ( e v e n f i e l d ) i m a g e d i s p l a y p e r i o d t v p : t i m i n g f r o m t h e e d g e o f v s y n c t o t h e s t a r t o f i m a g e d i s p l a y vp 7 6 5 4 3 2 1 0 min. max. l h h h h h h h h 260.5h l l l l l l l 5.5h minimum and maximum tvp setting values lcx026 vp 7 6 5 4 3 2 1 0 min. max. l h h h h h h h h 259.5h l l l l l l l 4.5h lcx016/lcx012bl vp 7 6 5 4 3 2 1 0 min. max. l h h h h h h h h 259.5h l l l l l l l 4.5h lcx016/lcx012bl (b) pal t v p v s y n c h s y n c ( o d d f i e l d ) h s y n c ( e v e n f i e l d ) i m a g e d i s p l a y p e r i o d t v p : t i m i n g f r o m t h e e d g e o f v s y n c t o t h e s t a r t o f i m a g e d i s p l a y vp 7 6 5 4 3 2 1 0 min. max. l h h h h h h h h 260.5h l l l l l l l 5.5h minimum and maximum tvp setting values lcx026
C 22 C CXD2464R (d) hstp3, 2, 1, 0 these bits control the hst phase relative to hck, and correct the delay between hst and hck that occurs within the panel. the phase of 12 position (in 1 clk increments) can be controlled with 4 bits. h c k 1 h s t : l l l l 0 h s t p 3 , 2 , 1 , 0 : l l l h 1 1 c l k ( 1 1 c l k ) h c k 1 h s t : h l h l 1 0 h s t p 3 , 2 , 1 , 0 : h l h h , h h x x > 1 0 1 1 c l k ( 1 1 1 c l k ) 1 0 c l k ( 1 0 1 c l k ) notes) 1. when setting to the lcx012bl mode, the phases of hst and hck1, 2 are as shown above regardless of rgt. 2. in the lcx026 and lcx016 modes, when set to the svga mode and rgt: l or to a mode other than the svga mode and rgt: h, the phase relationship between hst and hck1, 2 is as shown above. 3. the polarity of hck1, 2 is reversed when set to panel mode switching, panel display area switching and right/left inversion modes other than as described in notes 1 and 2 above.
C 23 C CXD2464R (e) pcgp4, 3, 2, 1, 0/prgp4, 3, 2, 1, 0 these bits set the width of pcg and prg pulses to 32 positions with 5 bits in 4 clk units. the rise positions of pcg and prg pulses are determined by serial data hp (see (b)), modes 1, 2 and 3 (see (h-7)) and pcg (see (h-12)) position. the pulse widths of pcg and prg can be arbitrarily set within the above range using the rise positions for the reference. when setting pcgp4, 3, 2, 1, 0 = n (decimal), the panel width at that time is calculated by: (n + 1) 4 (clk) when setting pcgp4 to 0, the pulse fall position changes relative to the pulse rise position. this applies similarly to prgp4 to 0. for example, when setting pcgp4, 3, 2, 1, 0: hllhh = 19 (decimal), the panel width becomes: (19 + 1) 4 = 80 clk since the optimum values for pulse width of pcg and prg pulses vary according to the lcd panel used, set while also referring to the panel specifications. example) mck: 50mhz (1 clk = 20ns) p c g : l h h h l ( l s b ) = 1 4 ( d e c i m a l ) p r g : h l h l l ( l s b ) = 2 0 ( d e c i m a l ) p c g p 4 , 3 , 2 , 1 , 0 p r g p 4 , 3 , 2 , 1 , 0 8 4 c l k = 1 . 6 8 s 6 0 c l k = 1 . 2 s notes) pcgpol and prgpol are both assumed to be "h". polarity is reversed when pcgpol and prgpol are each "l".
C 24 C CXD2464R (f) clpp1, 0 these bits adjust the clamp pulse output timing. the timing can be set to 4 positions with 2 bits. t c l p 1 w c l p 1 c l p 1 t c l p 2 w c l p 2 c l p 2 h s t t h e c e n t e r s o f t h e c l p 1 a n d c l p 2 p u l s e s m a t c h . xga (lcx026), macintosh16 (lcx016) clpp1 clpp0 tclp1 tclp2 wclp1 wclp2 l l 46 clk 23 clk 69 clk 115 clk l h h h l h 69 clk 92 clk 115 clk 46 clk 69 clk 92 clk 69 clk 69 clk 69 clk 115 clk 115 clk 115 clk hp limit (clp2) hhhhhhhh (255): lsb hhhhllhh (243): lsb hhlhhhll (220): lsb hp limit (clp1) hhhhhhhh (255): lsb hhhhllhh (243): lsb note) when clpp1, 0 is set to hl or hh, the pulses may not be output due to the internal logic depending on the hp serial data setting value. hp limit is the upper limit for the serial data hp that allows output of clp1 and 2 pulses when setting each mode. hstp is llhh (lsb) (serial data). svga (lcx026, lcx016) clpp1 clpp0 tclp1 tclp2 wclp1 wclp2 l l 38 clk 19 clk 58 clk 96 clk l h h h l h 57 clk 76 clk 95 clk 38 clk 57 clk 76 clk 58 clk 58 clk 58 clk 96 clk 96 clk 96 clk hp limit (clp2) hhhhhhhh (255): lsb hhhhlhhl (246): lsb hhhlllhh (227): lsb hp limit (clp1) hhhhhhhh (255): lsb hhhhlhhl (246): lsb vga/ntsc, pal, pc-98 (lcx026, lcx012bl), vga/ntsc, pal, pc-98, wide (lcx016) clpp1 clpp0 tclp1 tclp2 wclp1 wclp2 l l 26 clk 13 clk 38 clk 64 clk l h h h l h 39 clk 52 clk 65 clk 26 clk 39 clk 52 clk 38 clk 38 clk 38 clk 64 clk 64 clk 64 clk hp limit (clp2) hhhhhhhh (255): lsb hhhhhlll (248): lsb hhhlhlhh (235): lsb hp limit (clp1) hhhhhhhh (255): lsb hhhhhlll (248): lsb
C 25 C CXD2464R (g) inv, shp3, 2, 1, 0 this ic allows control of the sample-and-hold position of the cxa2112r sample-and-hold driver by setting serial data in place of not having a sample-and-hold pulse output. inv set by serial data is output from the inv pin (pin 49). connect this inv to inv_cnt (pin 52) of the cxa2112r. in addition, data set with shp3, 2, 1, 0 is reflected in the shpa, shpb, shpc and shpd output pins (pins 45, 46, 47 and 48) as shown in the table below. setting shp3, 2, 1, 0 llll lllh llhl llhh lhll lhlh lhhl lhhh output shpa l h z z l l z z shpb l h l h l h l h shpc l l l l h h h h shpd l l l l h h h h setting shp3, 2, 1, 0 hlll hllh hlhl hlhh hhll hhlh hhhl hhhh output shpa l h z z l l z z shpb l h l h l h l h shpc z z z z z z z z shpd l l l l h h h h * z: high impedance state the sample-and-hold position of the cxa2112r can be set by connecting shpa to shpd as shown in the diagram below. refer to the specification of the cxa2112r for further details. c x d 2 4 6 4 r s h p a ( p i n 4 5 ) ( s h p c ( p i n 4 7 ) ) s h p b ( p i n 4 6 ) ( s h p d ( p i n 4 8 ) ) 4 5 ( 4 7 ) 4 6 ( 4 8 ) 1 ( 2 ) p o s _ c n t 1 ( p i n 1 ) ( p o s _ c n t 2 ( p i n 2 ) ) c x a 2 1 1 2 r
C 26 C CXD2464R (h) mode settings mode mode description fld frp1 frp0 cktest0, 1 rck vpol hpol hdnpol clppol pcgpol prgpol mbkb mbka mbk2 mbk1 mbk0 mode021 modeb modea mode3 mode2 mode1 vgav hr dwn rgt hst pcg dsp pc98 h-1 h-2 h-3 h-4 h-5 h-6 h-7 h-8 h-9 h-10 h-11 h-12 h-13 h-14 fld pulse output switching (h: fld, l: clp2) frp polarity inversion cycle switching (h: 1f, l: 2f) frp polarity inversion cycle switching (h: 1h, l: f) test setting (set to h.) clock output setting (h: clk stop, l: clk out) input vsync polarity switching (h: positive, l: negative) input hsync polarity switching (h: positive, l: negative) hdn pulse output polarity switching (h: positive, l: negative) clp pulse output polarity switching (h: positive, l: negative) pcg pulse output polarity switching (h: positive, l: negative) prg pulse output polarity switching (h: positive, l: negative) skip scan interval switching skip scan (frp) timing switching (h: main, l: sub) skip scan mode switching (h/h: no skip scan, h/l: 6, 4 skip scan, l/h: 5, 4 skip scan, l/l: 6, 7 skip scan) test setting (set to l.) panel mode switching (h/h: lcx026 mode, l/h: lcx016 mode, l/l: lcx012bl mode) panel display area switching input signal attribute switching (h: data, l: av) external reset switching (h: no reset, l: reset) up/down inversion discrimination signal input (h: down, l: up) right/left inversion discrimination signal input (h: normal, l: reverse) hst width switching (h: 12 dots wide, l: 24 dots wide) pcg width switching (h: main, l: sub) double-speed mode switching (h: normal, l: double-speed) pc-98 (400 line) display switching (h: no display, l: display)
C 27 C CXD2464R (h-1) fld this bit switches the outputs of field identification pulse fldo and clamp pulse clp2. the fldo pulse when fld is h and the clp2 pulse when fld is l are output from pin 41 (clp2/fldo). refer to the timing chart for details. (h-2) frp1, 0 these bits are the data for switching the lcd ac conversion signal cycle. frp1, 0 should normally be set to hh. f r p 1 , 0 : h h f r p 1 , 0 : l h f r p 1 , 0 : h l f r p 1 , 0 : l l 1 f 1 h ( 1 f / 1 h i n v e r s i o n ) ( 2 f / 1 h i n v e r s i o n ) ( 1 f i n v e r s i o n ) ( 2 f i n v e r s i o n ) (h-3) cktst0, 1 these bits set testing. cktst0, 1 should normally be set to h. note) if these bits are set to l, pulses may not be output normally. (h-4) rck this bit sets testing. rck should normally be set to h.
C 28 C CXD2464R (h-5) vpol, hpol, hdnpol, clppol, pcgpol, prgpol these bits are the data for switching input or output signal polarity. set these bits according to the explanation below. (1) vpol and hpol are the data for switching the input vertical and horizontal sync signal polarity. since signal processing is performed with the sync signal polarity fixed to positive by the internal logic, the data must be switched according to the polarity of the input sync signal. therefore, individually set vpol and hpol to h when the polarity of the input sync signal is positive, and to l when the polarity is negative. (2) the hdn pulse (h return pulse) is the 1/n frequency divider output pulse for the pll ic. the width of the hdn pulse is calculated according to the setting of pllp10 to 0 for the value of frequency division n, and that value is n/2. hdnpol is the data for setting the output polarity of this hdn pulse, and the relationship between its setting and pulse polarity is shown in the diagram below. h s y n c h d n h p o l : l n / 2 c l k h d n p o l : l h d n p o l : h n c l k (3) clppol sets the output polarity of clamp pulses clp1 and clp2. when clppol is h, both clp1 and clp2 have positive polarity, and when clppol is l, both clp1 and clp2 have negative polarity. see the timing charts for details. (4) pcgpol and prgpol set the output polarity for the pcg and prg pulses, respectively. when pcgpol is h, the polarity of the pcg pulse is positive, and when pcgpol is l, polarity is negative. this applies similarly to the relationship between prgpol and prg pulses. see the timing charts for details.
C 29 C CXD2464R (h-6) mbk2, 1, 0, b, a these bits set the skip-scan-related mode timings. these timings enable xga (scanning line conversion from 768 to 598 vertical lines by 5, 4 skip scan) display for the lcx026, xga (scanning line conversion from 768 to 615 vertical lines by 6, 4 skip scan) display for the lcx016, and svga (scanning line conversion from 600 to 480 vertical lines by 6, 4 skip scan) and double-speed pal (scanning line conversion from 575 to 480 vertical lines by 6, 7 skip scan) display for the lcx012bl. however, for xga and svga display, the horizontal direction is supported by external signal processing. note) supported input signals (xga, svga) differ for each panel. use the xga skip scan display of the lcx026 in the xga mode, the xga skip scan display of the lcx016 in the macintosh16 mode, and the svga skip scan display of the lcx012bl in the vga or svga mode. at that time, the display area other than the image display area is written by the blanking level of the video signal according to the mode. setting during lcx026 panel driving when the input signal is xga (1024 768), set the operation of the CXD2464R to the xga mode of the lcx026, and set the serial data hstp to hstp3/2/1/0: hllh (lsb). see the timing charts for details. (1) mbk2 this bit sets the frp-related skip scan timing. 9 c l k h s t h c k 1 h c k 2 h s t p 3 , 2 , 1 , 0 : h l l h ( l s b ) v s t v c k f r p h s t / p c g e n b m b k 2 : h ( m a i n ) m b k 2 : l ( s u b )
C 30 C CXD2464R note) mbk2: h and mbkb, a: ll. mbk1, 0 skip scan mode ll lh 5, 4 skip scan hl 6, 4 skip scan hh no skip scan 6, 7 skip scan (2) mbk1, 0 these bits set the skip scan mode. select the xga, svga or double-speed pal skip scan mode. v s t v c k f r p h s t / p c g e n b 1 2 3 4 5 6 7 1 2 3 4 5 6 7 o d d / e v e n f i e l d v s t v c k f r p h s t / p c g e n b 1 2 3 4 5 d i s p l a y s t a r t t i m i n g m b k 1 , 0 : l h ( 0 2 6 x g a 5 , 4 s k i p s c a n ) d i s p l a y s t a r t t i m i n g d i s p l a y s t a r t t i m i n g m b k 1 , 0 : h l ( 0 1 6 x g a , 0 1 2 b l s v g a 6 , 4 s k i p s c a n ) m b k 1 , 0 : l l ( 0 1 2 b l d o u b l e - s p e e d , p a l 6 , 7 s k i p s c a n )
C 31 C CXD2464R (3) mbk b, a these bits change skip scan timing for each field (interlace) or for each v cycle (progressive). these bits determine the skip scan timing for the next 1v period using the skip scan timing when the field identification pulse (fldo) is l as the reference. the optimal skip scan position can be set by setting a skip scan interval of 0 to 3h. although the charts below show 5, 4 skip scan timing, but the timing is the same for 6, 4 and 6, 7 skip scan. v s t v c k f r p h s t / p c g e n b 1 2 3 4 5 6 7 f l d o l v s t v c k f r p h s t / p c g e n b f l d o 1 2 3 4 5 6 7 h m b k b , a : l l 1 2 3 4 5 6 7 8 h m b k b , a : l h v s t v c k f r p h s t / p c g e n b f l d o 1 2 3 4 5 6 7 8 h m b k b , a : h l 1 2 3 4 5 6 7 8 h m b k b , a : h h d i s p l a y s t a r t t i m i n g d i s p l a y s t a r t t i m i n g d i s p l a y s t a r t t i m i n g d i s p l a y s t a r t t i m i n g d i s p l a y s t a r t t i m i n g r e f e r e n c e t i m i n g note) mbk2: h, mbk1, 0: lh
C 32 C CXD2464R mode 1 2 3 xga (804 604) svga (804 604) pal (762 572) vga/ntsc (644 484) pc-98 (644 404) l l l l h l l h h l l h l h l mode 1 2 3 macintosh16 (832 624) svga (800 600) pal (762 572) vga/ntsc (640 480) pc-98 (640 400) wide (832 480) l l l l h h l l h h l l l h l h l h when using the lcx016 mode 1 2 3 vga/ntsc (644 484) l h h * also supports pal display. mode b, a panel ll lh lcx016 hh lcx026 lcx012bl (h-7) mode021 these bits are a test mode. mode021 should normally be set to l. (1) mode b, a these bits switch each timing according to the mode. operation shifts to lcx026 mode when mbkb, a is hh, to lcx016 mode when lh, and to lcx012bl mode when ll. be sure to set this data when using the CXD2464R in these modes. (2) mode3, 2, 1 these bits switch the panel display area. however, since the panel display area cannot be switched for the lcx012bl, vga/ntsc mode should be set when using the lcx012bl. in addition, set to the xga mode during xga skip scan display using the lcx026, and to the macintosh16 mode during xga skip scan display using the lcx016. when using the lcx026 * xga skip scan display when using the lcx012bl
C 33 C CXD2464R (h-8) vgav this bit switches the CXD2464R according to the attributes of the input signal. the CXD2464R supports input of data signals when vgav is set to h, and input of interlaced video signals when set to l. only the double- speed ntsc, pal and wide (lcx016 only) modes are supported, when using the built-in double-speed controller. set vgav to l during input of these signals. (h-9) hr this bit controls the input horizontal sync signal (hsync)-based pll counter reset operation, and supports external clock input. (reset operation is allowed when hr is l.) resetting the internal pll counter at the front edge of the input hsync generates an output pulse synchronized to hsync. this function should be used with systems which do not use a pll. in addition, set the pll frequency division ratio (1/n) resulting from the use of this mode according to: number of clk for the horizontal period C 2 = actual number of clk set (see page 16). i n p u t h o r i z o n t a l s y n c s i g n a l ( h s y n c ) r e s e t t h e i n t e r n a l p l l c o u n t e r a t t h i s t i m i n g . h p o l : h note) since h-position specifications described in this data sheet are not satisfied due to the configuration of the internal logic, the screen center must be adjusted each time. (h-10) dwn, rgt these bits set the up/down and right/left inversion discrimination data. these settings allow display to be performed in accordance with each display system. see the timing charts for details. (h-11) hst this bit adjusts the hst width. hst should normally be set to h.
C 34 C CXD2464R (h-12) pcg this bit adjusts the rise (fall) position (pulse starting timing) of the pcg pulse using vck as a reference. this is linked with prg and frp. timing at that time. pcg should normally be set to h. t m v c k p r g p c g f r p mode tm tm xga, macintosh16 svga pal vga/ntsc pc-98 wide 57 clk 48 clk 32 clk 46 clk 38 clk 26 clk pcg = h pcg = l note) pcgpol: h, prgpol: h tm value for each mode
C 35 C CXD2464R (h-13) dsp this bit performs the double-speed display mode switching settings. operation shifts to double-speed display mode when dsp is l. however, dsp should be set h for other modes. this function is only supported when the built-in double-speed controller is used. this controller is designed to use the pd485505 (nec/high-speed line buffer) as the system line memory ic, and generates the double- speed processing pulses rstw (reset write), wck (write clock), rstr (reset read) and rck (read clock). the operation of the pd485505 is as follows. write operation is started at the rstw timing, and this memory data is read at double speed at the rstr timing which is delayed by 1/2h from the rstw timing. labeling the master clock frequency (mck) as f, the write and read clock frequencies at this time are expressed as f/2 and f, respectively. however, the master clock should have a frequency of 33.3mhz or less when using this mode. see the ic specifications for a detailed description of pd485505 operation. note) see the timing charts for details. a d c l i n e m e m . p d 4 8 5 5 0 5 c x d 2 4 6 4 r d a c r s t r r c k m c k : f r s t w w c k r , g , b i n h s y n c v s y n c h s y n c r s t w w c k r s t r r c k f / 2 f h s y n c r s t w r s t r d o u b l e - s p e e d d i s p l a y s y s t e m d i a g r a m d o u b l e - s p e e d d i s p l a y t i m i n g
C 36 C CXD2464R (h-14) pc-98 this bit switches the pc-98 (400-vertical line) display mode. operation shifts to pc-98 mode when pc98 is l. however, since this function supports the lcx012bl, pc98 is normally (modes other than lcx012bl/pc-98 mode) set h. this function is used to display pc-98 (640 400) images in the display area of the lcx012bl (644 484). the upper and lower 42 lines outside of the display area are black display during this mode. the vertical high-speed scanning and precharge black writing methods have been introduced as methods for writing these black areas. vck is shifted to double-speed operation to realize vertical double-speed transfer and enable black display within the limited v blanking. also, the black level during this period is determined by the psig (lcx012bl) level and written at the pcg (lcx012bl) timing. at this time, hst is masked, limiting the video signal input. 4 2 ( a ) 4 0 0 ( b ) 4 2 ( c ) 4 8 4 6 4 4 e f f e c t i v e d i s p l a y a r e a ( 4 0 0 l i n e s ) u n i t : d o t v s t f r p v c k p c g h s t ( a ) ( c ) a a a a a a a a a a a a a a a 2 - l i n e i n v e r s i o n ( f r p ) e f f e c t i v e d i s p l a y a r e a ( b ) : b l a c k f r a m e d i s p l a y a r e a s lcx012bl panel pc-98/400-line display timing note) frp is inverted every two lines during double-speed scanning. see the timing charts for details.
C 37 C CXD2464R (i) to (l) scan converter pulse settings the following settings are not required when not using the scan converter or digital signal driver cxd2449q. (i-1) sllap sllap is used when converting the number of pixels using the scan converter, when the clock differs between input signals and output signals, etc. sllap should be l during the normal operating mode. sllap should be h when operating with cki1 synchronized only with input signals of the internal circuits of the ic, serial interface, pll counter and phase comparator, and other components are operated with cki2. (i-2) ird10 to 0, iru10 to 0 iract is an output pulse in sync with input hsync at an arbitrary position and width. set the pulse fall position for ird10 (msb) to ird0 (lsb), and the pulse rise position for iru10 (msb) to iru0 (lsb). the setting range is from 0 to n C 1. in addition, do not set ird and iru to the same value. h s y n c i r a c t 1 2 8 c l k i r d : l l l l l l l l l l l ( l s b ) , i r u : l l l h l l l l l l l ( l s b ) , h r : h (j-1) orrs3, 2, 1, 0 when sllap is set l, oract pulse is completely identical to iract pulse when serial data sllap is l, and when sllap is set h, this is generated from a dedicated counter (loop counter similar to the pll counter, and referred to as an or counter) that operates by cki2, an asynchronous clock that is independent from the input signal. in addition, pulses for lcd panel driving are also generated at this time based on the output of this counter, enabling the lcd panel to be driven with a horizontal cycle and clock that differ from the input signal. the above or counter applies a reset with vsync and a fixed cycle input hsync in order to be in sync with input hsync. orrs3, 2, 1, 0 perform this reset by hsync every h seconds or a cycle is set. when orrs3, 2, 1, 0 (lsb) are set to llll, reset is applied for 16h cycles, and at the set number of cycles when set to other settings. reset can be applied from 1h to a maximum of 16h cycles. v s y n c i r a c t 1 h o r a c t s l l a p : h , o r r s : l h l l ( l s b ) t i m i n g b y w h i c h r e s e t i s a p p l i e d t o o r c o u n t e r
C 38 C CXD2464R (j-2) orp10 to 0 orp sets the number of frequency divisions of the or counter described above. similar to pllp10 to 0, up to 2048 divisions can be set with 11 bits of data. set the actual number of frequency divisions m as follows: m C 2 = actual number of clk set (k) ord10 to 0, oru10 to 0 oract pulses can be output at an arbitrary position and width of the or counter operated by clock cki2 that is asynchronous with input hsync when serial data sllap is set h. set the pulse fall position for ord10 (msb) to ord0 (lsb), and the pulse rise position for oru10 (msb) to oru0 (lsb). the setting range is from 0 to m C 1. in addition, similar to iract, do not set ord and oru to the same value. as previously mentioned, when serial data sllap is l, oract pulses are identical to iract pulses regardless of the settings for serial data oru and ord. (l) hprs10 to 0 although the counter (h position counter) that generates horizontal display pulses is normally reset based on the pll counter, when serial data sllap is h, reset can be applied to the horizontal direction display counter at an arbitrary position according to an 11-bit setting hprs based on the or counter. consequently, the horizontal display starting position can be varied over a wide range. setting of serial data hp7 to 0 becomes valid at this time. o r d : l l l l l l l l l l l ( l s b ) , o r u : l l l h l l l l l l l ( l s b ) , h p : h h h h h h h h ( l s b ) h p r s : l l l l l h h l l l l ( l s b ) , s l l a p : h h s y n c o r a c t e n b 4 9 c l k 1 2 8 c l k h s y n c w h e n r e s e t i s a p p l i e d t o o r c o u n t e r
C 39 C CXD2464R (m) pre this bit sets preset. internal preset is reflected in the output when pre is set l, and serial data settings are reflected in the output when pre is set h. when the power is turned on, all internal systems are reset, and serial data pre is set l. namely, the CXD2464R is in the preset setting status. always make sure to make all necessary settings before canceling this status (by setting pre h). if serial data pre is set h before making all required serial settings, all serial data that has not been set is set l. when serial settings have been changed when pre is set h, those settings are immediately reflected in the output. after xclr (system reset) pin 19 is set l to reset the system, serial data pre is set l and the CXD2464R enters preset setting status even after the power has been turned on. make all required settings similar to when turning on the power after xclr has been set h. the preset setting is vesa svga72 (horizontal frequency: 48.08khz, vertical frequency: 72.19hz, dot clock: 50.00mhz). detailed setting values are as shown below. address data msb lsb 0 0 0 0 0 0 0 0 pllp10 to 8: hll (lsb) 0 0 0 0 0 0 0 1 pllp7 to 0: llllhhhl (lsb) 0 0 0 0 0 0 1 0 hp7 to 0: hhhlhllh (lsb) 0 0 0 0 0 0 1 1 vp7 to 0: lllhllhl (lsb) 0 0 0 0 0 1 0 0 hstp3 to 0: lllh (lsb) 0 0 0 0 0 1 0 1 pcgp4 to 0: lhhhl (lsb) 0 0 0 0 0 1 1 0 prgp4 to 0: hlhll (lsb) 0 0 0 0 0 1 1 1 clpp1 to 0: ll (lsb) 0 0 0 0 1 0 0 0 inv: l, shp3 to 0: llll (lsb) 0 0 0 0 1 0 0 1 fld: l, frp1 to 0: hh (lsb), cktst: h, rck: h 0 0 0 0 1 0 1 0 vpol : h , hpol : h , hdnpol : h , clppol : h , pcgpol : h , prgpol : h 0 0 0 0 1 0 1 1 mbkb, a: ll, mbk2, 1, 0: hhh 0 0 0 0 1 1 0 0 mode021: l, modeb, a: hh, mode3, 2, 1: hll 0 0 0 0 1 1 0 1 vgav: h, hr: l, dwn: h, rgt: h, hst: h, pcg: h, dsp: h, pc98: h 0 0 0 1 0 0 0 0 sllap: l, ird10 to 8: lll (lsb) 0 0 0 1 0 0 0 1 ird7 to 0: llllllll (lsb) 0 0 0 1 0 0 1 0 iru10 to 8: lll (lsb) 0 0 0 1 0 0 1 1 iru7 to 0: hlllllll (lsb) 0 0 0 1 0 1 0 0 orrs3 to 0: lllh (lsb), orp10 to 8: lhh (lsb) 0 0 0 1 0 1 0 1 orp7 to 0: hhhllhhl (lsb) 0 0 0 1 0 1 1 0 ord10 to 8: lll (lsb) 0 0 0 1 0 1 1 1 ord7 to 0: llllllll (lsb) 0 0 0 1 1 0 0 0 oru10 to 8: lll (lsb) 0 0 0 1 1 0 0 1 oru7 to 0: hlllllll (lsb) 0 0 0 1 1 0 1 0 hprs10 to 8: lll (lsb) 0 0 0 1 1 0 1 1 hprs7 to 0: llllllll (lsb) 0 0 0 1 1 1 0 0 pre: l
C 40 C CXD2464R xhs and xvs pulses introduction xhs and xvs pulses are pulses for digital signal driver cxd2449q sync signal input. xhs and xvs do not support systems using the built-in double-speed controller. use the double-speed scan converter (cxd2428q) with the cxd2449q during ntsc or pal double-speed display. xhs pulses xhs pulses are output with negative polarity in 32 clock widths 34 clocks after the fall of the iract pulse when serial data sllap is l. similarly, xhs pulses are output with negative polarity in 32 clock widths 34 clocks after the fall of the oract pulse when serial data sllap is h. therefore, in order to output xhs pulses correctly, respectively set serial data ird10 to 0 and iru10 to 0 when serial data sllap is l, and ord10 to 0 and oru10 to 0 when serial data sllap is h. h s y n c o r a c t x h s o r d 1 0 t o 0 : l l l l l l l l l l l , o r u 1 0 t o 0 : l l l h l l l l l l 3 4 c l k 3 2 c l k 1 2 8 c l k xvs pulses xvs pulses are output with negative polarity in 3h widths 2h after the vertical sync signal. the phase relationship between xhs and xvs pulses at this time is as shown in the diagram below. v s y n c h s y n c x v s x h s note) xhs and xvs pulses output enb and blk pulses (negative polarity), respectively, for the sake of convenience when using the built-in double-speed controller.
C 41 C CXD2464R m o d e 3 / 2 / 1 : h / l / l m o d e b / a : h / h m o d e 0 2 1 : l d w n : h v p : l l l h l l h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h 1 2 v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 2 0 1 0 1 6 0 0 5 8 8 3 1 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 svga 800 600
C 42 C CXD2464R r g t : h p l l p : h l l l l l l h h h l ( l s b ) h p : h h h l h l l l ( l s b ) h s t p : l l h h ( l s b ) p c g p : l h h h l ( l s b ) p r g p : h l h l l ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 4 0 c l k m c k f : 5 0 . 0 0 m h z ( 2 0 . 0 0 n s ) m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r v c k p c g f r p b l k r s t r r c k w c k o r a c t x h s e n b p r g r s t w i r a c t 9 1 0 9 2 0 9 3 0 9 4 0 9 5 0 9 6 0 9 7 0 9 8 0 9 9 0 1 0 0 0 1 0 1 0 1 0 2 0 1 0 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 8 9 5 6 c l k 1 2 0 c l k 1 2 0 c l k 1 9 c l k 3 2 c l k 1 2 8 c l k 1 2 8 c l k 3 4 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 svga_1 800 600
C 43 C CXD2464R r g t : h p l l p : h l l l l l l h h h l ( l s b ) h p : h h h l h l l l ( l s b ) h s t p : l l h h ( l s b ) p c g p : l h h h l ( l s b ) p r g p : h l h l l ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 4 0 c l k m c k f : 5 0 . 0 0 m h z ( 2 0 . 0 0 n s ) m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 0 9 6 4 c l k 1 9 c l k 1 9 c l k 1 5 0 5 8 c l k 4 8 c l k 1 2 0 c l k 8 4 c l k 6 0 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 svga_2 800 600
C 44 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : h / h m o d e 0 2 1 : l d w n : h v p : l l l h l h l l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 4 7 0 4 8 0 1 1 0 2 0 3 0 4 0 4 9 1 2 4 6 0 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 vga 640 480
C 45 C CXD2464R r g t : h p l l p : l h h l l h h h h h l ( l s b ) h p : h h l l h l h l ( l s b ) h s t p : l l h h ( l s b ) p c g p : l h l l h ( l s b ) p r g p : l h h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 8 3 2 c l k m c k f : 3 1 . 5 0 m h z ( 3 1 . 7 5 n s ) m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 7 9 2 8 0 2 8 1 2 8 2 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 2 4 c l k 4 0 c l k 1 2 0 c l k 1 2 8 c l k 3 8 c l k 1 3 c l k 3 2 c l k 8 0 c l k 5 6 c l k 4 0 c l k 1 2 8 c l k 1 2 8 c l k 3 2 c l k 3 4 c l k 1 3 c l k 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 vga 640 480
C 46 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : h / h m o d e 0 2 1 : l d w n : h v p : l l l l h h l l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 4 7 4 4 8 0 4 8 5 2 3 2 0 1 0 1 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 ntsc (odd) 640 480
C 47 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : h / h m o d e 0 2 1 : l d w n : h v p : l l l l h h l l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 2 3 1 2 4 0 2 4 3 2 6 6 2 6 0 2 5 0 2 4 4 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 ntsc (even) 640 480
C 48 C CXD2464R l o o p c o u n t e r : 1 5 6 0 c l k m c k f : 2 4 . 5 4 m h z ( 4 0 . 7 5 n s ) r g t : h p l l p : h h l l l l h l h h l ( l s b ) h p : h h h h h h l l ( l s b ) h s t p : l l h h ( l s b ) p c g p : l l h h l ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 5 2 0 1 5 3 0 1 5 4 0 1 5 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 7 9 3 7 c l k 1 1 5 c l k 1 1 5 c l k 3 8 c l k 1 3 c l k 3 2 c l k 8 0 c l k 4 0 c l k 2 8 c l k 1 2 8 c l k 1 2 8 c l k 8 0 c l k 1 2 0 c l k 1 3 c l k 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 ntsc_1 640 480
C 49 C CXD2464R l o o p c o u n t e r : 1 5 6 0 c l k m c k f : 2 4 . 5 4 m h z ( 4 0 . 7 5 n s ) r g t : h p l l p : h h l l l l h l h h l ( l s b ) h p : h h h h h h l l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h h l ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 3 8 0 7 8 0 7 8 9 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 ntsc_2 640 480
C 50 C CXD2464R m o d e 3 / 2 / 1 : l / h / l m o d e b / a : h / h m o d e 0 2 1 : l d w n : h v p : l l l h l l h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 2 7 6 2 8 0 2 8 8 2 8 9 3 0 0 3 0 6 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 pal (odd) 762 572
C 51 C CXD2464R m o d e 3 / 2 / 1 : l / h / l m o d e b / a : h / h m o d e 0 2 1 : l d w n : h v p : l l l h l l h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 5 6 4 5 7 0 5 7 6 1 1 0 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . 1 8 lcx026 pal (even) 762 572
C 52 C CXD2464R l o o p c o u n t e r : 1 8 8 0 c l k m c k f : 2 9 . 3 8 m h z ( 3 4 . 0 4 n s ) r g t : h p l l p : h h h l h l h l h h l ( l s b ) h p : h h l h l h l l ( l s b ) h s t p : l l h h ( l s b ) p c g p : l h l l l ( l s b ) p r g p : l h l h h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l 1 8 3 0 1 8 4 0 1 8 5 0 1 8 6 0 1 8 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 6 9 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 3 7 c l k 1 3 8 c l k 1 2 0 c l k 3 8 c l k 1 7 0 c l k 1 3 c l k 3 2 c l k 8 0 c l k 4 8 c l k 3 6 c l k 1 2 8 c l k 1 2 8 c l k 8 0 c l k 1 3 c l k 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 pal_1 762 572
C 53 C CXD2464R r g t : h p l l p : h h h l h l h l h h l ( l s b ) h p : h h l h l h l l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h l l l ( l s b ) p r g p : l h l h h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l l o o p c o u n t e r : 1 8 8 0 c l k m c k f : 2 9 . 3 8 m h z ( 3 4 . 0 4 n s ) m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 9 4 9 n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . 9 4 0 lcx026 pal_2 762 572
C 54 C CXD2464R m o d e 3 / 2 / 1 : l / l / h m o d e b / a : h / h m o d e 0 2 1 : l d w n : h v p : l l l h l h h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 3 8 0 3 9 0 4 0 0 1 1 0 2 0 3 0 4 0 4 7 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 pc98 640 400
C 55 C CXD2464R r g t : h p l l p : l h h l h l l h h h l ( l s b ) h p : h h l h h h l h ( l s b ) h s t p : l l h h ( l s b ) p c g p : l l h l h ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 8 4 8 c l k m c k f : 2 1 . 0 5 m h z ( 4 7 . 5 0 n s ) m c k 7 8 8 7 9 8 8 0 8 8 1 8 8 2 8 8 3 8 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 5 9 h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 5 9 c l k 6 4 c l k 1 3 c l k 1 2 0 c l k 3 8 c l k 8 0 c l k 1 3 c l k 3 2 c l k 2 4 c l k 3 6 c l k 1 2 8 f h 1 2 8 f h 3 2 c l k 3 4 c l k 8 5 c l k 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 pc98 640 400
C 56 C CXD2464R m o d e 3 / 2 / 1 : l / l / l m o d e b / a : h / h m o d e 0 2 1 : l d w n : h v p : l l l h l h h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / l / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h 1 2 v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 7 4 2 7 5 0 7 6 0 7 6 8 1 1 0 2 0 3 0 4 0 4 5 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 xga 1024 768
C 57 C CXD2464R r g t : h p l l p : h l l l l l h h l l l ( l s b ) h p : h h l h h l h h ( l s b ) h s t p : h l l h ( l s b ) p c g p : l h h h h ( l s b ) p r g p : h l h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 5 0 c l k m c k f : 5 2 . 8 1 m h z ( 1 8 . 9 4 n s ) m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 9 6 0 9 7 0 9 8 0 9 9 0 1 0 0 0 1 0 1 0 1 0 2 0 1 0 3 0 1 0 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 2 9 1 9 c l k 1 0 6 c l k 1 2 0 c l k 2 3 c l k 1 4 3 c l k 1 2 8 c l k 1 2 8 c l k 3 2 c l k 3 4 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 xga_1 1024 768
C 58 C CXD2464R r g t : h p l l p : h l l l l l h h l l l ( l s b ) h p : h h l h h l h h ( l s b ) h s t p : h l l h ( l s b ) p c g p : l h h h h ( l s b ) p r g p : h l h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 5 0 c l k m c k f : 5 2 . 8 1 m h z ( 1 8 . 9 4 n s ) 1 3 0 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 4 9 1 2 5 c l k 6 9 c l k 2 3 c l k 2 3 c l k 1 4 3 c l k 5 7 c l k 8 8 c l k 6 4 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx026 xga_2 1024 768
C 59 C CXD2464R m o d e 3 / 2 / 1 : l / l / l m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l h l l l h h ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 5 9 6 6 0 0 6 1 0 6 2 0 6 2 4 1 1 0 2 0 3 0 3 8 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 macintosh16_1 832 624
C 60 C CXD2464R r g t : h p l l p : h l l l h h h h h h l ( l s b ) h p : l h h l l h h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : h l l l l ( l s b ) p r g p : h l h h h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 1 5 2 c l k m c k f : 5 7 . 2 8 m h z ( 1 7 . 4 6 n s ) m c k 1 0 2 2 h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 0 3 2 1 0 4 2 1 0 5 2 1 0 6 2 1 0 7 2 1 0 8 2 1 0 9 2 1 1 0 2 1 1 1 2 1 1 2 2 1 1 3 2 1 1 4 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 8 9 1 2 0 c l k 3 2 c l k 1 2 8 c l k 1 2 8 c l k 3 2 c l k 3 4 c l k 6 4 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 macintosh16_1 832 624
C 61 C CXD2464R l o o p c o u n t e r : 1 1 5 2 c l k m c k f : 5 7 . 2 8 m h z ( 1 7 . 4 6 n s ) r g t : h p l l p : h l l l h h h h h h l ( l s b ) h p : l h h l l h h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : h l l l l ( l s b ) p r g p : h l h h h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h m c k 9 0 h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 0 9 2 2 4 c l k 5 7 c l k 6 9 c l k 1 4 3 c l k 9 6 c l k 5 7 c l k 6 8 c l k 2 3 c l k 2 3 c l k 2 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 macintosh16_2 832 624
C 62 C CXD2464R lcx016 svga 800 600 m o d e 3 / 2 / 1 : h / l / l m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l h l l h h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 5 8 8 6 0 0 1 1 0 2 0 3 1 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s .
C 63 C CXD2464R lcx016 svga_1 800 600 r g t : h p l l p : h l l l h h h h h h l ( l s b ) h p : h h h l l l h l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h h h l ( l s b ) p r g p : h l h l l ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 4 0 c l k m c k f : 5 0 . 0 0 m h z ( 2 0 . 0 0 n s ) 9 1 0 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 9 2 0 9 3 0 9 4 0 9 5 0 9 6 0 9 7 0 9 8 0 9 9 0 1 0 0 0 1 0 1 0 1 0 2 0 1 0 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 8 9 1 9 c l k 1 2 0 c l k 1 2 0 c l k 5 6 c l k 3 2 c l k 3 4 c l k 1 2 8 c l k 1 2 8 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s .
C 64 C CXD2464R r g t : h p l l p : h l l l h h h h h h l ( l s b ) h p : h h h l l l h l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h h h l ( l s b ) p r g p : h l h l l ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 4 0 c l k m c k f : 5 0 . 0 0 m h z ( 2 0 . 0 0 n s ) m c k 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 0 9 h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 6 4 c l k 1 9 c l k 1 9 c l k 5 8 c l k 1 2 0 c l k 4 8 c l k 8 4 f h 6 0 f h n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 svga_2 800 600
C 65 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l l h h l l l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h 1 2 v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t x h s x v s 4 6 0 4 7 0 1 1 0 2 0 3 0 4 0 4 9 4 8 0 o r a c t n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f i t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 vga 640 480
C 66 C CXD2464R r g t : h p l l p : l h h l l h h h h h l ( l s b ) h p : h h l l l h l l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h l l h ( l s b ) p r g p : l h h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 8 3 2 c l k m c k f : 3 1 . 5 0 m h z ( 3 1 . 7 5 n s ) m c k 7 9 2 8 0 2 8 1 2 8 2 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 2 8 c l k 1 2 0 c l k 4 0 c l k 2 4 c l k 1 3 c l k 3 8 c l k 1 3 c l k 8 0 c l k 4 0 c l k 5 6 c l k 3 2 c l k 1 2 8 c l k 1 2 8 c l k 3 2 c l k 3 4 c l k 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 vga 640 480
C 67 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l l l h h h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 2 3 2 0 1 0 1 4 8 5 4 8 0 4 7 4 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 ntsc (odd) 640 480
C 68 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l l l h h h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 2 4 3 2 4 0 2 3 1 2 4 4 2 5 0 2 6 0 2 6 6 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 ntsc (even) 640 480
C 69 C CXD2464R l o o p c o u n t e r : 1 5 6 0 c l k m c k f : 2 4 . 5 4 m h z ( 4 0 . 7 5 n s ) r g t : h p l l p : h h l l l l h l h h l ( l s b ) h p : h h h h l h h l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h h l ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l 1 5 2 0 1 5 3 0 1 5 4 0 1 5 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 7 9 1 1 5 f h 1 1 5 c l k 1 2 0 c l k 3 8 c l k 1 3 c l k 1 3 c l k 1 3 c l k 3 2 c l k 8 0 c l k 4 0 c l k 2 8 c l k 8 0 c l k 1 2 8 c l k 1 2 8 c l k 3 7 c l k m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 ntsc_1 640 480
C 70 C CXD2464R l o o p c o u n t e r : 1 5 6 0 c l k m c k f : 2 4 . 5 4 m h z ( 4 0 . 7 5 n s ) r g t : h p l l p : h h l l l l h l h h l ( l s b ) h p : h h h h l h h l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h h l ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 3 8 0 7 8 0 7 8 9 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 ntsc_2 640 480
C 71 C CXD2464R m o d e 3 / 2 / 1 : l / h / l m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l l h l l h h ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 3 0 0 3 0 6 2 8 9 1 2 2 8 8 2 8 0 2 7 6 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 pal (odd) 762 572
C 72 C CXD2464R m o d e 3 / 2 / 1 : l / h / l m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l l h l l h h ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 1 0 1 1 8 5 7 6 5 7 0 5 6 4 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 pal (even) 762 572
C 73 C CXD2464R l o o p c o u n t e r : 1 8 8 0 c l k m c k f : 2 9 . 3 8 m h z ( 3 4 . 0 4 n s ) r g t : h p l l p : h h h l h l h l h h l ( l s b ) h p : h h l l h h h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h l l l ( l s b ) p r g p : l h l h h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l 1 8 3 0 1 8 4 0 1 8 5 0 1 8 6 0 1 8 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 6 9 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 3 c l k 1 3 c l k 3 8 c l k 1 3 c l k 1 3 8 c l k 1 2 0 c l k 3 2 c l k 3 7 c l k 8 0 c l k 4 8 c l k 3 6 c l k 8 0 c l k 1 2 8 c l k 1 2 8 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . 1 7 0 c l k lcx016 pal_1 762 572
C 74 C CXD2464R r g t : h p l l p : h h h l h l h l h h l ( l s b ) h p : h h l l h h h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h l l l ( l s b ) p r g p : l h l h h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l l o o p c o u n t e r : 1 8 8 0 c l k m c k f : 2 9 . 3 8 m h z ( 3 4 . 0 4 n s ) 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 9 4 0 9 4 9 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 pal_2 762 572
C 75 C CXD2464R m o d e 3 / 2 / 1 : h / l / h m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l l h h l l l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 4 8 0 1 1 0 2 0 3 0 4 7 0 4 6 0 4 5 4 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . 4 9 lcx016 ntsc_wide 832 480
C 76 C CXD2464R r g t : h p l l p : l h h l l h h h h h l ( l s b ) h p : h h l l h h h l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h l l h ( l s b ) p r g p : l h h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 1 4 c l k m c k f : 3 1 . 9 0 m h z ( 3 1 . 3 5 n s ) 9 7 4 9 8 4 9 9 4 1 0 0 4 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 2 0 c l k 7 9 c l k 3 8 c l k 1 3 c l k 1 3 c l k 1 3 c l k 3 2 c l k 8 0 c l k 5 6 c l k 4 0 c l k 3 2 c l k 7 9 c l k 2 4 c l k 3 4 c l k 1 2 8 c l k 1 2 8 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 ntsc_wide 832 480
C 77 C CXD2464R m o d e 3 / 2 / 1 : l / l / h m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l l h h l h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h 1 4 0 0 1 0 2 0 3 0 4 0 3 9 0 3 8 0 v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 1 2 4 7 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 pc98 640 400
C 78 C CXD2464R r g t : h p l l p : l h h l h l l h h h l ( l s b ) h p : h h l h l h h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h l h ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 8 4 8 c l k m c k f : 2 1 . 0 5 m h z ( 4 7 . 5 0 n s ) 1 2 0 c l k 3 8 c l k 1 3 c l k 1 3 c l k 3 2 c l k 8 0 c l k 3 6 c l k 2 4 c l k 1 2 8 c l k 1 2 8 c l k 5 9 c l k 6 4 c l k 3 4 c l k 7 8 8 7 9 8 8 0 8 8 1 8 8 2 8 8 3 8 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 5 9 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . 8 5 c l k 3 2 c l k lcx016 pc98 640 400
C 79 C CXD2464R m o d e 3 / 2 / 1 : l / l / l m o d e b / a : l / h m o d e 0 2 1 : l d w n : h v p : l l l h l h h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / l / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 1 7 6 8 1 0 2 0 3 0 4 0 1 2 7 5 2 4 5 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . 7 6 0 7 5 0 lcx016 xga 1024 768
C 80 C CXD2464R r g t : h p l l p : h l l l h l l l l h l ( l s b ) h p : h h l l h l l l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h h h h ( l s b ) p r g p : h l h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 9 2 c l k m c k f : 5 2 . 8 1 m h z ( 1 8 . 9 4 n s ) 1 0 0 2 1 0 1 2 1 0 2 2 1 0 3 2 1 0 4 2 1 0 5 2 1 0 6 2 1 0 7 2 1 0 8 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 2 9 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 2 0 c l k 1 1 0 c l k 1 2 0 c l k 1 2 8 c l k 1 2 8 c l k 2 3 c l k 3 2 c l k 3 4 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 xga_1 1024 768
C 81 C CXD2464R r g t : h p l l p : h l l l h l l l l h l ( l s b ) h p : h h l l h l l l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h h h h ( l s b ) p r g p : h l h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 1 0 9 2 c l k m c k f : 5 2 . 8 1 m h z ( 1 8 . 9 4 n s ) 6 9 c l k 1 3 0 c l k 2 3 c l k 1 4 3 c l k 5 7 c l k 8 8 c l k 6 4 c l k 2 3 c l k 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 4 9 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 a r e i n v e r s e d . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx016 xga_2 1024 768
C 82 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / l m o d e 0 2 1 : l d w n : h v p : l l l h l h h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 1 1 0 2 0 3 0 4 0 4 9 4 8 0 4 7 0 4 6 0 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl vga 640 480
C 83 C CXD2464R r g t : h p l l p : l h h l l h h h h h l ( l s b ) h p : h h l l l h h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h l l h ( l s b ) p r g p : l h h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 8 3 2 c l k m c k f : 3 1 . 5 0 m h z ( 3 1 . 7 5 n s ) 1 2 0 c l k 3 8 c l k 1 3 c l k 3 2 c l k 8 0 c l k 5 6 c l k 4 0 c l k 3 2 c l k 1 2 8 c l k 1 2 8 c l k 2 4 c l k 4 0 c l k 1 2 8 c l k 3 4 c l k 7 9 2 8 0 2 8 1 2 8 2 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 8 0 c l k 1 3 c l k 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 h a v e t h e s a m e p o l a r i t y . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl vga 640 480
C 84 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / l m o d e 0 2 1 : l d w n : h v p : l l l l h h l h ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 1 4 8 5 1 0 2 0 2 3 4 8 0 4 7 4 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl ntsc (odd) 640 480
C 85 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / l m o d e 0 2 1 : l d w n : h v p : l l l l h h l h ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 2 4 3 2 4 0 2 4 4 2 5 0 2 6 0 2 6 6 2 3 1 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl ntsc (even) 640 480
C 86 C CXD2464R l o o p c o u n t e r : 1 5 6 0 c l k m c k f : 2 4 . 5 4 m h z ( 4 0 . 7 5 n s ) r g t : h p l l p : h h l l l l h l h h l ( l s b ) h p : h h h h h l l h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h h l ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l 1 5 2 0 1 5 3 0 1 5 4 0 1 5 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 7 9 1 1 5 c l k 1 1 5 c l k 1 2 0 c l k 3 8 c l k 3 2 c l k 8 0 c l k 4 0 c l k 2 8 c l k 8 0 c l k 1 2 8 c l k 1 2 8 c l k 3 7 c l k m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 3 c l k 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 h a v e t h e s a m e p o l a r i t y . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . 1 3 c l k lcx012bl ntsc_1 640 480
C 87 C CXD2464R l o o p c o u n t e r : 1 5 6 0 c l k m c k f : 2 4 . 5 4 m h z ( 4 0 . 7 5 n s ) r g t : h p l l p : h h l l l l h l h h l ( l s b ) h p : h h h h h l l h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h h l ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 8 0 1 9 0 2 0 2 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 3 8 0 7 8 0 7 8 9 n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 h a v e t h e s a m e p o l a r i t y . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl ntsc_2 640 480
C 88 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / l m o d e 0 2 1 : l d w n : h v p : l l l h l l h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / l / l / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 2 7 6 2 8 0 2 8 8 2 8 9 3 0 0 3 0 6 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl pal (odd) 640 480
C 89 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / l m o d e 0 2 1 : l d w n : h v p : l l l h l l h l ( l s b ) m b k 2 / 1 / 0 / b / a : h / l / l / l / l f r p 1 / 0 : h / h v p o l : l v g a v : l p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 5 6 4 5 7 0 5 7 6 1 1 0 1 2 1 8 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p p o l a r i t y i s n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl pal (even) 640 480
C 90 C CXD2464R l o o p c o u n t e r : 1 5 6 0 c l k m c k f : 2 4 . 3 8 m h z ( 4 1 . 0 2 n s ) r g t : h p l l p : h h l l l l h l h h l ( l s b ) h p : h h h l h h h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h h l ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l 1 8 3 0 1 8 4 0 1 8 5 0 1 8 6 0 1 8 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 6 9 1 4 1 c l k 1 1 5 c l k 1 2 0 c l k 3 8 c l k 1 3 c l k 3 2 c l k 8 0 c l k 4 0 c l k 2 8 c l k 8 0 c l k 1 2 8 c l k m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 8 0 c l k 1 2 8 c l k 1 3 c l k 1 3 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 h a v e t h e s a m e p o l a r i t y . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . 3 7 c l k lcx012bl pal_1 640 480
C 91 C CXD2464R r g t : h p l l p : h h l l l l h l h h l ( l s b ) h p : h h h l h h h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h h l ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : l l o o p c o u n t e r : 1 5 6 0 c l k m c k f : 2 1 . 3 8 m h z ( 4 1 . 0 2 n s ) m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 2 7 0 2 8 0 2 9 0 3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 9 4 0 9 4 9 n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 h a v e t h e s a m e p o l a r i t y . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl pal_2 640 480
C 92 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / l m o d e 0 2 1 : l d w n : h v p : l l l l l h l l ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / h / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : l v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 3 8 0 1 1 0 2 0 3 9 0 4 0 0 3 0 4 0 1 2 4 7 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl pc98 640 400
C 93 C CXD2464R r g t : h p l l p : l h h l h l l h h h l ( l s b ) h p : h h l h h l h h ( l s b ) h s t p : l l l h ( l s b ) p c g p : l l h l h ( l s b ) p r g p : l h l l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 8 4 8 c l k m c k f : 2 1 . 0 5 m h z ( 4 7 . 5 0 n s ) 1 2 0 c l k 3 8 c l k 1 3 c l k 3 2 c l k 8 0 c l k 3 6 c l k 2 4 c l k 3 2 c l k 1 2 8 c l k 5 9 c l k m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 8 0 c l k 1 2 8 c l k 1 3 c l k 1 3 c l k 7 8 8 7 9 8 8 0 8 8 1 8 8 2 8 8 3 8 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 5 9 6 4 c l k 8 5 c l k 3 4 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 h a v e t h e s a m e p o l a r i t y . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl pc98 640 400
C 94 C CXD2464R m o d e 3 / 2 / 1 : h / h / l m o d e b / a : l / l m o d e 0 2 1 : l d w n : h v p : l l l h l l h h ( l s b ) m b k 2 / 1 / 0 / b / a : h / h / l / l / l f r p 1 / 0 : h / h v p o l : l v g a v : h p c 9 8 : h v s y n c h s y n c h d h d n ( b l k ) v s t v c k f r p h s t e n b c l p 1 c l p 2 p c g p r g c l r f r p f l d o b l k i r a c t o r a c t x h s x v s 1 1 0 2 0 6 0 0 3 1 5 8 8 1 2 n o t e ) w h e n d w n i s l o w , v s t i s i n v e r s e d . t h e 1 h a n d 1 v c y c l e f r p a n d f l d o p o l a r i t y a r e n o t s p e c i f i e d . t h e f i f t h r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl svga 640 480
C 95 C CXD2464R r g t : h p l l p : l h h l l h h h h h l ( l s b ) h p : h h l h h h l l ( l s b ) h s t p : l l l h ( l s b ) p c g p : l h l l h ( l s b ) p r g p : l h h l h ( l s b ) c l p p : l l ( l s b ) h p o l : l h d n p o l : h c l p p o l : h p c g p o l : h p r g p o l : h h r : h h s t : h p c g : h d s p : h l o o p c o u n t e r : 8 3 2 c l k m c k f : 4 0 . 0 0 m h z ( 2 5 . 0 0 n s ) 1 3 c l k 3 2 c l k m c k h s y n c ( b l k ) h d h d n c l p 1 c l p 2 h s t h c k 1 h c k 2 c l r e n b v c k p r g p c g f r p b l k r s t r r c k r s t w w c k i r a c t o r a c t x h s 1 3 c l k 1 3 c l k 7 8 2 7 9 2 8 0 2 8 1 2 8 2 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 9 4 5 c l k 9 6 c l k 1 2 0 c l k 5 1 c l k 3 8 c l k 8 0 c l k 8 0 c l k 3 2 c l k 5 6 c l k 4 0 c l k 1 2 8 c l k 1 2 8 c l k 3 4 c l k n o t e ) w h e n r g t i s l o w , h c k 1 a n d 2 h a v e t h e s a m e p o l a r i t y . t h e t h i r d r o w o f t h e t i m i n g c h a r t ( b l k ) i s a p u l s e i n d i c a t e d a s a r e f e r e n c e a n d i s n o t a p u l s e o u t p u t f r o m p i n s . lcx012bl svga 640 480
C 96 C CXD2464R application circuit 1 0 0 k 1 0 0 k 1 0 k 1 / 1 6 v 0 . 1 4 7 / 1 6 v + 5 v * p l l i c h s y n c v s y n c t s t 0 t s t 1 t s t 2 t s t 3 t s t 4 v s s 0 t s t 5 t s t 6 t s t 7 t s t 8 t s t 9 t s t 1 0 t s t 1 1 t s t 1 2 s h p d s h p c s h p b s h p a x f r p f r p p r g c l p 2 / f l d o c l p 1 h d d w n p c g t s t 1 4 v s t v c k v s s 2 e n b c l r b l k h c k 2 h c k 1 h s t x r g t r g t v d d 0 v s s 1 m o d e 1 m o d e 2 m o d e 3 x c l r t s t 1 3 c k i 2 i n v x v s x h s i r a c t o r a c t r s t r v s s 3 v d d 1 r c k r s t w w c k s c t r s c l k s d a t h d n c k i 1 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 3 6 4 6 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 c x d 2 4 6 4 r c x d 2 1 1 2 r c x d 2 1 1 2 r q q 2 3 s / h d r i v e r i c c x a 2 1 1 2 r ( w h e n c x a 2 1 1 1 r i s n o t u s e d ) l c d s i g n a l p r o c e s s i n g i c c x a 2 1 1 2 r ( w h e n c x a 2 1 1 1 r i s n o t u s e d ) l c d p a n e l l i n e b u f f e r p d 4 8 5 5 0 5 s e r i a l i / f s y n c s i g n a l i n p u t * p l l i c : s o n y c x a 3 1 0 6 q ( b u i l t - i n p h a s e c o m p a r a t o r , f r e q u e n c y d i v i d e r ) i s r e c o m m e n d e d . application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
C 97 C CXD2464R s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 1 2 . 0 0 . 2 * 1 0 . 0 0 . 1 ( 0 . 2 2 ) 0 . 1 8 0 . 0 3 + 0 . 0 8 1 1 6 1 7 3 2 3 3 4 8 4 9 6 4 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 6 4 p i n l q f p ( p l a s t i c ) l q f p - 6 4 p - l 0 1 l q f p 0 6 4 - p - 1 0 1 0 0 . 3 g d e t a i l a 0 . 5 0 . 2 ( 1 1 . 0 ) 0 . 1 2 7 0 . 0 2 + 0 . 0 5 a 1 . 5 0 . 1 + 0 . 2 0 . 1 s o l d e r / p a l l a d i u m n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 3 m 0 . 5 package outline unit: mm

▲Up To Search▲

Price & Availability of CXD2464R

	To Download CXD2464R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .