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touch screen digitizer ad7843 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 4-wire touch screen interface specified throughput rate of 125 ksps low power consumption: 1.37 mw max at 125 ksps with v cc = 3.6 v single supply, v cc of 2.2 v to 5.25 v ratiometric conversion high speed serial interface programmable 8-bit or 12-bit resolution 2 auxiliary analog inputs shutdown mode: 1 a max 16-lead qsop and tssop packages applications personal digital assistants smart hand-held devices touch screen monitors point-of-sales terminals pagers general description the ad7843 is a 12-bit successive approximation adc with a synchronous serial interface and low on resistance switches for driving touch screens. the part operates from a single 2.2 v to 5.25 v power supply and features throughput rates greater than 125 ksps. the external reference applied to the ad7843 can be varied from 1 v to +v cc , while the analog input range is from 0 v to v ref. the device includes a shutdown mode that reduces the current consumption to less than 1 a. the ad7843 features on-board switches. this, coupled with low power and high speed operation, make this device ideal for battery-powered systems such as personal digital assistants with resistive touch screens, and other portable equipment. the part is available in a 16-lead 0.15" quarter size outline package (qsop) and a 16-lead thin shrink small outline package (tssop). functional block diagram 02144-b-001 ad7843 +v cc +v cc penirq sport din cs dout dclk busy pen interrupt charge redistribution dac sar + adc control logic 4-to-1 i/p mux t/h comp gnd x+ y+ x? y? in3 in4 v ref figure 1. product highlights 1. ratiometric conversion mode available eliminating errors due to on-board switch resistances. 2. maximum current consumption of 380 a while operating at 125 ksps. 3. power-down options available. 4. analog input range from 0 v to v ref . 5. versatile serial i/o port.
ad7843 rev. b | page 2 of 20 table of contents specifications..................................................................................... 3 timing specifications .................................................................. 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 terminology ...................................................................................... 7 typical performance characteristics ............................................. 8 circuit information ........................................................................ 11 adc transfer function............................................................. 11 typical connection diagram ................................................... 11 analog input ............................................................................... 12 control register ......................................................................... 14 power vs. throughput rate....................................................... 15 serial interface ............................................................................ 16 detailed serial interface timing .............................................. 17 pen interrupt request................................................................ 19 grounding and layout .............................................................. 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 3/04data sheet changed from rev. a to rev. b updated format..................................................................universal changes to absolute maximum ratings ....................................... 5 addition to the pd0 and pd1 section......................................... 14 additions to ordering guide........................................................ 20 3/03data sheet changed from rev. 0 to rev. a updated outline dimensions ....................................................... 16
ad7843 rev. b | page 3 of 20 specifications v cc = 2.7 v to 3.6 v, v ref = 2.5 v, f sclk = 2 mhz, t a = ?40c to +85c, unless otherwise noted. table 1. parameter ad7843a 1 unit test conditions/comments dc accuracy resolution 12 bits no missing codes 11 bits min integral nonlinearity 2 2 lsb max offset error 2 6 lsb max v cc = 2.7 v offset error match 3 1 lsb max 0.1 lsb typ gain error 2 4 lsb max gain error match 3 1 lsb max 0.1 lsb typ power supply rejection 70 db typ switch drivers on-resistance 2 y+, x+ 5 ? typ y?, x? 6 ? typ analog input input voltage ranges 0 to v ref v dc leakage current 0.1 a typ input capacitance 37 pf typ reference input v ref input voltage range 1.0/+v cc v min/max dc leakage current 1 a max v ref input impedance 5 g? typ cs = gnd or +v cc v ref input current 3 20 a max 8 a typ 1 a typ f sample = 12.5 khz 1 a max cs = +v cc ; 0.001 a typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.4 v max input current, i in 1 a max typically 10 na, v in = 0 v or +v cc input capacitance, c in 4 10 pf max logic outputs output high voltage, v oh v cc ? 0.2 v min i source = 250 a; v cc = 2.2 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 250 a penirq output low voltage, v ol 0.4 v max i sink = 250 a; 100 kw pull-up floating-state leakage current 10 a max floating-state output capacitance 4 10 pf max output coding straight (natural) binary conversion rate conversion time 12 dclk cycles max track-and-hold acquisition time 3 dclk cycles min throughput rate 125 ksps max footnotes on next page.
ad7843 rev. b | page 4 of 20 parameter ad7843a 1 unit test conditions/comments power requirements v cc (specified performance) 2.7/3.6 v min/m ax functional from 2.2 v to 5.25 v i cc 5 digital i/ps = 0 v or v cc normal mode (f sample = 125 ksps) 380 a max v cc = 3.6 v, 240 a typ normal mode (f sample = 12.5 ksps) 170 a typ v cc = 2.7 v, f dclk = 200 khz normal mode (static) 150 a typ v cc = 3.6 v shutdown mode (static) 1 a max power dissipation 5 normal mode (f sample = 125 ksps) 1.368 mw max v cc = 3.6 v shutdown 3.6 w max v cc = 3.6 v 1 temperature range as follows: a version: ?40c to +85c. 2 see the terminology section. 3 guaranteed by design. 4 sample tested @ 25c to ensure compliance. 5 see the power vs. throughput rate section. timing specifications t a = t min to t max , unless otherwise noted; v cc = 2.7 v to 3.6 v, v ref = 2.5 v. table 2. timing specifications 1 parameter limit at t min , t max unit description f dclk 2 10 khz min 2 mhz max t acq 1.5 s min acquisition time t 1 10 ns min cs falling edge to first dclk rising edge t 2 60 ns max cs falling edge to busy three-state disabled t 3 60 ns max cs falling edge to dout three-state disabled t 4 200 ns min dclk high pulse width t 5 200 ns min dclk low pulse width t 6 60 ns max dclk falling edge to busy rising edge t 7 10 ns min data setup time prior to dclk rising edge t 8 10 ns min data valid to dclk hold time t 9 3 200 ns max data access time after dclk falling edge t 10 0 ns min cs rising edge to dclk ignored t 11 200 ns max cs rising edge to busy high impedance t 12 4 200 ns max cs rising edge to dout high impedance 1 sample tested at 25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v cc ) and are timed from a voltage level of 1.6 v. 2 mark/space ratio for the sc lk input is 40/60 to 60/40. 3 measured with the load circuit in figure 2 and defined as the time required for the output to cross 0.4 v or 2.0 v. 4 t 12 is derived from the measured t ime taken by the data outputs to change 0.5 v when loaded with the circuit in figure 2. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 12 , quoted in the timing characteri stics is the true bus relinquish time of the part and is in dependent of the bus loading. 02144-b-002 200 a 1.6v 200 a i ol i oh to output pin c l 50pf figure 2. load circuit for digital output timing specifications
ad7843 rev. b | page 5 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating +v cc to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v cc + 0.3 v digital input voltage to gnd ?0.3 v to v cc + 0.3 v digital output voltage to gnd ?0.3 v to v cc + 0.3 v v ref to gnd ?0.3 v to v cc + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c qsop, tssop package, power dissipation 450 mw ja thermal impedance 149.97c/w (qsop) 150.4c/w (tssop) jc thermal impedance 38.8c/w (qsop) 27.6c/w (tssop) ir reflow soldering peak temperture time-to-peak temperture ramp-down rate 220c (5c) 10 sec to 30 sec 6c/sec max pb-free parts only peak temperture 250c time-to-peak temperture ramp-up rate ramp-down rate 20 sec to 40 sec 3c/sec max 6c/sec max ________________ 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum rating may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7843 rev. b | page 6 of 20 pin configuration and fu nction descriptions 02144-b-003 1 2 3 4 5 6 7 10 8 9 11 12 13 14 15 16 ad7843 top view (not to scale) +v cc x+ y+ x? y? gnd in3 in4 dclk cs din busy dout penirq +v cc v ref figure 3. pin configuration qsop/tssop table 4. pin function descriptions pin no. mnemonic function 1, 10 +v cc power supply input. the +v cc range for the ad7843 is from 2.2 v to 5.25 v. both +v cc pins should be connected directly together. 2 x+ x+ position inp ut. adc input channel 1. 3 y+ y+ position input. adc input channel 2. 4 x? x? position input. 5 y? y? position input. 6 gnd analog ground. ground reference point for all circuitry on the ad7843. all analog inp ut signals and any external reference signal should be refe rred to this gnd voltage. 7 in3 auxiliary input 1. adc input channel 3. 8 in4 auxiliary input 2. adc input channel 4. 9 v ref reference input for the ad7843. an extern al reference must be applied to th is input. the voltage range for the external reference is 1.0 v to +v cc . for specified performance, it is 2.5 v. 11 penirq pen interrupt. cmos logic open-drain output (require s 10 k? to 100 k? pull-up register externally). 12 dout data out. logic output. the conversion result from the ad7843 is provided on this output as a se rial data stream. the bits are clocked out on the falling edge of the dclk input. this output is high impedance when cs is high. 13 busy busy output. logic output. this output is high impedance when cs is high. 14 din data in. logic input. data to be writte n to the ad7843 control register is provid ed on this input an d is clocked into the register on the rising edge of dc lk (see the control register section). 15 cs chip select input. active low logic in put. this input provides the dual func tion of initiating conversions on the ad7843 and also enables the seri al input/output register. 16 dclk external clock input. logic input. dclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the ad7843 conversion process.
ad7843 rev. b | page 7 of 20 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00000) to (00001) from the ideal, that is, agnd + 1 lsb. gain error this is the deviation of the last code transition (111110) to (111111) from the ideal (v ref ? 1 lsb) after the offset error has been adjusted out. track-and-hold acquisition time the track-and-hold amplifier enters the acquisition phase on the fifth falling edge of dclk after the start bit has been detected. three dclk cycles are allowed for the track-and-hold acquisition time. the input signal is fully acquired to the 12-bit level within this time even with the maximum specified dclk frequency. see the analog input section for more details. on resistance this is a measure of the ohmic resistance between the drain and source of the switch drivers.
ad7843 rev. b | page 8 of 20 typical performance characteristics 198 199 200 201 202 203 204 205 206 207 supply current ( a) 02144-b-004 ?40 ?20 0 20 40 60 80 100 temperature (c) figure 4. supply current vs. temperature 150 160 170 180 190 200 supply current ( a) 210 220 230 02144-b-005 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 +v cc (v) f sample = 12.5khz v ref = +v cc figure 5. supply current vs. +v cc ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 delta from +25c (lsb) 0.10 0.15 0.20 02144-b-006 ?40 ?20 0 20 40 60 80 100 temperature (c) figure 6. change in gain vs. temperature 134 135 136 137 138 139 140 141 supply current (na) 02144-b-007 ?40 ?20 0 20 40 60 80 100 temperature (c) figure 7. power-down supply current vs. temperature 3.2 3.7 2.2 2.7 4.2 4.7 5.2 +v cc (v) 02144-b-008 100 1000 sample rate (ksps) v ref = +v cc figure 8. maximum sample rate vs. +v cc ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 delta from +25c (lsb) 02144-b-009 ?40 ?20 0 20 40 60 80 100 temperature (c) figure 9. change in offset vs. temperature
ad7843 rev. b | page 9 of 20 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 reference current ( a) 70 55 25 40 10 85 100 115 130 sample rate (khz) 02144-b-010 figure 10. reference current vs. sample rate y+ x+ x? y? 4 5 6 7 8 9 10 r on ( ? ) 02144-b-011 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 +v cc (v) figure 11. switch-on resistance vs. +v cc (x+, y+: +v cc to pin; x?, y?: pin to gnd) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 error (lsb) 15 35 55 75 95 115 135 155 175 195 sampling rate (ksps) 02144-b-012 inl: r = 2k ? inl: r = 500 ? dnl: r = 2k ? dnl: r = 500 ? figure 12. maximum sampling rate vs. r in 2 4 6 5 3 8 7 reference current ( a) 10 9 12 11 14 13 020 ?40 ?20 40 60 80 temperature (c) 02144-b-013 figure 13. reference current vs. temperature y+ x+ x? y? 3 4 5 6 7 8 9 r on ( ? ) 02144-b-014 ?40 ?20 0 20 40 60 80 100 temperature (c) figure 14. switch-on resistance vs. temperature (x+, y+:+v cc to pin; x?, y?: pin to gnd) 120 100 80 60 40 20 0 snr (db) 30.0 22.5 7.5 15.0 0 37.5 45.0 52.5 60.0 frequency (khz) 02144-b-015 f sample = 125khz f in = 15khz snr = 68.34db figure 15. auxiliary channel dynamic performance (f sample =125 khz, f input = 15 khz)
ad7843 rev. b | page 10 of 20 ?120 ?100 ?80 ?60 ?40 ?20 0 psrr (db) 0 102030405060708090100 v cc ripple frequency (khz) 02144-b-016 v cc = 3v, v ref = 2.5v 100mv p-p sinewave on +v cc f sample = 125khz, f in = 20khz figure 16. ac psrr vs. supply ripple frequency figure 16 shows the power supply rejection ratio versus v cc supply frequency for the ad7843. the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency f s to the power of a 100 mv sine wave applied to the adc v cc supply of frequency f s : psrr (db) = 10 log ( pf/pfs ) where: pf is the power at frequency f in adc output. pfs is the power at frequency f s coupled onto the adc v cc supply. here a 100 mv p-p sine wave is coupled onto the v cc supply. decoupling capacitors of 10 f and 0.1 f were used on the supply.
ad7843 rev. b | page 11 of 20 circuit information the ad7843 is a fast, low-power, 12-bit, single-supply, a/d converter. the ad7843 can be operated from a 2.2 v to 5.25 v supply. when operated from either a 5 v supply or a 3 v supply, the ad7843 is capable of throughput rates of 125 ksps when provided with a 2 mhz clock. the ad7843 provides the user with an on-chip track-and-hold, multiplexer, adc, and serial interface housed in tiny 16-lead qsop or tssop packages, which offer the user considerable space-saving advantages over alternative solutions. the serial clock input (dclk) accesses data from the part and also provides the clock source for the successive approximation adc. the analog input range is 0 v to v ref (where the externally-applied v ref can be between 1 v and v cc ). the analog input to the adc is provided via an on-chip multiplexer. this analog input can be any one of the x and y panel coordinates. the multiplexer is configured with low resistance switches that allow an unselected adc input channel to provide power and an accompanying pin to provide ground for an external device. for some measurements, the on resistance of the switches could present a source of error. however, with a differential input to the converter and a differential reference architecture, this error can be negated. adc transfer function the output coding of the ad7843 is straight binary. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsbs, and so forth.). the lsb size equals v ref /4096. the ideal transfer characteristic for the ad7843 is shown in figure 17. 02144-b-017 adc code analog input 1lsb 0v +v ref ?1lsb 1lsb = v ref /4096 111...111 111...110 111...000 011...111 000...010 000...001 000...000 figure 17. ad7843 transfer characteristic typical connection diagram figure 18 shows a typical connection diagram for the ad7843 in a touch screen control application. the ad7843 requires an external reference and an external clock. the external reference can be any voltage between 1 v and v cc . the value of the reference voltage sets the input range of the converter. the conversion result is output msb first, followed by the remaining 11 bits and three trailing zeroes, depending on the number of clocks used per conversion. (see the serial interface section.) for applications where power consumption is a concern, the power management option should be used to improve power performance. see table 7 for the available power management options. 02144-b-018 16 15 14 13 12 11 9 8 1 2 3 4 7 6 5 10 touch screen 1 f to 10 f (optional) 2.2v to 5v 0.1 f 0.1 f auxiliary inputs ad7843 +v cc x+ y+ x? y? gnd in3 in4 dclk cs din busy dout penirq +v cc v ref serial/conversion clock chip select serial data in converter status serial data out pen interrupt 100k ? (optional) figure 18. typical application circuit
ad7843 rev. b | page 12 of 20 analog input figure 19 shows an equivalent circuit of the analog input structure of the ad7843, which contains a block diagram of the input multiplexer, the differential input of the adc, and the differential reference. table 5 shows the multiplexer address corresponding to each analog input, both for the ser/ dfr bit in the control register set high and low. the control bits are provided serially to the device via the din pin. for more information on the control register, see the control register section. when the converter enters hold mode, the voltage difference between the +in and ?in inputs (see figure 19) is captured on the internal capacitor array. the input current on the analog inputs depends on the conversion rate of the device. during the sample period, the source must charge the internal sampling capacitor (typically 37 pf). once the capacitor is fully charged, there is no further input current. the rate of charge transfer from the analog source to the converter is a function of conversion rate. acquisition time the track-and-hold amplifier enters tracking mode on the falling edge of the fifth dclk after the start bit us detected (see figure 24). the time required for the track-and-hold amplifier to acquire an input signal depends on how quickly the 37 pf input capacitance is charged. with zero source impedance on the analog input, three dclk cycles are always sufficient to acquire the signal to the 12-bit level. with a source impedance r in on the analog input, the actual acquisition time required is calculated using the formula: ( ) pf 37 100 4 . 8 ? + = in acq r t where r in is the source impedance of the input signal and 100 ? and 37 pf is the input rc value. depending on the frequency of dclk used, three dclk cycles may or may not be sufficient to acquire the analog input signal with various source impedance values. 02144-b-019 v cc x+ x+ y+ ref ext x? y? gnd x+ y+ in3 in4 x? y+ y? on-chip switches 4-to-1 mux 3-to-1 mux 3-to-1 mux in+ in+ in? ref? ref+ adc core data out figure 19. equivalent analog input circuit table 5. analog input, reference, and touch screen control a2 1 a1 1 a0 1 ser/ dfr analog input x switches y switches +ref 2 Cref 2 0 0 1 1 x+ off on v ref gnd 0 1 0 1 in3 off off v ref gnd 1 0 1 1 y+ on off v ref gnd 1 1 0 1 in4 off off v ref gnd 0 0 1 0 x+ off on y+ y? 1 0 1 0 y+ on off x+ x? 1 1 0 0 outputs identity code, 1000 0000 0000 1 all remaining configuration s are invalid addresses. 2 internal no de ? not direct ly accessible by the user.
ad7843 rev. b | page 13 of 20 touch screen settling in some applications, external capacitors could be required across the touch screen to filter noise associated with it, for example, noise generated by the lcd panel or backlight circuitry. the value of these capacitors causes a settling time requirement when the panel is touched. the settling time typically appears as a gain error. there are several methods for minimizing or eliminating this issue. the problem could be that the input signal, reference, or both have not settled to their final value before the sampling instant of the adc. additionally, the reference voltage could still be changing during the conversion cycle. one option is to stop, or slow down the dclk for the required touch screen settling time. this allows the input and reference to stabilize for the acquisition time, which resolves the issue for both single-ended and differential modes. the other option is to operate the ad7843 in differential mode only for the touch screen and to program the ad7843 to keep the touch screen drivers on and not go into power-down (pd0 = pd1 = 1). several conversions might be required, depending on the settling time required and the ad7843 data rate. once the required number of conversions are made, the ad7843 can then be placed into a power-down state on the last measurement. the last method is to use the 15 dclk cycle mode, which maintains the touch screen drivers on until it is commanded to stop by the processor. reference input the voltage difference between +ref and ?ref (see figure 19) sets the analog input range. the ad7843 operates with a refer- ence input in the range of 1 v to v cc . the voltage into the v ref input is not buffered and directly drives the capacitor dac portion of the ad7843. figure 20 shows the reference input circuitry. typically, the input current is 8 a with v ref = 2.5 v and f sample = 125 khz. this value varies by a few microamps, depending on the result of the conversion. the reference current diminishes directly with both conversion rate and reference voltage. as the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period does not reduce the overall current drain from the reference. 02144-b-020 x+ y+ v ref 3-to-1 mux adc figure 20. reference input circuitry when making touch screen measurements, conversions can be made in the differential (ratiometric) mode or the single-ended mode. if the ser/ dfr bit is set to 1 in the control register, a single-ended conversion is performed. figure 21 shows the configuration for a single-ended y-coordinate measurement. the x+ input is connected to the analog to digital converter, the y+ and y? drivers are turned on, and the voltage on x+ is digitized. the conversion is performed with the adc referenced from gnd to v ref . the advantage of this mode is that the switches that supply the external touch screen can be turned off once the acquisition is complete, resulting in a power saving. however, the on resistance of the y drivers affects the input voltage that can be acquired. the full touch screen resistance may be in the order of 200 ? to 900 ?, depending on the manu- facturer. therefore if the on resistance of the switches is approximately 6 ?, true full-scale and zero-scale voltages cannot be acquired regardless of where the pen/stylus is on the touch screen. note that the minimum touch screen resistance recommended for use with the ad7843 is approximately 70 ?. 02144-b-021 +v cc v ref gnd y+ y? x+ in+ in+ in? ref+ adc core ref? figure 21. single-ended reference mode (ser/ dfr = 1) in this mode of operation, therefore, some voltage is likely to be lost across the internal switches and, in addition to this, it is unlikely that the internal switch resistance will track the resis- tance of the touch screen over temperature and supply, providing an additional source of error. the alternative to this situation is to set the ser/ dfr bit low. if one again considers making a y-coordinate measurement, but now the +ref and ?ref nodes of the adc are connected directly to the y+ and y? pins, this means the analog-to-digital conversion is ratiometric. the result of the conversion is always a percentage of the external resistance, independent of how it could change with respect to the on resistance of the internal switches. figure 22 shows the configuration for a ratiometric y- coordinate measurement. it should be noted that the differential reference mode can be used only with +v cc since the source of the +ref voltage and cannot be used with v ref . the disadvantage of this mode of operation is that during both the acquisition phase and conversion process, the external touch screen must remain powered. this results in additional supply current for the duration of the conversion. 02144-b-022 +v cc gnd y+ y? x+ in+ in+ in? ref+ adc core ref? figure 22. differential reference mode (ser/ dfr = 0)
ad7843 rev. b | page 14 of 20 control register the control word provided to the adc via the din pin is shown in table 6. this provides the conversion start, channel addressing, adc conversion resolution, configuration, and power-down of the ad7843. table 6 provides detailed information on the order and description of these control bits within the control word. initiate start the first bit, the s bit, must always be set to 1 to initiate the start of the control word. the ad7843 ignores any inputs on the din line until the start bit is detected. channel addressing the next three bits in the control register, a2, a1, and a0, select the active input channel(s) of the input multiplexer (see table 5 and figure 19), touch screen drivers, and the reference inputs. mode the mode bit sets the resolution of the analog to digital converter. with 0 in this bit, the following conversion has 12 bits of resolution. with 1 in this bit, the following conversion has 8 bits of resolution. ser/ dfr the ser/ dfr bit controls the reference mode, which can be either single-ended or differential if 1 or 0 is written to this bit, respectively. the differential mode is also referred to as the ratiometric conversion mode. this mode is optimum for x-position and y-position measurements. the reference is derived from the voltage at the switch drivers, which is almost the same as the voltage to the touch screen. in this case, a separate reference voltage is not needed because the reference voltage to the adc is the voltage across the touch screen. in single-ended mode, the reference voltage to the converter is always the difference between the v ref and gnd pins. see table 5 and figure 19 through figure 22 for further information. because the supply current required by the device is so low, a precision reference can be used as the supply source to the ad7843. it may also be necessary to power the touch screen from the reference, which could require 5 ma to 10 ma. a ref19x voltage reference can source up to 30 ma and, as such, could supply both the adc and the touch screen. care must be taken, however, to ensure that the input voltage applied to the adc does not exceed the reference voltage and therefore the supply voltage. see the absolute maximum ratings section. note that the differential mode can only be used for x-position and y-position measurements. all other measurements require single-ended mode. pd0 and pd1 the power management options are selected by programming the power management bits, pd0 and pd1, in the control register. table 7 summarizes the available options. on power-up, pd0 defaults to 0, while pd1 defaults to 1.. table 6. control register bit function description msb lsb s a2 a1 a0 mode ser/dfr pd1 pd0 bit mnemonic comment 7 s start bit. the control word starts with the first high bi t on din. a new control word can start every 15th dclk cycle when in the 12-bit conversion mode, or every 11th dclk cycle when in 8-bit conversion mode. 6C4 a2Ca0 channel select bits. these three a ddress bits, along with the ser/dfr bit, control the setting of the multiplexer input, switches, and reference inputs, as described in table 5. 3 mode 12-bit/8-bit conversion select bit. this bit controls the resolution of the following conversion. with 0 in this bit, the conversion has a 12-bit resolution, or with 1 in th is bit, the conversion has a 8-bit resolution. 2 ser/dfr single-ended/differential reference sele ct bit. along with bits a2Ca0, this bi t controls the setting of the multiplexer input, switches, and reference inp uts, as described in table 5. 1, 0 pd1, pd0 power management bits. these two bits decode the power-down mode of the ad7843, as shown in table 7.
ad7843 rev. b | page 15 of 20 power vs. throughput rate by using the power-down options on the ad7843 when not converting, the average power consumption of the device decreases at lower throughput rates. figure 23 shows how, as the throughput rate is reduced while maintaining the dclk frequency at 2 mhz, the device remains in its power-down state longer and the average current consumption over time drops accordingly. for example, if the ad7843 is operated in a 24 dclk continuous sampling mode, with a throughput rate of 10 ksps and a sclk of 2 mhz, and the device is placed in the power- down mode between conversions, (pd0, pd1 = 0, 0), the current consumption is calculated as follows. the power dissipation during normal operation is typically 210 a (v cc = 2.7 v). the power-up time of the adc is instantaneous, so when the part is converting, it consumes 210 a. in this mode of operation, the part powers up on the fourth falling edge of dclk after the start bit is recognized. it goes back into power-down at the end of conversion on the 20th falling edge of dclk. this means the part consumes 210 a for 16 dclk cycles only, 8 s, during each conversion cycle. with a throughput rate of 10 ksps, the cycle time is 100 s and the average power dissipated during each cycle is (8/100) (210 a) = 16.8 a. supply current ( a) 1 100 10 1000 0 120 throughput (ksps) 02144-b-023 40 60 0 20 80 100 f dclk = 16 f sample f dclk = 2mhz v cc = 2.7v t a = ?40c to +95c figure 23. supply current vs. throughput (a) table 7. power management options pd1 pd0 penirq description 0 0 enabled this configuration results in powe r-down of the device between conver sions. the ad7843 only powers down between conversions. once pd1 and pd0 are set to 0, 0, the conversion is performed first, and the ad7843 powers down upon completion of that conversion. at th e start of the next conversi on, the adc instantly powers up to full power. this means there is no need for additional delays to ensure full ope ration, and the very first conversion is valid. the y? switch is on while in power-down. 0 1 disabled this configuration results in the same behavior as wh en pd1 and pd0 have been programmed with 0, 0, except that penirq is disabled. the y? switch is off while in power-down. 1 0 enabled this configuration results in keeping th e ad7843 permanently powered up with penirq enabled. 1 1 disabled this configuration results in keeping the ad7843 always powered up with penirq disabled.
ad7843 rev. b | page 16 of 20 serial interface figure 24 shows the typical operation of the serial interface of the ad7843. the serial clock provides the conversion clock and also controls the transfer of information to and from the ad7843. one complete conversion can be achieved with 24 dclk cycles. the cs signal initiates the data transfer and conversion process. the falling edge of cs takes the busy output and the serial bus out of three-state. the first eight dclk cycles are used to write to the control register via the din pin. the control register is updated in stages as each bit is clocked in. once the converter has enough information about the following conversion to set the input multiplexer and switches appropriately, the converter enters acquisition mode and, if required, the internal switches are turned on. during the acquisition mode, the reference input data is updated. after the three dclk cycles of acquisition, the control word is complete (the power management bits are now updated) and the converter enters conversion mode. at this point, track-and-hold goes into hold mode, the input signal is sampled, and the busy output goes high (busy returns low on the next falling edge of dclk). the internal switches may also turn off at this point if in single-ended mode. the next 12 dclk cycles are used to perform the conversion and to clock out the conversion result. if the conversion is ratiometric (ser/ dfr set low), the internal switches are on during the conversion. a 13th dclk cycle is needed to allow the dsp/microcontroller to clock in the lsb. three more dclk cycles clock out the three trailing zeroes and complete the 24 dclk transfer. the 24 dclk cycles can be provided from a dsp or via three bursts of 8 clock cycles from a microcontroller. 02144-b-024 cs dclk din busy dout x/y switches 1 (ser/dfr high) x /y switches 1,2 (ser/dfr low) three-state (start) idle off off (msb) (lsb) on on off off acquire conversion idle zero filled three-state three-state three-state t acq 18 8 8 11 10 9 8 7 6 5 4 3 2 1 0 1 1 s a2 pd1 pd0 a1 a0 mode ser/ dfr notes 1 y drivers are on when x+ is selected input channel (a2?a0 = 001); x drivers are on when y+ is selected input channel (a2?a0 = 101). 1 when pd1, pd0 = 10 or 00, y? will turn on at the end of the conversion. 2 drivers will remain on if power-down mode is 11 (no power-down) until selected input channel, reference mode, 1 or power-down mode is changed. figure 24. conversion timing, 24 dclks per conversion cycle, 8-bi t bus interface. no dclk delay required with dedicated serial port.
ad7843 rev. b | page 17 of 20 detailed serial interface timing figure 25 shows the detailed timing diagram for serial interfacing to the ad7843. writing information to the control register takes place on the first eight rising edges of dclk in a data transfer. the control register is written to only if a start bit is detected (see the control register section) on din. the initiation of the following conversion also depends on the presence of the start bit. throughout the eight dclk cycles when data is being written to the part, the dout line is driven low. the msb of the conversion result is clocked out on the falling edge of the ninth dclk cycle and is valid on the rising edge of the tenth dclk cycle; therefore, nine leading zeros can be clocked out prior to the msb. this means the data seen on the dout line in the 24 dclk conversion cycle is presented in the form of nine leading zeros, twelve bits of data, and three trailing zeros. the rising edge of cs puts the bus and the busy output back into three-state, the din line is ignored, and, if a conversion is in progress at the time, this is also aborted. however, if cs is not brought high after the completion of the conversion cycle, then the part waits for the next start bit to initiate the next conversion. this means that each conversion does not necessarily need to be framed by cs , because once cs goes low, the part detects each start bit and clocks in the control word after it on din. when the ad7843 is in the 12-bit conversion mode, a second start bit is not detected until seven dclk pulses have elapsed after a control word is clocked in on din, that is, another start bit can be clocked in on the eighth dclk rising edge after a control word is written to the device (see the fifteen clocks per cycle section). if the device is in the 8-bit conversion mode, a second start bit is not recognized until three dclk pulses elapse after the control word is clocked in, that is, another start bit can be clocked in on the fourth dclk rising edge after a control word is written to the device. because a start bit can be recognized during a conversion, the control word for the next conversion can be clocked in during the current conversion, enabling the ad7843 to complete a conversion cycle in less than 24 dclks. 02144-b-025 cs dclk din busy dout db11 pd0 db10 t 1 t 4 t 5 t 6 t 6 t 9 t 10 t 11 t 7 t 2 t 3 t 8 t 12 figure 25. detailed timing diagram
ad7843 rev. b | page 18 of 20 sixteen clocks per cycle the control bits for the next conversion can be overlapped with the current conversion to allow for a conversion every 16 dclk cycles, as shown in figure 26. this timing diagram also allows for the possibility of communication with other serial peripherals between each (eight dclk) byte transfer between the processor and the converter. however, the conversion must be completed within a short enough time frame to avoid capacitive droop effects that could distort the conversion result. it should also be noted that the ad7843 is fully powered while other serial communications are taking place between byte transfers. fifteen clocks per cycle figure 27 shows the fastest way to clock the ad7843. this scheme does not work with most microcontrollers or dsps because, in general, they are not capable of generating a 15-clock-cycle-per-serial transfer. however, some dsps allow the number of clocks per cycle to be programmed; this method could also be used with fpgas (field programmable gate arrays) or asics (application specific integrated circuits). as in the 16-clocks-per-cycle case, the control bits for the next conversion are overlapped with the current conversion to allow a conversion every 15 dclk cycles, using 12 dclks to perform the conversion and three dclks to acquire the analog input. this effectively increases the throughput rate of the ad7843 beyond that used for the specifications that are tested using 16 dclks per cycle, and dclk = 2 mhz. 8-bit conversion by setting the mode bit to 1 in the control register, the ad7843 can operate in 8-bit rather than 12-bit mode. this mode allows a faster throughput rate to be achieved, assuming 8-bit resolution is sufficient. when using the 8-bit mode, a conversion is complete four clock cycles earlier than in the 12-bit mode. this could be used with serial interfaces that provide 12 clock transfers, or two conversions could be completed with three 8-clock transfers. the throughput rate increases by 25% as a result of the shorter conversion cycle, but the conversion itself can occur at a faster clock rate because the internal settling time of the ad7843 is not as critical because settling to 8 bits is all that is required. the clock rate can be as much as 50% faster. the faster clock rate and fewer clock cycles combine to provide double the conversion rate. 02144-b-026 cs dclk din busy dout 1 s s 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 111 888 control bits control bits figure 26. conversion timing, 16 dclks per cycle, 8-bit bus in terface. no dclk delay required with dedicated serial port. 02144-b-027 cs dclk din busy dout s a2 pd1 pd0 a1 a0 mode ser/ dfr mode ser/ dfr 1 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 15 1 15 1 sa2 sa2 a1 pd1 pd0 a0 figure 27. conversion timing, 15 dclks per cycle, maximum throughput rate
ad7843 rev. b | page 19 of 20 pen interrupt request the pen interrupt equivalent output circuitry is outlined in figure 28. by connecting a pull-up resistor (10 k? to 100 k?) between v cc and this cmos logic open-drain output, the penirq output remains high normally. if penirq is enabled (see table 7), when the touch screen connected to the ad7843 is touched via a pen or finger, the penirq output goes low, initiating an interrupt to a microprocessor that can then instruct a control word to be written to the ad7843 to initiate a conver- sion. this output can also be enabled between conversions during power-down (see table 7 ), allowing power-up to be initiated only when the screen is touched. the result of the first touch screen coordinate conversion after power-up is valid, assuming any external reference is settled to the 12- or 8-bit level as required. 02144-b-028 touch screen penirq enable external pull-up penirq on y+ 100k ? +v cc +v cc y? x+ figure 28. penirq functional block diagram figure 29 assumes that the penirq function is enabled in the last write or that the part has just been powered up, so penirq is enabled by default. once the screen is touched, the penirq output goes low a time t pen later. this delay is approximately 5 s, assuming a 10 nf touch screen capacitance, and varies with the touch screen resistance actually used. once the start bit is detected, the pen interrupt function is disabled and the penirq cannot respond to screen touches. the penirq output remains low until the fourth falling edge of dclk after the start bit has been clocked in, at which point it returns high as soon as possible, regardless of the touch screen capacitance. this does not mean that the pen interrupt function is now enabled again because the power-down bits have not yet been loaded to the control register. regardless of whether penirq is to be enabled again or not, the penirq output normally always idles high. assuming that the penirq is enabled again as shown in figure 29, once the conversion is complete, the penirq output responds to a screen touch again. the fact that penirq returns high almost immediately after the fourth falling edge of dclk means the user avoids any spurious interrupts on the microprocessor or dsp, which could occur if the interrupt request line on the microprocessor/dsp was unmasked during or toward the end of conversion with the penirq pin still low. once the next start bit is detected by the ad7843, the penirq function is disabled again. if the control register write operation overlaps with the data read, a start bit is always detected prior to the end of conversion. this means that even if the penirq function has been enabled in the control register, it is disabled by the start bit again before the end of the conversion is reached; therefore the penirq function effectively cannot be used in this mode. however, as conversions are occurring continuously, the penirq function is not necessary and, therefore, redundant. grounding and layout for information on grounding and layout considerations for the ad7843, refer to application note an-577, layout and grounding recommendations for touch screen digitizers. 02144-b-029 sa2a1a0 1 0 8 1 1 13 16 mode ser/ dfr screen touched here interrupt processor no response to touch t pen penirq cs dclk din (start) pd1 = 1, pd0 = 0, penirq enabled again figure 29. penirq timing diagram
ad7843 rev. b | page 20 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.010 0.006 0.050 0.016 8 0 coplanarity 0.004 0.065 0.049 0.069 0.053 0.154 bsc 0.236 bsc compliant to jedec standards mo-137ab 0.193 bsc figure 30. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab figure 31. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range linearity error (lsb) 1 package description package option ad7843arq ?40c to +85c 2 qsop rq-16 ad7843arq-reel ?40c to +85c 2 qsop rq-16 ad7843arq-reel7 ?40c to +85c 2 qsop rq-16 ad7843arqz 2 ?40c to +85c 2 qsop rq-16 ad7843arqz-reel 2 ?40c to +85c 2 qsop rq-16 ad7843arqz-reel7 2 ?40c to +85c 2 qsop rq-16 ad7843aru ?40c to +85c 2 tssop ru-16 ad7843aru-reel ?40c to +85c 2 tssop ru-16 ad7843aru-reel7 ?40c to +85c 2 tssop ru-16 eval-ad7843cb 3 evaluation board eval-control brd2 4 controller board 1 linearity error here refers to integral linearity error. 2 z = pb-free part. pb-free parts are br anded with a # before the date code. 3 this can be used as a stand-alone evaluation board, or in conjunction with the evaluation board controller for evaluation/demo nstration purposes. 4 this evaluation board controller is a complete unit allowing a pc to control and communicate with all analog devices evaluatio n boards ending in the cb designator. ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c02144C0C3/04(b)

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