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1. abstract a new high voltage mosfet structure is presented which results in static as well as dynamic performances far ahead conventional power mosfet devices. the impact of the particular features of the device is analyzed and quantified in a case study regarding a dc-dc boost converter, which is used in a power factor corrector (pfc) converter. results obtained from the analysis of the electrical and thermal behavior of the component in the specific are discussed. 2. introduction. standard technology for high voltage suited power mosfets has been dramatically improved, thus the physical limit in terms of reduction of the devices on-state resistance is going to be reached. in fact, such a device parameter is strongly affected by the drain resistivity value, which is designed according to the requirements of the high voltage blocking capability. recently, an innovative concept of power mosfet design has been proposed that is able to enhance the devices performance [1, 2]. in these new devices the charge balance makes the electric field constant over the whole drain volume in spite of the low resistivity in this conducting region. in breakdown conditions the electric field has a value almost equal to the critical one for silicon. in this paper the main issues of process technology are shortly recalled and discussed. the static and dynamic characteristics are shown aiming to evaluate the advantages of the new device in comparison to standard power mosfets having both the same rated voltage and current carrying capability. finally, the evaluation of the performance is focused on in a specific application, in particular in a boost-based power factor corrector (pfc) converter. 3. trends on power mosfet (mdmesh?) device technology. a revolutionary three-dimensional design of the drain device volume is at the basis of the mdmesh? mosfet device. the extension of the top strip layout to the whole drain volume, by p-doped column insertion under device stripes, allows a strong resistivity reduction of the conduction n-doped layer and an impressive decrease of the devices on-state resistance when compared to a conventional mosfet [1]. the cross section of an mdmesh? device is depicted in figure 1, where both the strip layout and the column insertion under the device stripes are shown. as a consequence of this approach, the known theoretical limit of performance for vertical power mosfet devices decreases. in fact, the mdmesh? mosfet overcomes this limit allowing a mass production of devices with improved performance and reduced area. for example, a 500v mdmesh? mosfet is almost three times smaller than a conventional mosfet having the same blocking voltage. november 2001 1/14 AN1485 application note mdmesh? performance evaluation in a continuous mode pfc boost converter g. belverde - m. melito - a. raciti - m. saggio - s. musumeci
AN1485 - application note 2/14 figure 1: three-dimensional cross section of mdmesh? device the static output characteristics of an mdmesh? mosfet in comparison to a standard device with the same silicon area are reported in figure 2. moreover, simulation analysis and theoretical considerations show that in mdmesh? technology the devices on-state resistance increases linearly as function of the breakdown voltage, according to the traces shown in figure 3. the direct consequence of this result is that the extension of the mdmesh? mosfets towards higher blocking voltage values will continually increase the advantages of this technology. the fabrication of a 1000v mdmesh? mosfet will require, as expected from the design, a silicon area seven (7) times smaller than a conventional mosfet with the same on-state resistance and blocking voltage capability. this will cause a package reduction and a major improvement in any application based on these devices, as consequence of the strong reduction obtained on volume and weight of the board. the extension to very high blocking voltage of mdmesh? mosfets will represent a real revolution in high voltage converter applications. figure 2: static output characteristics (i/v curves) of an mdmesh? (stp12nm50) and a standard mosfet having equal silicon area back metal substrate drain p-mesh n- so ur c e gate finger 0 2 4 6 8 10 12 14 16 18 0123456789 10 vds(v) ids(a) vgs=10v vgs=6v mdmesh? std technology
AN1485 - application note 3/14 figure 3: standard mosfet and mdmesh? dependence of on-state resistance as a function of the breakdown voltage another important feature obtained by the proposed approach reduction of the intrinsic capacitances [3], in comparison to the one of a more traditional device, as seen in table 1. in switch mode power supply (smps) and pfc applications the reduction of the intrinsic parasitic capacitance allows a commutation time decrease, thus enabling the increase of the switching frequency. as known, this will result in important reduction of both volume and cost of the reactive components used to filter the output and/or electrical quantities. table 1. main characteristics comparison 4. switching characteristics. a characterization of the new device has been carried out in order to give evidence to the good switching performance of the new device. the silicon area shrinking allowed by the mdmesh? technology adds a further benefit to the devices gate charge due to the parasitic capacitance reduction. the gate charge comparison of figure 4 refers to two devices with equal rated electrical characteristics. at the driving voltage of 10v the mdmesh? requires a gate charge reduced by a factor of 3.5 in respect to the traditional counterpart, at a drain current of 12a and a drain-source voltage of 200v. the charge stored in the input capacitance is reduced from 50nc (stw15nb50) to 25nc (stp12nm50). this immediately suggests to the end-user an effective driving loss reduction. moreover, as a consequence, this feature allows an improvement of the performance during the switching transients in comparison with conventional devices [4]. part number bv dss [v] r ds(on) @ 25c [ohm] ciss [pf] coss [pf] crss [pf] package standard stw15nb50 >500 0.36 2600 330 40 to-247 mdmesh? stp12nm50 >500 0.38 1000 160 25 to-220 10 100 1000 100 1000 breakdown voltage [v] ron area [m w cm 2 ] m o s f e t m d s i l i c o n i d e a l l i m i t c o n v e n t i o n a l t e c hn o l o g y 10 100 1000 100 1000 breakdown voltage [v] ron area [m w cm 2 ] m o s f e t m d s i l i c o n i d e a l l i m i t c o n v e n t i o n a l t e c hn o l o g y
AN1485 - application note 4/14 the switching transient evaluation has been performed at room temperature on inductive load at several gate-driving conditions. the main quantities of a typical commutation, in hard switching conditions on inductive load, are reported in table 2, while in figure 5 the traces of an experimental turn-off switching transients are shown. figure 4: gate charge behavior of two different power mosfet devices table 2. mdmesh? typical switching quantities (rg=4.7ohm) e off [j] t fall [ns] t rise [ns] di/dt [a/ns] dv/dt [v/ns] t delay [ns] 28.6 10.8 7.6 888.9 36.84 33.6 0 10 20 30 40 50 60 charge [nc] 0 5 10 15 stw14nb50 stp12nm50 gate charge v gs (v)
AN1485 - application note 5/14 figure 5: current and voltage traces during a typical turn-off transient of an mdmesh? (v ds =100v/div, v gs =10v/div, i d =5a/div, t=20ns/div) 5. intrinsic body-drain diode. in some industrial equipment, which requires a converter configuration with bi-directional switches, the intrinsic diode of the mosfet device may be used as antiparallel diode if its own characteristics are adequate. in order to optimize the design, the performance of the body-drain diode of the new device has been investigated. in particular, the switching behavior of the body-drain diode has been widely tested. the well-established technique of platinum implanting has been performed in order to reduce the reverse recovery time (t rr ) of the body-drain diode by reducing the carrier lifetime. platinum implanting acts as a lifetime killer by introducing a mid gap center in the silicon. by increasing the platinum dose ( f ) a t rr reduction is observed. the obtained experimental waveforms during a reverse recovery transient for three devices with different platinum doses are reported in figure 6 that is related to a current slope di/dt equal to 100a/ms. figure 6: reverse recovery of the body-drain diode in case of different platinum doses (id=5a/div, t=100ns/div) f2 f1 bv dss =600v f1 < f2 no lifetime killer 100ns/div id (a) vds=100v, di/dt=100a/ m s, id=12a
AN1485 - application note 6/14 6. mdmesh device in a pfc converter application. power mosfet devices are very suitable for many power converter applications, operating at high frequency, which have been proposed aiming to develop smps with high power factor value. in these applications the devices experience high voltage, low current and high frequency. in particular, a pfc circuit has been considered, which is based on a boost converter topology in order to obtain high power factor. the control of the converter is performed by an l4981a integrated circuit that behaves as a continuous mode pfc controller and uses the technique of the average current control [5]. a prototype of the converter has been prepared and its simplified schematic is shown in figure 7. figure 7: a simplified block schematic of the control stage and power stage of the pfc application the constraints adopted to design the pfc converter are the following: input ac voltage from universal mains vin=88v up to 264v, frequency 50/60hz; dc regulated output voltage vout=400v; full load output ripple voltage dvr<16v; rated output power pout=200w; maximum output voltage vo(max)=450v; switching frequency in the range of 100-200khz; maximum inductor current ripple dil=35%; input power factor pf>0.99; total harmonic distortion of the line current < 5%. the values of some passive components of the converter circuit are reported in table 3 in the case of two different switching frequencies, namely 100khz and 200khz. in the structure of the pfc converter a sinusoidal reference 1 k controller circuit multiplier z=xy x y _ + voltage error amplifier v ref _ + current sensing current error amplifier + _ pwm modulator c in l 0 i d c 0 snubber r l v out i out i 0 v in d
AN1485 - application note 7/14 snubber circuit has been used for the switching device in order to reduce its power losses and to maintain a low value of the dv/dt looking for the emi requirements. according to the design criteria of the rcd snubber, and by imposing for the drain voltage to have a rise time t r =40ns, the capacitor value has been fixed at c=350pf (630v) while the resistance value depends on the working frequency. the value is r=1.8kohm at 100khz, and 680ohm at 200khz. the efficiency of the power converter is mainly dependant on the power losses of both the switching device and the snubber circuit. table 3. passive component values selected for two switching frequencies 7. thermal behavior of the power switch. the total power losses p t of a switching device can be split into the following components: the commutation power losses (turn-on and turn-off) and the on-state power losses: the turn-on losses, which depend on both the diode choice and the dv/dt imposed by the r g(on) , can be designed as a trade off between the power losses and the emi requirements. the snubber circuit reduces the turn-off switching power losses, which, in turn, cannot be included. the main contribute to the device power losses is given by the conduction component that depends on the r ds(on) of the device. with reference to the symbol used in figure 7, the rms current on the inductor is given by: where h is the converter efficiency. the current reaches a maximum value at the minimum value of the main voltage v in,min . from relation (2) and by considering that the duty cycle of the switch is modulated at twice the frequency of the main line, the rms current in the mosfet can be calculated by (as given in [6]): where the function k operates as a reduction factor. finally the on-state power losses p con can be evaluated by: at constant output power this value changes according to the variation of the main voltage. the maximum value of this rms current occurs in the case of the lowest value of the main voltage v in,min (88v). in the case study a typical figure for the efficiency h is in the range 0.88-0.90. the maximum peak value of the device current is given by: switching frequency [khz] l 0 [mh] c in [nf] c 0 [f] 100 0.9 220 100 200 0.45 114 100 p t p on = p off p con ++ 1 () i 0 p out h v in ------------- =2 () i d p out h v in ------------- k v in v out ------------- lf s r , 0 , ? ?? =3 () p con r ds on () i d 2 =4 () i dmax , i 0 max , d i 0 2 -------- + =5 ()
AN1485 - application note 8/14 where d i 0 is the current ripple on the inductor. calculating from (5) for the i d,max gives a current of 4a in the case of 200w output of the converter. moreover, accounting for the peak of the current due to the reverse recovery of the diode, and by adding a suitable safe margin, a switching device with a rated current carrying capability of 8a has been selected. the breakdown voltage of the device is determined according to the following relation: where the voltage v m is a suitable value ranging between 10% and 15% of the maximum output voltage. with the above constraints, we need a device having at least bv dss =500v. finally, the freewheeling diode has been specified as a 6a, 600v fast diode, with a reverse recovery time t rr =25ns. 8. junction temperature calculation. a dynamic characterization of the power mosfet has been carried out. the device is very fast and has a good switching performance. the current and voltage waveforms of the device during a typical turn-off transient are reported in figure 8. we can observe that the rise time of the drain voltage in the case shown is coherent with the design constraints on the voltage slope. figure 8: turn-off switching transient in the pfc converter at a main voltage of 88v (v ds =100v/ div, i d =2a/div, e=1kva/div, t=50ns/div) the thermal behavior has been performed by a set-up measurement shown in figure 9, where the thermal model of the device is also indicated. in steady state condition we measured the heatsink temperature at a different value of the input voltage, and namely at 88v, 110v and 220v. the junction temperature is higher than the heatsink temperature and can be estimated by the following procedure. bv dss v out d v r v m ++ 3 6 ()
AN1485 - application note 9/14 figure 9: block schematic of the measurement system to determine the heatsink temperature, as well as the steady state thermal model of the device firstly, the power loss is calculated: where t h is the measured heatsink temperature, t a is the ambient temperature fixed at 27c, and r th,h,a is the thermal resistance of the heatsink established at 7c/w. then the junction temperature is calculated by: where t j is the junction temperature, r th(j,c) is the thermal resistance between the junction and the case and r th(c,h) is the thermal resistance between the case and the heatsink. the results for the two switching frequencies considered are reported in table 4. other results obtained for the same output power and the results of the experimental tests done at different voltages and frequencies are reported in table 5. the tests have been carried out at the beginning of the experiments (room temperature, t=27c) and in steady state conditions. table 4. heatsink and junction temperatures for different voltage and frequency values v in [v] t h [c] p d [w] t j [c] 100khz 88 92 9.28 107 110 70 6.14 80 220 46 2.71 50 220khz 88 98 10.14 114.5 110 75 6.86 86.2 220 49 3.14 54.1 t a r th, s, a r th, c, s r th, j, c t j temperature measurement p d t h t a C r th h a , () -------------------- = 7 () t j t h p d r thjc , () r thch , () + () + =8 ()
AN1485 - application note 10/14 table 5. results of the experimental tests at different voltages and frequencies 9. harmonic distortion. the main results for the converter from the stand point of the harmonic content are reported in table 6, where the term a-thd% stands for the total-harmonic-distortion (in percentage) of the main current, and pf is the power factor. the test-rig used to obtain the data given in table 6 is depicted in figure 10. the better performance of the pfc is at a main voltage of 110v and 60hz. in figure 11 we can see the near zero-value of the phase shift between the input waveforms of the voltage and current. the pf measured in such a case is 0.999, as reported in table 6. finally, the voltage and current traces in a whole switching cycle of the mdmesh? device are reported in figure 12a, 12c. the test conditions are switching frequency 200khz and main voltage v in, min =88v. figure 10: experimental set-up to measure the harmonic distortion and the power factor t h [c] v in [v] i in [a] p in [w] v out [v] i out [a] p out [w] h % 100khz 27 88 2.4 211 393.7 0.485 191 90.5 92 2.472 217 395.8 0.488 193.1 89 27 110 1.88 206.6 394.6 0.484 190.9 92.4 70 1.931 212.3 397.1 0.49 194.6 91.8 27 220 0.934 204.5 396.8 0.49 194.4 95.1 46 0.948 206.3 397 0.489 194.1 94.7 200khz 27 88 2.487 217.8 395 0.482 190.4 87.4 98 2.577 226.7 395 0.483 190.8 84.2 27 110 1.957 211.9 398 0.489 195 92 75 2.016 220.7 398 0.499 198.6 90 27 220 0.959 211 398.5 0.49 195.3 93 49 0.968 213 398 0.49 195 91.6 pfc controller ic c o load multimeter oscilloscope ac source and power meter main vprobe iprobe v 0 t
AN1485 - application note 11/14 figure 11: experimental traces of the input and output waveforms (v in =110v, | =60hz, f s =200khz, v in =100v/div, v out =100v/div, i out =500ma, i in =1a/div, t=2ms/div) figure 12a: working cycles of the power mosfet device in loaded conditions @ 200khz (v ds =100v/div, i d =2a/div, t=1s/div)
AN1485 - application note 12/14 figure 12b: the mdmesh? turn-off in loaded conditions (v ds =100v/div, i d =2a/div, e=1kva/div, t=50ns/div) figure 12c: the mdmesh? turn-on in loaded conditions (v ds =100v/div, i d =2a/div, e=1kva/div, t=50ns/div)
AN1485 - application note 13/14 table 6. performance of the pfc as a non-linear switching load 10. discussion of the results. the new device features good performance in the experimental tests. in particular, the device works very well in terms of efficiency and harmonic distortion in a typical power conversion application, like the pfc. however, it is worth it to note that equivalent results may be obtained by traditional power mosfets having a larger silicon area. in fact, an equivalent standard device should have two times the area of the device presented here. the consequence is a smaller package for the mdmesh? device than a standard mosfet, and a lower cost. however, in such a case at equal power losses the smaller device will assume a greater junction temperature. obviously we are presuming different total thermal resistance, which is the case. on the other hand, the new equivalent device has a high current density, good switching performance and on-state losses comparable to standard mosfets. 11. conclusion. in this paper an extended characterization of a new class of power mosfets has been performed. the advantages and drawbacks relative to the new device has been highlighted. an important improvement in comparison with equivalent conventional devices consists in the area reduction of the silicon. as a consequence the current density of the proposed device is higher than the current density of a standard one. the switching performance is improved due to the lower parasitic capacitance and the low on-state resistance adds major advantages in terms of forward voltage drop. v in [v] ? s [hz] i in [a] pf a - thd% v out [v] d v out [v] f = 100khz 88 60 2.472 0.9984 4 393.7 13 110 60 1.931 0.994 2.4 394.6 13 220 50 0.948 0.9976 4.9 396.8 14 f = 200khz 88 60 2.577 0.9986 3.7 393 15 110 60 2.016 0.997 1.7 394.6 14 220 50 0.968 0.9981 4.4 397 15
AN1485 - application note 14/14 references: [1] m. saggio, d. fagone, s. musumeci mdmesh?: innovative technology for high voltage power mosfets, conf. rec. ispsd 2000, toulouse, france, may 22-25 2000. [2] l. lorenz , l. zverev, a. mittal, j. hancock coolmos C a new approach towards system miniaturization and energy saving conf. rec. ieee ias 2000; roma, italia, october 2000. [3] f. di giovanni, a. magri stripfet: innovative low voltage power mosfets proceedings of the power conversion intelligent motion pcim 1998 conference, june 1998, santa clara, ca. [4] s. musumeci, a. raciti, a. testa, m. melito, a. galluzzo switching behavior improvement of insulated gate controlled devices ieee transactions on power electronics, vol. 12, no. 4, july 1997, pp.645-653. [5] j. rajasgopalan, f.c. lee, p. nora a general technique for derivation of average current mode control laws for single-phase power-factor correction circuits without voltage sensing ieee transactions on power electronics, vol. 14, no. 4. [6] g. commandatore, u. moriconi designing a high power factor pre-regulator with the l4981 continuous mode application note an628/0795 by stmicroelectronics. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - isreal - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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