june 1996 introduction ac power mains occasionally have transient surge voltages. lightning strikes and ac mains load switching are just two examples of many possible conditions causing transient voltages. consequently, all off-line power supplies must provide some level of protection to suppress the effects of such transient voltages. this application note presents design techniques which improve topswitch power supply operation through most ac mains transient surge voltages. properly designed transformers, pc boards, and emi filters not only suppress the effects from transient voltages but also reduce both conducted and radiated emi emissions as well. these techniques can also be used in applications with dc input voltages such as telecom and television cable communication (or cablecom). the st202a reference design board using the top202yai topswitch will be used as an example throughout this application note. refer to the st202a data sheet as well as an-14 and an-15 for additional information. typical transient test voltages figure 1 shows a typical surge voltage waveform specified by iec 1000-4-5 (formerly iec 801-4-5). peak test voltages (u) of 3kv are common but in some applications higher peak voltages are specified. the surge voltage waveform has a 1.2 m s front time t 1 and 50 m s time to half value t 2 as shown. figure 2 shows a typical ring wave voltage waveform specified by ieee-587. peak test voltages (v peak ) of 3kv are common but in some applications higher voltages are specified. the open circuit ring wave voltage waveform has a 0.5 m s rise time to 90% of peak value and exponentially decays while oscillating at 100 khz with each peak being 60% of the preceding peak. the transient test voltage may be applied both in common mode and differential mode configurations. the common mode configuration shown in figure 3 applies the transient test voltage first to one ac mains conductor and then the other with respect to earth ground. the topswitch power supply output should be connected either directly to earth ground or ac coupled through a capacitor to earth ground. this transient test voltage causes high peak transient ringing currents to flow between the topswitch power supply primary and secondary. without proper attention to emi filter design, transformer design, and pc layout design, transient currents couple into signal traces and generate voltage spikes capable of setting the topswitch shutdown latch. u t t t 1 t 2 1.0 0.9 0.5 0.3 0.1 0.0 pi-1709-120595 front time
t 1 = 1.67 x t = 1.2 m s ?30%
time to half value
t 2 = 50 m s ?20%
figure 1. waveshape of open circuit voltage (1.2/50 m s) from iec-1000-4-5. 0.9 v peak 60% of v peak 0.1 v peak 0.5 m s t = 10 m s (f = 100 khz) v peak pi-1710-120595 figure 2. 0.5 m s-100 khz ring wave (open-circuit voltage) from ieee-587. ? transient suppression techniques for topswitch ? power supplies application note AN-20
AN-20 a 6/96 2 transient generator decoupling network ac (dc) power supply network l r c r = 10 w c = 9 m f l = 20 mh n pe ground reference unit under test pi-1711-120595 figure 3. typical test set-up for capacitive coupling on ac lines; common mode or line to ground coupling. figure 4. typical test set-up for capacitive coupling on ac lines; differential mode or line to line coupling. transient generator decoupling network ac (dc) power supply network l c = 18 m f l = 20 mh n pe ground reference pi-1712-120595 unit under test
a 6/96 AN-20 3 +1 -1 0 0 -10 +10 volts volts 160v 450v -20 -30 -40 pi-1716-120595 v o v diode (envelope) figure 5. output voltage and envelope of diode voltage waveform during normal mode transient surge. circuit countermeasures the following circuit countermeasures have been shown to improve topswitch power supply operation under transient spike or surge voltage conditions. topswitch st202a power supplies have been demonstrated to successfully operate through both ring wave and 1.2 m s/50 m s surge voltages with peak voltages up to 3 kv with the following circuit modifications. all common mode countermeasures apply to differential mode transient test conditions as well. common mode countermeasures eliminate all pc board arcing! dim the lights and closely examine the pc board during testing for signs of arcing between pc traces or conductors. change the pc layout temporarily with trace cuts and jumpers to increase the spacing and make permanent changes on the pc board artwork. slots in the pc board can be used to increase effective clearance. replace common mode choke with wider bandwidth style. one example of a wide bandwidth common mode choke is shown in figure 6. note that each common mode inductor is wound in two series connected sections to reduce capacitance. two section construction also divides or splits the transient test voltage to reduce voltage stress and prevent arcing between common mode choke windings. use 10 mh to 33 mh common mode chokes such as the panasonic elf-18d290x series for output power under 20 watts and elf-18d2xx series for output power over 20 watts. (toroidal common mode chokes are not recommended.) the differential mode configuration shown in figure 4 applies the transient test voltage across both ac mains conductors. the topswitch power supply output should be connected either directly to earth ground or ac coupled through a capacitor to earth ground. this transient test voltage causes high differential mode transient currents which can overcharge the power supply bulk energy storage capacitor (c1 in figure 7) or high voltage dc bus (v+) to a high value. during transient testing, directly measuring the v+ high voltage dc bus is dangerous and can lead to equipment damage. fortunately, the v+ high voltage dc bus can be measured indirectly on the secondary side of the power supply. figure 5 shows the st202a power supply output voltage and the envelope of the output rectifier (d2 in figure 7) anode voltage during a differential mode test. the anode voltage is useful because the envelope above reference is proportional to power supply output voltage v o and the envelope below reference is proportional to the v+ high voltage dc bus. during the transient test, input capacitor c1 and the v+ high voltage dc bus is charged from 160 vdc up to 450 vdc but the topswitch simply operates through with just a minor output voltage correction. some differential mode transient test voltages are capable of charging input capacitor c1 up to a voltage sufficient to cause the bridge rectifier diodes to enter avalanche breakdown which essentially clamps the high voltage dc bus (v+). sometimes the fuse opens, sometimes the bridge rectifier fails and then the fuse opens. in the worst case scenario, the transient test voltage charges up input capacitor c1 to a sufficiently high dc bus voltage (v+) that topswitch drain voltage rating is exceeded. 0.8 13.0?.5 21.0?.0 10.0?.5 16.0?.0 21.5?.0 3.5?.5 pi-1635-111695 figure 6. spool wound common mode choke (dimensions in mm).
AN-20 a 6/96 4 figure 7 shows a typical 2-wire input topswitch st202a power supply modified with y2-safety capacitors c7, c8, and c11. the schematic is drawn to emphasize that c7, c8, and c11 should connect directly to the transformer pins. this capacitor connection keeps peak transient currents flowing through known paths and out of sensitive pc traces. note that c11 connects to the high voltage dc bus (v+), c7 connects to the high voltage dc bus return (v-), and c8 connects directly to secondary return. c7, c8, and c11 must have very short leads and be connected with short, wide traces. pi-1706-120495 7.5 v rtn c5 47 m f d2 ug8bt r2 68 w r6 270 w to 620 w vr2 1n5995b 6.2 v c3 120 m f 25 v t1 d1 uf4005 c2 680 m f 25 v vr1 p6ke150 br1 400 v c1 33 m f 400 v c11 2.2 nf y2 r1 39 w u2 nec2501-h u1 top202yai drain source control c4 0.1 m f l1 3.3 m h f1 3.15 a j1 c6 0.1 m f x2 l2 22 mh l n t1202 1 8 2 7 3 4 c8 2.2 nf y2 c7 2.2 nf y2 d3 in4148 v+ v- figure 7. modified st202a power supply, 2-wire input.
a 6/96 AN-20 5 figure 8. modified st202a power supply, 3-wire input. figure 8 shows a typical 3-wire modification to the st202a topswitch power supply. the earth ground wire is threaded through a ferrite bead or toroid to damp power cord resonances (see an-15). because of the connection to earth ground, c8 no longer needs to be a y-capacitor but can be replaced with a simple, general purpose and low cost ceramic 0.1 uf capacitor. c7, c8, and c11 must have very short leads and be connected with short, wide traces. pi-1708-120495 7.5 v rtn c5 47 m f d2 ug8bt r2 68 w r6 270 w to 620 w vr2 1n5995b 6.2 v c3 120 m f 25 v t1 d1 uf4005 c2 680 m f 25 v vr1 p6ke150 br1 400 v c1 33 m f 400 v c11 2.2 nf y2 r1 39 w u2 nec2501-h u1 top202yai drain source control c4 0.1 m f l1 3.3 m h f1 3.15 a j1 c6 0.1 m f x2 l2 22 mh l n t1202 1 8 2 7 3 4 c8 0.1 m f c7 2.2 nf y2 d3 in4148 bead or toroid v+ v-
AN-20 a 6/96 6 figure 9 shows a typical 3-wire input power supply with cascaded lc emi filters. the sum of common mode inductance l2 and l3 should be 10 mh or less and l3 should be at least twice the value of l2 to prevent superposition of filter resonant frequencies. l2 will tend to have higher bandwidth and effectively filters higher frequency common mode currents close to the input power connection. pi-1707-120495 7.5 v rtn c5 47 m f d2 ug8bt r2 68 w r6 270 w to 620 w vr2 1n5995b 6.2 v c3 120 m f 25 v t1 d1 uf4005 c2 680 m f 25 v vr1 p6ke150 br1 400 v c1 33 m f 400 v c12 0.1 m f x2 c11 2.2 nf y2 r1 39 w u2 nec2501-h u1 top202yai drain source control c4 0.1 m f l1 3.3 m h f1 3.15 a j1 c6 0.1 m f x2 l2 3.3 mh l3 6.8 mh l n t1202 1 8 2 7 3 4 c8 0.1 m f c7 2.2 nf y2 d3 in4148 bead or toroid v+ v- figure 9. modified st202a power supply, 3-wire input with two cascaded lc emi filters.
a 6/96 AN-20 7 figure 12 shows a split sandwich primary transformer. the "noisy" or topswitch connected half of the primary is wound followed by 1 or 2 tape layers and the bias winding. to reduce transformer capacitance, 3 to 5 tape layers are placed followed by the secondary. 3 to 5 more tape layers are placed before winding the "quiet" or v+ connected half of the primary. the primary bias winding should be connected directly with a single trace to the topswitch source pin as shown in figures 7, 8, and 9. bias filter capacitor c4 should also connect directly to the topswitch source pin with a single trace. auto-restart capacitor c5 should be connected directly across topswitch control and source pins to reduce noise voltages on the control pin. reducing transformer capacitance reduces the peak transient currents. to reduce transformer capacitance, the primary must be properly located relative to the other windings. 3 to 5 layers of 2 mil thick polyester film tape should also be used between the secondary and all primary referenced windings. three typical transformer design examples are given below: figure 10 shows a transformer with single primary layer, single tape layer and bias winding layer. to reduce capacitance, 3 to 5 tape layers are added before the secondary is wound. figure 11. two-layer primary transformer cross section. pi-1714-120595 outer insulation primary bias 3 to 5 layers tape secondary 3 to 5 layers tape quiet primary half basic insulation noisy primary half figure 11 shows a two layer primary transformer with the "noisy" or topswitch connected half of the primary buried or shielded beneath the "quiet" or v+ connected half of the primary. to reduce transformer capacitance, 3 to 5 tape layers are placed before the secondary is wound. 3 to 5 more tape layers are placed over the secondary before the primary bias winding is wound. pi-1715-120595 outer insulation quiet primary half 3 to 5 layers tape secondary 3 to 5 layers tape primary bias 1 to 2 layers tape noisy primary half figure 12. split sandwich primary transformer cross section. when using triple insulated wire secondaries, the number of tape layers can be reduced to 1 or 2 layers due to the inherent spacing and reduced capacitance provided by the insulated wire. the highest transformer secondary resistance (smallest wire diameter) should be used which is still consistent with power supply efficiency requirements. slightly higher secondary resistance helps limit peak transient currents. heat sinks should be either connected only to topswitch tab or completely isolated from both topswitch tab and circuit. if the heat sink is connected elsewhere in circuit but isolated from topswitch tab, capacitance between topswitch tab and heat sink can resonate with circuit inductance causing high frequency ringing currents which may trigger topswitch shutdown latch. additional countermeasures for differential mode add resistor r6 (approximately 270 to 620 ohms) in series with the optocoupler (u2) phototransistor emitter as shown in figures 7, 8, and 9. r6 limits peak current flow below the latched shutdown trigger current threshold during output voltage and control loop overshoot. select larger input capacitor c1 to control the final dc bus voltage. carefully select bridge rectifier br1 (or discrete diodes) for avalanche and voltage clamping capability. select a common mode choke to withstand some excessive normal mode current levels (occurring when bridge diodes pi-1713-120595 outer insulation 3 to 5 layers tape primary bias primary basic insulation secondary figure 10. single layer primary transformer cross section.
AN-20 a 6/96 8 pi-1717-120595 f1 l2 br1 v+ v- to power supply c6 0.1 m f x2 vr3 mov common mode choke l n figure 13. mov vr3 position relative to x-capacitor c6, common mode choke l2 and bridge rectifier br1. avalanche and clamp the v+ high voltage dc bus) without causing sufficient coil magnetostriction to stress and crack the ferrite core. for lower power 100 to 115 vac applications, use higher voltage top2xx topswitch for improved voltage breakdown margin relative to peak dc bus voltage v+ (across c1) which occurs following application of the transient test voltage. select mov or metal-oxide-varistor transient suppressor to clip the peak off the higher transient test voltages. connect varistor vr3 between fuse f1 and common mode choke l2 as shown in figure 13. long term reliability of vr3 should be high because vr3 absorbs only a portion of the energy associated with the highest peak transient test voltages. lower peak transient test voltages can be safely tolerated without vr3 absorbing significant energy. japan power integrations, k.k. keihin-tatemono 1st bldg. 12-20 shin-yokohama 2-chome, kohoku-ku, yokohama-shi, kanagawa 222 japan phone: 81?(0)?45?471?1021 fax: 81?(0)?45?471?3717 asia & oceania for your nearest sales/rep office please contact customer service phone: 408?523?9265 fax: 408?523?9365 world headquarters power integrations, inc. 477 n. mathilda avenue sunnyvale, ca 94086 usa main: 408?523?9200 customer service: phone: 408?523?9265 fax: 408?523?9365 americas for your nearest sales/rep office please contact customer service phone: 408?523?9265 fax: 408?523?9365 power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. pi logo and topswitch are registered trademarks of power integrations, inc. ?copyright 1994, power integrations, inc. 477 n. mathilda avenue, sunnyvale, ca 94086 applications hotline world wide 408?523?9260 applications fax americas 408?523?9361 europe/africa 44?(0)?1753?622?209 japan 81?(0)?45?471?3717 asia/oceania 408?523?9364 europe & africa power integrations (europe) ltd. mountbatten house fairacres windsor sl4 4le united kingdom phone: 44?(0)?1753?622?208 fax: 44?(0)?1753?622?209
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