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| d a t a sh eet product speci?cation supersedes data of 1998 jun 24 file under integrated circuits, ic01 1998 nov 12 integrated circuits TEA0679t i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications
1998 nov 12 2 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t features dual noise reduction (nr) channels head preamplifiers reverse head switching automatic music search (ams) blank skip mute position equalization with electronically switched time constants switch functions and level adjustment controlled via i 2 c-bus optional switch inputs ttl compatible dolby reference level = 387.5 mv contained in a 32-pin small outline package improved emc behaviour. general description the TEA0679t is a bipolar integrated circuit that provides two channels of dolby b noise reduction for playback applications in car radios. it includes head and equalization amplifiers with electronically switchable time constants. the device also includes electronically switchable inputs for tape drivers with reverse heads. this device detects pauses of music in the automatic music search (ams) scan mode (for applications with an intelligent controlled tape driver) or ams latch mode (for applications with a simple controlled tape driver). for both modes the delay time can be fixed by using an external resistor. in the blank skip mode the ic can detect pauses of music during playback and allows a microcontroller to react on this situation. the equalization amplifier gain adjustment, the output offset adjustment and all switching functions are i 2 c-bus controlled. head switching and equalization time constant switching can be controlled via separate pins (optional). the device operates with power supplies from 7.6 to 12 v. the output overload level increases with increases in supply voltage. current drain varies with the following variables: supply voltage noise reduction on/off ams on/off. because of this current drain variation it is advisable to use a regulated power supply or a supply with a long time constant. quick reference data ordering information remark dolby*: available only to licensees of dolby laboratories licensing corporation, san francisco, ca94111, usa, from whom licensing and application information must be obtained. dolby is a registered trade-mark of dolby laboratories licensing corporation. symbol parameter min. typ. max. unit v cc supply voltage 7.6 - 12 v i cc supply current - 35 40 ma signal plus noise-to-noise ratio 78 84 - db type number package name description version TEA0679t so32 plastic small outline package; 32 leads; body width 7.5 mm sot287-1 sn + n -------------- 1998 nov 12 3 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagram handbook, full pagewidth mhb117 i 2 c-bus pre amp logic eq amp 13 v cc pre amp eq amp power supply level detector delay time latch and rise time ams processor mute 14 ina1 15 v ref 12 eqfa 11 eqa 16 ina2 dolby b dolby b 20 agnd blank skip 19 inb1 18 hs hs (opt) 21 eqfb 22 eqb 17 inb2 TEA0679t 10 sca hpa 23 scb 9 contra 24 hpb 8 inta 25 26 contrb 7 outa 27 intb 6 5 eqs eqs (opt) 28 29 30 outb dgnd ams 3 td scl 2 bsc 31 sda 1 mad 32 ben 4 btc output a 100 m f 470 pf 470 pf 4.7 nf 15 nf 2.7 k w 10 m f 8.2 nf 5.6 k w 24 k w ( 2%) r t (ref) 180 k w ( 10%) 390 k w 470 pf 470 pf 2.7 k w 10 m f 8.2 nf 5.6 k w 390 k w 270 k w ( 10%) ( 5%) 100 nf ( 10%) 47 nf 220 nf 330 nf ( 10%) ( 5%) 10 m f output b 4.7 nf ( 5%) 15 nf ( 5%) 24 k w ( 2%) 180 k w ( 10%) 270 k w ( 10%) 100 nf ( 10%) 330 nf ( 10%) 10 m f fig.1 block and application diagram. 1998 nov 12 4 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t pinning symbol pin description mad 1 programmable address bit bsc 2 blank skip reference capacitance td 3 delay time constant btc 4 blank skip integration capacitance eqs 5 equalization switch input (optional) outa 6 output channel a inta 7 integrating ?lter channel a contra 8 control voltage channel a hpa 9 high-pass ?lter channel a sca 10 side chain channel a eqa 11 equalizing output channel a eqfa 12 equalizing input channel a v cc 13 supply voltage ina1 14 input channel a1 (forward or reverse) v ref 15 reference voltage ina2 16 input channel a2 (reverse or forward) inb2 17 input channel b2 (reverse or forward) hs 18 head switch input (optional) inb1 19 input channel b1 (forward or reverse) agnd 20 analog ground eqfb 21 equalizing input channel b eqb 22 equalizing output channel b scb 23 side chain channel b hpb 24 high-pass ?lter channel b contrb 25 control voltage channel b intb 26 integrating ?lter channel b outb 27 output channel b ams 28 automatic music search (ams) output dgnd 29 digital ground scl 30 serial clock input sda 31 serial data input/output ben 32 bus enable fig.2 pin configuration. handbook, halfpage TEA0679t mhb118 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mad bsc td btc eqs outa inta contra hpa sca eqa eqfa v cc ina1 ben sda scl dgnd outb intb ams contrb hpb scb eqb eqfb agnd inb1 v ref ina2 hs inb2 1998 nov 12 5 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t functional description the following functions can be controlled via the i 2 c-bus: equalization time constant switching head switching automatic music search (ams) modes and blank skip noise reduction (nr) on/off switching mute switching equalization amplifier gain adjustment output offset adjustment. dolby b noise reduction only operates correctly if the 0 db dolby level is adjusted at 387.5 mv. the gain adjustment can also be used to change the ams level detector threshold. the ic is able to generate an internal power-on reset to guarantee a proper start-up behaviour. two of the above functions can be controlled via separate pins (optional), if required. head switching is achieved when pin hs is connected to a low level (input in2 active) or connected to a high level (input in1 active). equalization time constant switching (70 or 120 m s) is achieved when pin eqs is connected to a low level (70 m s) or connected to a high level (120 m s). if i 2 c-bus control is used the respective external function control pin has to be left open-circuit. when open-circuit the current state of the function can be observed at these pins. automatic music search (ams) modes and blank skip if ams is active (search mode bits smod1 = 1 and smod0 = 0 or 1) the nr function is internally switched off and the equalization time constant is internally forced to 70 m s. the signals of both channels are full-wave rectified and then added. this means that even if one channel appears inverted to the other channel the normal ams function is ensured. it is possible to choose between the ams scan and the ams latch mode via the i 2 c-bus. due to the usage of an internal flip-flop the switching from one mode to the other must be done via the ams off state. this guarantees an appropriate flip-flop reset: start from the initial ams off state (smod1 = 0 and smod0 = 0 or 1) enable the desired ams operation mode: ams latch mode (smod1 = 1 and smod0 = 0) or ams scan mode (smod1 = 1 and smod0 = 1). for further information on music search see figs 4 to 8. if blank skip is active (smod1 = 0 and smod0 = 1) periods of music can be detected in the playback mode using the ams pin as the detector output. it is possible to defeat this function via the i 2 c-bus (smod1 = 0 and smod0 = 0). for further information on blank skip see figs 9 and 10. offset adjustment procedure the offset adjustment is performed using two bits in the i 2 c-bus write byte 0. the offset monitor bit omor enables the ams output to indicate whether the selected offset value is positive or negative. the channel select bit ofch selects the channel (a or b) which is currently monitored by the output at pin ams. the monitoring needs a few microseconds until the output result is valid. a complete offset adjustment is performed in the following way: adjust the output to dolby level using the i 2 c-bus controlled equalization gain adjustment enable the offset monitor and select the channel to be monitored by transmitting the bits omor = 1 and ofch (0 = channel a, 1 = channel b) to the ic if the monitor output (pin ams) is low send the next offset value offcha or offchb one offset step below the last valid value. if the monitor output (pin ams) is high send the next offset value offcha or offchb one offset step above the last valid value repeat the last two steps until the monitor output changes its polarity if necessary store the transmitted digital offset value for the selected channel. the start value is either set by the power-on reset or the last i 2 c-bus transmission. the offset adjustment can be performed during the power-on reset condition and also each time the tape driver is not active. a complete digital offset data set consists of four values: one for each head (head 1 and head 2) in each channel. after an offset value transmission the ic stores one value for channel a and one value for channel b. if a head switch is performed these values have to be updated via the i 2 c-bus for the alternative head. 1998 nov 12 6 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t i 2 c-bus operation mode the ic is capable of operating with i 2 c-bus systems that provide either 5 v or digital supply voltage related logic levels below 5 v. this is achieved using the bus enable (pin 32) with different input voltages. an open pin or input voltages above 5 v enable 5 v related i 2 c-bus logic levels. if input voltages between 3 and 5 v are used the ic operates with i 2 c-bus logic levels related to these input voltages. to disable the i 2 c-bus receiver it is necessary to use pin voltages below the specified low level. limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. the TEA0679t allows a high level at switching pins without voltage (v cc = 0; standby mode). this means a maximum input voltage of 6.5 v for the switching pins. 2. human body model (1.5 k w ; 100 pf). 3. machine model (0 w ; 200 pf). thermal characteristics symbol parameter conditions min. max. unit v cc supply voltage 0 14 v v i input voltage (pins 1 to 32) except pin 5 (eqs), pin 15 (v ref ), pin 18 (hs), pin 30 (scl) and pin 31 (sda) to v cc - 0.3 v cc v v i(n1) input voltage at pin 30 (scl) and pin 31 (sda) - 0.3 +12 v v i(n2) input voltage at pin 5 (eqs) and pin 18 (hs) - 0.3 +6.5 v v i(stb) standby input voltage at pin 1 (mad), pin 32 (ben), pin 5 (eqs) and pin 18 (hs) note 1 - 0.3 +6.5 v t sc pin 15 (v ref ) to v cc short-circuiting duration - 5s t stg storage temperature - 55 +150 c t amb operating ambient temperature - 40 +85 c v es electrostatic handling voltage for all pins note 2 - 2+2kv note 3 - 500 +500 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 62 k/w 1998 nov 12 7 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t characteristics v cc = 10 v; f = 20 hz to 20 khz; t amb =25 c; all levels are referenced to v o = 387.5 mv (rms) (0 db) at test point (tp) pin outa or outb; see fig.1; nr on/ams off; eq switch in the 70 m s position; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit v cc supply voltage 7.6 10 12 v i cc supply current - 35 40 ma a m channel matching f = 1 khz; v o = 0 db; nr off - 0.5 -+ 0.5 db thd total harmonic distortion (2nd and 3rd harmonic) f = 1 khz; v o =0db - 0.08 0.15 % f = 10 khz; v o =10db - 0.15 0.3 % h r headroom at output v cc = 7.6 v; thd = 1%; f = 1 khz 12 -- db signal plus noise-to-noise ratio internal gain 40 db, linear; ccir/arm weighted; decode mode; see fig.41 78 84 - db psrr power supply ripple rejection v i(rms) = 0.25 v; f = 1 khz; see fig.38 52 57 - db v o output voltage frequency response; referenced to tp encode mode; see fig.41 - 25 db; f = 0.2 khz - 25.9 - 24.4 - 22.9 db 0 db; f = 1 khz - 1.5 0 + 1.5 db - 25 db; f = 1 khz - 20.8 - 19.3 - 17.8 db - 25 db; f = 5 khz - 21.1 - 19.6 - 18.1 db - 35 db; f = 10 khz - 27.4 - 25.9 - 24.4 db a cs channel separation v o = 10 db; f = 1 khz; see fig.39 57 63 - db a ct crosstalk between active and inactive input f = 1 khz; v o = 10 db; nr off; see fig.39 70 77 - db r l load resistance at output ac-coupled; f = 1 khz; v o = 12 db; thd = 1% 10 -- k w g v voltage gain of preampli?er pin ina1/ina2 to pin eqfa; pin inb1/inb2 to pin eqfb; f = 1 khz 29 30 31 db v i(offset)(dc) dc input offset voltage - 2 - mv i i(bias) input bias current - 0.1 0.4 m a r eq internal equalization resistor pin eqa/eqb to eq ampli?er a/b output 4.7 5.8 6.9 k w r i input resistance of head inputs 60 100 - k w g v(ol) open-loop gain pin ina1 or ina2 to pin eqa; pin inb1 or inb2 to pin eqb; additional gai n=0db f = 10 khz 80 86 - db f = 400 hz 104 110 - db v ref - v out dc output offset voltage at pins outa and outb after adjustment nr off; pins ina1, ina2, inb1 and inb2 connected to v ref - 20 -+ 20 mv sn + n -------------- 1998 nov 12 8 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t i o dc output current pins outa and outb connected to ground - 2 -- ma pins outa and outb connected to v cc 0.3 -- ma z o output impedance - 80 100 w v no(rms) equivalent input noise voltage (rms value) nr off; unweighted; f = 20 hz to 20 khz; r source =0 w - 0.7 1.4 m v v td ams timing (dc level) resistor r t connected to pin td v cc - 3 - v cc v v offset(dc) dc offset voltage at pins outa and outb f = 900 mhz; v i(rms) =6v - 40 - mv v offset(ad) overall offset voltage between agnd (pin 20) and dgnd (pin 29) - 0.4 - +0.4 v level adjustment g cr gain control range note 1 24.2 25.2 26.2 db g step step size - 0.4 - db g e step error between any adjacent step -- 0.4 db switching thresholds o ptional equalization time constant switch (pin eqs) v il low-level input voltage 70 m s; i l 3- 200 m a - 0.3 - +0.8 v v ol low-level output voltage 70 m s; i l 1ma -- 0.4 v v ih high-level input voltage 120 m s2 -- v v oh high-level output voltage 120 m s; i l 3- 50 m a 2.8 - 3.3 v o ptional head switch (pin hs) v il low-level input voltage input 2 on; i l 3- 150 m a - 0.3 - +0.8 v v ol low-level output voltage input 2 on; i l 10 m a -- 0.4 v v ih high-level input voltage input 1 on 2 -- v v oh high-level output voltage input 1 on; i l 3- 50 m a 2.8 - 3.3 v search modes b lank skip bs th(m-p) dynamic level threshold blank skip mode; f = 10 khz - 30 - 27 - 24 db t sw(p-m) switching time pause-to-music blank skip mode; f = 10 khz; signal on channel a and b; note 2 2.1 4.15 6.3 ms blank skip mode; f = 10 khz; signal on one channel; note 2 4.1 8.3 12.5 ms t sw(m-p) switching time music-to-pause blank skip mode; f = 10 khz; note 2 10 19 30 ms symbol parameter conditions min. typ. max. unit 1998 nov 12 9 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t notes 1. for dolby nr level adjust and ams pause detection level setting. 2. all blank skip timing characteristics are based on the assumption that a signal level change from - 33 to - 21 db pause-to-music or - 21 to - 33 db music-to-pause occurs in the specified channels. 3. the high speed of the tape (ff and rew) at the tape head during ams mode causes a transformation of level and frequency of the originally recorded signal. it means a boost of signal level of approximately 10 db and more for recorded frequencies from 500 hz to 4 khz. so the threshold level of - 22 db corresponds to signal levels in playback (pb) mode of approximately - 32 db. the ams inputs for each channel are pins sca and scb. as the frequency spectrum is transformed by a factor of approximately 10 to 30 due to the higher tape speed in ff and rew, the high-pass filter (4.7 nf/24 k w ) removes the effect of offset voltages but does not affect the music search function. in the block and application diagram (see fig.1) the frequency response of the system between tape heads input, e.g. pins ina2 and inb2, to the ams input pins sca and scb is constant over the whole frequency range (see fig.3). 4. these levels correspond to a gain setting of dolby level at tp (for tp see fig.41). the gain adjustment can be used to change the threshold level during ams operation. 5. the characteristics are in accordance with the i 2 c-bus specification. information about the i 2 c-bus can be found in the brochure the i 2 c-bus and how to use it (order number 9398 393 40011). a utomatic m usic s earch (ams) t w(min)(r) minimum pulse width rise time ams scan mode 2 - 10 ms ams latch mode 130 - 170 ms ams (p-m) signal level at output for ams switching pause-to-music ams mode; f = 10 khz; notes 3 and 4; see fig.40 - 23.7 - 21 - 18 db ams (m-p) ams switching hysteresis music-to-pause ams mode; f = 10 khz - 0.7 - 1 - 1.3 db o utput (pin ams) v oh high-level output voltage i l 3- 1 ma 2.8 - 3.3 v v ol low-level output voltage i l 1ma -- 0.4 v digital part (pins mad and ben) v ih high-level input voltage 3 - v cc v v il low-level input voltage - 0.3 -+ 1.5 v i ih high-level input current - 10 -+ 10 m a i il low-level input current - 10 -+ 10 m a digital part (pins sda and scl); note 4 v ih high-level input voltage ben (pin 32) open-circuit 3 - v cc v 5v v ben v cc 3 - v cc v 3v v ben < 5 v 0.7v ben - v cc v v il low-level input voltage ben (pin 32) open-circuit - 0.3 -+ 1.5 v 5v v ben v cc - 0.3 -+ 1.5 v 3v v ben <5v - 0.3 - 0.3v ben v i ih high-level input current v cc =0to12v - 10 -+ 10 m a i il low-level input current - 10 -+ 10 m a v ol low-level output voltage sda i l =3ma -- 0.4 v symbol parameter conditions min. typ. max. unit 1998 nov 12 10 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t general note it is recommended to switch off v cc with a gradient of 400 v/s at maximum to avoid plops on tape in the event of contact between tape and tape head while switching off. ams delay time table 1 ams delay time set by resistor r t at pin td ams threshold level resistor value r t (k w ) delay time t d typ. (ms) tolerance (%) 68 23 20 150 42 15 180 48 15 220 56 15 270 65 10 330 76 10 470 98 10 560 112 10 680 126 10 820 142 10 1000 160 10 fig.3 ams threshold level. (1) ams threshold level for application circuit (see fig.1). (2) ams threshold level for test circuit (see fig.40). handbook, halfpage - 20 - 60 - 40 - 30 - 50 mhb119 10 2 10 3 10 4 10 5 ams (p-m) (db) f (hz) (1) (2) 1998 nov 12 11 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t short description of music search a system for music search consists mainly of a level and a time detection circuit (see fig.4). for adapting and decoupling the input signal is amplified (a), then rectified (b) and smoothed with a time constant (c). thus the voltage at (c) corresponds to the signal level and will be compared to the predefined pause level at the first comparator (d), the level detector. if the signal level becomes smaller than the pause level, the level detector changes its output signal. due to the output level of the level detector the capacitor of the second time constant (e) will be charged, respectively discharged. if the pause level of the input signal remains for a certain time period, the voltage at the capacitor reaches a certain value, which corresponds to an equivalent time value. the voltage at the capacitor will be compared to a predefined time-equivalent voltage by the second comparator (f), the time detector. if the pause level of the input signal remains for this predefined time, the time detector changes its output level to pause found status. fig.4 integrated music search function. handbook, full pagewidth med624 comparator 1 comparator 2 t 1 t 2 input amplifier rectifier (a) (b) (c) (d) (e) (f) output v t v i level detector time detector 1998 nov 12 12 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t description of the principle timing diagram for ams scan mode without initial input signal (see fig.5) by activating the ams scan mode the ams output level directly indicates whether the input level corresponds to a pause level (v amseq = low) or not (v amseq = high). at t 0 the ams scan mode is activated. without a signal at v in , the following initial procedure runs until the ams output changes to a low level: due to no signal at v in the voltage at the level detector input v i (contra) remains below the level threshold and the second time constant will be discharged (time detector input v t ). when v t exceeds the time threshold level, the time detector output changes to low level. now the initial procedure is completed. if a signal burst appears at t 3 , the level detector input voltage rises immediately and causes its output to charge the second time constant, which supplies the input voltage v t for the time detector. when v t exceeds the upper threshold level after the rise time t r (at t 4 ) the ams output changes to high. if the signal burst ends at t 5 the level detector input v i falls to its low level. discharging of the second time constant begins when the level threshold is exceeded at t 6 . the circuit then measures the delay time t d , which is externally fixed by a resistor and defines the length of a pause to be detected. if no signal appears at v in within the time interval t d , the time detector output switches the ams output to a low level at t 7 . if a plop noise pulse appears at v in (t 8 ) with a pulse width less than the rise time t r >t b , the plop noise will not be detected as music. the ams output remains low. similarly the system handles no music pulses t p : when music appears at t 11 with a small interruption at t 13 , this interruption will not affect the ams output for t p 1998 nov 12 14 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t description of the principle timing diagram for ams latch mode without initial input signal (see fig.7) this is similar to the description of the principle timing diagram from ams scan mode. it only differs in its initial behaviour and its rise time t r (it should be noted that the different t r does not occur in the principle timing diagrams for latch and scan mode). running in ams latch mode, the circuit may be simply applied to drive a stop solenoid via a power fet. so a further processing of the ams output signal is not necessary. because there is no processor to make a decision whether there is plop noise or not, for this mode the rise time t r is extended to approximately 150 ms. by activating the ams latch mode the ams output will not change to a low level at t 0 if there is no initial signal at v in . a latch forces the ams output to remain high until a signal appears at v in (t 4 ). after t 4 the latch will not affect the output until the ams latch mode is started again. the existence of the latch appears necessary if the ams output, for example, drives a stop solenoid via a power fet. the low output level will cause a drive of the stop solenoid. this will happen after a maximum time of t d occurs without any input signal. if there is no music on tape for a long time (e.g. at tape end), the ams mode will be activated repeatedly as long as there is no signal at v in . thus the circuit waits until music appears before detecting the pauses. fig.7 ams latch mode without initial input signal. handbook, full pagewidth mhb122 output signal to power fet 4.5 v v amseq time threshold upper threshold (hysteresis) v t v ref level threshold v l v in v l : voltage at level detector input pin 8 (contra) v t : voltage at time detector input pin 25 (contrb) t t t t internal latch status h l t ams on t r t d t f t b < t r t p < t d t 0 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t r = rise time; t d = delay time; t b = burst time; t p = pause time; t f = fall time. 1998 nov 12 15 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t description of the principle timing diagram for ams latch mode with initial input signal (see fig.8) this is similar to the description in section description of the principle timing diagram for ams scan mode with initial input signal (see fig.6). it only differs in its rise time t r and a release of its internal latch when voltage v t exceeds the upper threshold between t 0 and t 1 . the initial procedure is now completed. the following behaviour does not differ from the description in section description of the principle timing diagram for ams latch mode without initial input signal (see fig.7). fig.8 ams latch mode with initial input signal. handbook, full pagewidth mhb123 output signal to power fet 4.5 v v amseq time threshold upper threshold (hysteresis) v t v ref level threshold v l v in v l : voltage at level detector input pin 8 (contra) v t : voltage at time detector input pin 25 (contrb) t t t t internal latch status l h t ams on t d t f t b < t r t p < t d t 0 t 1 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t r = rise time; t d = delay time; t b = burst time; t p = pause time; t f = fall time. 1998 nov 12 16 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t short description of blank skip the blank skip system is intended to detect pauses of music during playback mode. it consists of two input signal level comparators, an integration capacitor and an output comparator with hysteresis. the dc voltage of the inputs a and b, increased by the level threshold value, is used as the reference voltage for the input comparators. if input a or b exceeds this voltage the integration capacitor is discharged. if this voltage falls below the lower threshold the output comparator changes its polarity to the music found status. in the event that none of the two inputs a or b exceeds the level threshold the integration capacitor is charged. after its voltage has exceeded the upper threshold of the output comparator the output changes its polarity to the pause found status. it is recommended to process the output signal with a microcontroller to perform, for example, spike suppression for a certain time. fig.9 integrated blank skip function. (1) v c : integration capacitor voltage. handbook, full pagewidth mhb124 comparator comparator reference voltage t 1 input a comparator output input b v c (1) 1998 nov 12 17 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t fig.10 blank skip timing diagram. v c ; integration capacitor voltage: t sw(p-m) ; switching time pause-to-music: t sw(m-p) ; switching time music-to-pause. handbook, full pagewidth lower threshold upper threshold input v c t t v low v high output t t sw(p-m) t sw(p-m) t sw(m-p) t sw(m-p) mhb125 soft head switching in general the head switching procedure is recommended to be performed in four steps: 1. activate the mute function 2. switch to the alternative head 3. adjust the offset for the new head 4. deactivate the mute function. in applications without a mute function a soft head switch via the i 2 c-bus can be realized using a capacitor connected to pin 18. a proposal for this switching mechanism is shown in fig.11. to guarantee the internal timing for the head switching operation an externally connected device to pin 18 should not modify the output current significantly. an additional resistor is necessary if the head switching is performed externally via the optional switching input capability at pin 18. a proposal for this kind of switching is shown in fig.12. in general soft head switching is only suitable if equal offset values for head 1 and head 2 exist. a soft offset value switching is not possible with the TEA0679t. fig.11 soft head switching via the i 2 c-bus. handbook, halfpage mhb126 10 m f pin 18 hs (optional) fig.12 external soft head switching. handbook, halfpage mhb127 8 k w 10 m f in2 in1 pin 18 hs (optional) 1998 nov 12 18 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t i 2 c-bus protocol i 2 c-bus format table 2 explanation of i 2 c-bus format to read (slave transmits data) table 3 write byte 0; select s slave address a data a p name description s start condition slave address 101 100 00 (mad = low) 101 100 10 (mad = high) a acknowledge; generated by the slave data see tables 3 to 10 p stop condition functions bits of data byte select msb lsb smod1 smod0 hsw mute nrof ofch omor eqt equalization time constant 70 m s ------- 0 120 m s ------- 1 offset monitor ams output ------ 0 - offset monitor ------ 1 - offset channel channel a ----- 0 -- channel b ----- 1 -- nr on/off on ---- 0 --- off ---- 1 --- mute off/on off --- 0 ---- on --- 1 ---- head switch in2 -- 0 ----- in1 -- 1 ----- search mode off 0 0 ------ blank skip 0 1 ------ ams latch mode 1 0 ------ ams scan mode 1 1 ------ 1998 nov 12 19 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t table 4 write byte 1; eqadja additional gain positions (db) bits of data byte eqadja msb lsb not used not used eqa5 eqa4 eqa3 eqa2 eqa1 eqa0 0 0 0 000000 0.4 0 0 000001 0.8 0 0 000010 1.2 0 0 000011 1.6 0 0 000100 2.0 0 0 000101 2.4 0 0 000110 2.8 0 0 000111 3.2 0 0 001000 3.6 0 0 001001 4.0 0 0 001010 4.4 0 0 001011 4.8 0 0 001100 5.2 0 0 001101 5.6 0 0 001110 6.0 0 0 001111 6.4 0 0 010000 6.8 0 0 010001 7.2 0 0 010010 7.6 0 0 010011 8.0 0 0 010100 8.4 0 0 010101 8.8 0 0 010110 9.2 0 0 010111 9.6 0 0 011000 10.0 0 0 0 1 1 0 0 1 10.4 0 0 0 1 1 0 1 0 10.8 0 0 0 1 1 0 1 1 11.2 0 0 011100 11.6 0 0 011101 12.0 0 0 0 1 1 1 1 0 12.4 0 0 0 1 1 1 1 1 12.8 0 0 1 0 0 0 0 0 13.2 0 0 1 0 0 0 0 1 13.6 0 0 1 0 0 0 1 0 14.0 0 0 1 0 0 0 1 1 14.4 0 0 1 0 0 1 0 0 1998 nov 12 20 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t 14.8 0 0 1 0 0 1 0 1 15.2 0 0 1 0 0 1 1 0 15.6 0 0 1 0 0 1 1 1 16.0 0 0 1 0 1 0 0 0 16.4 0 0 1 0 1 0 0 1 16.8 0 0 1 0 1 0 1 0 17.2 0 0 1 0 1 0 1 1 17.6 0 0 1 0 1 1 0 0 18.0 0 0 1 0 1 1 0 1 18.4 0 0 1 0 1 1 1 0 18.8 0 0 1 0 1 1 1 1 19.2 0 0 1 1 0 0 0 0 19.6 0 0 1 1 0 0 0 1 20.0 0 0 1 1 0 0 1 0 20.4 0 0 1 1 0 0 1 1 20.8 0 0 1 1 0 1 0 0 21.2 0 0 1 1 0 1 0 1 21.6 0 0 1 1 0 1 1 0 22.0 0 0 1 1 0 1 1 1 22.4 0 0 1 1 1 0 0 0 22.8 0 0 1 1 1 0 0 1 23.2 0 0 1 1 1 0 1 0 23.6 0 0 1 1 1 0 1 1 24.0 0 0 1 1 1 1 0 0 24.4 0 0 1 1 1 1 0 1 24.8 0 0 1 1 1 1 1 0 25.2 0 0 1 1 1 1 1 1 additional gain positions (db) bits of data byte eqadja msb lsb not used not used eqa5 eqa4 eqa3 eqa2 eqa1 eqa0 1998 nov 12 21 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t table 5 write byte 2; eqadjb additional gain positions (db) bits of data byte eqadjb msb lsb not used not used eqb5 eqb4 eqb3 eqb2 eqb1 eqb0 0 0 0 000000 0.4 0 0 000001 0.8 0 0 000010 1.2 0 0 000011 1.6 0 0 000100 2.0 0 0 000101 2.4 0 0 000110 2.8 0 0 000111 3.2 0 0 001000 3.6 0 0 001001 4.0 0 0 001010 4.4 0 0 001011 4.8 0 0 001100 5.2 0 0 001101 5.6 0 0 001110 6.0 0 0 001111 6.4 0 0 010000 6.8 0 0 010001 7.2 0 0 010010 7.6 0 0 010011 8.0 0 0 010100 8.4 0 0 010101 8.8 0 0 010110 9.2 0 0 010111 9.6 0 0 011000 10.0 0 0 0 1 1 0 0 1 10.4 0 0 0 1 1 0 1 0 10.8 0 0 0 1 1 0 1 1 11.2 0 0 011100 11.6 0 0 011101 12.0 0 0 0 1 1 1 1 0 12.4 0 0 0 1 1 1 1 1 12.8 0 0 1 0 0 0 0 0 13.2 0 0 1 0 0 0 0 1 13.6 0 0 1 0 0 0 1 0 14.0 0 0 1 0 0 0 1 1 14.4 0 0 1 0 0 1 0 0 1998 nov 12 22 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t table 6 write byte 3; offcha 14.8 0 0 1 0 0 1 0 1 15.2 0 0 1 0 0 1 1 0 15.6 0 0 1 0 0 1 1 1 16.0 0 0 1 0 1 0 0 0 16.4 0 0 1 0 1 0 0 1 16.8 0 0 1 0 1 0 1 0 17.2 0 0 1 0 1 0 1 1 17.6 0 0 1 0 1 1 0 0 18.0 0 0 1 0 1 1 0 1 18.4 0 0 1 0 1 1 1 0 18.8 0 0 1 0 1 1 1 1 19.2 0 0 1 1 0 0 0 0 19.6 0 0 1 1 0 0 0 1 20.0 0 0 1 1 0 0 1 0 20.4 0 0 1 1 0 0 1 1 20.8 0 0 1 1 0 1 0 0 21.2 0 0 1 1 0 1 0 1 21.6 0 0 1 1 0 1 1 0 22.0 0 0 1 1 0 1 1 1 22.4 0 0 1 1 1 0 0 0 22.8 0 0 1 1 1 0 0 1 23.2 0 0 1 1 1 0 1 0 23.6 0 0 1 1 1 0 1 1 24.0 0 0 1 1 1 1 0 0 24.4 0 0 1 1 1 1 0 1 24.8 0 0 1 1 1 1 1 0 25.2 0 0 1 1 1 1 1 1 offset channel a positions bits of data byte offcha msb lsb ofa7 ofa6 ofa5 ofa4 ofa3 ofa2 ofa1 ofa0 maximum positive 0 0 0 0 0 0 0 0 ... ... ... ... ... ... ... ... maximum negative 1 1 1 1 1 1 1 1 additional gain positions (db) bits of data byte eqadjb msb lsb not used not used eqb5 eqb4 eqb3 eqb2 eqb1 eqb0 1998 nov 12 23 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t table 7 write byte 4; offchb table 8 optionally pin controlled switch functions table 9 mad switch table 10 ben switch offset channel b positions bits of data byte offchb msb lsb ofb7 ofb6 ofb5 ofb4 ofb3 ofb2 ofb1 ofb0 maximum positive 00000000 ... ... ... ... ... ... ... ... maximum negative 11111111 functions hs (pin 18) eqs (pin 5) pin state data bit hsw pin state data bit eqt output input output input equalization time constant 70 m s --- low open-circuit 0 120 m s --- high open-circuit 1 70 m s --- low low - head switch in2 low open-circuit 0 --- in1 high open-circuit 1 --- in2 low low ---- module address mad (pin 1) 101 100 10 open-circuit 101 100 10 high 101 100 00 low i 2 c-bus operation mode ben (pin 32) active; 5 v thresholds open-circuit active; 5 v thresholds high (5 v to v cc ) active; v ben related thresholds high (3 to 5 v) inactive low 1998 nov 12 24 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t i 2 c-bus transmission types the i 2 c-bus format depends on the kind of data which should be transmitted. to speed up the offset adjustment procedure three types of transmissions from master to slave are possible. the transmission type is controlled by bits ofch and omor in write byte 0. if the omor bit is set to logic 0 the standard transmission type is used. the corresponding byte sequence is shown in fig.13. this kind of transmission should by used for changes in the ic settings during normal operation. if the omor bit is set to logic 1 and the ofch bit is set to logic 0 the transmission type for an offset adjust in channel a is selected. the byte sequence is shown in fig.14. during this kind of transmission the pin ams is used as the offset monitor output for channel a. if the omor bit is set to logic 1 and the ofch bit is set to logic 1 the transmission type for an offset adjust in channel b is selected. the byte sequence is shown in fig.15. during this kind of transmission the pin ams is used as the offset monitor output for channel b. fig.13 standard transmission. handbook, full pagewidth mhb128 a s chip address a a x0 r/w address byte 0 byte 1 ap a a byte 2 byte 3 byte 4 fig.14 offset adjust channel a transmission. handbook, full pagewidth mhb129 a s chip address a a 01 r/w address byte 0 byte 3 ap a a byte 3 byte 3 fig.15 offset adjust channel b transmission. handbook, full pagewidth mhb130 a s chip address a a 11 r/w address byte 0 byte 4 ap a a byte 4 byte 4 1998 nov 12 25 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t internal pin configurations fig.16 pin 1: programmable address bit. handbook, halfpage mhb131 1 + 1.6 v fig.17 pin 2: blank skip reference capacitance. handbook, halfpage 2 + 80 k w 160 w 80 k w 160 w mhb132 fig.18 pin 3: delay time constant. handbook, halfpage mhb133 3 + 8 v 1 k w fig.19 pin 4: blank skip integration capacitance. handbook, halfpage mhb134 4 + 1998 nov 12 26 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t fig.20 pin 5: eq switch input. handbook, halfpage mhb135 5 + 3 v fig.21 pins 6 and 27: output channel. handbook, halfpage mhb136 6 + 5 v 85 w 85 w 47 w fig.22 pin 7: integrating filter channel a. handbook, halfpage mhb137 7 + v ref 0.23 v 3.6 k w fig.23 pin 8: control voltage channel a. handbook, halfpage mhb138 8 + 5 v 1.2 k w 3.4 k w 3.6 k w 40 k w 5 v 1998 nov 12 27 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t fig.24 pins 9 and 24: high-pass filter. handbook, halfpage mhb139 9 + + 5 v 5 v 9 k w 9 k w 670 w fig.25 pins 10 and 23: side chain. handbook, halfpage mhb140 10 + 5 v fig.26 pins 11 and 22: equalizing output. handbook, halfpage mhb141 11 + 5 v 160 w 5.8 k w 20 k w 20 k w fig.27 pins 12 and 21: equalizing input. handbook, halfpage mhb142 12 + 5 v 2.7 pf 10 k w 1998 nov 12 28 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t fig.28 pin 13: supply voltage. handbook, halfpage mhb143 13 10 v fig.29 pins 14, 16, 17 and 19: input channel. handbook, halfpage mhb144 6.25 pf 5 v 240 w 100 k w + 14 5 v fig.30 pin 15: reference voltage. handbook, halfpage mhb145 2.55 k w 2.55 k w + 15 5 v fig.31 pin 18: head switch input. handbook, halfpage mhb146 + 18 1998 nov 12 29 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t fig.32 pin 25: control voltage channel b. handbook, halfpage mhb147 25 + + 5 v 1.2 k w 3.4 k w 3.6 k w fig.33 pin 26: integrating filter channel b. handbook, halfpage mhb148 26 + v ref 0.23 v 3.6 k w fig.34 pin 28: ams output. handbook, halfpage 28 + mhb149 3 v fig.35 pin 30: serial clock input. handbook, halfpage mhb150 + 1.9 k w 30 1998 nov 12 30 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t fig.36 pin 31: serial data input/output. handbook, halfpage mhb151 + 1.9 k w 31 fig.37 pin 32: bus enable. handbook, halfpage mhb152 32 + 1998 nov 12 31 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... test and application information handbook, full pagewidth mhb153 i 2 c-bus pre amp logic eq amp 13 v cc = 10 v pre amp eq amp power supply level detector delay time latch and rise time ams processor mute 14 ina1 15 v ref 12 eqfa 11 eqa 16 ina2 dolby b dolby b 20 agnd blank skip 19 inb1 18 hs hs (opt) 21 eqfb 22 eqb 17 inb2 TEA0679t 10 sca hpa 23 scb 9 contra 24 hpb 8 inta 25 26 contrb 7 outa 27 intb 6 5 eqs eqs (opt) 28 29 30 outb dgnd ams 3 td scl 2 bsc 31 sda 1 mad 32 ben 4 btc output a 4.7 nf 15 nf 24 k w r t (ref) 180 k w 10 m f 10 k w 270 k w 100 nf 47 nf 220 nf 330 nf 10 m f output b 4.7 nf 15 nf 24 k w 20 k w 180 k w 270 k w 100 nf 330 nf 10 m f 10 m f 10 k w 100 m f 100 nf 0.25 v (rms) 1 khz 1000 m f 20 k w 10 k w fig.38 test circuit for power supply ripple rejection. 1998 nov 12 32 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... a ndbook, full pagewidth mhb154 i 2 c-bus pre amp logic eq amp 13 v cc pre amp eq amp power supply level detector delay time latch and rise time ams processor mute 14 ina1 15 v ref 12 eqfa 11 eqa 16 ina2 dolby b dolby b 20 agnd blank skip 19 inb1 18 hs hs (opt) 21 eqfb 22 eqb 17 inb2 TEA0679t 10 sca hpa 23 scb 9 contra 24 hpb 8 inta 25 26 contrb 7 outa 27 intb 6 5 eqs eqs (opt) 28 29 30 outb dgnd ams 3 td scl 2 bsc 31 sda 1 mad 32 ben 4 btc output a 4.7 nf 15 nf 24 k w r t (ref) 180 k w 10 m f 10 k w 270 k w 100 nf 47 nf 220 nf 330 nf 10 m f output b 4.7 nf 15 nf 24 k w 20 k w 180 k w 270 k w 100 nf 330 nf 10 m f 10 m f 10 k w 200 w 100 m f 100 nf 20 k w 10 v 10 m f fig.39 test circuit for channel separation. 1998 nov 12 33 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... a ndbook, full pagewidth mhb155 i 2 c-bus pre amp logic eq amp 13 v cc pre amp eq amp power supply level detector delay time latch and rise time ams processor mute 14 ina1 15 v ref 12 eqfa 11 eqa 16 ina2 dolby b dolby b 20 agnd blank skip 19 inb1 18 hs hs (opt) 21 eqfb 22 eqb 17 inb2 TEA0679t 10 sca hpa 23 scb 9 contra 24 hpb 8 inta 25 26 contrb 7 outa 27 intb 6 5 eqs eqs (opt) 28 29 30 outb dgnd ams 3 td scl 2 bsc 31 sda 1 mad 32 ben 4 btc output a 4.7 nf 15 nf 24 k w r t (ref) 180 k w 10 m f 10 k w 270 k w 100 nf 47 nf 220 nf 330 nf 10 m f output b 4.7 nf 15 nf 24 k w 20 k w 180 k w 270 k w 100 nf 330 nf 10 m f 10 m f 10 k w 100 m f 100 nf 20 k w 10 v voltage input fig.40 test circuit for ams threshold level. 1998 nov 12 34 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... d book, full pagewidth mhb156 i 2 c-bus pre amp logic eq amp 13 v cc pre amp eq amp power supply level detector delay time latch and rise time ams processor mute 14 ina1 15 v ref 12 eqfa 11 eqa 16 ina2 dolby b dolby b 20 agnd blank skip 19 inb1 18 hs hs (opt) 21 eqfb 22 eqb 17 inb2 TEA0679t 10 sca hpa 23 scb 9 contra 24 hpb 8 inta 25 26 contrb 7 outa 27 intb 6 5 eqs eqs (opt) 28 29 30 outb dgnd ams 3 td scl 2 bsc 31 sda 1 mad 32 ben 4 btc output a 4.7 nf 15 nf 24 k w r t (ref) 180 k w 10 m f 10 m f 200 w 10 k w 270 k w 100 nf 47 nf 220 nf 330 nf 10 m f output b 4.7 nf 15 nf 24 k w 20 k w 25 k w 180 k w 270 k w 100 nf 330 nf 10 m f 10 m f 10 k w 100 m f 100 nf 20 k w 25 k w 25 k w 25 k w 10 v v i tp tp 470 pf 10 m f v cc v i fig.41 test circuit for frequency response (channel b). channel a: decode mode: pre-amplifier 30 db and eq amplifier 10 db linear. channel b: encode mode. 1998 nov 12 35 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... a ndbook, full pagewidth mhb157 200 w 470 pf 200 w 470 pf 200 w 470 pf 200 w 470 pf i 2 c-bus pre amp logic eq amp 13 v cc pre amp eq amp power supply level detector delay time latch and rise time ams processor mute 14 ina1 15 v ref 12 eqfa 11 eqa 16 ina2 dolby b dolby b 20 agnd blank skip 19 inb1 18 hs hs (opt) 21 eqfb 22 eqb 17 inb2 TEA0679t 10 sca hpa 23 scb 9 contra 24 hpb 8 inta 25 26 contrb 7 outa 27 intb 6 5 eqs eqs (opt) 28 29 30 outb dgnd ams 3 td scl 2 bsc 31 sda 1 mad 32 ben 4 btc output a 4.7 nf 15 nf 24 k w r t (ref) 180 k w 10 m f 10 k w 270 k w 100 nf 47 nf 220 nf 330 nf 10 m f output b 4.7 nf 15 nf 24 k w 20 k w 180 k w 270 k w 100 nf 330 nf 10 m f 10 m f 10 k w 100 m f 100 nf 20 k w 40 w 10 w 10 v fig.42 emc test circuit. 1998 nov 12 36 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t package outline unit a max. a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.10 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot287-1 (1) 0.012 0.004 0.096 0.086 0.02 0.01 0.050 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w m b p d h e z e c v m a x a y 32 17 16 1 q a a 1 a 2 l p q detail x l (a ) 3 e pin 1 index 0 5 10 mm scale so32: plastic small outline package; 32 leads; body width 7.5 mm sot287-1 95-01-25 97-05-22 1998 nov 12 37 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1998 nov 12 38 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1998 nov 12 39 philips semiconductors product speci?cation i 2 c-bus controlled dual dolby* b-type noise reduction circuit for playback applications TEA0679t notes internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545102/750/02/pp40 date of release: 1998 nov 12 document order number: 9397 750 04298 |
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