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asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 1 - general description the AK4640 targeted at pda and other low - power, small size applications. it features a 16 - bit stereo codec with a built - in microphone - amplifier, headphone - amplifier and speaker - amplifier. input circuits inclu de a microphone - amplifier and an alc (auto level control) circuit. the AK4640 is available in a smaller 57 - bga in addition to a 52 - qfn which has compatibility with the ak4534/8, utilizing less board space than competitive offerings. features 1. resolution : 16bits 2. recording function 1ch mon o input 1 st mic amplifier : +20db or 0db 2 nd amplifier with alc : +27.5db ~ - 8db, 0.5db step adc performance : s/(n+d) : 79db, dr, s/n : 83db 3. playback function digital de - emphasis filter (tc=50/15 m s, fs=32khz, 44 .1khz, 48khz) digital volume (0db ~ - 127db, 0.5db step, mute) headphone - amp - s/(n+d) : 70db, s/n : 90db - output power : 15mw@16 w (hvdd=3.3v) - click noise free at power on/off mono speaker - amp with alc - s/(n+d) : 64db@150mw, s/n : 90db - btl outpu t - alc circuit - output power : 300mw@8 w , thd+n=10% (hvdd=3.3v) mono and stereo beep inputs 4. phone i/f full - differential aux input full - differential mono output 5. power management 6. master clock (1) pll mode frequencies : 11.2896mhz, 12mhz and 12.288mhz input level : cmos (2) external clock mode frequencies : 1.792mhz ~ 12.288mhz 7. output master clock frequencies : 32fs/64fs/128fs/256fs 8. sampling rate (1) pll mode 8khz, 11.025khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz (2) external clock mode 8khz ~ 48k hz 9. control mode: 4 - wire serial / i 2 c bus 10. master/slave mode 16bit d s codec with mic/hp/spk - amp AK4640 = preliminary =
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 2 - 11. audio interface format : msb first, 2?s compliment adc : i 2 s, 16bit msb justified dac : i 2 s, 16bit msb justified, 16bit lsb justified 12. ta = - 10 ~ 70 c 13. power supply: 2.4v ~ 3.6v (typ. 3.3v) 14. pow er supply current avdd+dvdd : 19ma pvdd : 1.2ma hvdd (hp - amp=on, spk - amp=off) : 4ma hvdd (hp - amp=off, spk - amp=on) : 7ma 15. package : 57pin bga (5mm x 5mm, 0.5mm pitch) 52pin qfn (pin compatible with ak4534/8vn) 16. register compatible with ak4534/8 n bl ock diagram alc1 (ipga) pmmic att avdd avss micout ain lrck bick sdto sdti pdn dsp and up dvdd dvss hvdd hvss vcom mutet min mout2 mout- auxin+ mix hpl pmhpl hp-amp hpr pmhpr hp-amp control register interface audio pmspk spk- amp spp spn i2c csn/cad1 cclk/scl cdti/sda cdto volume pmmo mout cad0 auxin- mout+ att beepl pll xti/mcki xto mcko vcoc pmpll pvdd pvss mix mix mix mix pmaux mpe mic power supply ext int mic-amp 0db or 20db mpi mic power supply m/s pmbps hpf adc pmadc pmdac datt smute dac beepr mix att alc2 beepm pmbpm pmhpl or pmhpr or pmspk figure 1 . block diagram
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 3 - n ordering guide AK4640vg - 10 ~ +70 c 57pin bga (0.5mm pitch) AK4640vn - 10 ~ +70 c 52pin qfn (0.4mm pitch) akd4640 evaluation board for AK4640 n pin layout (AK4640vg) a top view b c e d f g h j 6 7 8 9 5 3 4 1 2 AK4640 9 nc hpr hvss hvdd spn spp m/s xti/mcki nc 8 hpl mutet hvss hvdd spn spp xto dvdd dvss 7 min nc nc mcko 6 mout2 mout - bick lrck 5 mout+ auxin - t op v iew sdti sdto 4 b eepm auxin+ cdto i2c 3 beepl beepr nc cclk/scl cdti/sda 2 micout ain mpi vcom avdd avdd pvss csn/cad1 pdn 1 nc ext mpe int avss pvdd vcoc cad0 nc a b c d e f g h j
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 4 - n pin layout (AK4640vn) min mout2 nc nc mout - mout+ auxin - auxin+ beepm mutet hpl hpr hvss hvdd spn spp m/s micout nc ext mpe mpi int vcom avss avdd nc mcko bick lrck sdto sdti i2c cdto cdti/sda top view 40 41 42 43 44 45 46 47 48 39 38 37 1 26 25 24 23 22 21 20 19 18 xti/mcki 36 35 34 33 32 31 2 3 4 5 6 7 8 9 beepr beepl ain cclk/scl csn/cad1 pdn 49 50 51 17 16 15 xto dvss pvdd pvss vcoc dvdd 30 29 28 10 11 12 nc cad0 52 14 nc nc 27 13 AK4640
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 5 - n comparison with ak 4534, ak4538 1. function function ak4534 ak4538 AK4640 spk - amp output power at dac path 150mw 150mw 300mw dac digital filter stopband attenuation 43db 43db 59db aux input not available available available mout gain select not available available available path from ipga to analog output not available ava ilable available hp - amp mono mode not available available available stereo line out not available available not available mic detect not available available not available hp - amp power supply current (typ) 6.5ma 6.5ma 4ma spk - amp power s upply current (typ) 9ma 9ma 7ma package 52pin qfn (7.2mm x 7.2mm) 52pin qfn (7.2mm x 7.2mm) 52pin qfn (7.2mm x 7.2mm), 57pin bga (5mm x 5mm) 2. pin pin# ak4534 ak4538 AK4640vn 2 tst1 mdt nc 42 tst2 rout nc 43 tst3 lout nc 46 tst4 auxin - auxin - 47 t st5 auxin+ auxin+ 3. register addr data ak4534 ak4538 AK4640 00h d2 0 pmaux pmaux d4 0 pmlo 0 02h d4 0 micm micm d7 0 mogn mogn 03h d4 0 micl micl d5 0 auxl auxl d6 0 pslo 0 05h d2 0 hpm hpm d3 hplm hplm 0 d4 hprm hprm 0 07h d7 0 auxad a uxad 0eh d3 - 0 0 gn3 - 0 gn3 - 0 d6 - 4 0 atts2 - 0 atts2 - 0 d7 0 attm attm 0fh d0 - dtmic -
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 6 - pin/function (AK4640vg) no. pin name i/o function a1 nc - no connect. nc pin should be left floating. b1 ext i external microphone input pin c1 mpe o mic pow er supply pin for external microphone c2 mpi o mic power supply pin for internal microphone d1 int i internal microphone input pin d2 vcom o common voltage output pin, 0.45 x avdd bias voltage of adc inputs and dac outputs. e1 avss - analog ground pin e2 avdd - analog power supply pin f2 avdd - analog power supply pin f1 pvdd - pll power supply pin g2 pvss - pll ground pin g1 vcoc o output pin for loop filter of pll circuit this pin should be connected to pvss with one resistor and capacitor in ser ies. h1 cad0 i chip address 0 select pin j1 nc - no connect. nc pin should be left floating. j2 pdn i power - down mode pin ? h ? : power up, ? l ? : power down reset and initializes the control register. csn i chip select pin (i2c pin = ? l ? ) h2 cad1 i chip address 1 select pin (i2c pin = ? h ? ) cclk i control data clock pin (i2c pin = ? l ? ) h3 scl i control data clock pin (i2c pin = ? h ? ) cdti i control data input pin (i2c pin = ? l ? ) j3 sda i/o control data input pin (i2c pin = ? h ? ) h4 cdto o control data output pin (i2c pin = ? l ? ) j4 i2c i control mode select pin ? h ? : i 2 c bus, ? l ? : 4 - wire serial h5 sdti i audio serial data input pin j5 sdto o audio serial data output pin j6 lrck i /o input / output channel clock pin h6 bick i/o audio serial data clock pin h7 nc - no connect. nc pin should be left floating. j7 mcko o master clock output pin h8 dvdd - digital power supply pin
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 7 - no. pin name i/o function j9 nc - no connect. nc pin should be left floating. j8 dvss - digital ground pin g8 xto o x ? t al output pin xti i x ? tal input pin h9 mcki i external master clock input pin g9 m/s i master / slave mode pin ? h ? : master mode, ? l ? : slave mode f8 spp o speaker amp positive output pin f9 spp o speaker amp positive output pin e8 spn o speaker amp negative output pin e9 spn o speaker amp negative output pin d8 hvdd - headphone/speaker amp power supply pin d9 hvdd - headphone/speaker amp power supply pin c8 hvss - headphone/speaker amp ground pin c9 hvss - headphone/speaker amp ground pin b9 h pr o rch headphone amp output pin a9 nc - no connect. nc pin should be left floating. a8 hpl o lch headphone amp output pin b8 mutet o mute time constant control pin connected to hvss pin with a capacitor for mute time constant. b7 nc - no connect. nc pin should be left floating. a7 min i alc2 input pin a6 mout2 o analog mixing output pin b6 mout - o mono line negative output pin a5 mout+ o mono line positive output pin b5 auxin - i mono aux negative input pin b4 auxin+ i mono aux positive input pin a4 beepm i mono beep signal input pin b3 beepr i rch stereo beep signal input pin a3 beepl i lch stereo beep signal input pin b2 ain i analog input pin a2 micout o microphone analog output pin c3 nc - no connect. nc pin should be left floating. note: all input pins except analog input pins (int, ext, ain, min, auxin+, auxin - , beepm, beepl, and beepr ) should not be left floating.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 8 - pin/function (AK4640vn) no. pin name i/o function 1 micout o microphone analog output pin 2 nc - no connect. nc pin should be left floating. 3 ext i external microphone input pin ( mon o input) 4 mpe o mic power supply pin for external microphone 5 mpi o mic power supply pin for internal microphone 6 int i internal microphone input pin ( mon o input) 7 vcom o co mmon voltage output pin, 0.45 x avdd bias voltage of adc inputs and dac outputs. 8 avss - analog ground pin 9 avdd - analog power supply pin 10 pvdd - pll power supply pin 11 pvss - pll ground pin 12 vcoc o output pin for loop filter of pll circuit t his pin should be connected to pvss with one resistor and capacitor in series. 13 nc - no connect. nc pin should be left floating. 14 cad0 i chip address 0 select pin 15 pdn i power - down mode pin ? h ? : power up, ? l ? : power down reset and initializes the control register. csn i chip select pin (i2c pin = ? l ? ) 16 cad1 i chip address 1 select pin (i2c pin = ? h ? ) cclk i control data clock pin (i2c pin = ? l ? ) 17 scl i control data clock pin (i2c pin = ? h ? ) cdti i control data input pin (i2c pin = ? l ? ) 18 sda i/o control data input pin (i2c pin = ? h ? ) 19 cdto o control data output pin (i2c pin = ? l ? ) 20 i2c i control mode select pin ? h ? : i 2 c bus, ? l ? : 4 - wire serial 21 sdti i audio serial data input pin 22 sdto o audio serial data output pin 23 lrck i /o input / output channel clock pin 24 bick i/o audio serial data clock pin 25 mcko o master clock output pin 26 nc - no connect. nc pin should be left floating.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 9 - no. pin name i/o function 27 nc - no connect. nc pin should be left floating. 28 d vdd - digital power supply pin 29 dvss - digital ground pin 30 xto o x ? tal output pin xti i x ? tal input pin 31 mcki i external master clock input pin 32 m/s i master / slave mode pin ? h ? : master mode, ? l ? : slave mode 33 spp o speaker amp positive output pin 34 spn o speaker amp negative output pin 35 hvdd - headphone amp power supply pin 36 hvss - headphone amp ground pin 37 hpr o rch headphone amp output pin 38 hpl o lch headphone amp output pin 39 mutet o mute time constant control pin conn ected to hvss pin with a capacitor for mute time constant. 40 min i alc2 input pin 41 mout2 o analog mixing output pin 42 nc - no connect. nc pin should be left floating. 43 nc - no connect. nc pin should be left floating. 44 mout - o mono line negativ e output pin 45 mout+ o mono line positive output pin 46 auxin - i mono aux negative input pin 47 auxin+ i mono aux positive input pin 48 beepm i mono beep signal input pin 49 beepr i rch stereo beep signal input pin 50 beepl i lch stereo beep signal input pin 51 ain i analog input pin 52 nc - no connect. nc pin should be left floating. note: all input pins except analog input pins (int, ext, ain, min, auxin+, auxin - , beepm, beepl, and beepr ) should not be left floating.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 10 - a bsolute maximum ratin gs (avss , dvss, pvss, hvss= 0v ; note 1 ) parameter symbol min max units power supplies: analog avdd - 0.3 4.6 v digital dvdd - 0.3 4.6 v pll pvdd - 0.3 4.6 v headphone - amp / speaker - amp hvdd - 0.3 4.6 v |avss ? pvss| ( note 2 ) d gnd1 - 0.3 v |avss ? dvss| ( note 2 ) d gnd2 - 0.3 v |avss ? hvss| ( note 2 ) d gnd3 - 0.3 v input current, any pin exce pt supplies iin - 10 ma analog input voltage vina - 0.3 avdd+0.3 v digital input voltage vind - 0.3 dvdd+0.3 v ambient temperature (powered applied) ta - 10 70 c storage temperature tstg - 65 150 c note 1 . all voltages with resp ect to ground . note 2 . avss, dvss, pvss and hvss must be connected to the same analog ground plane . warning : operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at th ese extremes. recommended operating conditions ( avss, dvss, pvss , hvss =0v ; note 1 ) parameter symbol min typ max units power supplies analog avdd 2.4 3.3 3.6 v ( note 3 ) digital dvdd 2.4 3.3 avdd v pll pvdd 2.4 3.3 avdd v hp / spk - amp hvdd 2.4 3.3 3.6 v note 1 . all voltages with resp ect to ground . note 3 . the power up sequence between avdd, dvdd, hvdd and pvdd is not cr itical. it is recommended that dvdd and pvdd are the same voltage as avdd in order to reduce the current at power down mode. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 11 - analog characteristics ( ta=25 c ; avdd , dvdd, pvdd, hvdd = 3.3v ; a vss=dvss=pvss=hvss=0v; fs=4 4.1k hz , bick=64fs; signal frequency =1khz ; 16bit data; measurement frequency=20hz ~ 20khz; unless otherwise specified) parameter min typ max units mic amplifier: input resistance tbd 30 tbd k w (mgain bit = ? 0 ? ) - 0 - db gai n (mgain bit = ? 1 ? ) - 20 - db mic power supply: output voltage ( note 4 ) tbd 2.47 tbd v load resistance 2 - - k w load capacitance - - 30 pf input pga characteristics: input resistance ( note 5 ) tbd 10 tbd k w step size tbd 0.5 tbd db gain control range - 8 - +27.5 db adc analog input characteristics: mic gain=20db, ipga=0db, alc1=off, mic ? ipga ? adc resolution - - 16 bits input v oltage ( note 6 ) tbd 0.198 tbd vpp s/(n+d) ( - 1dbfs) tbd 79 - dbfs d - range ( - 60dbfs, a - weighted) tbd 83 - db s/n (a - weighted) tbd 83 - db dac characteristics: resolution - - 16 bits mono line output characteristi cs: r l =20k w , dac ? mout+/mout - pins output voltage mogn bit = ? 1 ? , - 17db - 0.31 - vpp ( note 7 ) mogn bit = ? 0 ? , +6db 3.56 3.96 4.36 vpp s/(n+d) ( - 3dbfs) mogn bit = ? 1 ? , - 17db - 76 dbfs mogn bit = ? 0 ? , +6db 79 89 dbfs s/n (a - weighted) mogn bit = ? 1 ? , - 17db - 79 db mogn bit = ? 0 ? , +6db 85 95 db load resistance mogn bit = ? 1 ? , - 17db 2 k w mogn bit = ? 0 ? , +6db 20 k w load capacitance 30 pf note 4 . output voltage is proporti onal to avdd voltage. vout = 0.75 x avdd(typ). note 5 . when ipga gain is changed, this typical value changes between 8k w and 11k w . note 6 . input voltage is proportional to avdd voltage. vin = 0.06 x avdd (typ). note 7 . output voltage is proportional to avdd voltage. vout = 1.2 x avdd(typ)@mogn bit = ? 0 ? at full - differential output. vout = 0.6 x avdd(typ) @mogn bit = ? 0 ? at single - end output.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 12 - parameter min typ max units headphone - amp char acteristics: r l =22.8 w , dac ? hpl/hpr pins, datt=0db output voltage ( note 8 ) tbd 1.92 tbd vpp s/(n+d) ( - 3dbfs) tbd 70 - dbfs s/n (a - weighted) tbd 90 - db interchannel isolation tbd 85 - db interchannel gain m ismatch - 0.1 tbd db load resistance 20 - - w (c1 in figure 2 ) - - 30 pf load capacitance (c2 in figure 2 ) - - 300 pf speaker - amp characteristics: r l =8 w , btl, dac ? mou t2 pin ? min pin ? spp/spn pins, alc2=off output voltage ( - 3dbfs) tbd 3.09 tbd vpp ( note 9 ) (0dbfs) - 4.38 - vpp ( - 3dbfs, po=150mw) tbd 64 - db (0dbfs, po=300mw) - 20 - db s/(n+d) (alc2=on, po=250mw) - 60 - db s/n (a - weighted) tbd 90 - db load resistance 8 - - w load capacitance - - 30 pf beep input: beepl, beepr, beepm pins maximum input voltage ( note 10 ) - - 1.98 vpp feedback resistance tbd 20 tbd k w mon o inp ut: min pin maximum input voltage ( note 11 ) - - 1.98 vpp input resistance ( note 12 ) tbd 24 tbd k w mon o output: r l =10k w , dac ? mix ? mout2 pin output voltage ( note 13 ) - 1.94 - vpp load resistance 10 - - k w load capacitance ( note 14 ) - - 30 pf note 8 . output voltage is proportional to avdd voltage. vout = 0.582 x avdd(typ). note 9 . output voltage is proportional to a vdd voltage. vout = 0.936 x avdd(typ)@ - 3dbfs at full - differential output. note 10 . beep - amp can ? t output more than this maximum voltage. note 11 . maximum input voltage is proportional to avdd voltage. vin = 0.6 x avdd(typ). note 12 . when alc2 gain is changed, this typical value changes between 22k w and 26k w . note 13 . output voltage is propor tional to avdd voltage. vout = 0.588 x avdd(typ). note 14 . when the output pin drives a capacitive load, a resistor should be added in series between the output pin and capacitive load. hpl/hpr pin hp-amp 47 m f c1 16 w c2 > 6.8 w figure 2 . headphone - amp output circuit
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 13 - parameter min typ max units aux input: auxin+, auxin - pins maximum input voltage ( note 15 ) - - 1.98 vpp input resistance tbd 40 tbd k w step size tbd 3 tbd d b gain control range - 21 - +24 db power supplies power up (pdn pin = ? h ? ) all circuit power - up: avdd+dvdd ( note 16 ) - 16 tbd ma pvdd - 1.2 tbd ma hvdd: hp - amp normal operation no output ( note 17 ) - 4 tbd ma hvdd: spk - amp normal operation no output ( note 18 ) - 7 tbd ma power down (pdn pin = ? l ? ) ( note 19 ) avdd+ dvdd - 10 tbd m a pvdd - 10 tbd m a hvdd - 10 tbd m a note 15 . maximum input voltage is proportional to avdd voltage. vin = 0.6 x avdd(typ). note 16 . pmmic=pmadc=pmdac=pmmo=pmspk=pmhpl=pmhpr=pmvcm=pmpll=pmxt l=pmbpm= pmbps= pmaux= ? 1 ? , mcko= ? 1 ? and master mode. avdd=10ma (typ.), dvdd=6ma (typ.). avdd=10ma (typ.), dvdd=4ma (typ.) at mcko= ? 0 ? in slave mode . note 17 . pmmic=pmadc=pmdac=pmmo=pmhpl=pmhpr=pmvcm=pmpll= pmxtl=pmbpm=pmbps= pmaux= ? 1 ? and pmspk= ? 0 ? . note 18 . pmmic=pmadc=pmdac=pmmo=pmspk=pmvcm=pmpll=pmxtl= pmbpm =pmbps=pmaux= ? 1 ? and pmhpl=pmhpr= ? 0 ? . note 19 . all digital input pins are fixed to dvdd or dvss.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 14 - filter characteristics ( ta= - 10 ~ 70 c ; a vdd , d vdd, pvdd, hvdd = 2.4 ~ 3.6v; fs=4 4.1k hz ; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 20 ) 0.1db pb 0 - 17.4 khz - 1.0db - 20.0 - kh z - 3.0db - 21.1 - khz stopband sb 25.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 65 - - db group delay ( note 21 ) gd - 17.0 - 1/fs group delay distortion d gd - 0 - m s adc digital fi lter (hpf): frequency response ( note 20 ) - 3.0db fr - 3.4 - hz - 0.5db - 10 - hz - 0.1db - 22 - hz dac digital filter: passband ( note 20 ) 0.1db pb 0 - 19.6 khz - 0.7db - 20.0 - khz - 6.0db - 22.05 - khz stopband sb 25.2 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 59 - - db group delay ( note 21 ) gd - 16.8 - 1/fs dac digital filter + scf: frequency response: 0 ~ 20.0khz fr - 1.0 - db boost filter: ( note 22 ) min 20hz fr - 5.74 - db 100hz - 2.92 - db 1khz - 0.0 - db mid 20hz fr - 5.94 - db 100hz - 4.71 - db 1khz - 0.14 - db max 20hz fr - 16.04 - db 100hz - 10.55 - db frequency response 1khz - 0.3 - db note 20 . the passband and stopband frequencies scale with fs ( system sampling rate ) . for example, adc is pb=0.454*fs ( @-1.0db ) , dac is pb=0.454*fs ( @-0. 0 1db ) . note 21 . the calculat ed delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16 - bit data of both channels from the input register to the output register of the adc. this time include s the group delay of the hpf . for the dac, this time is from setting the 16 - bit data of both channels from the input register to the output of analog signal. note 22 . these frequency response s scale with fs . if a high - level and low f requency signal is input, the analog output clips to the full - scale.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 15 - dc characteristics ( ta= - 10 ~ 70 c ; avdd , dv d d, pvdd, hvdd=2.4 ~ 3.6 v ) parameter symbol min typ max units high - level input voltage vih 70%dvdd - - v low - level input voltage vil - - 30%dvdd v input voltage at ac coupling ( note 23 ) vac 50%dvdd - - v high - level output voltage (iout= - 200 m a) voh dvdd - 0.2 - - v low - level output voltage (except sda pin: iout=200 m a) vol - - 0.2 v (sda pin: iout=3ma) vol - - 0.4 v input leakage current iin - - 10 m a note 23 . when ac coupled capacitor is connected to mcki pin. switching characteristics ( ta= - 10 ~ 70 c ; avdd, dvdd, pvdd, hvdd = 2.4 ~ 3.6 v ; c l =2 0pf ) parameter symbol min t yp max units master clock timing crystal resonator frequency 11.2896 - 12.288 mhz external clock frequency fclk 2.048 - 12.288 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns ac p ulse width ( note 24 ) tacw 0.4/fclk - - ns mcko output frequency fmck 0.256 - 12.288 mhz duty cycle: except fs=32khz dmck 40 50 60 % fs=32khz at 256fs ( note 25 ) dmc k - 33 - % lrck timing frequency fs 8 - 48 khz duty cycle slave mode duty 45 - 55 % master mode duty - 50 - % audio interface timing slave mode bick period tbck 312.5 - - ns bick pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns lrck edge to bick ? - ? ( note 26 ) tlrb 50 - - ns bick ? - ? to lrck edge ( note 26 ) tblr 50 - - ns lrck to sdto (msb) (except i 2 s mode) tlrs - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns master mode bick frequency (bf bit = ? 0 ? ) fbck - 64fs - hz (bf bit = ? 1 ? ) fbck - 32fs - hz bick duty dbck - 50 - % bick ? ? to lrck tmblr - 80 - 80 ns bick ? ? to sdto tbsd - 80 - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 24 . pulse width to ground level when mcki is connected to a capacitor in series and a resistor is connected to ground ( refer to figure 4 ). note 25 . pmpll bit = ? 1 ? . note 26 . bick rising edge must not occur at the same time as lrck edge.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 16 - parameter symbol min t yp max units control interface timing ( 4 - wire serial mode): cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ? h ? time tcsw 150 - - ns csn ? ? to cclk ? - ? tcss 50 - - ns cclk ? - ? to csn ? - ? tcsh 50 - - ns cdto delay tdcd - - 50 ns csn ? - ? to cdto hi - z tccz - - 70 ns control interface timing (i 2 c bus mode): scl clock frequency fscl - - 100 khz bus free time between transmissions tbuf 4.7 - - m s star t condition hold time (prior to first clock pulse) thd:sta 4.0 - - m s clock low time tlow 4.7 - - m s clock high time thigh 4.0 - - m s setup time for repeated start condition tsu:sta 4.7 - - m s sda hold time from scl falling ( note 27 ) thd:dat 0 - - m s sda setup time from scl rising tsu:dat 0.25 - - m s rise time of both sda and scl lines tr - - 1.0 m s fall time of both sda and scl lines tf - - 0.3 m s setup time for stop condition tsu:sto 4.0 - - m s pul se width of spike noise suppressed by input filter tsp 0 - 50 ns reset timing pdn pulse width ( note 28 ) tpd 150 - - ns pmadc ? - ? to sdto valid ( note 29 ) tpdv - 2081 - 1/fs note 27 . data must be held long enough to bridge the 300ns - transition time of scl. note 28 . the AK4640 can be reset by the p dn pin = ? l ? . note 29 . this is the count of lrck ? - ? fr om the pmadc bit = ? 1 ? . purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 17 - n timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil mcko dmck dmck 50%dvdd fmck figure 3 . clock timing mcki input measurement point agnd tacw t acw agnd 1/fclk 1000pf 100k w vac figure 4 . mcki ac coupling timing
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 18 - lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih figure 5 . au dio interface timing (slave mode) lrck vih vil bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tmblr dbck figure 6 . audio interface timing (master mode)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 19 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w cdto hi-z figure 7 . write/read command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 cdto hi-z d2 figure 8 . write data input timing
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 20 - csn vih vil cclk vih vil cdti vih vil a0 cdto a1 50%dvdd tdcd d7 d6 hi-z figure 9 . read data output timing 1 csn vih vil tcsh cclk vih vil cdti vih tcsw vil cdto 50%dvdd d2 d1 d0 tccz hi-z figure 10 . read data output tim ing 2
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 21 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 11 . i 2 c bus mode timing csn vih vil tpdv sdto tpd 50%dvdd pdn vil figure 12 . power down & reset timing
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 22 - operation overview n master clock source the AK4640 require s a master clock (mcki). this master clock is input to the AK4640 by connecting a x ? tal oscillator to xti and xto pins or by inputting an external cmos - level clock to the xti pin or by inputting an external clock that is greater than 50% of the dvdd level to the xti pin through a capacitor. when using a x ? tal oscillator , there should be capacitors between xti/xto pins and dvss. when using an external clock, there are two choices: direct, where an external clock is input directly to the xti pin and indirect , where the external clock is input through a capacitor. master clock status pmxtl bit mckpd bit x ? tal oscillator ( figure 13 ) oscillator on 1 0 oscillator off 0 1 external clock direct input ( figure 14 ) clock is input to mcki pin. 0 0 mcki pin is fixed to ? l ? . 0 0/1 mcki pin is fixed to ? h ? . 0 0 mcki pin is hi - z 0 1 ac coupling input ( figure 15 ) clock is input to mcki p in. 1 0 clock isn?t input to mcki pin. 0 1 table 1 . master clock status by pmxtl bit and mckpd bit (1) x ? tal oscillator xti xto AK4640 25k w (typ) mckpd = "0" pmxtl = "1" c c figure 13 . x ? tal mode note: the capacitor values depend on the x ? tal oscillator used. (c : typ. 10 ~ 30pf)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 23 - (2) external clock direct input xti xto AK4640 25k w (typ) mckpd = "0" pmxtl = "0" external clock figure 14 . external clock mode (input : cmos level) note: this clock level must not exceed dvdd level. (3) ac coupling input xti xto AK4640 25k w (typ) mckpd = "0" pmxtl = "1" external clock c figure 15 . external clock mode (input : 3 50%dvdd) note: this clock level must n o t exceed dvdd level. (c : 0.1 m f)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 24 - n system clock (1) pll mode (pmpll bit = ? 1 ? ) a fully integrated analog phase locked loop (pll) generates a clock that is selected by the pll1 - 0 and fs2 - 0 bits (see table 2 and table 3 ). the frequency of the mcko output is selectable via the ps1 - 0 bits registers as defined in table 4 and the mcko output enable is controlled by the mcko bit . the pll should be powered - up after the x ? tal oscillator becomes stable or external master clock is inputted. it takes x ? tal oscillator 20ms(typ) to be stable after pmxtl bit = ? 1 ? . the pll needs 40ms lock time, whenever the sampling frequency changes or the pll is powered - up (pmpll bit= ? 0 ? ? ? 1 ? ). if the sampling frequency is changed when the adc or the dac operates (pmadc bit = ? 1 ? or pmdac bit = ? 1 ? ), the click noise may occu r. the click noise of headphone and speaker amps can be avoided by using the mute sequence examples ( figure 51 and figure 52 , respectively). lrck and bick are output from th e AK4640 in master mode. when the clock input to mcki pin stops during normal operation (pmpll bit = ? 1 ? ), the internal pll continues to oscillate (a few mhz), and lrck and bick outputs go to ? l ? (see table 5 ). in slave mode, the l rck input should be synchronized with mcko. the master clock (mcki) should be synchronized with sampling clock (lrck). the phase between these clocks does not matter. lrck and bick must be present whenever the AK4640 is operating (pmadc bit = ? 1 ? or pmdac bit = ? 1 ? ). if these clocks are not provided, the AK4640 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK4640 in power - down mode (pmadc bit = pmdac bit = ? 0 ? ). mode pll1 p ll0 mcki 0 0 0 12.288mhz default 1 0 1 11.2896mhz 2 1 0 12mhz 3 1 1 n/a table 2 . mcki input frequency (pll mode) fs2 fs1 fs0 sampling frequency 0 0 0 44.1khz default 0 0 1 22.05khz 0 1 0 11.025khz 0 1 1 48khz 1 0 0 32khz 1 0 1 24khz 1 1 0 16khz 1 1 1 8khz table 3 . sampling frequency (pll mode) mode ps1 ps0 mcko 0 0 0 256fs default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 4 . mcko frequency (pll mode, m cko bit = ? 1 ? )
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 25 - master mode (m/s pin = ? h ? ) power up power down pll unlock mcki pin frequency set by pll1 - 0 bits (refer to table 2 ) refer to table 1 frequency set by pll1 - 0 bits (refer to table 2 ) mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : unsettling bick pin bf bit = ? 0 ? : 64fs output bf bit = ? 1 ? : 32fs output ? l ? ? l ? lrck pin output ? l ? ? l ? table 5 . clock operation at master mode (pll mode) slave mode (m/s pin = ? l ? ) power up power down pll unlock mcki pin frequency set by pll1 - 0 bits (refer to table 2 ) refer to table 1 frequency set by pll1 - 0 b its (refer to table 2 ) mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : unsettling bick pin input fixed to ? l ? or ? h ? externally input lrck pin input fixed to ? l ? or ? h ? externally i nput table 6 . clock operation at slave mode (pll mode) (2) external mode (pmpll bit = ? 0 ? ) when the pmpll bit = ? 0 ? , the AK4640 works in external clock mode. the mcko pin outputs a buffered clock of mcki input. for example, when mck i = 256fs, the sampling frequency is changeable from 8khz to 48khz ( table 7 ). the mcko bit controls mcko output enable . the frequency of mcko is selectable via register the ps1 - 0 bits as defined in table 8 . i f ps1 - 0 bits are changed before lrck is input, mcko is not output. ps1 - 0 bits should be changed after lrck is input in slave mode. ). if the master clock frequency is changed when the adc or the dac operates (pmadc bit = ? 1 ? or pmdac bit = ? 1 ? ), the click noise may occur. the click noise of headphone and speaker amps can be reduced by using the mute sequence examples ( figure 51 and figure 52 , respectively). lrck and bick are output from the AK4640 in master mode. the clock to the mcki pin must n o t stop during normal operation (pmpll bit = ? 1 ? ). if this clock is not provided, the AK4640 may draw excess current due to its use of internal dynamically refreshed logic. if the exter nal clocks are not present, place the AK4640 in power - down mode (pmadc bit = pmdac bit = ? 0 ? ). mcki, bick and lrck clocks are required in slave mode. the master clock (mcki) should be synchronized with sampling clock (lrck). the phase between these clocks does not matter. lrck and bick should always be present whenever the AK4640 is in normal operation (pmadc bit = ? 1 ? or pmdac bit = ? 1 ? ). if these clocks are not provided, the AK4640 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK4640 in power - down mode (pmadc bit = pmdac bit = ? 0 ? ). mode fs1 fs0 sampling frequency (fs) mcki 0 0 0 8khz ~ 48khz 256fs default 1 0 1 8khz ~ 24khz 512fs 2 1 0 8khz ~ 12khz 1024fs 3 1 1 8k hz ~ 48khz 256fs table 7 . sampling frequency select (ext mode)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 26 - mode ps1 ps0 mcko 0 0 0 256fs default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 8 . mcko frequency (ext mode, mcko bit = ? 1 ? ) maste r mode (m/s pin = ? h ? ) power up power down mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? bick pin bf bit = ? 0 ? : 64fs output bf bit = ? 1 ? : 32fs output ? l ? lrck pin output ? l ? table 9 . clock operation at master mod e (ext mode) slave mode (m/s pin = ? l ? ) power up power down mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? bick pin input fixed to ? l ? or ? h ? externally lrck pin input fixed to ? l ? or ? h ? externally table 10 . cloc k operation at slave mode (ext mode) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out - of - band noise. when the out - of - band noise can be improved by using higher frequency of the master clock. the s/n of t he dac output through headphone amp at fs=8khz is shown in table 11 . mcki s/n (fs=8khz, a - weighted) 256fs 84db 512fs 88db 1024fs 88db table 11 . relationship between mcki and s/n of hp - amp n master mode /slave mode the m/s pin selects either master or slave modes. m/s pin = ? h ? selects master mode and ? l ? selects slave mode. the AK4640 outputs mcko, bick and lrck in master mode. the AK4640 outputs only mcko in slave mode, while bick and lrck must be inpu t separately. mode mcko bick / lrck slave mode mcko = output bick = input lrck = input master mode mcko = output bick = output lrck = output table 12 . master mode/slave mode
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 27 - n system reset upon power - up, reset the AK4640 by bringing the pdn pin = ?l?. this ensures that all internal registers reset to their initial value s . the adc enters an initializ ation cycle that starts when the pmadc bit is changed from ? 0 ? to ? 1 ? . the initializ ation cycle time is 2081/fs, or 47.2ms@fs=44 .1khz . during the initializ ation cycle, the adc digital data outputs of both channels are forced to a 2's compliment, ?0?. the adc output reflects the analog input signal after the initializ ation cycle is complete . the dac does n o t require an initializ atio n cycl e. n audio interface format three types of data formats are available and are selected by setting the dif1 - 0 bits ( table 13 ). in all modes, the serial data is msb first, 2 ? s complement format. the sdto is c locked out on the falling edge of bick and the sdti is latched on the rising edge. all data formats can be used in both master and slave modes. lrck and bick are output from AK4640 in master mode, but must be input to AK4640 in slave mode. if 16 - bit data t hat adc outputs is converted to 8 - bit data by removing lsb 8 - bit, ? - 1 ? at 16bit data is converted to ? - 1 ? at 8 - bit data. and when the dac playbacks this 8 - bit data, ? - 1 ? at 8 - bit data will be converted to ? - 256? at 16 - bit data and this is a large offset. t his offset can be removed by adding the offset of ? 128 ? to 16 - bit data before converting to 8 - bit data. mode dif1 dif0 sdto (adc) sdti (dac) bick figure 0 0 0 msb justified lsb justified 3 32fs figure 16 1 0 1 m sb justified msb justified 3 32fs figure 17 2 1 0 i 2 s i 2 s 3 32fs figure 18 default 3 1 1 n/a n/a n/a - table 13 . audio interface format lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 13 13 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 13 1 0 15 15 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 0 1 15 15 2 1 0 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data figure 16 . mode 0 timing
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 28 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 13 13 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 13 1 0 15 15 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 15 15 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 1 0 13 1 0 15 figure 17 . mode 1 timing lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 1 0 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 don't care 2 15 1 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 2 1 14 2 1 8 8 8 0 0 0 0 figure 18 . mode 2 timing n digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut - off frequency of the hpf is 3.4hz (@fs=44.1khz) and scales with sampling rate (fs).
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 29 - n mic gain amplifier AK4640 has a gain amplifier for microphone input. this gain is 0db or +20db, selected by the mgain bit ( table 14 ). the typical input impedance is 30k w . mgain bit input gain 0 0db 1 +20db default table 14 . mic input gain n mic power the mpi and mpe pins supply p ower for the microphone. these output voltages are 0.75 x avdd (typ) and the load resistance is 2k w (min). no capacitor must not be connected directly to mpi and mpe pins. mpi/mpe 3 2k w mic power microphone int/ext mic - amp figure 19 . mic power
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 30 - n manua l mode the AK4640 becomes a manual mode at alc1 bit = ? 0 ? . this mode is used in the case shown below. 1. after exiting reset state, set up the registers for the alc1 operation (ztm1 - 0, lmth and etc) 2. when the registers for the alc1 operation (limiter p eriod, recovery period and etc) are changed. for example ; when the change of the sampling frequency . 3. when ipga is used as a manual volume. when writing to the ipga6 - 0 bits continually , the control register should be written by an interval more than ze ro crossing timeout. n mic - alc operation the alc (automatic level control) of mic input is done by alc1 block when alc1 bit is ? 1 ? . (1) alc1 limiter operation when the alc1 limiter is enabled, and ipga output exceeds the alc1 limiter detection level (lmth ), the ipga value is attenuated by the amount defined in the alc1 limiter att step (lmat1 - 0 bits) automatically. when the zelm bit = ? 1 ? , the timeout period is set by the ltm1 - 0 bits. the operation for attenuation is done continuously until the input sign al level becomes lmth or less. if the alc1 bit does not change into ? 0 ? after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds lmth. when the zelm bit = ? 0 ? , the timeout period is set by the ztm1 - 0 bits. this enables the zero - crossing attenuation function so that the ipga value is attenuated at the zero - detect points of the waveform. (2) alc1 recovery operation the alc1 recovery refers to the amount of time that the AK4640 will allow a signal to exc eed a predetermined limiting value prior to enabling the limiting function. the alc1 recovery operation uses the wtm1 - 0 bits to define the wait period used after completing an alc1 limiter operation. if the input signal does not exceed the ? alc1 recovery w aiting counter reset level ? , the alc1 recovery operation starts. the ipga value increases automatically during this operation up to the reference level (ref6 - 0 bits). the alc1 recovery operation is done at a period set by the wtm1 - 0 bits. zero crossing is detected during wtm1 - 0 period, the alc1 recovery operation waits wtm1 - 0 period and the next recovery operation starts. during the alc1 recovery operation, when lch or rch input signal level exceeds the alc1 limiter detection level (lmth), the alc1 recover y operation changes immediately into an alc1 limiter operation. in the case of (recovery waiting counter reset level) (ipga output level) < (limiter detection level ) during the alc1 recovery operation, the wait timer for the alc1 recovery operation is r eset. therefore, in the case of (ipga output level) < (recovery waiting counter reset level), the wait timer for the alc1 recovery operation starts. the alc1 operation corresponds to the impulse noise. when the impulse noise is input, the alc1 recovery op eration becomes faster than a normal recovery operation.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 31 - (3) example of alc1 operation table 15 shows the examples of the alc1 setting. in case of this examples, alc1 operation starts from 0db. fs=8khz fs=1 6khz fs=44.1khz register name comment data operation data operation data operation lmth limiter detection level 1 - 4dbfs 1 - 4dbfs 1 - 4dbfs ltm1 - 0 limiter operation period at zelm = 1 00 don ? t use 00 don ? t use 00 don ? t use zelm limiter zero crossing detection 0 enable 0 en able 0 enable ztm1 - 0 zero crossing timeout period 00 16ms 01 16ms 10 11.6ms wtm1 - 0 recovery waiting period *wtm1 - 0 bits should be the same data as ztm1 - 0 bits 00 16ms 01 16ms 10 11.6ms ref6 - 0 maximum gain at recovery operation 47h +27.5db 47h +27.5db 47 h +27.5db ipga6 - 0 gain of ipga before alc1 operation start 10h 0db 10h 0db 10h 0db lmat1 - 0 limiter att step 00 1 step 00 1 step 00 1 step ratt recovery gain step 0 1 step 0 1 step 0 1 step alc1 alc1 enable bit 1 enable 1 enable 1 enable table 15 . example of the alc1 setting the following registers should not be changed during the alc1 operation. these bits should be changed after the alc1 operation is finished by alc1 bit = ? 0 ? or pmmic bit = ? 0 ? . ltm1 - 0, lmth, lmat1 - 0, wtm1 - 0, ztm1 - 0, ratt, ref6 - 0, zelm bits ipga gain at alc1 operation start can be changed from the default value of ipga6 - 0 bits while pmmic bit is ? 1 ? and alc1 bit is ? 0 ? . when alc1 bit is changed from ? 1 ? to ? 0 ? , ipga holds the last gain value set by alc1 op eration. manual mode * the value of ipga should be t he same or smaller than ref ? s wr (ztm1 - 0, wtm1 - 0, ltm1 - 0) wr (ref6 - 0) wr (ipga6 - 0) alc1 operation wr (alc1= ? 1 ? , lmat1 - 0, ratt, lmth, zelm) example: limiter = zero crossing enable recovery cycle = 16ms @ fs= 8khz limiter and recovery step = 1 maximum gain = +27.5db limiter detection level = - 4dbfs alc2 bit = ? 1 ? ( default ) (1) addr=08h, data=00h (2) addr=0ah, data=47h (4) addr=09h, data=61h (3) addr=0bh, data=10h note : wr : write figure 20 . registers set - up sequence at alc1 operation
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 32 - n de - emphasis filter the AK4640 includes the digital de - emphasis filter (tc = 50/15 m s) by iir filter. s etting the de m1 - 0 bits enables the de - emphasis filter ( table 16 ). dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 16 . de - emphasis control n bass boost function the bst1 - 0 bits control the amount of low frequency boost applied to the dac output signal ( table 17 ) . if the bst1 - 0 bits are set to ? 10 ? (mid level), use a 47 m f capacitor for ac - coupling. if the boosted signal exceeds full scale, the analog output clips to the full scale. figure 21 shows the boost frequency response at ? 20db signal input. figure 21 . boost frequency (fs=44.1khz) bst1 bst0 mode 0 0 off default 0 1 min 1 0 mid 1 1 max table 17 . low frequency boost control boost frequency (fs=44.1khz) -25 -20 -15 -10 -5 0 0.01 0.1 1 10 frequency [khz] output level [db] min mid max
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 33 - n digital attenuator the AK4640 has a channel - independent digital attenuator (256 levels, 0.5db step, mute). the attenuation level of each channel can be set by the attl/r7 - 0 bits. when the dattc bit = ? 1 ? , the attl7 - 0 bits control both lch and rch attenuation levels. when the dattc bit = ? 0 ? , the attl7 - 0 bits control lch level and attr7 - 0 bits control rch level. this attenuator has a soft transition function. it takes 1061/fs(24ms@fs=44.1kh z) from 00h(0db) to ffh(mute). attl/r7 - 0 attenuation 00h 0db default 01h - 0.5db 02h - 1.0db 03h - 1.5db : : : : fdh - 126.5db feh - 127.0db ffh mute ( - ) table 18 . datt attenuation table n soft mute soft mute oper ation is performed in the digital domain. when the smute bit goes to a ? 1 ? , the output signal is attenuated by - ( ? 0 ? ) during the cycle set by the tm1 - 0 bits. when the smute bit is returned to ? 0 ? , the mute is cancelled and the output attenuation graduall y changes to 0db during the cycle set of the tm1 - 0 bits. if the soft mute is cancelled within the cycle set by the tm1 - 0 bits after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the sig nal source without stopping the signal transmission ( figure 22 ). the soft mute function is independent of output volume and cascade connected between both functions. smute bit attenuation tm1-0 bit 0db - tm1-0 bit gd gd (1) (2) (3) analog output figure 22 . soft mute function (1) the output signal is attenuated until - ( ? 0 ? ) by the cycle set by the tm1 - 0 bits. (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within the cycle of setting the tm 1 - 0 bits, the attenuation is discounted and returned to 0db(the set value).
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 3 4 - n aux input stereo mixer volume auxin+ auxin - ? auxl ? mixer for adc ? auxad ? ? gn3 - 0 ? figure 23 . aux input aux input is differential input. the AK4640 has a volume for aux input. this volume is co ntrolled by gn3 - 0 bits as shown in table 19 . the AK4640 register control for gn3 - 0 does not offer any de - clicking function at volume setting change. gn3 - 0 gain (db) fh +24.0 eh +21.0 dh +18.0 : : 7h +0.0 default : : 2h - 15.0 1h - 18.0 0h - 21.0 table 19 . aux input gain setting
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 35 - n beep input when the bmbps bit is set to ? 1 ? , the stereo beep input is powered up. and when the bpshp bit is set to ? 1 ? , the input signals from th e beepl and beepr pins are mixed to headphone outputs. when the bpssp bit is set to ? 1 ? , the signal of (beepl + beepr)/2 is input to speaker - amp. when the bmbpm bit is set to ? 1 ? , mono beep input is powered up. and when the bpmhp bit is set to ? 1 ? , the inp ut signal from the beepm pin to headphone - amp. when the bpmsp bit is set to ? 1 ? , the signal from the beepm pin is input to speaker output. the external resisters ri adjust the signal level of each beep input that are mixed to headphone and speaker outputs. the signal from the beepm pin is mixed to the headphone - amp through a ? 20db gain stage. the signal from the beepm pin is mixed to the speaker - amp without gain. the internal feedback resistance is 20k w 30%. beepl ri rf beepr ri rf AK4640 beepm ri rf bpmhp spk mix hpl mix hpr mix bpshp bpshp -20db bpmsp bpssp 1/2 1/2 figure 24 . block diagram of beep pins (rf = 20k w 30%)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 36 - n headphone output power supply voltage for the headphone - amp is supplied from the hvdd pin and centered on the hvdd/2 voltage. the headphone output load resistance is min.20 w . when the pmhpl and pmhpr bits are ? 0 ? , the common voltage of headphone - amp falls and the outputs (hpl and hpr pins) go to ? l ? (hvss). when the pmhpl and pmhpr bits are ? 1 ? , the common voltage rises to hvdd/2. a capacitor between the mutet pin and ground reduces cl ick noise at power - up . [example] : a capacitor between the mutet pin and ground = 1.0 m f: time constant of rise/fall time: t = 100ms(typ) when hpl and hpr bits are ? 1 ? , the headphone - amp is powered - down, and the outputs (hpl and hpr pins) go to ? l ? (hvss) . pmhpl/r bit hpl/r bit hpl/r pin (1) (2) (4) (3) figure 25 . power - up/power - down timing for headphone - amp (1) headphone - amp power - up (hpl, hpr bit= ? 0 ? ). the outputs are still hvss. (2) headphone - amp common voltage rise up (pmhpl, pmhpr bit= ? 1 ? ). common v oltage of headphone - amp is rising . this rise time depends on the capacitor value connected with the mutet pin. the time constant is t = 100k(typ) x c when the capacitor value on mutet pin is ? c ? . (3) headphone - amp common voltage fall down (pmhpl, pmhpr bit= ? 0 ? ). common voltage of headphone - amp is fall ing . this fall time depends on the capacitor value connected with the mutet pin. the time constant is t = 100k(typ) x c when the capacitor value on mutet pin is ? c ? . (4) headphone - amp power - down (hpl, hpr bit= ? 1 ? ). t he outputs are hvss. if the power supply is switched off or headphone - amp is powered - down before the common voltage goes to hvss, some click noise occurs.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 37 - the cut - off frequency of headphone - amp output depends on the external resistor and capacitor used . table 20 shows the cut off frequency and the output power for various resistor/capacitor combinations. the headphone impedance r l is 16 w . output powers are shown at hvdd = 2.7, 3.0 and 3.3v. the output voltage of headphone is 0.6 x avdd (vpp). when an external resistor r is smaller than 12 w , put an oscillation prevention circuit (0.22 m f 20% capacitor and 10 w 20% resistor ) because it has the possibility that headphone - amp oscillates . AK4640 hp-amp 16 w headphone 10 w +/- 20% 0.22 m +/- 20% r c figure 26 . external circuit example of headphone output power [mw] r [ w ] c [ m f] fc [hz] boost=off fc [hz] boost=mid 2.7v 3.0v 3.3v 6.2 47 152.5 63 10.0 12.4 15.0 16 47 105.8 43 4.8 6.0 7.2 6.2 100 71.2 27 10.0 12.4 15.0 16 100 49.7 20 4.8 6.0 7.2 table 20 . external circuit example
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 38 - n speaker output the output signal from analog volume is converted into a mon o signal [(l+r)/2] and this signal is input to the speaker - amp via the alc2 circuit. this speaker - amp is a mono output controlled by btl and can output a maximum of 300mw@alc2=off and 250mw@alc2=on at 8 w load when hvdd = 3.3v. alc2 po(max) 0 300mw 1 250mw default table 21 . spk - amp maximum output power speaker blocks (mout2, alc2 and sp eaker - amp) can be powered up/down by controlling the pmspk bit. when the pmspk bit is ? 0 ? , the mout2, spp and spn pins are placed in a hi - z state. when the spps bit is ? 0 ? , the speaker - amp enters power - save - mode. in this mode, the spp pin is placed in a h i - z state and the spn pin goes to hvdd/2 voltage . and then the speaker output gradually changes to the hvdd/2 voltage and this mode can reduce click noise at power - up. when the AK4640 is powered down, click noise can be also reduced by first entering power - save - mode. pmspk bit spps bit spp pin spn pin hvdd/2 hvdd/2 hi-z hi-z hi-z hi-z figure 27 . power - up/power - down timing for speaker - amp n mono output (mout2 pin) the mixed lch/rch signal of dac is output from the mout2 pin. when the mout2 bit is ? 0 ? , this output is of f and the mout2 pin is forced to vcom voltage. the load impedance is 10k w (min.). when the pmspk bit is ? 0 ? , the speaker - amp enters power - down - mode and the output is placed in a hi - z state.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 39 - n mono output (mout+/mout - pins) att+dac mic in +20db/0db ipga lch att attm bit micout pin ain pin AK4640 mout+ pin 1/2 mout - pin +6db/ - 17db 1/2 mic m bit damo bit m ogn bit f igure 28 . mono line output when damo bit is ? 1 ? , mono mixer mixes lch and rch signal from dac. this mixed signal is output to mono line output that is differential output. when micm bit is ? 1 ? , lch signal from ipga is output to mo no line output. either mout+ or mout - pin can be used as single - ended output pin. the load impedance is 20k w (min.). when the pmmo bit is ? 0 ? , the mono line output enters power - down - mode and the output is placed in a hi - z state. attl7 - 0 and attr7 - 0 bits s et the volume control of dac output. attm bit sets the volume control of ipga lch output. amp for mono line output has 6db gain and - 17db gain that are set by the mogn bit.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 40 - n alc2 operation input resistance of the alc2 (min pin) is 24k w (typ) and cente red around vcom voltage. (see figure 29 . 0dbv=1vrms =2.828vpp) the limiter detection level is proportional to hvdd. the output level is limited by the alc2 circuit when the input signal exceeds ? 5.2dbv (=fs - 1.9db@hv dd=3.3v). when a continuous signal of ? 5.2dbv or greater is input to the alc2 circuit, the change period of the alc2 limiter operation is set by the rotm bit and the attenuation level is 0.5db/step. the alc2 recovery operation uses zero crossings and gain s of 1db/step. the alc2 recovery operation is done until the input level of the speaker - amp goes to ? 7.2dbv (=fs-3.9db@hvdd=3.3v) . the rotm bit sets the alc2 recovery operation period . when the input signal is between ? 5.2dbv and ? 7.2dbv, the alc2 limiter or recovery operations are not done. when the pmspk bit changes from ? 0 ? to ? 1 ? , the initilization cycle (2048/fs = 46.4ms @fs=44.1khz at rotm bit = ? 0 ? , 512/fs = 11.4ms @fs=44.1khz at the rotm bit = ? 1 ?) starts. the alc2 is disabled during the initilizat ion cycle and the alc2 starts after completing the initilization cycle. parameter alc 2 limiter operation alc2 recovery operation operation start level - 5.2dbv - 7.2dbv rotm bit = ? 0 ? 2/fs = 45 m s@fs=44.1khz 2048/fs = 46.4ms@fs=44.1khz period rotm bit = ? 1 ? 2/fs = 181 m s@fs=11.025khz 512/fs = 46.4ms@fs=11.025khz zero - crossing detection disabled enabled (timeout = 2048/fs) att/gain 0.5db step 1db step table 22 . limiter /recovery of alc2 at hvdd=3.3v -15.3dbv fs fs-12db 0dbv fs-1.9db = -5.2dbv 1.0dbv full-differential -3.3dbv -10dbv -3.0dbv -20dbv -30dbv -23.3dbv -8db -15.3dbv -11.3dbv -3.3dbv fs-3.9db = -7.2dbv +8.1db +16.1db +4.1db -1.9db +8.2db -8db single-ended datt dac alc2 spk-amp 3.0dbv(250mw@8ohm) +8.2db +2.2db -5.0dbv +2.2db figure 29 . speaker - amp output level diagram (hvdd=3.3v, datt= - 8.0db , alc2= ? 1 ? )
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 41 - n serial control interface (1) 4 - wire serial control mode (i2c pin = ? l ? ) internal registers may be written by using the 4 - wire p interface pins ( c sn , cclk, cdti and cdto). the data on this interface consists of a 2 - bit chip address, read/write, register address (msb first, 5bits) and control data (msb first, 8bits). the chip address high bit is fixed to ? 1 ? and the lower bit is set by the cad0 pin. address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. after a low - to - high transition of csn , data is latched for write operations and cdto bit outputs hi - z. the clock speed of cclk is 5mhz (max). the value o f internal registers is initialized at pdn pin = ? l ? . csn cclk cdti 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 c1 c0 r/w a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cdto hi-z write cdti c1 c0 r/w a4 a3 a2 a1 a0 cdto hi-z read d7 d6 d5 d4 d3 d2 d1 d0 hi-z c1 - c0 : chip address (c1="1", c0=cad0) r/w : read / write ("1" : write, "0" : read) a4 - a0 : register address d7 - d0 : control data figure 30 . serial control i/f timing
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 42 - (2) i 2 c - bus control mode (i2c pin = ? h ? ) the AK4640 supports the standard - mode i 2 c - bus (max: 100khz). the AK4640 does n o t support a fast - mode i 2 c - bus system (max: 400khz). (2) - 1. write operations figure 31 shows the data transfer sequence for the i 2 c - bus mode. all commands are preceded by a start condition. a high to l ow transition on the sda line while scl is high indicat es a start condition ( figure 37 ) . after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit that is a data direct ion bit (r/w). the most significant five bits of the slave address are fixed as ? 00 10 0 ?. the next two bits are cad1 and cad0 (device address bits ) . these two bits identify the specific device on the bus. the hard - wired input pins (cad1 and cad0 pin s ) set t he se device address bits ( figure 32 ) . if the slave address matches that of the AK4640, the AK4640 generates an acknowledge and the operation is executed. the master must generate the acknowledge - related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 38 ). a r/w bit value of ? 1 ? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK4640. the format is msb first, and those most significant 3 - bits are fixed to zeros ( figure 33 ). the data after the second byte contains control data . the format is msb first, 8bits ( figure 34 ). the AK4640 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the s da line while scl is high defines a stop condition ( figure 37 ) . the AK4640 can perform more than one byte write operation per sequence . after receipt of the third byte the AK4640 generates an acknowledge and awaits the next data. t he master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 5 - bit address counter is incremented by one , and the next data is autom atically taken into the next address. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low ( figure 39 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 31 . data transfer sequence at the i 2 c - bus mode 0 0 1 0 0 cad1 cad0 r/w ( those cad1/0 should match with cad1/0 pins) figure 32 . the first byte 0 0 0 a4 a3 a2 a1 a0 figure 33 . the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 34 . byte structure after the second byte
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 43 - (2) - 2. read operations set the r /w bit = ? 1 ? for the read operation of the AK4640 . after transmission of data, t he master can read the next address ? s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. after receiving each data packet the in ternal 5 - bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 0fh prior to generating a stop condition, the address counter will ?roll over? to 00h and the previous data will be o verwritten. the AK4640 supports two basic read operations: current address read and random address read . (2) - 2 - 1. current address read t he AK4640 contains an internal address counter that maintains the address of the last word accessed, incremented by o ne. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ? 1 ?, the AK4640 generates an acknowledge , transmits 1 - byte of data to the address set by the internal address counter and increments the internal address counter by 1 . if t he master does not generate an acknowledge to the data but instead generate s a stop condition, the AK4640 ceases transmission . sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 35 . current address read (2) - 2 - 2. random address read the random read operation allow s the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ? 1 ? , the master must first perform a ?dummy? write operation. the master issues a start request , a slave address ( r/w bit = ? 0 ? ) and then the register address to read. after the register address i s acknowledge d , the master immediately reissues the start reque st and the slave address with the r/w bit set to ? 1 ?. the AK4640 then generates an acknowledge , 1 byte of data and increments the internal address counter by 1. if t he master does not generate an acknowledge to the data but instead generate s a stop conditi on, the AK4640 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 36 . random address read
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 44 - scl sda stop condition start condition s p figure 37 . start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 38 . acknowledge on the i 2 c - bus scl sda data line stable; data valid change of data allowed figure 39 . bit transfer on the i 2 c - bus
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 45 - n register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmvcm pmbps pmbpm 0 pmmo pmaux pmmic pmadc 01h power management 2 mckpd pmxtl pmpll 0 pmspk pmhpl pmhpr pmdac 02h signal select 1 mogn psmo damo micm bpssp bpmsp alcs mout2 03h signal select 2 dahs 0 auxl micl bpshp bpmhp hpl hpr 04h mode control 1 pll1 pll0 ps1 ps0 mcko bf dif1 dif0 05h mode cont rol 2 fs2 fs1 fs0 0 0 hpm loop spps 06h dac control tm1 tm0 smute dattc bst1 bst0 dem1 dem0 07h mic control 0 0 auxad mpwre mpwri micad msel mgain 08h timer select 0 rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 09h alc mode control 1 0 alc2 alc1 zelm lmat1 lmat0 ratt lmth 0ah alc mode control 2 0 ref6 erf5 ref4 ref3 ref2 ref1 ref0 0bh input pga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 0ch lch digital att control attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 0dh rch digital att control attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 0eh volume control attm atts2 atts1 atts0 gn3 gn2 gn1 gn0 pdn pin = ? l ? resets the registers to their default values. note: unused bits must contain a ? 0 ? value. note: only write to address 00h to 0fh.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 46 - n registe r definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmvcm pmbps pmbpm 0 pmmo pmaux pmmic pmadc r/w r/w r/w r/w rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmadc: adc block power control 0: power down (default) 1: power up when the pm adc bit changes from ?0? to ?1?, the initializ ation cycle (2081/fs=47.2ms@44.1khz) starts. after initializing , digital data of the adc is output. pmmic: mic in block power control 0: power down (default) 1: power up pmaux: aux in po wer control 0: power down (default) 1: power up pmmo: mono line out power control 0: power down (default) 1: power up pmbpm: mono beep in power control 0: power down (default) 1: power up even if pmbpm= ? 0 ? , the path is still connected bet ween beepm and hp/spk - amp. bpmhp and bpmsp bits should be set to ? 0 ? to disconnect these paths, respectively. pmbps: stereo beep in power control 0: power down (default) 1: power up even if pmbps= ? 0 ? , the path is still connected between beepl/r and hp/spk - amp. bpshp and bpssp bits should be set to ? 0 ? to disconnect these paths, respectively. pmvcm: vcom block power control 0: power down (default) 1: power up each block can be powered down respectively by writing ? 0 ? in each bit. when the pdn p in is ? l ? , all blocks are powered down. when all bits except mckpd bit are ? 0 ? in the 00h and 01h addresses, all blocks are powered down. the register values remain unchanged. ipga gain is reset when pmmic bit is ? 0 ? (refer to the ipga6 - 0 bits description ). when any of the blocks are powered up, the pmvcm bit must be set to ? 1 ? . mcki, bick and lrck must always be present unless pmmic=pmadc=pmdac=pmspk= ? 0 ? or pdn pin = ? l ? . the paths from beep to hp - amp and spk - amp can operate without these clocks.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 47 - ad dr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 mckpd pmxtl pmpll 0 pmspk pmhpl pmhpr pmdac r/w r/w r/w r/w rd r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 pmdac: dac block power control 0: power down (default) 1: power up pmhpr: rch of headphone - amp common voltage power control 0: power down (default) 1: power up pmhpl: lch of headphone - amp common voltage power control 0: power down (default) 1: power up pmspk: speaker block power control 0: power down (default) 1: powe r up pmpll: pll block power control select 0: ext mode and power down (default) 1: pll mode and power up pmxtl: x ? tal oscillation block power control 0: power down (default) 1: power up mckpd: xti/mcki pin pull down control 0: master clock input enable 1: pull down by 25k w (default)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 48 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 mogn psmo damo micm bpssp bpmsp alcs mout2 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 mout2: mout2 output enable ( mixing = ( l+r ) /2 ) 0: off (default) 1: on when the mout2 bit = ? 0 ? , the mout2 pin outputs vcom voltage. the mout2 pin outputs signal at the mout2 bit = ? 1 ? . this bit is valid at the pmspk bit = ? 1 ? . hi - z is output at the pmspk bit = ? 0 ? . alcs: alc2 to speaker - a mp enable 0: off (default) 1: on alc 2 output signal is mixed to speaker - amp at the alcs bit = ? 1 ? . bpmsp: beep m to speaker - amp enable 0: off (default) 1: on mono beep signal (beepm pin) is mixed to speaker - amp at the bpmsp bit = ? 1 ?. bpssp: beep l/beep r to speaker - amp enable 0: off (default) 1: on stereo beep signal s (beepl/beepr pins) are mixed to speaker - amp at the bpssp bit = ? 1 ?. micm: switch control from mic in to mono mixer. 0: off (default) 1: on ipga output signal is output through mono line output (mout+/mout - pins) at the micm bit = ? 1 ?. damo: dac to mout+/mout - enable 0: off (default) 1: on dac output signal is output through mono line output (mout+/mout - pins) at the damo bit = ? 1 ?. psmo: mout+/mout - output enable ( mixing = ( l+r ) /2 ) 0 : power save mode (default) 1: normal operation when the psmo bit = ? 0 ? , mono line output is in power save mode and the mout+ and mout - pins output 0.45 x avdd voltage. mogn: gain control for mono output 0: +6db (default) 1: - 17db
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 49 - att+dac mic in volume alc2 spk - amp auxin+ auxin - beepm 0db/+20db ipga att ?mic l ? ? dahs ? ? auxl ? beepl beepr 1/2 1/2 ? bpmsp ? ? bpssp ? ? alcs ? figure 40 . speaker - amp switch control addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 dahs 0 auxl micl bpshp bpmhp hpl hpr r/w r/w rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 1 hpr: rch of headp hone - amp power control 0: normal operation 1: off(default) hpl: lch of headphone - amp power control 0: normal operation 1: off(default) bpmhp: beep m to headphone - amp enable 0: off (default) 1: on mono beep signal (beepm) is mixed to headphone - amp at t he bpmhp bit = ? 1 ?. bpshp: beepl/beepr to headphone - amp enable 0: off (default) 1: on stereo beep signal s (beepl/beepr) is mixed to headphone - amp at the bpshp bit = ? 1 ?. micl: ipga to headphone - amp and mout2 enable 0: off (default) 1: on ipga output signal is mixed to headphone - amp and mout2 at the micl bit = ? 1 ? . auxl: aux in to stereo mixer enable 0: off (default) 1: on aux input signal is mixed to headphone - amp and mout2 at the auxl bit = ? 1 ? .
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 50 - dahs: dac to headphone - amp and mout2 enable 0: of f (default) 1: on dac signal is mixed to headphone - amp and mout2 at the dahs bit = ? 1 ? . att+dac mic in 0db/+20db ipg a att volume auxin+ auxin - beepm in ? dahs ? ? auxl ? ?mic l ? beepl in ? bpmhp ? beepr in ? bpshp ? hpl mute hpl hpr mute hpr - 20db figure 41 . headphone - amp switch control
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 51 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll1 pll 0 ps1 ps0 mcko bf dif1 dif0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 dif1 - 0: audio interface format select ( table 13 ) default: ? 10 ? (adc: i 2 s, dac: i 2 s) bf: bick frequency select at master mode 0: 64fs (default) 1: 32fs this bit is invalid in slave mode. mcko: master clock output enable 0: disable (default) 1: enable ps1 - 0: output master clock select ( table 4 , table 8 ) default: ? 00 ? (256fs) pll 1 - 0: input master clock select at pll mode ( table 2 ) default: ? 00 ? (12.288mhz)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 52 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 fs2 fs1 fs0 0 0 hpm loop spps r/w r/w r/w r/w rd rd r/w r/w r/w default 0 0 0 0 0 0 0 0 spps: speaker - amp power - save - mode 0: power save mode (default) 1: normal operation when the spps bit = ? 1 ? , the speaker - amp is in power - save - mode and the sp p pin becomes hi - z and sp n pin is se t to hvdd/2 voltage. when the pmspk bit = ? 1 ? , this bit is valid. after the pdn pin changes from ? l ? to ? h ? , the pmspk bit is ? 0 ? , which powers down speaker - amp loop: loopback on/off 0: off (default) 1: on when this bit is ? 1 ? , the adc output is passed to the dac input internally. the external input data to dac is ignored. hpm: mono output select of headphone 0: stereo (default) 1: mono when the hpm bit = ? 1 ? , (l+r)/2 signals are output to lch and rch of the headphone - amp. fs2 - 0: sampling frequency modes ( table 3 , table 7 ) default: ? 000 ? (fs=44.1khz)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 53 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h dac control tm1 tm0 smute dattc bst1 bst0 dem1 dem0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 1 dem1 - 0: de - emphases response ( table 16 ) default is ? 01 ? (off). bst1 - 0: select low frequency boost function ( table 17 ) default is ? 00 ? (off). dattc: dac digital attenuator control mode select 0: independent 1: dependent (default) when dattc= ? 1 ? , attl7 - 0 bits control both lch and rch at same time. attr7 - 0 bits are n o t changed when the attl7 - 0 bits are written. smute: soft mute control 0: normal operation (default) 1: dac outputs soft - muted soft mute operation is independent of digital a ttenuator and is performed in the digital domain. tm1 - 0: soft mute time select ( table 23 ) default: ? 00 ? (1024/fs) tm1 tm0 cycle 0 0 1024/fs default 0 1 512/fs 1 0 256/fs 1 1 128/fs table 23 . soft mute time setting
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 54 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h mic/hp control 0 0 auxad mpwre mpwri micad msel mgain r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 mgain: 1 st mic - amp gain control 0: 0db 1: +20db (default) msel: m icrophone select 0: internal mic (default) 1: external mic micad: switch control from mic in to adc 0: off (default) 1: on alc1 output signal is input to adc when micad bit = ? 1 ? . mpwri: power supply control for internal microphone 0: off (default) 1: on the setting of mpwri is enabled when pmmicl bit = ? 1 ? . mpwre: power supply for external microphone 0: off (default) 1: on the setting of mpwre is enabled when pmmicl bit = ? 1 ? . auxad: switch control from aux in to adc. 0: off (default) 1: on aux inp ut signal is input to adc when auxad bit = ? 1 ? .
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 55 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h timer select 0 rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 ltm1 - 0: alc1 limiter operation period at zer o crossing disable (see table 24 ) the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period specified by the ltm1 - 0 bits. default is ? 00 ? (0.5/fs). alc1 limiter o peration period ltm1 ltm0 8khz 16khz 44.1khz 0 0 0.5/fs 63 m s 31 m s 11 m s default 0 1 1/fs 125 m s 63 m s 23 m s 1 0 2/fs 250 m s 125 m s 45 m s 1 1 4/fs 500 m s 250 m s 91 m s table 24 . alc1 limiter operation period at zero crossing disable (zelm b it = ? 1 ? ) wtm1 - 0: alc1 recovery waiting period (see table 25 ) a period of recovery operation when any limiter operation does not occur during the alc1 operation. default is ? 00 ? (128/fs). alc1 recovery operation waiting period wtm1 wtm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 25 . alc1 recovery operation waiting period ztm1 - 0: zero crossing t imeout for the write operation by the m p, alc1 recovery, and zero crossing enable (zelm bit = ? 0 ? ) of the alc1 operation (see table 26 ) when the ipga performs zero crossing or timeout, the ipga value is changed by the m p write opera tion, alc1 recovery operation or alc1 limiter operation (zelm bit = ? 0 ? ). default is ? 00 ? (128/fs). zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6m s 1 1 1024/fs 128ms 64ms 23.2ms table 26 . zero crossing timeout period rotm: period time for alc2 recovery operation 0: 2048/fs (default) 1: 512/fs
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 56 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h alc mode control 1 0 alc2 a lc1 zelm lmat1 lmat0 ratt lmth r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 0 0 0 lmth: alc1 limiter detection level / recovery waiting counter reset level (see table 27 ) the alc1 limiter detection level and the alc1 re covery counter reset level may be offset by about 2db . default is ? 0 ? . lmth alc1 limiter detection level alc1 recovery waiting counter reset level 0 adc input 3 - 6.0dbfs - 6.0dbfs > adc input 3 - 8.0dbfs default 1 adc input 3 - 4.0dbfs - 4.0dbfs > adc inp ut 3 - 6.0dbfs table 27 . alc1 limiter detection level / recovery waiting counter reset level ratt: alc1 recovery gain step (see table 28 ) during the alc1 recovery operation, the number of steps changed fro m the current ipga value is set. for example, when the current ipga value is 30h and ratt bit = ? 1 ? is set, the ipga changes to 32h by the alc1 recovery operation and the output signal level is gained up by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6 - 0 bits), the ipga value does not increase. ratt gain step 0 1 default 1 2 table 28 . alc1 recovery gain step setting lmat1 - 0: alc1 limiter att step (see table 29 ) during the alc1 limiter operation, when either lch or rch exceeds the alc1 limiter detection level set by lmth, the number of steps attenuated from the current ipga value is set. for example, when the current ipga value is 47h and the lmat1 - 0 bits = ? 11 ? , the ipga transi tion to 43h when the alc1 limiter operation starts, resulting in the input signal level being attenuated by 2db (=0.5db x 4). when the attenuation value exceeds ipga = ? 00 ? ( - 8db), it clips to ? 00 ? . lmat1 lmat0 att step 0 0 1 default 0 1 2 1 0 3 1 1 4 table 29 . alc1 limiter att step setting zelm: enable zero crossing detection at alc1 limiter operation 0: enable (default) 1: disable when the zelm bit = ? 0 ? , the ipga of each l/r channel perform a zero crossing or timeo ut independently and the ipga value is changed by the alc1 operation. the zero crossing timeout is the same as the alc1 recovery operation. when the zelm bit = ? 1 ? , the ipga value is changed immediately .
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 57 - alc1: alc1 enable flag 0: alc1 disable (defaul t) 1: alc1 enable alc2: alc2 enable flag 0: alc2 disable 1: alc2 enable (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 1 1 0 1 1 0 ref6 - 0: reference value at a lc1 recovery operation (see table 30 ) during the alc1 recovery operation , if the ipga value exceeds the setting reference value by gain operation, then the ipga does not become larger than the refere nce value. for example, when ref7 - 0 = ? 30h ? , ratt = 2step, ipga = 2fh, even if the input signal does not exceed the ? alc1 recovery waiting counter reset level ? , the ipga does n o t change to 2fh + 2step = 31h, and keeps 30h. default is ? 36h ? . data (hex) gai n (db) step 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 default : : 10 +0.0 : : 06 - 5.0 05 - 5.5 04 - 6.0 03 - 6.5 02 - 7.0 01 - 7.5 00 - 8.0 0.5db table 30 . setting reference value at alc1 recover y operation
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 58 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh input pga control 0 ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 ipga6 - 0: input analog pg a (see table 31 ) default: ? 10h ? (0db) when ipga gain is changed, ipga6 - 0 bits should be written while pmmic bit is ? 1 ? and alc1 bit is ? 0 ? . ipga gain is reset when pmmic bit is ? 0 ? , and then ipga operation starts from the default value when pmmic is changed to ? 1 ? . when al c1 bit is changed from ? 1 ? to ? 0 ? , ipga holds the last gain value set by alc1 operation. when ipga6 - 0 bits are read, the register values written by the last write operation are read out regardless the actual gain. data (hex) gain (db) step 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 : : 10 +0.0 default : : 06 - 5.0 05 - 5.5 04 - 6.0 03 - 6.5 02 - 7.0 01 - 7.5 00 - 8.0 0.5d b table 31 . input gain setting addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 ch lch digital att control attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 0dh rch digital att control attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 attl/r7 - 0: digital att output control ( see table 18 ) default: ? 00h ? (0db)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 59 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh volume control attm atts2 atts1 atts0 gn3 gn2 gn1 gn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 1 0 1 1 1 gn3 - 0: volume control of aux in (see table 19 ) atts2 - 0: attenuator select of signal from mic in to stereo mixer (see table 32 ) atts2 - 0 attenuation 7h - 6db 6h - 9db 5h - 12db default 4h - 15db 3h - 18db 2h - 21db 1h - 24db 0h - 27db table 32 . attenuat ion table attm: attenuator control for signal from mic in to mono mixer 0: off. 0db (default) 1: on. - 4db
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 60 - system design (AK4640vg) fig ure 42 shows the system connection diagram for the AK4640vg. an evaluation board [akd4640] is available which demonstrates the optimum layout, power supply arrangements and measurement results. reset dsp and up 10 0.1 m 10 m nc micout beepl nc pdn beepm mout+ mout2 cad0 nc lrck cdti /sda i2c sdto ext ain mpe mpi int vcom avss pvdd avdd avdd vcoc pvss csn /cad1 beepr auxin+ auxin- mout- nc mutet min hvdd hpl hvss hvss hvdd spn hpr spp spp xto m/s spn cdto cclk /scl sdti bick nc mcko dvss nc xti /mcki dvdd top view nc c c 8 w 0.1 m 10 m analog supply 2.4 ~ 3.6v 16 w 16 w 6.8 w 6.8 w 47 m 10 w 0.22 m 10 w 0.22 m 1 m 1 m r r r 1 m 1 m 1 m c c 1 m 1 m 1 m 2.2k 1 m 2.2k 1 m 0.1 m 10 m 2.2 m 0.1 m 0.1 m 10 m analog supply 2.4 ~ 3.6v 10k w 4.7n notes: - avss, d vss, pvss and hvss of the AK4640 should be distributed separately from the ground of external controllers. - values of r and c in fig ure 42 should depend on system. - all input pins should not be left floating. fig ure 42 . typical connection diagram
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 61 - system design (AK4640vn) figure 43 shows the system connection diagram for the AK4640vn. an evaluation board [akd4640] is available which demonstrates the optimum layou t, power supply arrangements and measurement results. 0.1 m 10 m 0.1 m 10 m analog supply 2.4 ~ 3.6v 0.1 m 10 m 2.2 m 0.1 m 0.1 m 10 m analog supply 2.4 ~ 3.6v micout 1 2 3 4 5 6 7 8 9 10 11 12 13 nc ext mpe mpi int vcom avss avdd pvdd pvss vcoc nc nc 52 51 50 49 ain beepl beepr 48 47 45 44 46 42 41 43 40 beepm auxin+ auxin- mout+ mout- nc nc mout min 39 38 37 36 35 34 33 32 31 30 29 28 27 mutet hpl hpr hvss hvdd spn spp m/s xti/mcki xto dvss dvdd cad0 14 pdn 15 16 csn/cad1 17 cclk/scl 18 cdti/sda 19 cdto 20 i2c 21 sdti 22 sdto 23 lrck 24 bick 25 mcko 26 reset dsp and up top view r r r 1 m 8 w 10k w 4.7n 10 1 m 2.2k 1 m 2.2k 1 m 1 m 1 m 1 m 1 m nc nc 16 w 16 w c c c c 6.8 w 6.8 w 47 m 10 w 0.22 m 10 w 0.22 m 1 m 1 m notes: - avss, dvss, pvss and hvss of the AK4640 should be distributed separately from the ground of external controllers. - values of r and c in figure 43 should depend on system. - all input pins should not be left floating. figure 43 . typical connection diagram
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 62 - 1. grounding and power supply decoupling the AK4640 requires careful attention to power supply and gro unding arrangements. avdd, dvdd, pvdd and hvdd are usually supplied from the system ? s analog supply. if avdd, dvdd, pvdd and hvdd are supplied separately, the correct power up sequence should be observed . avss, dvss, pvss and hvss of the AK4640 should be c onnected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4640 as possible, with the sma ll value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 m f electrolytic capacitor in parallel with a 0.1 m f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vref and vcom pins in order to avoid unwanted coupling into the AK4640. 3. analog inputs the mic and beep inputs are single - ended. the input signal range scales with nominally at 0.06 x avdd vpp for the mic input and 0.6 x avdd vpp for the beep input, centered around the internal common voltage (approx. 0.45 x avdd). usually the input signal is ac coupled using a capacitor. the cut - off frequency is f c = (1/2 p rc). the AK4640 can accept input voltages from avss to avdd. 4. analog outputs the input data format for the dac is 2 ? s complement. the output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). mono o utput from the mout2 pin and mono line output from the mout+ and mout - pins are centered at 0.45 x avdd. the headphone - amp and speaker - amp outputs are centered at hvdd/2.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 63 - contorol sequence n power up upon power - up, bring the pdn pin = ?l?. initializ e the internal registers to default value s after the pdn pin = ?h?. set the following registers to establish the initial condition. power supply pdn pin pmvcm bit (addr:00h, d7) dif1-0 bits (addr:04h, d1-0) bf bit (addr:04h, d2) pll1-0 bits (addr:04h, d7-6) mout2 bit (addr:02h, d0) alcs bit (addr:02h, d1) hpl/r bits (addr:03h, d1-0) dahs bit (addr:03h, d7) (2) 10 xx x xx 00 0 (3) (4) (5) (6) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz (1) power supply (2) pdn pin = ? l ? ? ? h ? (3) addr:00h, data 80h (4) addr:02h, data 03h (5) addr:03h, data 80h (6) addr:04h, data 42h figure 44 . power up sequence (1) power supply (2) pdn pin = ? l ? ? ? h ? ? l ? time of 150ns or more is needed to reset the AK4640. (3) power up vcom : pmvcm bit = ? 0 ? ? ? 1 ? vcom should first be powered up before the other block operates. (4) set up register 02h : mout2 bit = alcs bit = ? 0 ? ? ? 1 ? set the mout2 and alcs bits to ? 1 ? when using the speaker - amp. (5) set up register 03h : hpl bit = hpr bit = ? 1 ? ? ? 0 ? , dahs bit = ? 0 ? ? ? 1 ? (6) set up register 04h dif1 - 0 bits set the audio interface format. bf bit sets bick output frequency in master mode. pll1 - 0 bits set mcki input frequency in pll mode.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 64 - n clock set up when adc, dac, alc1 and alc2 are used, the clocks (mcki, bick and lrck) must be supplied. 1. when x'tal is used in pll mode. (slave mode) mckpd bit (addr:01h, d7) bick, lrck (slave mode) ps1-0 bits (addr:04h, d5-4) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40ms(max) output input (1) 20ms(typ) (2) (3) (4) (5) (6) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:40h (2) addr:01h, data:60h (3) addr:04h, data 4ah (4) mcko output starts (5) bick and lrck input start (6) addr:04h, data 6ah figure 45 . clock set up sequence (1) (1) release the pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? and power - up the x ? tal oscillator: pmxtl bit = ? 0 ? ? ? 1 ? (2) power - up the pll : pmpll bit = ? 0 ? ? ? 1 ? the pll should be powere d - up after the x ? tal oscillator becomes stable. if x'tal and pll are powered - up at the same time, the pll does not start. it takes x ? tal oscillator 20ms(typ) to be stable after pmxtl bit= ? 1 ? . this time depends on x ? tal. pll needs 40ms lock time the pmpll bit = ? 0 ? ? ? 1 ? . (3) enable mcko output : mcko bit = ? 0 ? ? ? 1 ? (4) mcko is output after pll becomes stable. (5) input bick and lrck synchronized with the mcko output. (6) set the mcko output frequency (ps1 - 0 bits) if ps1 - 0 bits are changed before lrck is input, mcko is n ot output. ps1 - 0 bits should be changed after lrck is input.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 65 - 2. when x'tal is used in pll mode. (master mode) mckpd bit (addr:01h, d7) bick, lrck (master mode) ps1-0 bits (addr:04h, d5-4) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40msec(max) output output (1) 20ms(typ) (2) (3) (4) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:40h (2) addr:01h, data:60h (3) addr:04h, data 6ah (4) mcko, bick and lrck output starts figure 46 . clock set up sequence (2) (1) release the p ull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? and and power - up the x ? tal oscillator: pmxtl bit = ? 0 ? ? ? 1 ? (2) power - up pll : pmpll bit = ? 0 ? ? ? 1 ? the pll should be powered - up after the x ? tal oscillator becomes stable. if x'tal and pll are powered - up at the same time, the pll does not start. it takes x ? tal oscillator 20ms(typ) to be stable after pmxtl bit= ? 1 ? . this time depends on x ? tal. pll needs 40ms lock time the pmpll bit = ? 0 ? ? ? 1 ? . (3) enable mcko output : mcko bit = ? 0 ? ? ? 1 ? and set up mcko output freq uency (ps1 - 0 bits) (4) mcko, bick and lrck are output after pll lock time.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 66 - 3. when an external clock is used in pll mode. (slave mode) mckpd bit (addr:01h, d7) ps1-0 bits (addr:04h, d5-4) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 (1) output bick, lrck (slave mode) input external mclk input (2) (3) 40ms(max) (4) (5) (6) (7) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:00h (2) input external mclk (3) addr:01h, data 2 0h (5) mcko output starts (6) bick and lrck input start (7) addr:04h, data 6ah (4) addr:04h, data 4ah figure 47 . clock set up sequence (3) (1) release the pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? (2) input an external mcki (3) power - up pll : pmpll bit = ? 0 ? ? ? 1 ? pll needs 40ms lock time after the pmpll bit = ? 0 ? ? ? 1 ? . (4) enable mcko output : mcko bit = ? 0 ? ? ? 1 ? (5) mcko is output after pll loc k time. (6) input bick and lrck that synchronized in the mcko output. (7) set up mcko output frequency (ps1 - 0 bits) if ps1 - 0 bits are changed before lrck is input, mcko is not output. ps1 - 0 bits should be changed after lrck is input.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 67 - 4. when an external clock is used in pll mode. (master mode) mckpd bit (addr:01h, d7) ps1-0 bits (addr:04h, d5-4) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40ms(max) output bick, lrck (master mode) output external mclk input (1) (2) (3) (4) (5) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:00h (2) input external mclk (3) addr:01h, data 20h (5) mcko, bick and lrck output starts (4) addr:04h, data 6ah figure 48 . clock set up sequence (4) (1) release the pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? (2) input an external mcki (3) power - up pll : pmpll bit = ? 0 ? ? ? 1 ? pll needs 40ms lock time after the pmpll bit = ? 0 ? ? ? 1 ? . (4) enable mcko output : mcko bit = ? 0 ? ? ? 1 ? and set up mcko output frequency (ps1 - 0 bits) (5) mcko, bick and lrck are output after pll lock time. 5. external clock mode mckpd bit (addr:01h, d7) fs1-0 bits (addr:05h, d6-5) xx 00 bick, lrck (slave mode) input external mclk input bick, lrck (master mode) output (1) (2) (3) (4) (5) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock frequency : 256fs output master clock frequency : 64fs (1) addr:01h, data:00h (2) addr:05h, data 00h (3) input external mclk (4) input bick and lrck(slave) (5) bick and lrck output(master) figure 49 . clock set up sequence (5) (1) release the pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? (2) set up mcki frequency (fs1 - 0 bits) (3) input an external mcki (4) in slave mode, input mcki, bick and lrck. (5) in master mode, while mcki is input, bick and lrck are output.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 68 - n mic input recording fs2-0 bits (addr:05h, d7-5) mic control (addr:07h, d2-0) pmadc bit (addr:00h, d0) pmmic bit (addr:00h, d1) adc internal state xxx 000 00001 xx1xx power down initialize normal state power down 2081 / fs (1) (2) (6) (7) alc1 state alc1 enable alc1 disable alc1 disable (5) alc1 control 1 (addr:08h) xxh 00h (3) alc1 control 2 (addr:0ah) xxh 47h (4) alc1 control 3 (addr:09h) xxh 61h or 21h example : x ? tal and pll are used. sampling frequency : 8khz mic select : internal mic pre mic amp : +20db mic power on alc1 setting : refer to figure 9 alc2 bit = ? 1 ? (default) (1 ) addr:05h, data:e0h (3) addr:08h, data:00h (4) addr:0ah, data:47h (5) addr:09h, data:61h (2) addr:07h, data:0dh ( 6) addr:00h, data 83h recording (7) addr:00h, data 80h figure 50 . mic input recording sequence this sequence is an example of alc1 setting at fs=8khz. if the parameter of the alc1 is changed, please refer to ? figure 20 . registers set - up sequence at alc1 operation ? at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs2 - 0 bits). when the AK4640 is pll mode, mic and adc should be powered - up in consideration of pll lock time after a sampling frequency is changed. (2) set up mic input (addr: 07h) (3) set up timer select for a lc1 (addr: 08h) (4) set up ref value for alc1 (addr: 0ah) (5) set up lmth, ratt, lmat1 - 0, alc1 bits (addr: 09h) (6) power up mic and adc: pmmic bit = pmadc bit = ? 0 ? ? ? 1 ? the initialization cycle time of adc is 2081/fs=47.2ms@fs=44.1khz. after the alc1 bit is set to ? 1 ? and mic block is powered - up, the alc1 operation starts from ipga initial value (0db). (7) power down mic and adc: pmmic bit = pmadc bit = ? 1 ? ? ? 0 ? when the registers for the alc1 operation are not changed, alc1 bit may be keeping ? 1 ?. the alc1 operation i s disable d because the mic block is powered - down. if the registers for the alc1 operation are also changed when the sampling frequency is changed, it should be done after the AK4640 goes to the manual mode (alc1 bit = ? 0 ? ) or mic block is powered - down (pmm ic bit = ? 0 ? ). ipga gain is reset when pmmic bit is ? 0 ? , and then ipga operation starts from the default value when pmmic is changed to ? 1 ? .
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 69 - n headphone - amp output fs2-0 bits (addr:05h, d7-5) attl7-0 bits (addr:0ch 0dh, d7-0) hpl/r bit (addr:03h, d1-0) pmhpl/r bits (addr:01h, d2-1) hpl/r pins xxx 000 0000000 xxxxxxx normal output external mute (1) bst1-0 bits (addr:06h, d3-2) 00 xx 00 (2) (3) (7) (8) (12) pmdac bit (addr:01h, d0) (4) (11) (5) (9) (6) (10) example : x ? tal and pll are used. sampling frequency : 44.1khz dattc bit = ? 1 ? (default) digital attenuator level : - 8db bass boost level : middle de - emphases response : off soft mute time : 1024/fs (1) addr:05h, data:00h (3) addr:0ch, data 10h (4) addr:01h, data 61h (7) release external mute playb ack (2) addr:06h, data 19h (8) enable external mute (9) addr:01h, data 61h (10) addr:02h, data 83h (5) addr:02h, data 80h (6) addr:01h, data 67h (11) addr:01h, data 60h (12) addr:06h , data 11h figure 51 . headphone - amp output sequence at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs2 - 0 bits) if pll mode is used. (2) set up the low frequency boost level(bst1 - 0 bits) (3) set up the digital volum e(addr : 0ch and 0dh) at dattc bit = ? 1 ? (default), attl7 - 0 bits of address 0ch control both lch and rch attenuation level. (4) power up dac : pmdac bit = ? 0 ? ? ? 1 ? (5) power up headphone - amp : hpl bit = hpr bit = ? 1 ? ? ? 0 ? output voltage of headphone - amp is still hvss. (6) rise up the common voltage of headphone - amp : pmhpl bit = pmhpr bit = ? 0 ? ? ? 1 ? the rising time after power up headphone - amp depends on the capacitor value connected with the mutet pin. when this capacitor value is 1.0 m f, the time constant is t r = 10 0ms(typ). (7) release the external mute. (8) enable the external mute. (9) fall down the common voltage of headphone - amp : pmhpl bit = pmhpr bit = ? 1 ? ? ? 0 ? the rising time after power up headphone - amp depends on the capacitor value connected with the mutet pin. when this capacitor value is 1.0 m f, the time constant is t f = 100ms(typ). if the power supply is powered off or headphone - amp is powered - down before the common voltage goes to gnd, some click noise occurs. it takes 2times of t f that the common voltage goes to g nd. (10) power down headphone - amp : hpl bit = hpr bit = ? 0 ? ? ? 1 ? (11) power down dac : pmdac bit = ? 1 ? ? ? 0 ? (12) off the low frequency boost level (bst1 - 0 bits = ? 00 ? )
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 70 - n speaker - amp output fs2-0 bits (addr:05h, d7-5) attl7-0 bits (addr:0ch 0dh, d7-0) pmdac bit (addr:01h, d0) pmspk bit (addr:01h, d3) xxx 000 0000000 xxxxxxx spp pin normal output spps bit (addr:05h, d0) hi-z hi-z spn pin normal output hi-z hi-z hvdd/2 hvdd/2 (1) (3) x 0 (2) alc2 bit (addr:09h, d6 (4) (5) (7) (6) example : x ? tal and pll are used. sampling frequency : 48khz dattc bit = ? 1 ? (default) digital attenuator level : 0db alc1 : disable alc2 : disable (1) addr:05h, data60h (3) addr:0ch, data 00h (4) addr:01h, data 69h (5) addr:05h, data 61h playback (2) addr:09h, data 00h (6) addr:05h, data 60h (7) add r:01h, data 60h figure 52 . speaker - amp output sequence at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs2 - 0 bits) if pll mode is used. (2) set up the alc2 enable/disable(alc2 bit) (3) set up the digital vol ume(addr : 0ch and 0dh) at dattc bit = ? 1 ? (default), attl7 - 0 bits of address 0ch control both lch and rch attenuation level. (4) power up of dac and speaker - amp : pmdac bit = pmspk bit = ? 0 ? ? ? 1 ? the initializing time of speaker - amp is 2048/fs=46.4ms@fs=44.1k hz. (5) exit the power - save - mode of speaker - amp : spps bit = ? 0 ? ? ? 1 ? (6) enter the power - save - mode of speaker - amp : spps bit = ? 1 ? ? ? 0 ? (7) power down dac and speaker - amp : pmdac bit = pmspk bit = ? 1 ? ? ? 0 ?
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 71 - n stop of clock mcki can be stopped when pmmic=pmadc= pmdac=pmspk= ? 0 ? . 1. when x ? tal is used in pll mode mckpd bit (addr:01h, d7) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:03h, d4) (1) (2) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:04h, data:62h (2) addr:01h, data:80h figure 53 . stop of clock sequence (1) (1) disable mcko output : mcko bit = ? 1 ? ? ? 0 ? (2) power down x ? tal and pll, pull do wn the xti pin : pmxtl bit = pmpll bit = ? 1 ? ? ? 0 ? , mckpd = ? 0 ? ? ? 1 ? 2. when an external clock is used in pll mode mckpd bit (addr:01h, d7) external mclk pmpll bit (addr:01h, d5) mcko bit (addr:03h, d4) input (1) (2) (3) example : audio i/f : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:04h, data:62h (2) addr:01h, data:80h (3) stop external clock figure 54 . stop of clock sequence (2) (1) stop mcko ou tput : mcko bit = ? 1 ? ? ? 0 ? (2) power down pll, pull down the xti pin : pmpll bit = ? 1 ? ? ? 0 ? , mckpd = ? 0 ? ? ? 1 ? when the external mcki becomes hi - z or the external mcki is input by ac couple, mcki pin should be pulled down. (3) stop an external mcki
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 72 - 3. external c lock mode mckpd bit (addr:01h, d7) external mclk input example : (1) addr:01h, data:80h (2) stop external clock figure 55 . stop of clock sequence (3) (1) pull down the xti pin : mckpd = ? 0 ? ? ? 1 ? when the external mcki becomes hi - z or the external mcki is input by ac c ouple, mcki pin should be pulled down. (2) stop an external mcki n power down power down vcom(pmvcm= ? 1 ? ? ? 0 ? ) after all blocks except vcom are powered down and mcki stops. the AK4640 is also powered - down by pdn pin = ? l ? . when pdn pin = ? l ? , the registers are initialized.
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 73 - package (AK4640vg) 57pin bga (unit: mm) 5.0 0.1 5.0 0.1 0.5 a b c d e f g 7 6 5 4 3 2 1 57 - f 0. 3 0.05 h j 9 8 0.08 s s f 0.05 a b s b 0.5 m a 4.0 1.0max 0.25 0. 05 n material & lead finish package molding compound: epoxy interposer material : bt resin solder ball material : snagcu
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 74 - package (AK4640vn) 52pin qfn (unit: mm) 7.2 0.20 14 26 7.2 0.20 0.30 0.10 7.0 0.10 7.0 0.10 0.21 0.05 0.60 0.10 0.05 0.02 + 0.03 - 0.02 0.78 + 0.17 - 0.28 0.80 + 0.20 - 0.00 13 1 52 40 27 39 27 39 40 52 13 1 14 26 0.20 + 0.10 - 0.20 45 45 0.05 m 4 - c0.6 0.18 0.05 0.40 note) the part of black at four corners on reverse side must not be soldered and must be open. n material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate (pb free)
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 75 - marking (AK4640vg) 4640 xxxx xxxx: date code (4 digit) pin #1 indication
asahi kasei akm confidential [ AK4640] rev 0.6 2003/07 - 76 - marking (AK4640vn) 1 AK4640vn xxxxxxx akm xxxxxxx : date code identifier (7 digits) i m portant notice these products and their specifications are subject to chang e without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectua l property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the c ountry of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one who se failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and r eliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or dist ributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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