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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad6622 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 four-channel, 75 msps digital transmit signal processor (tsp) functional block diagram ch a ch b ch c ch d rcf nco 18 18 port cic filter sport sport sport sport rcf rcf rcf cic filter cic filter cic filter nco nco nco jtag summation features wideband digital if parallel output wideband digital if parallel input allows cascade of chips for additional channels programmable if and modulation for each channel programmable interpolating ram coef?cient filter high-speed cic interpolating filter nco frequency translation worst spur better than 100 dbc tuning resolution better than 0.02 hz real or complex outputs digital summation of channels clipped or wrapped overrange twos complement or offset binary output separate 3-wire serial data input for each channel microprocessor control jtag boundary scan applications cellular/pcs base stations micro/pico cell base stations wbcdma wireless local loop base stations phase array beam forming antennas product description the ad6622 comprises four identical digital transmit signal processors (tsps) complete with synchronization circuitry and cascadable wideband channel summation. an external digital- to-analog converter (dac) is all that is required to complete a wide band digital up-converter. on-chip tuners allow the rela tive phase and frequency for each rf carrier to be independently controlled. each tsp has three cascaded signal processing elements: a ram-programmable coef?ient interpolating filter (rcf), a programmable cascaded integrator comb (cic) interpolating lter, and a numerically controlled oscillator/tuner (nco). the outputs of the four tsps are summed and scaled on-chip. in multichannel wideband transmitters, multiple ad6622s may be combined using the chip? cascadable output summation stage. each channel provides independent serial data inputs that may be directly connected to the serial port of dsp chips. user pro- grammable fir ?ters can be used to ?ter linear inputs. all control registers and coef?ient values are programmed through a generic microprocessor interface. two microprocessor bus modes are supported. all inputs and outputs are lvcmos compatible. all outp uts are lvcmos and 5 v ttl compatible.
C2C rev. 0 ad6622?pecifications recommended operating conditions test ad6622as parameter level min typ max unit vdd iv 2.4 3.0 3.3 v t ambient iv ?0 +25 +70 c electrical characteristics test ad6622as parameter (conditions) temp level min typ max unit logic inputs (5 v tolerant) 3.0 v cmos logic compatibility full logic ??voltage full iv 2.0 vdd + 0.3 v logic ??voltage full iv ?.3 +0.8 v logic ??current full iv 1 10 a logic ??current full iv 1 10 a input capacitance 25 cv 4 pf logic outputs logic compatibility full logic ??voltage (i oh = 0.25 ma) full iv vdd ?0.05 vdd ?0.035 v logic ??voltage (i ol = 0.25 ma) full iv 0.02 0.05 v idd supply current clk = 60 mhz, 3.3 v 1 full iv 506 566 1 ma clk = gsm example v 297 2 ma clk = is-136 example v 240 2 ma clk = wbcdma example v 209 2 ma sleep mode full iv 0.1 0.5 ma power dissipation clk = 60 mhz, 3.3 v 1 full iv 1.77 1.87 w clk = gsm example v 0.89 2 w clk = is-136 example v 0.72 2 w clk = wbcdma example v 0.627 2 w sleep mode full iv 0.33 1.65 mw notes 1 this speci?ation denotes an absolute maximum supply current for the device. the conditions include all channels active, minimu m interpolation in both cic stages, maximum switching of input data, and maximum vdd of 3.3 v. in an actual application the power will be less; see the ther mal management section of the data sheet for further details. 2 gsm interpolation = 120 at 65 mhz, 4 channels active, is-136 interpolation = 2560 at 62.208 mhz, 4 channels active. wbcdma inte rpolation = 64, 4 channels interleaved at 61.44 mhz. speci?ations subject to change without notice. ad6622 C3C rev. 0 timing characteristics 1 test ad6622as name parameter (conditions) temp level min typ max unit clk timing requirements : t clk clk period full iv 13.3 ns t clkl clk width low full iv 5.5 0.5 t clk ns t clkh clk width high full iv 5.5 0.5 t clk ns reset timing requirements : t resl reset width low full iv 30.0 ns input wideband data timing requirements : t si input to clk setup time full iv 0.5 ns t hi input to clk hold time full iv 3.5 ns parallel output switching characteristics : t so clk to output setup time full iv 12 ns t ho clk to output hold time full iv 4.1 ns t zo output three-state time full v 5 ns sync timing requirements : t ss sync to clk setup time full iv 2.6 ns t hs sync to clk hold time full iv 1.5 ns serial port timing requirements : t dsclk clk to sclk delay full v 8.5 ns t dsdfs sclk to sdfs delay full iv ?.2 +2.4 ns t ssi sdi to sclk setup time full iv 8.5 ns t hsi sdi to sclk hold time full iv 5.5 ns t scs serial clock skew full iv 7 ns microprocessor port, mode inm (mode = 0) mode inm write timing : t hwr wr (r/ w ) to rdy( dtack ) hold time full iv 0 ns t sam address/data to wr (r/ w ) setup time full iv 0 ns t ham address/data to rdy( dtack ) hold time full iv 0 ns t drdy wr (r/ w ) to rdy( dtack ) delay full iv 10.2 ns t acc fast wr (r/ w ) to rdy( dtack ) high delay full iv 2 t clk 3 t clk ns t acc medium wr (r/ w ) to rdy( dtack ) high delay full iv 3 t clk 4 t clk ns t acc slow wr (r/ w ) to rdy( dtack ) high delay full iv 4 t clk 5 t clk ns mode inm read timing : t sam address to rd ( ds ) setup time full iv 0 ns t ha address to data hold time full iv 0 ns t zd data three-state delay full iv 3.4 7 10.5 ns t dd rdy( dtack ) to data delay full iv t clk ?10 ns t drdy rd ( ds ) to rdy( dtack ) delay full iv 10.2 ns t acc fast rd ( ds ) to rdy( dtack ) high delay full iv 2 t clk 3 t clk ns t acc medium rd ( ds ) to rdy( dtack ) high delay full iv 3 t clk 4 t clk ns t acc slow rd ( ds ) to rdy( dtack ) high delay full iv 4 t clk 5 t clk ns (c load = 40 pf, all outputs unless speci?d) ad6622 C4C rev. 0 test ad6622as name parameter (conditions) temp level min typ max unit microprocessor port, mode mnm (mode = 1) mode mnm write timing : t hds ds ( rd ) to dtack (rdy) hold time full iv 0 ns t hrw r/ w ( wr ) to dtack (rdy) hold time full iv 0 ns t sam address/data to r/ w ( wr ) setup time full iv 0 ns t ham address/data to r/ w ( wr ) hold time full iv 0 ns t ddtack ds ( rd ) to dtack (rdy) delay full iv 1 t clk ns t acc fast r/ w ( wr ) to dtack (rdy) low delay full iv 2 t clk 3 t clk ns t acc medium r/ w ( wr ) to dtack (rdy) low delay full iv 3 t clk 4 t clk ns t acc slow r/ w ( wr ) to dtack (rdy) low delay full iv 4 t clk 5 t clk ns mode mnm read timing : t sam address to ds ( rd ) setup time full iv 0 ns t ha address to data hold time full iv 0 ns t zd data three-state delay full iv 0 ns t dd dtack (rdy) to data delay full iv t clk ?10 ns t ddtack ds ( rd ) to dtack (rdy) delay full iv 1 t clk ns t acc fast ds ( rd ) to dtack (rdy) low delay full iv 2 t clk 3 t clk ns t acc medium ds ( rd ) to dtack (rdy) low delay full iv 3 t clk 4 t clk ns t acc slow ds ( rd ) to dtack (rdy) low delay full iv 4 t clk 5 t clk ns notes 1 all timing speci?ations valid over vdd range of 2.4 v to 3.3 v. speci?ations subject to change without notice. clk out[17:0], qout t clk t clkl t clkh t zo t ho t zo oen t so figure 1. parallel output switching characteristics clk sclk sdfs sdi clkn datan t dsclk t dsdfs t dsdfs t ssi t hsi figure 2. serial port switching characteristics clk in[17:0], qin t si t hi figure 3. wideband input timing sync clk t ss t hs figure 4. sync timing inputs ad6622 C5C rev. 0 wr (r/ w ) rd ( ds ) cs a[2:0] d[7:0] rdy ( dtack ) t hwr t sam t ham t sam t ham t drdy t acc valid address valid data 1. t acc access time depends on the address accessed. access time is measured from the fe of wr to the re of rdy. 2. t acc fast requires a maximum of three clk periods and applies to a[2:0] = 7, 6, 5, 3, 2, 1 3. t acc medium requires a maximum of four clk periods and applies to a[2:0] = 4 and 0 if the access is to a control register versus a ram register. 4. t acc slow requires a maximum of five clk periods and applies to a[2:0] = 0 when accessing ram registers. figure 5. inm microport write timing requirements wr (r/ w ) rd ( ds ) cs a[2:0] d[7:0] rdy ( dtack ) t sam t acc valid address t zd t drdy valid data t dd t ha t zd 1. t acc access time depends on the address accessed. access time is measured from the fe of wr to the re of rdy. 2. t acc fast requires a maximum of three clk periods and applies to a[2:0] = 7, 6, 5, 3, 2, 1 3. t acc medium requires a maximum of four clk periods and applies to a[2:0] = 4 and 0 if the access is to a control register versus a ram register. 4. t a cc slow requires a maximum of five clk periods and applies to a[2:0] = 0 when accessing ram registers. figure 6. inm microport read timing requirements ad6622 C6C rev. 0 1. t acc access time depends on the address accessed. access time is measured from the fe of ds to the fe of dtack . 2. t acc fast requires a maximum of four clk periods and applies to a[2:0] = 7, 6, 3, 2, 1 3. t acc medium requires a maximum of five clk periods and applies to a[2:0] = 4, 5, and 0 if the access is to a control register versus a ram register. 4. t acc slow requires a maximum of six clk periods and applies to a[2:0] = 0 when accessing ram registers. r/ w ( wr ) ds ( rd ) cs a[2:0] d[7:0] dtack (rdy) t hrw t sam t ham t sam t ham t acc valid address valid data t ddtack t hds figure 7. mnm microport write timing requirements 1. t acc access time depends on the address accessed. access time is measured from the fe of ds to the fe of dtack . 2. t acc fast requires a maximum of four clk periods and applies to a[2:0] = 7, 6, 3, 2, 1 3. t acc medium requires a maximum of five clk periods and applies to a[2:0] = 4, 5, and 0 if the access is to a control register versus a ram register. 4. t acc slow requires a maximum of six clk periods and applies to a[2:0] = 0 when accessing ram registers. r/ w ( wr ) ds ( rd ) cs a[2:0] d[7:0] dtack (rdy) t sam t acc valid address t zd valid data t dd t ha t zd t hds t ddtack figure 8. mnm microport read timing requirements ad6622 C7C rev. 0 absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +3.6 v input voltage . . . . ?.3 v to vdd +0.3 v (not 5 v tolerant) in[17:0], qin, oen input voltage . . . . . . . . . . . . . ?.3 v to +3.6 v (5 v tolerant) clk, reset , ds , r/ w , mode, a[2:0], d[7:0], sync, trst , tck, tms, tdi, sdina, sdinb, sdinc, sdind output voltage swing . . . . . . . . . . . . ?.3 v to vdd + 0.3 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf junction temperature under bias . . . . . . . . . . . . . . . . . 125 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280 c * stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the devices at these or any other conditions greater than those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics 128-lead mqfp: ja = 33 c/w, no airflow ja = 27 c/w, 200 lfpm airflow ja = 24 c/w, 400 lfpm airflow jc = 5.5 c/w thermal measurements made in the horizontal po sition on a 2-layer board. explanation of test levels i. 100% production tested. ii. 100% production tested at 25 c, and sample tested at speci?d temperatures. iii. sample tested only. iv. parameter guaranteed by design and analysis. v. parameter is typical value only. vi. 100% production tested at 25 c, and sample tested at temperature extremes. ordering guide model temperature range package description package option ad6622as ?0 c to +70 c (ambient) 128-lead mqfp (metric quad flatpack) s-128a ad6622s/pcb evaluation board with ad6622 and software caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad6622 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ad6622 C8C rev. 0 pin configuration gnd tms tdo tdi sclka sdfsa sdina sclkb sdfsb gnd gnd gnd sdinb sclkc sdfsc sdinc vdd gnd vdd vdd sclkd sdfsd sdind gnd vdd gnd gnd tck trst gnd gnd in0 gnd gnd in1 in2 in3 in4 vdd in5 in6 in7 in8 gnd gnd in16 gnd gnd in17 qin gnd gnd clk vdd gnd gnd in9 in10 in11 in12 vdd in13 in14 in15 d7 gnd gnd gnd d6 gnd gnd sync reset cs vdd a0 a1 a2 mode gnd gnd vdd gnd r/ w ( wr ) dtack (rdy) ds ( rd ) d0 d1 d2 d3 d4 gnd vdd d5 gnd gnd gnd oen gnd gnd gnd out0 out1 out2 gnd out3 out4 out5 out6 vdd out7 out8 out9 out10 gnd gnd gnd out11 out12 out13 out14 vdd out15 out16 out17 qout gnd gnd 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 65 98 99 101 97 102 100 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 pin 1 identifier top view (not to scale) ad6622 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 59 55 50 51 52 53 54 56 57 58 66 denotes i/o power pin denotes core power pin ad6622 C9C rev. 0 pin function descriptions pin number name type description 1, 3?, 9, 19?1, 31, 32, gnd p ground connection 34?6, 38, 39, 42, 52?4, 63?5, 68, 69, 72, 73, 83?5, 95, 96, 98, 99, 102, 103, 105, 115?17, 126, 128 2 oen i active high output enable pin (actively pulled down if not conn ected) (not 5 v tolerant) 27?9, 22?5, 15?8, 10?3, out[17:0] o/t wideband output data 6? 14, 26, 41, 47, 122 vdd p +3.0 v supply (i/o supply) 59, 66, 78, 90, 104, 110, 127 vdd p +3.0 v supply (core supply) 30 qout o/t indicates q output data (complex output mode) 33, 37, 40, 43?6, 48 d[7:0] i/o/t microprocessor interface data 49 ds ( rd) i inm mode: read signal, mnm mode: data strobe signal 50 dtack (rdy) o acknowledgment of a completed transaction (signals when p port is ready for an access) open drain, must be pulled up externally 51 r/ w ( wr ) i read/write line (write signal) 55 mode i sets microport mode: mode = 1, mnm mode; mode = 0, inm mode 56?8 a[2:0] i microprocessor interface address 60 cs i chip select, enable the chip for p access 61 reset i active low reset pin (actively pulled up if not connected) 62 sync i sync signal for synchronizing multiple ad6622s (actively pulled down if not connected) 67 clk i input clock (actively pulled down if not connected) 70 qin i indicates q input data (complex input mode) (actively pulled down if not connected) (not 5 v tolerant) 71, 74?7, 79?2, 86?9, in[17:0] i wideband input data (allows cascade of multiple ad6622 chips in 91?4, 97 a system) (actively pulled down if not connect ed) (not 5 v tolerant) 100 trst i test reset pin (actively pulled up if not connected) 101 tck i test clock input (actively pulled down if not connected) 106 tms i test mode select (actively pulled up if not connected) 107 tdo o test data output 108 tdi i test data input (actively pulled down if not connected) 109 sclka o serial clock output channel a 111 sdfsa o serial data frame sync output channel a 112 sdina i serial data input channel a (actively pulled down if not connected) 113 sclkb o serial clock output channel b 114 sdfsb o serial data frame sync output channel b 118 sdinb i serial data input channel b (actively pulled down if not connected) 119 sclkc o serial clock output channel c 120 sdfsc o serial data frame sync output channel c 121 sdinc i s erial data input channel c (actively pulled down if not conn ected) 123 sclkd o serial clock output channel d 124 sdfsd o serial data frame sync output channel d 125 sdind i serial data input channel d ( actively pulled down if not c onnected) ad6622 C10C rev. 0 theory of operation as digital-to-analog converters (dacs) achieve higher sampling rates, analog bandwidth, and dynamic range, it becomes increas- ingly attractive to accomplish the ?st if stage of a transmitter in the digital domain. digital if signal processing provides repeatable manufacturing, higher accuracy, and more flexibility than comparable high-dynamic-range analog designs. the ad6622 four-channel t ransmit signal processor (tsp) is designed to bridge the gap between dsps and high-speed dacs. the wide range of interpolation factors in each ?ter stage makes the ad6622 useful for creating both narrowband and wideband carriers in a high-speed sample stream. the high-resolution nco allows flexibility in frequency plann ing and supports both digital and analog air interface standards. the ram-based architec- ture allows easy recon?uration for multimode applications. the interpolating ?ters remove unwanted images of signals sampled at a fraction of the wideband rate. when the channel of interest occupies far less bandwidth than the wideband output signal, rejecting out-of-band noise is called ?rocessing gain. for large interpolation factors, this processing gain allows a 14-bit dac to express the sum of multiple 16-bit signals sam pled at a lower rate without signi?antly increasing the noise floor about each carrier. in addition, the programmable ram coef? cient stage allows anti-imaging, and static equalization functions to be combined in a single, cost-effective ?ter. the high-speed nco can be used to tune a quadrature sampled signal to an if channel, or the nco can be directly frequency- modulated at an if channel. multicarrier phase synchronization pins and phase offset registers allow intelligent management of the relative phase of the independent rf channels. this capability supports the requirements for phased array antenna architec- tures and management of the wideband peak/power ratio to minimize clipping at the dac. the wideband input and output ports allow multiple ad6622s to be cascaded into a single dac. the master clock for the entire system is based on the dac clock rate (up to 75 msps). the external 18-bit resolution reduces summation of truncation noise. the wideband ports can be con?ured for real or quadra- ture outputs. quadrature sampled outputs (i and q) are limited to half the master clock rate on the shared output bus. functional overview the following descriptions explain the functionality of each of the core sections of the ad6622. detailed timing, application, and speci?ations are described in detail in their respective por- tions of the data sheet. serial data port the ad6622 has four independent serial ports (a, b, c, and d) of which accepts data to its own channel (1, 2, 3, or 4) of the device. each serial port has three pins: sclk, sdfs, and sdin. the sclk and sdfs pins are outputs that provide serial clock and framing. the sdin pins are inputs that accept channel data. the serial ports do not accept con?uration or control inputs. the serial ports do not accept external clock or framing signals, although it is possible to synchronize the ad6622 serial ports to meet an external timing requirement. the serial clock output, sclk, is created by a programmable internal counter that divides down the master clock. when the channel is reset, sclk is held low. sclk starts on the ?st rising edge of clk after channel reset is removed (d0 through d3 of external address 4). once active, the sclk fre quency is determined by the master clk frequency and the sclk divider, according to the equation below. the sclk d ivider is a 5-bit unsigned value located in channel register 0x0d. the user must select the sclk divider to en sure that sclk is fast enough to accept full input sample words at the input sample rate. see the design example at the end of this section. the maximum sclk frequency is 1/2 of the master clock frequency. the minimum sclk frequency is 1/64 of the master clock frequency. f f sclk sclk clk divider = + 21 () (1) sport sdina sdfsa sclka data rcf i q cic filter i q nco data jtag tdo tms trst tdi microport ds dtack r/ w d[7:0] mode a[2:0] cs sport sdinb sdfsb sclkb data rcf i q cic filter i q nco datb sport sdinc sdfsc sclkc data rcf i q cic filter i q nco datc sport sdind sdfsd sclkd data rcf i q cic filter i q nco datd summation clk reset qin in [17:0] sync oen qout out [17:0] tck ad6622 figure 9. functional block diagram ad6622 C11C rev. 0 the serial data frame sync output, sdfs, is pulsed high for one sclk cycle at the input sample rate. the input sample rate is determined by the master clock divided by channel interpolation factor. if the sclk rate is not an integer multiple of the input sample rate, the sdfs will continually adjust the period by one sclk cycle in order to keep the average sdfs rate equal to the input sample rate. when the channel is in sleep mode, sdfs is held low. the rst sdfs is delayed by the channel reset latency after the channel reset is removed. the channel reset latency varies dependent on channel con guration. the serial data input, sdin, accepts 32-bit words as channel input data. the 32-bit word is interpreted as two 16 bit two s complement quadrature words, i followed by q, msb rst. the rst bit is shifted into the serial port starting on the second rising edge of sclk after sdfs goes high, as shown by the timing diagram below. clk sclk sdfs sdi clkn datan t dsclk t dsdfs t dsdfs t ssi t hsi figure 10. serial port switching characteristics as an example of the serial port operation, consider a clk fre- quency of 62.208 msps and a channel interpolation of 2560. in that case, the input sample rate is 24.3 ksps (62.208 msps/ 2560), w hich is also the sdfs rate. substituting, f sclk 32 f sdfs into the equation below and solving for sclk divider , we nd the maximum value for sclk divider according to equation 2. sclk f divider sdfs f clk 64 1 (2) evaluating this equation for our example, sclk divider must be less than or equal to 39. since the sclk divider channel regis- ter is a 5-bit unsigned number it can only range from 0 to 31. any value in that range will be valid for this example, but if it is important that the sdfs period is constant, then there is another restriction. for regular frames, the ratio f sclk /f sdfs must be equal to an integer of 32 or larger. for this example, constant sdfs periods can only be achieved with an sclk divider of 19. in conclusion, the sdfs rate is determined by the ad6622 m aster clock rate and the interpolation rate of the channel. the sdfs rate is equal to the channel input rate. the cha nnel interpola- tion is equal to rcf interpolation times cic5 interpolation, times cic2 interpolation ll l l rcf cic cic = 52 (3) the sclk rate is determined by the ad6622 master clock rate and sclk divider . the sclk is a divided version of the ad6622 master clk. the s clk divide ratio is determined by sclk divider as shown in equation 2. the sclk must be fast enough to input 32 bits of data prior to the next sdfs. extra sclks are ignored by the serial port. programmable interpolating ram coefficient filter (rcf) each channel has a fully independent ram coef cient filter (rcf). the rcf accepts data from the serial port, lters it, and passes the result to the cic lter. the rcf implements a fir lter with optional interpolation. the fir lter can produce impulse responses up to 128 output samples long. the fir response may be inter polated up to a factor of 128, although the best lter performance is usually achieved if the rcf inter- polation factor is con ned to 8 or below. fir filter implementation the rcf accepts quadrature samples from the serial port with a xed point resolution of 16 bits each, for i and q. serial port data mem rcf rcf coarse scale coefficient mem iq to cic filter sdfs sclk sdin 16,16 accumulator 16,16 16,16 figure 11. rcf block diagram the ad6622 rcf realizes a sum-of-products lter using a poly- phase implementation. this mode is equivalent to an interpola- tor followed by a fir lter running at the interpolated rate. in figure 12, the interpolating block increases the rate by the rcf interpolation factor (l rcf ) by inserting l rcf -1 zero valued samples between every input sample. the next block is a lter with a nite impulse response length (n rcf ) and an im pulse response of h[n], where n is an integer from 0 to n rcf -1. l rcf f in a b c f in l rcf n rcf tap fir filter h[n] f in l rcf figure 12. rcf interpolation the difference equation for figure 12 is written below, where h[n] is the rcf impulse response, b[n] is the interpolated input sample sequence at point b in figure 12, and c[n] is the out- put sample sequence at point c in the figure 12. cn hk n bn k n rcf [] [ ] [] =? = ? 0 1 (4) this difference equation can be described by the transfer func- tion from point b to c as shown equation 5. hz hn z bc n n n rcf () [] = = ? ? 0 1 (5) the actual implementation of this lter uses a polyp hase decomposition to skip the multiply-accumulates when b[n] is zero. compared to the diagram above, this implementation has the bene ts of reducing by a factor of l rcf both the time needed to calculate an output and the required data memory (dmem). the price of these bene ts is that the user must place the coef cients into the coef cient memory (cmem) indexed by the interpo- lation phase. the process of selecting the coef cients and placing them into the cmem is broken into three steps shown below. ad6622 C12C rev. 0 1. select the impulse response length (n rcf ) and the inter- polation factor (l rcf ). the impulse response length (n rcf ) is limited in three ways: by the available calculation time, by the data memory size (dmem), and by the coef - cient memory size (cmem). the equation below shows that n rcf is limited to the minimum of these three conditions. time cmem restriction restriction n l l rcf rcf ? ? ? ? ? ? ? min , , 2 16 128 (6) dmem restriction where: l = l rcf l cic5 l cic2 2. the interpolation rate (l rcf ) may be any integer of n rcf ranging from 1 to 128, while meeting the above equation. most lter designs can be optimized by choosing the small- est l rcf that does not compromise the image rejection of the subsequent cic lter. the quality of an interpolating lter is a strong function of the n rcf /l rcf ratio and a w eaker function of n rcf . the best lters are usually achieved by maximizing n rcf /l rcf (no larger than 16) and then increasing both n rcf and l rcf by the same ratio until the lter becomes time or cmem limited. 3. once n rcf and l rcf are selected, channel register 0x0a is programmed to n rcf 1, and channel register 0x0c is programmed to n rcf /l rcf 1. 4. determine the impulse response. the impulse response relative to the rcf output rate can be calculated using ordi- nary fir design techniques. in most cases, it is desirable to precompensate the inband frequency roll-off of the cic l- ter that follows. there are no symmetry requirements, so the rcf can also be used for static phase equalization. the impulse response must be quantized to 16-bit two s comple- ment numbers for the cmem. the channel center gain and worst-case peak can be calculated for each of the l rcf phases (p) according to the equations below. a rcf coarse scale factor (g) that ranges between 0 and 3 is provided to limit the gain without excessive loss of resolution in the cmem. the coarse scale factor is located in channel register 0x0d. channelcentergain h k l p p g rcf k n l rcf rcf = + ? = 2 0 1 [] (7) 5. the channel center gain is the response to a constant full- scale in put at every output phase. the summ ation is split into phases because the interpolation of the data insures that only n rcf /l rcf coef cients can be active for any single output. for l rcf = 1, there is only one phase and the channel center gain is the simple sum of all the coef cients, scaled by 2 g . if the channel center gain is not the same for every value of p, some or all of the images of the channel center will be imperfectly rejected by the rcf. worstcasepeak h k l p p g rcf k n l rcf rcf = + ? = 2 0 1 |[ ]| (8) 6. the worst-case peak is calculated similarly to the channel center gain, except that the input sequence swings from full- scale positive to full-scale negative to match the polarity of the coef cient by which it will be multiplied, so that each prod- uct is positive. this results in a maximal that must be less than one to guarantee no possibility of wrapping. note that when l rcf is greater than one, each phase may produce its worst-case peak in response to a different input sequence. 7. programming dmem and cmem. the dmem must be initialized to all zeros to avoid any unpredictable start-up transients since a reset does not c lear the memory. the impulse response h[n] must be reordered by phase for the cmem as shown in the code below. several lters with impulse lengths that total less than 128 can be programmed into the cmem simultaneously and selected later using the rcf offset pointer (o rcf ) which is set by channel register 0x0b. / * reorder fir coef?ients for ad6622 cmem * / for (p=0; p ad6622 C14C rev. 0 table ii lists maximum bandwidth that will be rejected to various levels for cic5 interpolation factors from 1 to 32. figure 15 corresponds to the listing in the 110 db column and the l cic5 = 5 row. it is worth noting that the rejection of the cic5 improves as the interpolation factor increases. table ii. cic5 alias protection ?10 db ?00 db ?0 db ?0 db ?0 db 1 full full full full full 2 0.101 0.127 0.160 0.203 0.256 3 0.126 0.159 0.198 0.246 0.307 4 0.136 0.170 0.211 0.262 0.325 5 0.141 0.175 0.217 0.269 0.333 6 0.143 0.178 0.220 0.272 0.337 7 0.144 0.179 0.222 0.275 0.340 8 0.145 0.180 0.224 0.276 0.341 9 0.146 0.181 0.224 0.277 0.342 10 0.146 0.182 0.225 0.278 0.343 11 0.147 0.182 0.226 0.278 0.344 12 0.147 0.182 0.226 0.279 0.344 13 0.147 0.183 0.226 0.279 0.345 14 0.147 0.183 0.226 0.279 0.345 15 0.148 0.183 0.227 0.280 0.345 16 0.148 0.183 0.227 0.280 0.345 17 0.148 0.183 0.227 0.280 0.346 18 0.148 0.183 0.227 0.280 0.346 19 0.148 0.183 0.227 0.280 0.346 20 0.148 0.184 0.227 0.280 0.346 21 0.148 0.184 0.227 0.280 0.346 22 0.148 0.184 0.227 0.280 0.346 23 0.148 0.184 0.227 0.280 0.346 24 0.148 0.184 0.227 0.280 0.346 25 0.148 0.184 0.227 0.281 0.346 26 0.148 0.184 0.227 0.281 0.346 27 0.148 0.184 0.227 0.281 0.346 28 0.148 0.184 0.227 0.281 0.346 29 0.148 0.184 0.227 0.281 0.346 30 0.148 0.184 0.227 0.281 0.346 31 0.148 0.184 0.227 0.281 0.346 32 0.148 0.184 0.228 0.281 0.346 cic2 the cic2 is a second-order interpolating cascaded integrator comb whose impulse response is completely de ned by its inter- polation factor, l cic2 . the value l cic2 1 can be independently programmed for each channel at location 0x08. while this con- trol register is 8 bits wide, l cic2 should be con ned to the ranges shown by the table below according to the interpolation factor of the cic5. exceeding the recommended guidelines may result in overflow for i nput sequences at or near full scale. while relatively small va lues of l cic5 allow for the larger overall interpolation factors with minimal power consumption, l cic5 should be maxi- mized to achieve the best overall image rejection. table iii. maximum l cic2 limits l cic5 max l cic2 1 19 256 20 209 21 172 22 143 23 119 24 101 25 85 26 73 27 63 28 54 29 47 30 41 31 36 32 32 the transfer function of the cic2 is given by the following equations with respect to the cic2 output sample rate, f out . cic z z z l cic 2 1 1 2 1 2 () = ? ? ? ? ? ? (14) this polynomial fraction can be completely reduced as follows, demonstrating a nite impulse response with perfect phase lin- earity for all values of l cic 2 . cic z z z e k k l j k l k l cic cic cic 2 0 2 1 2 1 2 2 1 2 2 1 () = ? ? ? ? ? ? ? ? =? ? ? ? ? ? ? ? ? ? = ? = ? (15) the frequency response of the cic2 can be expressed as follows. the maximum gain is l cic2 at baseband. the initial 1/l cic2 factor normalizes for the increased rate, which is appropriate when the samples are destined for a dac with a zero order hold output. cic f l lf f f f cic cic out out 2 1 2 2 2 () sin sin = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (16) as an example, we will consider an input from the cic5 whose bandwidth is 0.0033 of the cic5 rate, centered at baseband. interpolation by a factor of ve reveals ve images, as shown below. ad6622 C15C rev. 0 150 2 1 db 0 12 130 110 90 70 50 30 10 10 figure 16. unfiltered cic2 interpolation images the cic2 rejects each of the undesired images while passing the image at baseband. the images of a pure tone at channel center (dc) are nulled perfectly, but as the bandwidth increases the rejection is diminished. the lower band edge of the rst image alw ays has the least rejection. in this example, the cic2 is interpolating by a factor of ve and the input signal has a band- width of 0.0033 of the cic5 output sample rate. figure 17 shows 110 dbc rejection of the lower band edge of the rst image. all other image frequencies have better rejection. 150 2 1 db 01 2 130 110 90 70 50 30 10 10 figure 17. filtered cic2 interpolation images table iv lists maximum bandwidth that will be rejected to various levels for cic2 interpolation factors from 1 to 32. the example above corresponds to the listing in the 110 db column and the l cic2 = 5 row. it is worth noting that the rejection of the cic2 improves as the interpolation factor increases. table iv. cic2 alias protection ?10 db ?00 db ?0 db ?0 db ?0 db 1 full full full full full 2 0.0023 0.0040 0.0072 0.0127 0.0226 3 0.0029 0.0052 0.0093 0.0165 0.0292 4 0.0032 0.0057 0.0101 0.0179 0.0316 5 0.0033 0.0059 0.0105 0.0186 0.0328 6 0.0034 0.0060 0.0107 0.0189 0.0334 7 0.0034 0.0061 0.0108 0.0192 0.0338 8 0.0035 0.0062 0.0109 0.0193 0.0341 9 0.0035 0.0062 0.0110 0.0194 0.0343 10 0.0035 0.0062 0.0110 0.0195 0.0344 11 0.0035 0.0062 0.0110 0.0195 0.0345 12 0.0035 0.0062 0.0111 0.0196 0.0346 13 0.0035 0.0062 0.0111 0.0196 0.0346 14 0.0035 0.0063 0.0111 0.0196 0.0347 15 0.0035 0.0063 0.0111 0.0197 0.0347 16 0.0035 0.0063 0.0111 0.0197 0.0347 17 0.0035 0.0063 0.0111 0.0197 0.0348 18 0.0035 0.0063 0.0111 0.0197 0.0348 19 0.0035 0.0063 0.0111 0.0197 0.0348 20 0.0035 0.0063 0.0111 0.0197 0.0348 21 0.0035 0.0063 0.0111 0.0197 0.0348 22 0.0035 0.0063 0.0111 0.0197 0.0348 23 0.0035 0.0063 0.0111 0.0197 0.0348 24 0.0035 0.0063 0.0112 0.0197 0.0348 25 0.0035 0.0063 0.0112 0.0198 0.0349 26 0.0035 0.0063 0.0112 0.0198 0.0349 27 0.0035 0.0063 0.0112 0.0198 0.0349 28 0.0035 0.0063 0.0112 0.0198 0.0349 29 0.0035 0.0063 0.0112 0.0198 0.0349 30 0.0035 0.0063 0.0112 0.0198 0.0349 31 0.0035 0.0063 0.0112 0.0198 0.0349 32 0.0035 0.0063 0.0112 0.0198 0.0349 ad6622 C16C rev. 0 numerically controlled oscillator (nco) tuner each channel has a fully independent tuner. the tuner accepts data from the cic lter, tunes it to a digital intermediate fre- quency (if), and passes the result to a shared summa tion block. the tuner consists of a 32-bit quadrature nco and a quadrature amplitude mixer (qam). the nco serves as a local oscillator and the qam translates the interpolated channel data from baseband to the nco frequency. the worst-case spurious signal from the nco is better than 100 dbc for all output frequencies. the tuner can produce real or complex outputs as requested by the shared summation block. in the complex mode, the nco serves as a quadrature local oscillator running at f clk /2, capable of producing any fre quency between f clk /4 and +f clk /4 with a resolution of f clk /2 33 (0.0087 hz for f clk = 75 mhz). in the real mode, the nco serves as a quadrature local oscilla- tor running at f clk , capable of producing any frequency between f clk /2 and +f clk /2 with a resolution of f clk /2 32 (0.017 hz for f clk = 75 mhz). the quadrature portion of the output is dis- carded. negative frequencies are distinguished from positive frequencies solely by spectral inversion. the digital if is calculated using equation 17 below. ff nco frequency if nco = _ 2 32 (17) where: nco_frequency is the value written to 0x02, f if is the desired intermediate frequency, and f nco is f clk /2 for complex outputs and f clk for real outputs. phase dither the ad6622 provides a phase dither option for improving the spurious performance of the nco. phase dither is enabled by writing a one to bit 3 of channel register 0x01. when phase dither is enabled, spurs due to phase truncation in the nco are randomized. the choice of whether phase dither is used in a system will ultimately be decided by the system goals and the choice of if frequency. the 18 most signi cant bits of the phase accumulator are used by the angle to cartesian conversion. if the nco frequency has all zeroes below the 18th bit, then phase dither has no effect. if the fraction below the 18th bit is near a 1/2 or 1/3, etc., of the 18th bit, then spurs will accumulate sepa- rated from the if by 1/2 or 1/3, etc., of the clk frequency. the smaller the denominator of this residual fraction, the larger the spurs due to phase truncation will be. if the phase truncation spurs are unacceptably high for a given frequency, the phase dither can reduce these at the penalty of a slight elevation in total error energy. if the phase truncation spurs are small, phase dither will not be effective in reducing them further, but a slight eleva- tion in total error energy will occur. amplitude dither amplitude dither can also be used to improve spurious perfor- mance of the nco. amplitude dither is enabled by writing a one to bit 4 of channel register at 0x01. when enabled, amplitude dither can reduce spurs due to truncation at the input to the qam. if the entire frequency word is close to a fraction that has a small denominator, the spurs due to amplitude truncation will be large and amplitude dither will spread these spurs effectively. amplitude dither also will increase the total error energy by approximately 3 db. for this reason amplitude dither should be used judiciously. phase offset the phase offset (channel register 0x04) adds an offset to the phase accumulator of the nco. this is a 16-bit register that is interpreted as a 16-bit unsigned integer. phase offset ranges from 0 to nearly 2 radians with a resolution of /32768 radians. this register allows multiple ncos to be synchronized to pro- duce sine waves with a known phase relationship. nco frequency update and phase offset update hold-off counters the update of both the nco frequency and phase offset can be synchronized with internal hold-off counters. both of these counters are 16-bit unsigned integers and are clocked at the master clk rate. these hold-off counters, used in conjunction with the frequency or phase offset registers, allow beam form- ing and frequency hopping. see the synchronization section of this data sheet for additional details. the nco phase can also be cleared on sync (set to 0x0000) by setting bit 2 of channel register 0x01 high. nco output scale the output of the nco can be scaled in four steps of 6 db each via channel register 0x01, bits 1 0. table v is a table of the control scale. the nco always has loss to accommodate the possibility t hat both the i and q inputs may reach full-scale simul- taneously, resulting in a 3 db input magnitude. table v. control scale 0x01 bit 1 0x01 bit 0 nco output level 00 6 db 01 12 db 10 18 db 11 24 db 16 phase offset nco frequency word 16 32 32 32 32 i cos q sin i data from cic5 q data from cic5 on off on off clk phase amplitude pn gen. pn gen. d q d q angle to cartesian conversion figure 18. nco block diagram ad6622 C17C rev. 0 summation block the summation block of the ad6622 serves to combine the out- puts of each channel to create a composite multicarrier signal. the four channels are summed together and the result is then added with the 18-bit wideband input bus (in[17:0]). the nal summation is then driven on the 18-bit wideband output bus (out[17:0]) on the rising edge of the high speed clock. if the oen in put is high, this output bus is three-stated. if the oen input is low, this bus will be driven by the summed data. the oen is active high to allow the wide band output bus to be con nected to other buses without using extra logic. most other buses (like 374-type registers) require a low output e nable, which is opposite the ad6622 oen, thus eliminating extra circuitry. the wideband output bus may be interpreted as a two s comple- ment number or as an offset binary number as de ned by bit 1 of the summation mode control register at ad dress 0x000. when this bit is high, the wideband out put is in two's comple- ment mode and when it is low it is con gured for offset binary output data. the msb (bit 17) of the wideband output bus is typically used as a guard bit for the purpose of clipping the wideband output bus when bit 0 of the summation mode control register at address 0x000 is high. if clip detection is enabled, bit 17 of the output bus is not used as a data bit. instead, bit 16 will become the msb and be connected to the msb of the dac. con guring the dac in this manner gives the summation block a gain of 0 db. when clip detection is not enabled and bit 17 is used as a data bit, then the summation block will have a gain of 6.02 db. there are two data output modes. the rst is offset binary. this mode is used only when driving offset binary d acs. two s comple- ment mode may be used in one of two circumstances. the rst is when driving a dac that accepts two s complement data. the second is when driving another ad6622 in cascade mode. when clipping is enabled, the two s complement mode output bus will clip to 0x0ffff for output signals more positive than the output can express, and it will clip to 0x10000 for signals more negative than the output can express. in offset binary mode the output bus will clip to 0x1ffff for output signals more positive than the output can express, and it will clip to 0x00000 for sig nals more negative than the output can express. table vi. numerical data representation number represented output representation +full-scale two s complement 0x0ffff full-scale two s complement 0x10000 +full-scale offset binary 0x1ffff full-scale offset binary 0x00000 the wideband input is always interpreted as an 18-bit two s complem ent number and is typically connected to the wideband output bus of another ad6622 in order to send more than four carriers to a single dac. the output bus of the proceeding ad6622 should be con gured in two's complement mode and clip detection disabled. the 18-bit resolution ensures that the noise and spur performance of the wideband data stream does not become the limiting factor as large numbers of carriers are summed. there is a two-clock cycle latency from the wideband input bus to the wideband output bus. this latency may be cali brated out of the system by use of the start hold-off counter. the pre- ceding ad6622 in a cascaded chain can be started two high-speed clock cycles before the following ad6622 is started and the data from each ad6622 will arrive at the dac on the same clock cycle. in systems where the individual signals are not corre- lated, this is usu ally not necessary. the ad6622 is capable of outputting both real and complex data. when in real mode, the qin input is tied low signaling that all inputs on the wideband input bus are real and that all outputs on the wideband output bus are real. the wideband input bus will be pulled low and no data will be added to the composite signal if this port is unused (not connected). if complex data is desired, there are two ways this can be obtained. the rst method is simply to set the qin input of the ad6622 high and set the wideband input bus low. this allows the ad6622 to output complex data on the wideband output bus. the i data samples would be identi ed when qout is low and the q data samples would be identi ed when qout is high. the second m ethod of obtaining complex data is to provide a qin signal that toggles on every rising edge of the high-speed clock. this could be obtained by connecting the qout of another ad6622 to qin. in a cascaded system the qin of the rst a d6622 in the chain would typically be tied high and the qout of the rst ad6622 would be connected to the qin of the following part. all ad6622s will synchronize themselves to the qin input so that the proper samples are always paired and the wideband out- put bus represents valid complex data samples. table vii. qin, qout functionality wideband output data type qin input in[17:0] out[17:0] qout low real real low high zero complex pulse pulsed complex complex pulse two's complement, clipping disabled ad6622 q in in [17:0] logic1 logic0 q out out [17:0] ad6622 q in in [17:0] out [16:3] 14-bit dac offset bin, clipping enabled figure 19. cascade operation of two ad6622s synchronization three types of synchronization can be achieved with the ad6622. these are start, hop, and beam. each is described in detail below. the synchronization is accomplished with the use of a shadow register and a hold-off counter. see figure 20 for a simp lified schematic of the nco shadow register and nco freq hold- off counter to understand basic operation. enabling the clock (ad6622 clk) for the hold-off counter can occur with e ither a soft sync (via the microport), or a pin sync (via the ad6622 sync pin, pin 62). the functions that include shadow registers to allow synchronization include: 1. start 2. hop (nco frequency) 3. beam (nco phase offset) ad6622 C18C rev. 0 start refers to the start-up of an individual channel, chip, or multiple chips. if a channel is not used, it should be put in the sleep mode to reduce power dissipation. following a hard reset (low pulse on the ad6622 reset pin), all channels are placed in the sleep mode. nco frequency register 32 32 d q 32 d q nco register nco phase accumulator hop hold-off 16 16 d q d hold-off counter pl c = 1 c = 0 ena start hold-off 16 16 d q d start counter pl c = 1 c = 0 ena start sync d q set sleep clk reset pin hop sync external address 4 ena microprocessor interface figure 20. nco shadow register and hold-off counter start with no sync if no synchronization is needed to start multiple cha nnels or multiple ad6622s, the following method can be used to ini- tialize the device. 1. to program a channel, it must rst be set to the program mode (bit high) and sleep mode (bit high) (exter nal address 4). the program mode allows programming of data memory and coef cient memory (all other registers are progra mmable whether or not in program mode). since no synchronization is used all sync bits are set low (external address 5). all appropriate control and memory registers ( lter) are then loaded. the start update hold-off counter (0x00) should be set to 0. 2. set the ap propriate program and sleep bits low (external address 4). this enables the channel. the channel must have program and sleep mode low to activate a channel. start with soft sync the ad6622 includes the ability to synchronize channels or chips under microprocessor control. one action to synchronize is the start of channels or chips. the start update hold-off counter (0x00) in conjunction with the start bit and sync bit (external address 5) allow this synchronization. basically the start up date hold-off counter delays the start of a channel(s) by its value (number of ad6622 clks). the following method is used to synchronize the start of multiple channels via microprocessor control. 1. set the appropriate channels to sleep mode (a hard reset to the ad6622 reset pin brings all four channels up in sleep mode). 2. write the start update hold-off counter(s) (0x00) to the appropriate value (greater than 1 and less than 2 16 1). if the chip(s) is not initialized, all other registers should be loaded at this step. 3. write the start bit and the syncx(s) bit high (external address 5). 4. this starts the start update hold-off counter counting down. the counter is clocked with the ad6622 clk signal. when it reaches a count of one the sleep bit of the appropri- ate channel(s) is set low to activate the channel(s). start with pin sync a sync pin is pro vided on the ad6622 to provide the most accurate synchronization, especially between multiple ad6622s. synchronization of start with an external signal is accomplished with the following method. 1. set the appropriate channels to sleep mode (a hard reset to the ad6622 reset pin brings all four channels up in sleep mode). 2. write the start update hold-off counter(s) (0x00) to the appropriate value (greater than 1 and less than 2 16 1). if the chip(s) is not initialized, all other registers should be loaded at this step. 3. set the start on pin sync bit and the appropriate sync pin enable high (0x001). 4. when the sync pin is sampled high by the ad6622 clk, it enables the countdown of the start update hold-off counter. the counter is clocked with the ad6622 clk signal. when it reaches a count of one, the sleep bit of the appropriate channe l(s) is set low to activate the channel(s). hop is a jump from one nco frequency to a new nco frequency. this change in frequency can be synchronized via microproces- sor control or an external sync signal as described below. to set the nco frequency without synchronization the follow- ing method should be used. set freq no hop 1. set the nco freq hold-off counter to 0. 2. load the appropriate nco frequency. the new frequency will immediately be loaded to the nco. hop with soft sync the ad6622 includes the ability to synchronize a change in nco frequency of multiple channels or chips under micro- processor contr ol. the nco freq hold-off counter (0x03), in conjunction with the hop bit and the sync bit (ext add ress 5), allow this synchronization. basically the nco freq hold-off counter delays the new frequency from being loaded into the nco by its value (number of ad6622 clks). the following method is used to synchronize a hop in frequency of multiple chan- nels via microprocessor control. ad6622 C19C rev. 0 1. write the nco freq hold-off (0x03) counter to the appro- priate value (greater than 1 and less then 2 16 1). 2. write the nco frequency register(s) to the new desired frequency. 3. write the hop bit and the sync(s) bit high (ext address 5). 4. this starts the nco freq hold-off counter counting down. the counter is clocked with the ad6622 clk signal. when it reaches a count of one, the new frequency is loaded into the nco. hop with pin sync a sync pin is provided on the ad6622 to provide the most accurate synchronization, especially between multiple ad6622s. synchronization of hopping to a new nco frequency with an external signal is accomplished with the following method. 1. write the nco freq hold-off counter(s) (0x03) to the appropriate value (greater than 1 and less than 2 16 1). 2. write the nco frequency register(s) to the new desired frequency. 3. set the hop on pin sync bit and the appropriate sync pin enable high (0x001). 4. when the sync pin is sampled high by the ad6622 clk this enables the countdown of the nco freq hold-off counter. the counter is clocked with the ad6622 clk signal. when it reaches a count of one the new frequency is loaded into the nco. beam is a change in phase for a particular channel and can be synchronized with respect to other channels or ad6622s. this change in phase can be synchronized via microprocessor control or an external sync signal as described below. to set the amplitude without synchronization the following method should be used. set phase no beam 1. set the nco phase offset update hold-off counter (0x05) to 0. 2. load the appropriate nco phase offset (0x04). the nco phase offset will be immediately loaded. beam with soft sync the ad6622 includes the ability to synchronize a change in nco phase of multiple channels or chips under microprocessor control. the nco phase offset update hold-off counter, in conjunction with the beam bit and the sync bit (ext address 5), allow this synchronization. basically the nco phase offset update hold-off counter delays the new phase from being loaded into the nco/rcf by its value (number of ad6622 clks). the following method is used to synchronize a beam-in phase of multiple channels via microprocessor control. 1. write the nco phase offset update hold-off counter (0x05) to the appropriate value (greater than 1 and less then 2 16 1). 2. write the nco phase offset register(s) to the new desired phase and amplitude. 3. write the beam bit and the sync(s) bit high (external address 5). 4. this starts the nco phase offset update hold-off counter counting down. the counter is clocked with the ad6622 clk signal. when it reaches a count of one, the new phase is loaded into the nco. beam with pin sync a sync pin is provided on the ad6622 to provide the most accurate synchronization, especially between multiple ad6622s. synchronization of beaming to a new nco phase offset with an external signal is accomplished with the following method. 1. write the nco phase offset hold-off (0x05) counter(s) to the appropriate value (greater than 1 and less than 2 16 1). 2. write the nco phase offset register(s) to the new desired phase and amplitude. 3. set the beam on pin sync bit and the appropriate sync pin enable high (0x001). 4. when the sync pin is sampled high by the ad6622 clk, it enables the countdown of the nco phase offset hold-off counter. the counter is clocked with the ad6622 clk sig- nal. when it reaches a count of one, the new phase is loaded into the nco registers. jtag interface the ad6622 supports a subset of ieee standard 1149.1 speci cations. for additional details of the standard, please see ieee standard test access port and boundary-scan architecture, ieee-1149 publication from ieee. the ad6622 has ve pins associated with the jtag interface. these pins are used to access the on-chip test access port and are listed in table viii. table viii. jtag pin list name pin number description trst 100 test access port reset tck 101 test clock tms 106 test access port mode select tdi 108 test data input tdo 107 test data output the ad6622 supports four op codes as shown in table ix. these i nstructions set the mode of the jtag interface. table ix. jtag op codes instruction op code idcode 10 bypass 11 sample/preload 01 extest 00 the vendor identi cation code can be accessed through the idcode instruction and has the following format. table x. jtag id string msb part manufacturing lsb version number id # mandatory 000 0010 000 1110 0101 1 0111 1000 0000 a bsdl le for this device is available from analog devices, inc. contact analog devices inc. for more information. ad6622 C20C rev. 0 scaling proper scaling of the wideband output is critical to maximize the spurious and noise performance of the ad6622. a relatively small overflow anywhere in the data path can cause the spurious free dynamic range to drop precipitously. scaling down the output levels also reduces dynamic range relative to an approximately constant noise floor. a well-balanced scaling plan at each point in the signal path will be rewarded with optimum performance. the scaling plan can be separated into two parts: multicarrier scaling and single-carrier scaling. multicarrier scaling an arbitrary number of ad6622s can be cascaded to create a composite digital if with many carriers. as the number of carriers increases, the peak-to-rms ratio of the composite digital if will increase as well. it is possible and bene cial to limit the peak-to- rms ratio through careful frequency planning and controlled phase offsets. nevertheless, in most cases with a large number of carriers, the worst-case peak is an unlikely event. the ad6622 immediately preceding the dac can be pr ogrammed to clip rather than wrap around (see the summation block descrip- tion). for a large number of carriers, a rare but nite chance of clipping at the ad6622 wideband output will result in superior dynamic range compared to lowering each carrier level until clipping is impossible. this will also be the case for most dacs. through analysis or experimentation, an optimal output level of individual carriers can be determined for any particular dac. single-carrier scaling once the optimal power level is determined for each carrier, one must determine the best way to achieve that level. the maximum snr can be achieved by maximizing the intermediate power level at each processing stage. this can be done by assuming the proper level at the output and working backwards along the signal path: summation, nco, cic, and nally, rcf. the summation block is intended to combine multiple carriers, with each carrier at least 6 db below full scale. for this con gu- ration, the ad6622 driving the dac should have clip detection enable. out17 becomes a clip indicator that reports clipping in both polarities. if the dac requires offset binary outputs, the internal offset binary conversion should be enabled as well. any preceding cascaded ad6622s should disable clip detection and offset binary conversion. the in17 in0 of the rst ad6622 in the cascade should be grounded. see the summation block section for details. in this con guration, intermediate out17s will serve as guard bits that allow intermediate sums to exceed full scale. as long as the nal output does not exceed 6 db over full scale, the clip detector will perform correctly. if a single carrier needs to exceed 6 db full scale, hardwired scaling can be accomplished according to the table below. this is most useful when the ad6622 is processing a single wide- band carrier such as umts or cdma 2000. table xi. output bit scaling m ax single- connect to clip offset binary carrier level dac msb detect compensation 12.04 db out17 n/a internal 6.02 db out16 internal 0 db out15 +only 0x18000 +6.02 db out14 +only 0x1c000 +12.04 db out13 +only 0x1e000 +18.06 db out12 +only 0x1f000 +24.08 db out11 +only 0x1f800 the nco/tuner is equipped with an output scalar that ranges from 6.02 db to 24.08 db below full scale, in 6.02 db steps. see the nco/tuner section for details. the best snr will be achieved by m aximizing the input level to the nco and using the largest possible nco attenuation. for example, to achieve an output level 20 db below full scale, one should set the cic output level to 1.94 db below full scale and attenuate by 18.06 db in the nco. the cic is equipped with an output scalar that ranges from 0 db to 150.51 db below full scale in 6.02 db steps. this large attenuation is ne cessary to compensate for the potentia lly large gains associated with cic interpolation. see the cic section for details. for example to achieve an output level of 1.94 db below full scale, with a cic5 interpolation of 27 (114.51 db gain) and a cic2 interpolation of 3 (9.54 db gain), one should set the cic_scale to 20 and the rcf output level to 5.59 db below full scale. . . .. . 1 94 9 54 114 51 20 6 02 5 59 + = (18) the rcf is equipped with an output scalar that ranges from 0 db to 18.06 db below full scale in 6.02 db steps. this attenua tion can be used to compensate for lter gain in the rcf. for example, if the desired rcf output is 5.59 db and the maxim gain of the rcf coef cients is 11.04 db, then the rcf_coarse_scale should be set to two and the coef cients should be scaled so that the largest coef cient is 4.59 db below full scale. the largest pos- sible gain of the rcf coef cients is when the largest coef cient of the impulse response is normalized to one. this means that all of the coef cients are as large as possible so the sum of the coef cients are as large as possible. this maximum gain will determine the rcf_coarse_scale, which should be used to make the total rcf gain between 0 db and 6.02 db. after the rcf_coarse_scale is chosen, the coef cients can be res caled, as in the example, to set the total rcf gain to a desired level. see the rcf section for additional information. . .. . 559 1104 2 602 459 + = (19) finally, as described in the rcf section, there may be a worst- case peak of a phase that is larger than the channel center gain. in the preceding example, if the worst-case to channel center ratio is larger than 4.59 db (potentially overflowing the rcf), the rcf_coarse_scale should be reduced by one and the cic_scale should be increased by one. in the preceding example, if the worst- case to channel center ratio is larger than 5.59 db (potentially overflowing the rcf and cic), the rcf_coarse_scale should be reduced by one and the nco_output_scale should be increased by one. microport interface the microport interface is the communications port between the ad6622 and the host controller. there are two modes of bus operation: intel nonmultiplexed mode (inm), and motorola nonmultiplexed mode (mnm), which is set by hard wiring the mode pin to either ground or supply. the mode is selected based on the use of the microport control lines ( ds or rd , dtack or rdy, r/ w or wr ) and the capabilities of the host processor. see the timing diagrams for details on the operation of both modes. the external memory map provides data and address registers to read and write the extensive control registers in the internal memory map. the control registers access global chip functions and multiple control functions for each independent channel. ad6622 C21C rev. 0 microport control all accesses to the internal registers and memory of the ad6622 are accomplished indirectly through the use of the microproces- sor port external registers shown in table xii. accesses to the external registers are accomplished through the 3-bit address bus (a[2:0]) and the 8-bit data bus (d[7:0]) of the ad6622 (microport). external address [3:0] provides access to data read from or written to the internal memory (up to 32 bits). external address [0] is the least signi cant byte and external address [3] is the most signi cant byte. external address [4] controls the resets of each channel. external address [5] controls the sync status of each channel. external address [7:6] determines the internal address selected and whether this address is increm ented after subsequent reads and/or writes to the internal registers. external memory map the external memory map is used to gain access to the inter- nal memory map described below. external address [7:6] sets the int ernal address to which subsequent reads or writes will be performed. the top two bits of external address [7] allow the user to set the address to autoincrement after reads, writes, or both. all internal data words have widths that are less than or equal to 32 bits. accesses to external address [0] trigger accesses to the ad6622 s internal memory map. thus during writes to the internal registers, external address [0] must be written last to ensure all data is transferred. reads are the oppo- site in that external address [0] must be the rst data register read (after setting the appropriate internal address) to initiate an internal access. external address [5:4] reads and writes are immediately trans- ferred to internal control registers. external address [4] is the reset register. the reset bits can be set collectively by the address. the reset bits can be cleared by operation of start syncs (de scribed below). external address [5] is the sync register. these bits are write only. there are three types of syncs: start, hop, and beam. each of these can be sent to any or all of the four channels. for example, a write of x0010100 would issue a start sync to channel c only. a write of x1101111 would issue a beam sync and a hop sync to all channels. the internal address bus is 11 bits wide and the internal data bus is 32 bits wide. external address 7 is the chan (c hannel) and stores the upper three bits of the address space in chan[2:0]. chan[7:6] de ne the autoincrement feature. if bit 6 is high, the internal address in incremented after an internal read. if bit 7 is high, the internal address is incremented after an internal write. if both bits are high, the internal address in incremented after either a write or a read. this feature is designed for sequential access to internal locations. external address 6 is the addr (address) and stores the lower eight bits of the internal address. external addresses 3 through 0 store the 32 bits of the internal data. all internal accesses are two clock cycles long. writing to an internal location with a data width of 16 bits is achieved by rst writing the upper three bits of the address to bits 2 through 0 of the chan. (bits 7 and 6 of the chan are written to determine whether or not the auto increment fea- ture is enabled.) the addr is then written with the lower eight bits of the internal address (it does not matter if the addr is written before the chan as long as both are written before the internal access). since the data width of the internal address is 16 bits, only data register 1 and data register 0 are needed. data register 1 must be written rst because the write to data register 0 triggers the internal access. data register 0 must always be the last register written to initiate the internal write. reading from the microport is accomplished in a similar manner. the internal address is rst written. a read from data register 0 activates the internal read, thus register 0 must always be read rst to initiate an internal read. this provides the 8 lsbs of the internal read through the microport (d[7:0]). additional bytes are then read by changing the external address (a[2:0]) and perfor ming additional reads. if data register 3 (or any other) is read before data register 0, incorrect data will be read. data register 0 must be read rst in order to transfer data from the core memory to the external memory locations. once data re gister is read, the remaining locations may be examined in any order. the microport of the ad6622 allows for multiple accesses while cs is held low ( cs can be tied permanently low if the microport is not shared with additional devices). the user can access multiple locations by pulsing the wr or rd line and changing the contents of the external 3-bit address bus. a ccess to the external registers of table xii is accomplished in one of two modes using the cs , rd , wr , and mode inputs. the access modes are intel nonmultiplexed mode and motorola nonmultiplexed mode. these modes are controlled by the mode i nput (mode = 0 for inm, mode = 1 for mnm). cs , rd , and wr control the access type for each mode. intel nonmultiplexed mode (inm) mode must be tied low to operate the ad6622 microport in inm mode. the access type is controlled by the user with the cs , rd ( ds ), and wr (r/ w ) inputs. the rdy ( dtack ) signal is produced by the microport to communicate to the user the m icroport is ready for an access. rdy ( dtack ) goes low at the start of the access and is released when the internal cycle is complete. see the timing diagrams for both the read and write modes in the speci cations. motorola nonmultiplexed mode (mnm) mode must be tied high to operate the ad6622 mic roprocessor in mnm mode. the access type is controlled by the user with the cs , ds ( rd ), and r/ w ( wr ) inputs. the dtack (rdy) signal is produced by the microport to acknowledge the comple- tion of an access to the user. dtack (rdy) goes low when an internal access is complete and then will return high after ds ( rd ) is deasserted. see the timing diagrams for both the read and w rite modes in the speci cations. the dtack pin is con gured as an open drain so that multiple devices may be tied together at the microprocessor/microcontroller without contention. ad6622 C22C rev. 0 external address 7 upper address register (chan) sets the three most signi cant bits of the internal address, effec- tively selecting channels 1, 2, 3, or 4 (d2:d0). the autoincrement of read and write are also set (d7:d6). external address 6 lower address register (addr) sets the internal address 8 lsbs (d7:d0). external address 5 sync this register is read only. bits in this address control the synchroni- zation of the ad6622 channels. if the user intends to bring up channels with no synchronization requirements, then all bits of this register should be written low. two types of sync signals are available with the ad6622. the rst is soft sync. soft sync is software synchronization enabled through the microport. the second synchronization method is pin sync. pin sync is enabled by a signal applied to the sync pin (pin 62). see the synchroni- zation section of the data sheet for detailed explanations of the different modes. external address 4 reset bits in this register determine how the chip is programmed and enables the channels. the program bits (d7:d4) must be set high to allow programming of cmem and dmem for each channel. sleep bits (d3:d0) are used to activate or sleep channels. these can be used manually by the user to bring up a channel by simply writing the required channel high. these bits can also be used in conjunction with the start and sync signals avail- able in external address 5 to synchronize the channels. see the sy nchronization section of the data sheet for detailed expla- nation of different modes. external address 3:0 (data bytes) these bits set the internal address to be accessed for a read or write. table xii. external memory map external external data address d7 d6 d5 d4 d3 d2 d1 d0 7: chan wrinc rdinc ia10 ia9 ia8 6: addr ia7 ia6 ia5 ia4 ia3 ia2 ia1 ia0 5: sync beam hop start sync d sync c sync b sync a 4: reset prog d prog c prog b prog a sleep d sleep c sleep b sleep a 3: byte3 id31 id30 id29 id28 id27 id26 id25 id24 2: byte2 id23 id22 id21 id20 id19 id18 id17 id16 1: byte1 id15 id14 id13 id12 id11 id10 id9 id8 0: byte0 id7 id6 id5 id4 id3 id2 id1 id0 ad6622 C23C rev. 0 internal control registers and on-chip ram listed below is the mapping of internal ad6622 registers. table xiii. internal memory map address bit width name notation description c ommon function registers (not associated with a particular channel) 0x000 8 summation mode control 0: clip wideband output 1: offset binary wideband output 2: reserved, must be set high 3 7: reserved, should be set low 0x001 8 sync mode control 0: ch. a sync pin enable 1: ch. b sync pin enable 2: ch. c sync pin enable 3: ch. d sync pin enable 4: start on pin sync 5: hop on pin sync 6: beam steer on pin sync 7: first sync only channel function registers (0x1xx = ch. a, 0x2xx = ch. b, 0x3xx = ch. c, 0x4xx = ch. d ) 0x100 16 start update hold-off counter start update hold off counter 0x101 8 nco control 1-0: ch. a nco output scale 2: ch. a nco clear phase accum on sync 3: ch. a nco phase dither enable 4: ch. a nco amp dither enable 7 5: reserved 0x102 32 nco frequency ch. a nco frequency value 0x103 16 nco freq hold off ch. a nco frequency update hold-off ctr 0x104 16 nco phase offset ch. a nco phase offset 0x105 16 nco phase hold off ch. a nco phase offset update hold-off ctr 0x106 8 cic scale 4 0: ch. a cic scale 7 5: reserved 0x107 8 reserved 7 0: reserved 0x108 8 cic2 interpolation-1 ch. a cic2 interpolation factor-1 0x109 8 cic5 interpolation-1 ch. a cic5 interpolation factor-1 0x10a 8 rcf coef cient count n rcf -1 6 0: ch. a rcf coef cient count, n rcf 1 7: reserved 0x10b 8 rcf coef cient offset o rcf 6 0: ch. a rcf coef cient offset 7: reserved 0x10c 8 channel mode control 1 n rcf /l rcf -1 3 0: ch. a n rcf /l rcf 1 5 4: ch. a input format: 00 = fir 6: reserved 7: reserved 0x10d 8 channel mode control 2 4 0: ch. a serial clock divider 5: ch. a phase eq enable 7 6: ch. a rcf coarse scale: 00 = 0 db 01 = 6 db 10 = 12 db 11 = 18 db 0x10e 16 15 0: reserved 0x10f 16 15 0: reserved 0x110 16 reserved reserved 0x111 16 reserved reserved 0x112 0x11f reserved reserved 0x120 0x13f 16 data memory ch. a data memory 0x140 0x17f 16 reserved reserved 0x180 0x1ff 16 coef cient memory ch. a coef cient memory additional channels 0x200 0x2ff various channel b ch. b registers (organized as ch. a above) 0x300 0x3ff various channel c ch. c registers (organized as ch. a above) 0x400-0x4ff various channel d ch. d registers (organized as ch. a above) ad6622 C24C rev. 0 (0x000) summation mode control controls functions in the summation block of the ad6622. when set high, bit 0 causes the output data to be clipped (no wrap- around) when overrange of the output occurs. when bit 0 is low, overrange will result in wraparound. when set low, bit 1 formats the output data as two's complement. bit 1 set high will for- mat output data as offset binary. (0x001) sync mode control bits 3 0 when high enable synchronization of these channels. see the synchronization section of the data sheet for detailed explanation. channel function registers the following registers are channel-speci c. 0x denotes that these values are represented as hexadecimal numbers. n repre- sents the speci ed channel. valid channels are n = 1, 2, 3, and 4. (0xn00) start update hold-off counter the start update hold-off counter is used to synchronize start up of ad6622 channels and can be used to synchronize multiple chips. the start update hold-off counter is clocked by the ad6622 clk (master clock). see the synchronization section of the data sheet for detailed explanation. if no synchronization is required, this register should be set to 0. (0xn01) nco control bit 1:0 set the nco scaling per the table xiv. table xiv. control scale 0x01 bit 1 0x01 bit 0 nco output level 00 6 db 01 12 db 10 18 db 11 24 db bit 2, when high, clears the nco phase accumulator to 0 on either a soft sync or pin sync (see synchronization for details). bit 3, when high, enables nco phase dither. bit 4, when high, enables nco amplitude dither. bits 7:5 are reserved and should be written low. (0xn02) nco frequency this register is a 32-bit unsigned integer that sets the nco frequency. the nco frequency contains a shadow register for synchronization purposes. the shadow can be read back directly, the nco frequency cannot. nco f clk frequency channel = ? ? ? ? ? ? 2 32 (20) (0xn03) nco frequency update hold-off counter the hold-off counter is used to synchronize the change of nco frequencies. see the synchronization section of the data sheet for detailed explanation. if no synchronization is required, this register should be set to 0. (0xn04) nco phase offset this register is a 16-bit unsigned integer that is added to the phase accumulator of the nco. this allows phase synchronization of multiple channels of the ad6622(s). see the synchronization section of the data sheet for details. the nco phase offset con- tains a shadow register for synchroni zation purposes. the shadow can be read back directly, the nco phase offset cannot. (0xn05) nco phase offset update hold-off counter the hold-off counter is used to synchronize the change of nco phases. see the synchronization section of the data sh eet for detailed explanation. if no synchronization is required, this register should be set to 0. (0xn06) cic scale bits 5:0 set the cic scaling per the equation below. cic scale ceil l l cic cic _ (log ( )) = 25 4 2 (21) see cic section of the data sheet for details. bits 7:6 are reserved and should be set to 0. (0xn07) reserved this register is reserved and should be set to 0. (0xn08) cic2 interpolation ?1 this register sets the interpolation rate for the cic2 lter stage (unsigned integer). the programmed value is the cic2 interpo- lation 1. maximum interpolation is limited by the cic scaling available (see cic section of the data sheet). (0xn09) cic5 interpolation ?1 this r egister sets the interpolation rate for the cic5 lter stage (unsigned inte ger). the programmed value is the cic5 interpolation 1. maximum interpolation is limited by the cic scaling available (see cic section of the data sheet). (0xn0a) number of rcf coef?ients ?1 this register sets the number of rcf coef cients and is limited to a maximum of 128. the programmed value is the number of rcf coef cients 1. (0xn0b) rcf coef?ient offset this register sets the offset for rcf coef cients and is normally set to 0. it can be viewed as a pointer that selects the portion of the cmem used when computing the rcf lter. this allows multiple lters to be stored in the coef cient memory space, selecting the appropriate lter by setting the offset. (0xn0c) channel mode control 1 bits 3:0 set n rcf /l rcf -1. bits 5:4 set the channel input format as shown below. table xv. filter mode bit 5 bit 4 input mode 0 0 fir 0 1 reserved 1 0 reserved 1 1 reserved bit 6 reserved. bit 7 reserved. (0xn0d) channel mode control 2 bits 4:0 set the sclk divider which determines the serial clock frequency based on the following equation. f clk sclk sclk divider = + 21 () (22) ad6622 C25C rev. 0 bit 5 reserved. must be set low. bits 7:6 set the rcf coarse scale as shown below. table xvi. rcf scaling bit 7 bit 6 rcf coarse scale 0 0 0 db 01 6 db 10 12 db 11 18 db (0xn0e) reserved (0xn0f) reserved (0xn10) reserved (must be written to 0) (0xn11) reserved (must be written to 0) (0xn12?xn1f) reserved (0xn20?xn3f) data memory this group of registers contain the rcf fil ter data. see the rcf section of the data sheet for additional detail. (0xn40?xn7f) reserved (0xn80?xnff) coef?ient memory this group of registers contain the rcf filter coef cients. see the rcf section of the data sheet for additional detail. write pseudocode void write_micro(ext_address, int data); main() { / * this code shows the programming of the nco frequency register using the write_micro function de ned above. the variable address is the external address a[2:0] and data is the value to be placed in the external interface register. internal address = 0x102, channel 1 * / / * holding registers for nco byte wide access data * / int d3, d2, d1, d0; / * nco frequency word (32 bits wide) * / nco_freq=0x1befefff; / * write chan * / write_micro(7, 0x01); / * write addr * / write_micro(6,0x02); / * write byte 3 * / d3=(nco_freq & 0xff000000)>>24; write_micro(3,d3); / * write byte 2 * / d2=(nco_freq & 0xff0000)>>16; write_micro(2,d2); / * write byte 1 * / d1=(nco_freq & 0xff00)>>8; write_micro(1,d1); / * write byte 0, byte 0 is written last and causes an internal write to occur * / d0=nco_freq & 0xff; write_micro(0,d0); } read pseudocode void read_micro(ext_address); main() { /* this code shows the reading of the nco frequency register using the read_micro function de ned above. the variable address is the external address a[2:0] internal address = 0x102, channel 1 * / / * holding registers for nco byte wide access data * / int d3, d2, d1, d0; / * nco frequency word (32 bits wide) * / / * write chan * / write_micro(7, 0x01); / * write addr * / write_micro(6,0x02); / * read byte 0, all data is moved from the internal registers to the interface registers on this access, thus byte 0 must be accessed rst for the other bytes to be valid * / d0=read_micro(0) & 0xff; / * read byte 1 * / d1=read_micro(1) & 0xff; / * read byte 2 * / d2=read_micro(2) & 0xff; / * read byte 0 * / d3=read_micro(3) & 0xff; } applications the ad6622 provides considerable flexibility for the control of the synchronization, relative phasing, and scaling of the ind ividual channel inputs. implementation of a multichannel transmitter invariably begins with an analysis of the output sp ectrum that must be generated. digital-to-analog converter (dac) selection the selection of a high-performance dac depends on a number of factors. the dynamic range of the dac must be considered from a noise and spectral purity perspective. the 14-bit ad9754 and ad9772 are the best choices for overall bandwidth, noise, and spectral purity. in order to minimize the complexity of the analog interpolation lter which must follow the dac, the sample rate of the master clock is generally set to at least three times the maximum analog frequency of interest. in the case where a 15 mhz band of interest is to be up-converted to rf, the lowest frequency might be 5 mhz and the upper band edge at 20 mhz (offset from dc to afford the best image reject lter after the rst digital if). the minimum sample rate would be set to 75 msps. consideration must also be given to data rate of the incoming data stream, interpolation factors, and the clock rate of the dsp. ad6622 C26C rev. 0 multiple tsp operation each of the four transmit signal processors (tsps) of the ad6622 can adequately reject the interpolation images of nar- row bandwidth carriers such as amps, is-136, gsm, edge, and phs. wider bandwidth carriers such as is-95 and umts require a coordinated effort of multiple processing channels. this section demonstrates how to coordinate multiple tsps to create wider bandwidth channels without sacri cing image rejection. as an example, a umts carrier is modulated using four tsps (an entire ad6622). the same principals can be applied to different designs using more or fewer tsps. this sec- tion does not explore techniques for using multiple tsps to solve problems other than serial port or rcf throughput. designing lter coef cients and control settings for deint erleaved tsps is no harder than designing a lter for a single tsp. for example, if four tsps are to be used, simply divide the input data rate by four and generate the lter as normal. for any design, a better lter can always be realized by incrementing the number of tsps to be used. when it is time to program the tsps, only two small differences must be programmed. first each channel is con gured with exactly the same lter, scalars, modes and nco frequency. since each channel receives data at 1/4 the data r ate and in a staggered fashion, the start hold-off counters must also be staggered (see programming multiple tsps section below). second, the phase offset of each nco must be set to match the demultiplexed ratio (1/4 in this example). thus the phase offset should be set to 90 degrees (16384, which is 1/4 of a 16-bit register). determining the number of tsps to use there are three limitations of a single tsp that can be over- come by deinterleaving an input stream into multiple tsps: serial port bandwidth, the time restriction to the rcf impulse response length (n rcf ), and the dmem restriction to n rcf . if the input sample rate is faster than the serial port can accept data, the data can be deinterleaved into multiple serial ports. recalling from the serial port description, the sclk frequency (f sclk ) is determined by the equation below. to minimize the number of processing channels, sclk divider should be set as low as possible to get the highest f sclk that the serial data source can accept. f f sclk sclk clk divider = + 21 () (23) a minimum of 32 sclk cycles are required to accept an input sample, so the minimum number of tsps (n tsp ) due to limited serial port bandwidth is a function of the input sample rate (f in ), as shown by the equation below. n ceil f f tsp in sclk ? ? ? ? ? ? 32 (24) for a sample umts system, we will assume f clk = 61.44 mhz, and the serial data source can drive data at 30.72 mbps (sclk divider = 0). to achieve f in = 3.84 mhz, the mini- mum n tsp is 4. (this is tsp channels, not tsp ics.) multiple tsps are also required if the rcf does not have enough time or dmem space to calculate the required rcf lter. r ecall- ing the maximum n taps equation from the rcf description, are three restrictions to the rcf impulse response length, n rcf . time cmem restriction restriction n l l rcf rcf ? ? ? ? ? ? ? min , , 2 16 128 (25) dmem restriction where: ll l l nf f rcf cic cic tsp clk in = = 52 deinterleaving the input data into multiple tsps will extend the time restriction and may possibly extend the dmem restriction, but will not extend the cmem restriction. deinterleaving the input stream to multiple tsps divides the input sample rate to each tsp by the number of tsps used (n tsp ). to keep the out- put rate xed, l must be increased by a factor of n ch , which extends the time restriction. this increase in l may be achieved by increasing any one or more of l rcf , l cic5 , or l cic2 within their normal limits. achieving a larger l by increasing l rcf instead of l cic5 or l cic2 , will relieve the dmem restriction as well. in a umts example, n tsp = 4, f clk = 61.44 mhz, and f in = 3.84 mhz, resulting in l = 64. factoring l into l rcf = 8, l cic = 8, and l cic2 = 1, results in a maximum n rcf = 32 due to the time restriction. figure 22 shows an example rcf impulse response that has a frequency response as shown in figure 23 from 0 hz to 7.68 mhz (f in l rcf /n tsp ). the composite rcf and cic frequency response is shown in figure 24, on the same fre- quency scale. this gure demonstrates a good approximation to a root-raised-cosine with a roll-off factor of 0.22, a pass-band ripple of 0.1 db, and a stopband ripple better than 65 db until the lobe of the rst image which peaks at 50 db about 5.6 mhz from the carrier center. this lobe could be reduced by shifting more of the interpolation towards the rcf, but that would sacri ce near-in performance. as shown, the rst image can easily be rejected by an analog lter further up the signal path. scaling must be considered as normal with an interpolation factor of l, to guarantee no overflow in the rcf, cic, or ncos. the output level at the summation port should be calculated using an interpolation factor of l/n tsp . programming multiple tsps con guring the tsps for deinterleaved operation is straight- forward. all of the channel registers and cmem of each tsp are programmed identically, except the start hold-off counters and nco phase offset. in order to separate the input timing to each tsp, the hold- off counters must be used to start each tsp successively in response to a common start sync. the start sync may origi- nate from the sync pin or the microport. each subsequent tsp must have a hold-off counter value l/n tsp larger than its predecessor s. if the tsps are located on cascaded ad6622s, the hold-off counters of the upstream device should be incre- mented by an additional one. in the umts example, l = 64 and n tsp = 4, so in order to respond as quickly as possible to a start sync, the hold-off counter values should be 1, 17, 33, and 49. ad6622 C27C rev. 0 driving multiple tsp serial ports when properly con gured, the ad6622 will drive each sdfs out of phase. each new piece of data should be driven only into the tsp that pulses its sdfs pin at that time. in the umts example, l = 64 and n tsp = 4, so each serial port need only accept every 4th input sample. each serial port is shifting at peak capacity, so sample 1, 2, and 3 begin shifting into serial ports b, c, and d before sample 0 is completed into serial port a. 0 1 2 3 4 5 6 7 sdfsa sdfsb sdfsc sdfsd figure 21. sdfs timing for wbcdma ram coef filter cic nco i q 8.196msps 65.536msps summation data reformatter 4.096 mcps 1.024 mcps 32 1.024 mcps 32 1.024 mcps 1.024 mcps 65.536 msps dac complex signal 32 bits (16 i, 16 q) real or imaginary signal ad6622 32 32 32 ram coef filter cic nco i q 8.196msps 65.536msps ram coef filter cic nco i q 8.196msps 65.536msps ram coef filter cic nco i q 8.196msps 65.536msps figure 22. block diagram for wbcdma 0 5 10 15 20 0 0.5 1.0 25 30 coef j figure 23. typical impulse response for wbcdma 70 dbc 60 50 40 30 20 10 0 10 100 90 80 ram coefficient filter 0 1000 2000 3000 4000 5000 6000 7000 8000 khz figure 24. typical fir frequency response for wbcdma 70 dbc 60 50 40 30 20 10 0 100 90 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 110 120 db(ad6624(f)) db () h cic (f) level 5 spec( f ) 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 f mhz figure 25. typical composite frequency response for wbcdma thermal management the power dissipation of the ad6622 is primarily determined by three factors: the clock rate, the number of channels active, and the distribution of interpolation rates. the faster the clock rate the more power dissipated by the cmos structures of the ad6622; the more channels active, the higher the overall power of the chip. low interpolation rates in the cic stages (cic5, cic2) results in higher power dissipation. all these factors should be analyzed as each application has different thermal requirements. the ad6622 128-lead mqfp is specially designed to provide excellent thermal performance. to achieve the best performance, the power and ground leads should be connected directly to planes on the pc board. this provides the best thermal transfer from the ad6622 to the pc board. C28C c3772C8C5/00 (rev. 0) 00968 printed in u.s.a. ad6622 rev. 0 outline dimensions dimensions shown in inches and (mm). 128-lead mqfp (metric quad flatpack) (s-128a) top view (pins down) 1 38 39 65 64 102 128 103 0.011 (0.27) 0.007 (0.17) 0.020 (0.50) bsc 0.555 (14.10) 0.547 (13.90) 0.685 (17.40) 0.669 (17.00) 0.791 (20.10) 0.783 (19.90) 0.921 (23.40) 0.906 (23.00) 0.041 (1.03) 0.031 (0.78) seating plane 0.134 (3.40) max 0.003 (0.08) max 0.010 (0.25) min 0.110 (2.80) 0.102 ( 2.60 ) |
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