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elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. hb56uw1673e-f 128mb buffered edo dram dimm 16-mword 72-bit, 4k refresh, 1 bank module (18 pcs of 16m 4 components) e0101h10 (1st edition) (previous ade-203-1123a (z)) jan. 31, 2001 description the hb56uw1673e belongs to 8-byte dimm (dual in-line memory module) family , and have been developed an optimized main memory solution for 4 and 8-byte processor applications. the hb56uw1673e is a 16 m 72 dynamic ram module, mounted 18 pieces of 64-mbit dram (hm5165405) sealed in tsop package and 2 pieces of 16-bit line driver sealed in tssop package. the hb56uw1673e offers extended data out (edo) page mode as a high speed access mode. an outline of the hb56uw1673e is 168-pin socket type package (dual lead out). therefore, the hb56uw1673e makes high density mounting possible without surface mount technology. the hb56uw1673e provides common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the its module board. features ? 168-pin socket type package (dual lead out) ? lead pitch : 1.27 mm ? single 3.3 v supply : 3.3 0.3 v ? high speed ? access time: t rac = 50 ns/60 ns (max) ? access time: t cac = 18 ns/20 ns (max) ? low power dissipation ? active mode: 8.46 w/7.16 w (max) ? standby mode (ttl): 166 mw (max) ? buffered input except ras and dq ? 4 byte interleave enabled, dual address input (a0/b0)
hb56uw1673e-f data sheet e0101h10 2 ? jedec standard outline buffered 8-byte dimm ? edo page mode capability ? 4096 refresh cycles: 64 ms ? 2 variations of refresh ? ras -only refresh ? cas -before- ras refresh ordering information type no. access time package contact pad hb56uw1673e-5f HB56UW1673E-6F 50 ns 60 ns 168-pin dual lead out socket type gold pin arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 oe 2 86 dq36 128 nc 3 dq1 45 re 2 87 dq37 129 nc 4 dq2 46 ce 4 88 dq38 130 nc 5 dq3 47 nc 89 dq39 131 nc 6v cc 48 we 290 v cc 132 pde 7 dq4 49 v cc 91 dq40 133 v cc 8 dq5 50 nc 92 dq41 134 nc 9 dq6 51 nc 93 dq42 135 nc 10 dq7 52 dq18 94 dq43 136 dq54 11 dq8 53 dq19 95 dq44 137 dq55 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq20 97 dq45 139 dq56 14 dq10 56 dq21 98 dq46 140 dq57 15 dq11 57 dq22 99 dq47 141 dq58
hb56uw1673e-f data sheet e0101h10 3 pin arrangement (cont) pin no. signal name pin no. signal name pin no. signal name pin no. signal name 16 dq12 58 dq23 100 dq48 142 dq59 17 dq13 59 v cc 101 dq49 143 v cc 18 v cc 60 dq24 102 v cc 144 dq60 19 dq14 61 nc 103 dq50 145 nc 20 dq15 62 nc 104 dq51 146 nc 21 dq16 63 nc 105 dq52 147 nc 22 dq17 64 nc 106 dq53 148 nc 23 v ss 65 dq25 107 v ss 149 dq61 24 nc 66 dq26 108 nc 150 dq62 25 nc 67 dq27 109 nc 151 dq63 26 v cc 68 v ss 110 v cc 152 v ss 27 we 0 69 dq28 111 nc 153 dq64 28 ce 0 70 dq29 112 nc 154 dq65 29 nc 71 dq30 113 nc 155 dq66 30 re 0 72 dq31 114 nc 156 dq67 31 oe 073 v cc 115 nc 157 v cc 32 v ss 74 dq32 116 v ss 158 dq68 33 a0 75 dq33 117 a1 159 dq69 34 a2 76 dq34 118 a3 160 dq70 35 a4 77 dq35 119 a5 161 dq71 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 pd1 121 a9 163 pd2 38 a10 80 pd3 122 a11 164 pd4 39 nc 81 pd5 123 nc 165 pd6 40 v cc 82 pd7 124 v cc 166 pd8 41 nc 83 id0(v ss ) 125 nc 167 id1 (v ss ) 42 nc 84 v cc 126 b0 168 v cc
hb56uw1673e-f data sheet e0101h10 4 pin description pin name function a0 to a11, b0 address input row address a0 to a11, b0 column address a0 to a11, b0 refresh address a0 to a11, b0 dq0 to dq71 data input/output re 0, re 2 row address strobe ( ras ) ce 0, ce 4 column address strobe ( cas ) we 0, we 2 read/write enable oe 0, oe 2 output enable pd1 to pd8 presence detect id0, id1 id bit pde presence detect enable v cc power supply v ss ground nc no connection presence detect pin assignment (controlled by pde pin) pde = low pde = high pin name pin no. 50 ns 60 ns all pd1 79 1 1 high-z pd2 163 1 1 high-z pd3 80 1 1 high-z pd4 164 1 1 high-z pd5 81 1 1 high-z pd6 165 0 1 high-z pd7 82 0 1 high-z pd8 166 0 0 high-z 1 : high level (driver output) 0 : low level (driver output)
hb56uw1673e-f data sheet e0101h10 5 block diagram re 0 ce 0 we 0 oe 0 *d0 to d17: hm5165405 : 16-bit line driver dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o i/o i/o i/o cas ras we oe d0 i/o i/o i/o i/o cas ras we oe d1 i/o i/o i/o i/o cas ras we oe d2 i/o i/o i/o i/o cas ras we oe d3 i/o i/o i/o i/o cas ras we oe d4 i/o i/o i/o i/o cas ras we oe d5 i/o i/o i/o i/o cas ras we oe d6 i/o i/o i/o i/o cas ras we oe d7 re 2 ce 4 we 2 oe 2 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq64 dq65 dq66 dq67 i/o i/o i/o i/o cas ras we oe d9 i/o i/o i/o i/o cas ras we oe d10 i/o i/o i/o i/o cas ras we oe d11 i/o i/o i/o i/o cas ras we oe d12 i/o i/o i/o i/o cas ras we oe d13 i/o i/o i/o i/o cas ras we oe d14 i/o i/o i/o i/o cas ras we oe d15 i/o i/o i/o i/o cas ras we oe d16 a0 v cc v ss 0.22 f 20 pcs d0 to d8 b0 d9 to d17 a1 to a11 d0 to d17 d0 to d17,16-bit line driver d0 to d17, 16-bit line driver dq32 dq33 dq34 dq35 i/o i/o i/o i/o cas ras we oe d8 dq68 dq69 dq70 dq71 i/o i/o i/o i/o cas ras we oe d17 pd1 to pd8 v cc v cc v cc v cc v cc v cc v ss v cc v ss v ss pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8
hb56uw1673e-f data sheet e0101h10 6 absolute maximum ratings parameter symbol value unit terminal voltage on any pin relative to v ss v t ?.5 to +4.6 v power supply voltage relative to v ss v cc ?.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 19 w storage temperature range tstg ?5 to +125 ? dc operating conditions parameter symbol min typ max unit notes supply voltage v cc 3.0 3.3 3.6 v 1, 2 v ss 000v2 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il ?.3 0.8 v 1 ambient temperature range ta 0 70 c notes: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hb56uw1673e-f data sheet e0101h10 7 dc characteristics hb56uw1673e 50 ns 60 ns parameter symbol min max min max unit test conditions operating current* 1 , * 2 i cc1 2350 1990 ma t rc = min standby current i cc2 46 46 ma ttl interface ras , cas = v ih dout = high-z 19 19 ma cmos interface ras , cas v cc 0.2 v dout = high-z ras -only refresh current* 2 i cc3 2350 1990 ma t rc = min standby current* 1 i cc5 100 100 ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 2350 1990 ma t rc = min edo page mode current* 1, * 3 i cc7 1990 1810 ma ras = v il , cas cycle, t hpc = t hpc min input leakage current i li ? 5 5 5 ? 0 v vin v cc + 0.3 v output leakage current i lo ? 5 5 5 ? 0 v vout v cc dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = 2 ma output low voltage v ol 0 0.4 0 0.4 v low iout = 2 ma notes : 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. measured with one sequential address change per edo cycle, t hpc . capacitance (ta = 25?c, v cc = 3.3 v ?0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 20 pf 1 input capacitance ( cas , we , oe )c i2 20 pf 1 input capacitance ( ras )c i3 78 pf 1 i/o capacitance (dq) c i/o 20 pf 1, 2 notes : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout.
hb56uw1673e-f data sheet e0101h10 8 ac characteristics (ta = 0 to +70?c, v cc = 3.3 v ?0.3 v, v ss = 0 v) * 1 , * 2 ,* 19 test conditions ? input rise and fall times: 2 ns ? input levels: v il = 0 v, v ih = 3.0 v ? input timing reference levels: 0.8 v, 2.0 v ? output timing reference levels: 0.8 v, 2.0 v ? output load: 1 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) 50 ns 60 ns parameter symbol min max min max unit notes random read or write cycle time t rc 84 104 ns ras precharge time t rp 30 40 ns cas precharge time t cp 8 10 ns ras pulse width t ras 50 10000 60 10000 ns cas pulse width t cas 8 10000 10 10000 ns row address setup time t asr 55ns row address hold time t rah 8 10 ns column address setup time t asc 00ns column address hold time t cah 8 10 ns ras to cas delay time t rcd 12 32 14 40 ns 3 ras to column address delay time t rad 10 20 12 25 ns 4 ras hold time t rsh 18 20 ns cas hold time t csh 38 40 ns cas to ras precharge time t crp 10 10 ns oe to din delay time t oed 18 20 ns 5 oe delay time from din t dzo 00ns6 cas delay time from din t dzc 00ns6 transition time (rise and fall) t t 2 50 2 50 ns 7
hb56uw1673e-f data sheet e0101h10 9 read cycle 50 ns 60 ns parameter symbol min max min max unit notes access time from ras t rac 50 60 ns 8, 9 access time from cas t cac 18 20 ns 9, 10, 17 access time from address t aa 30 35 ns 9, 11, 17 access time from oe t oea 18 20 ns 9 read command setup time t rcs 00ns read command hold time to cas t rch 00ns12 read command hold time from ras t rchr 50 60 ns read command hold time to ras t rrh 00ns12 column address to ras lead time t ral 30 35 ns column address to cas lead time t cal 15 18 ns cas to output in low-z t clz 22ns output data hold time t oh 33ns21 output data hold time from oe t oho 33ns output buffer turn-off time t off 18 20 ns 13, 21 output buffer turn-off to oe t oez 18 20 ns 13 cas to din delay time t cdd 18 20 ns 5 output data hold time from ras t ohr 33ns21 output buffer turn-off to ras t ofr 13 15 ns 13, 21 output buffer turn-off to we t wez 18 20 ns 13 we to din delay time t wed 18 20 ns ras to din delay time t rdd 13 15 ns write cycle 50 ns 60 ns parameter symbol min max min max unit notes write command setup time t wcs 00ns14 write command hold time t wch 8 10 ns write command pulse width t wp 8 10 ns write command to ras lead time t rwl 18 20 ns write command to cas lead time t cwl 8 10 ns data-in setup time t ds 00ns15 data-in hold time t dh 13 15 ns 15
hb56uw1673e-f data sheet e0101h10 10 read-modify-write cycle hb56uw1673e 50 ns 60 ns parameter symbol min max min max unit notes read-modify-write cycle time t rwc 116 140 ns ras to we delay time t rwd 72 84 ns 14 cas to we delay time t cwd 30 34 ns 14 column address to we delay time t awd 42 49 ns 14 oe hold time from we t oeh 13 15 ns refresh cycle 50 ns 60 ns parameter symbol min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 ns cas hold time (cbr refresh cycle) t chr 8 10 ns we setup time (cbr refresh cycle) t wrp 55ns we hold time (cbr refresh cycle) t wrh 8 10 ns ras precharge to cas hold time t rpc 55ns edo page mode cycle 50 ns 60 ns parameter symbol min max min max unit notes edo page mode cycle time t hpc 20 25 ns 20 edo page mode ras pulse width t rasp 100000 100000 ns 16 access time from cas precharge t cpa 33 40 ns 9, 17 ras hold time from cas precharge t cprh 33 40 ns output data hold time from cas low t doh 3 3 ns 9, 22 cas hold time referred oe t col 8 10 ns cas to oe setup time t cop 55ns read command hold time from cas precharge t rchc 28 35 ns write pulse width during cas precharge t wpe 8 10 ns oe precharge time t oep 8 10 ns
hb56uw1673e-f data sheet e0101h10 11 edo page mode read-modify-write cycle 50 ns 60 ns parameter symbol min max min max unit notes edo page mode read- modify-write cycle time t hprwc 57 68 ns we delay time from cas precharge t cpw 45 54 ns 14 refresh parameter symbol max unit notes refresh period t ref 64 ms 4096 cycles notes: 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200 ? is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, than the access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 10. assumes that t rcd t rcd (max) and t rcd + t cac (max) t rad + t aa (max). 11. assumes that t rad t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max), t oez (max), t wez (max) and t ofr (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd t rwd (min), t cwd t cwd (min), and t awd t awd (min), or t cwd t cwd (min), t awd t awd (min) and t cpw t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t ds and t dh are referred to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines ras pulse width in edo page mode cycles. 17. access time is determined by the longest among t aa , t cac and t cpa . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device.
hb56uw1673e-f data sheet e0101h10 12 19. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 20. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle (t cas + t cp + 2 t t ) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). 21. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh and between t ofr and t off . 22. t doh defines the time at which the output level go cross. v ol = 0.8 v, v oh = 2.0 v of output timing reference level. 23. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hb56uw1673e-f data sheet e0101h10 13 timing waveforms* 23 read cycle ras address we dout oe din t rc row column t rcs t rch t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez cas t rdd t wed t ofr t ohr t wez t ras t cas t rp t csh t rcd t rsh t crp t t t rad t ral t cal t asr t asc t cah t rchr t rrh t rah
hb56uw1673e-f data sheet e0101h10 14 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t cas
hb56uw1673e-f data sheet e0101h10 15 delayed write cycle* 18 address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t oep t clz t oez high-z invalid dout din high-z
hb56uw1673e-f data sheet e0101h10 16 read-modify-write cycle* 18 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z cas t oep
hb56uw1673e-f data sheet e0101h10 17 ras -only refresh cycle ras cas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off t ofr
hb56uw1673e-f data sheet e0101h10 18 cas -before- ras refresh cycle ras cas we address dout high-z t off t ofr t wrp t wrh t wrp t wrh t cp t rpc t csr t chr t cp t rpc t csr t chr t crp t rp t ras t rc t rc t rp t ras t rp t t
hb56uw1673e-f data sheet e0101h10 19 edo page mode read cycle (1) din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t cac t cpa t t oez t oea t oez t aa t cac t t rasp cop t rp t cas t cas t cas t cal t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 2 dout 4 dout 1 t cas t rcs t t rcs dout 3 t oho t t cprh t hpc t oea t wez dzo t oed oho doh rch t wpe t rchr t cal t cal t cal t rsh t rchc cpa asc t oep t oep
hb56uw1673e-f data sheet e0101h10 20 edo page mode read cycle (2) din oe we address t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t doh t t oez t t oez t aa t cac t cop t asr t rah t t cah t asc t cah t cah t asc t cah t asc t wed t ral dout 2 dout 4 dout 1 t rcs t oho t oea dzo t oed t doh t cac t rchc cpa asc ras cas t cp t cp t cp t t t rch t rrh t rasp t rp t cas t cas t cas t csh t hpc t hpc t hpc crp t t cas t cal t cal t cal t cal t rsh dout dout 3 dout 2 oho oea t cpa column 2 column 1 row column 3 column 4 t oep t oep
hb56uw1673e-f data sheet e0101h10 21 edo page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n cas
hb56uw1673e-f data sheet e0101h10 22 edo page mode delayed write cycle* 18 we din oe dout address ras t rasp t rp t crp t rsh t cas t hpc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z cas t oep t oep t oep
hb56uw1673e-f data sheet e0101h10 23 edo page mode read-modify-write cycle* 18 we din oe dout address ras t rasp t crp t cp t hprwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oep t oep t oep t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh cas
hb56uw1673e-f data sheet e0101h10 24 edo page mode mix cycle (1) ? 20 oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t cpa t oez t aa t oea t t rasp t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal row dout 2 dout 4 cpa t cas t wcs dout 3 t t t wp t cwl t wch t wed t wez t ds t dh t ds t dh din 3 din 1 t oea t oed t oep t cac t asc t cpw t awd oho t cal t rcs t rcs t csh t rcd t rsh doh asc t din
hb56uw1673e-f data sheet e0101h10 25 edo page mode mix cycle (2) ? 20 din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t oez t t oea t t rasp t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t rcs row dout 1 dout 4 cpa t cas t cwl dout 3 t oho t wed t wez t ds t dh t ds t din 3 din 2 t oea t t cac t cpw t rch t rcs t wch t rac t oed t col t oea t oho t oez t dh oed t rcs t cal t cal t rcd t rchr t wcs t rsh t wp t asc aa t oep t oep cop
hb56uw1673e-f data sheet e0101h10 26 physical outline hb56uw1673e series 6.35 0.250 3.175 0.125 detail b and c detail a 0.25 max 2.54 min 0.010 max 0.100 min 3.125 0.125 0.123 0.005 1.27 0.050 3.00 133.35 0.118 5.250 127.35 5.014 3.00 0.118 8.89 11.43 36.83 54.61 0.350 0.450 2.150 1.450 a b c 1 84 front side back side 1.27 0.10 4.00 min 0.157 min 0.050 0.004 4.00 max 0.157 max 85 4.00 0.157 17.78 0.700 31.75 1.250 168 2 3.00 2 0.118 1.00 0.05 0.039 0.002 2.00 0.10 0.079 0.004 component area (front) component area (back) unit: mm inch
hb56uw1673e-f data sheet e0101h10 27 cautions 1. elpida memory, inc. neither warrants nor grants licenses of any rights of elpida memory, inc.? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. elpida memory, inc. bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, contact elpida memory, inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by elpida memory, inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. elpida memory, inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. product does not cause bodily injury, fire or other consequential damage due to operation of the elpida memory, inc. product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from elpida memory, inc.. 7. contact elpida memory, inc. for any questions regarding this document or elpida memory, inc. semiconductor products.

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