asahi kasei [akd5701-a] 2006 / 06 - 1 - general description akd5701-a is an evaluation board for the portable di gital audio 16bit a/d converter, AK5701. akd5701-a also has the digital audio interf ace and can achieve the interface with digital audio systems via opt-connector. ? ordering guide akd5701-a --- evaluation board for AK5701 (cable for connecting with printer port of ibm-at compatible pc and control software are packed with this. this cont rol software does not support windows nt.) function ? dit with optical output ? rca connector for an external clock input ? 10pin header for serial control interface ak4114 (dit) 10pin header control data 10pin header dgnd opt out AK5701 vd avdd dsp 1 dvdd agnd mic 5v regulator 3.3v 10pin header dsp 2 ext/bclk rin1/ rin2 lin1/ lin2 ext/lrck clock gen figure 1. akd5701-a block diagram * circuit diagram and pcb layout are attached at the end of this manual. AK5701 evaluation board rev.1 a kd5701- a
asahi kasei [akd5701-a] 2006 / 06 - 2 - evaluation board manual ? operation sequence 1) set up the power supply lines. 1-1) when avdd, dvdd and vd are supplied from the regulator. [reg] (red) = 5v [avdd] (orange) = open [dvdd] (orange) = open [vd] (orange) = 2.7 3.6v : for logic [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground 1-2) when avdd, dvdd and vd are not supplied from the regulator. [reg] (red) = ?reg? jack should be open. [avdd] (orange) = 2.4 3.6v : for avdd of AK5701 (typ. 3.0v) [dvdd] (orange) = 1.6 3.6v : for dvdd of AK5701 (typ. 3.0v) [vd] (orange) = 2.7 3.6v : for logic [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground each supply line should be distributed from the power supply unit. 2) set up the evaluation mode, jumper pins and dip switches. (see the followings.) 3) power on. the AK5701 and ak4114 should be reset once by bringing sw1, 2 ?l? upon power-up. ? evaluation mode in case of AK5701 evaluation using ak4114, same audio interface format should be set for both AK5701 and ak4114. about AK5701?s audio interface format, refer to datasheet of AK5701. about ak4114?s audio interface format, refer to table 2 in this manual. applicable evaluation mode (1) evaluation of pll, master mode (default) (2) evaluation of pll, slave mode (pll reference clock: mcki pin) (3) evaluation of pll, slave mode (p ll reference clock: bclk or lrck pin) (4) evaluation of using dit of ak4114 (opt-connector): ext, slave mode (5) slave & bypass mode (6) bypass mode
asahi kasei [akd5701-a] 2006 / 06 - 3 - (1) evaluation of pll, master mode (default) connect port2 dsp1 with dsp. figure below shows port2 pin assign. port2 gnd gnd nc nc nc vd sdto lrck bclk mcko a) set up jumper pins of mcki clock when using x?tal as mcki clock, x?tal of 11. 2896mhz, 12mhz, 12.288mhz, 13mhz, 24mhz or 27mhz can be set to x1. x?tal of 11.2896mhz (default) is set on the akd5701-a. when an external clock (11.2896mhz, 12mhz, 12.288m hz, 13mhz, 24mhz or 27mhz) is supplied through an rca connector (j3: ext/bclk), select extclk/bclk on jp16 (xti) and select extclk/bclk on jp19 (mclk_sel). jp14 (ext1) and r20 should be properl y selected in order to match the output impedance of the clock generator. jp16 xti jp19 mclk_sel mcki jp11 mkfs extclk /bclk 5701- mcko extclk /bclk 4114- mcko 256fs 512fs 1024fs mck o b) set up jumper pins of bclk clock output frequency (32fs/64fs) of bclk should be set by ?bcko1-0 bit? in the AK5701. there is no necessity for set up jp12. jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk c) set up jumper pins of lrck clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck
asahi kasei [akd5701-a] 2006 / 06 - 4 - (2) evaluation of pll, slave mode (pll reference clock: mcki pin) connect port4 (dsp2) with dsp. figure below shows port4 pin assign. port4 gnd gnd nc nc sdto vd exsdti exlrck exbclk mcki a) set up jumper pins of mcki clock x?tal of 11.2896mhz (default) is set on the akd5701-a. in this case, the AK5701 corresponds to pll reference clock of 11.2896mhz. in this evaluation m ode, the output clock from mcko pin of the AK5701 is supplied to a divider (u3: 74vhc4040), exbclk and lrck clocks are generated by the divider. then ?mcko bit? in the AK5701 should be set to ?1?. when an external clock is supplied through an rca connector (j3: ext/bclk), select extclk/bclk on jp16 (xti) and select extclk/bclk on jp17 (mclk_ sel). jp14 (ext1) and r20 should be properly selected in order too match the output impedance of the clock generator. jp16 xti jp19 mclk_sel mcki jp11 mkfs extclk /bclk 5701- mcko extclk /bclk 4114- mcko 256fs 512fs 1024fs mck o b) set up jumper pins of bclk clock jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk c) set up jumper pins of lrck clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck
asahi kasei [akd5701-a] 2006 / 06 - 5 - (2-a) in the case of using ak4114. *this mode is bclk=64fs, lrck=1fs only. set up jumper pins of mcki clock *in the case of using x1, jp16 should be open. jp16 xti jp19 mclk_sel jp11 mkfs & |