View OM4085_1150324.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet product speci?cation supersedes data of 1996 nov 14 file under integrated circuits, ic12 1997 feb 25 integrated circuits OM4085 universal lcd driver for low multiplex rates
1997 feb 25 2 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 features single-chip lcd controller/driver selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing selectable display bias configuration: static, 1 2 or 1 3 internal lcd bias generation with voltage-follower buffers 24 segment drives: up to twelve 8-segment numeric characters; up to six 15-segment alphanumeric characters; or any graphics of up to 96 elements 24 4-bit ram for display data storage auto-incremented display data loading across device subaddress boundaries display memory bank switching in static and duplex drive modes versatile blinking modes lcd and logic supplies may be separated 2.0 to 6 v power supply range low power consumption power saving mode for extremely low power consumption in battery-operated and telephone applications i 2 c-bus interface ttl/cmos compatible compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers may be cascaded for large lcd applications (up to 1536 segments possible) cascadable with the 40 segment lcd driver pcf8576c optimized pinning for single plane wiring in both single and multiple OM4085 applications space-saving 40 lead plastic very small outline package (vso40; sot158-1) no external components required (even in multiple device applications) manufactured in silicon gate cmos process. general description the OM4085 is a peripheral device which interfaces to almost any liquid crystal display (lcd) having low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 24 segments and can easily be cascaded for larger lcd applications. the OM4085 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). ordering information type number package name description version OM4085t vso40 plastic very small outline package; 40 leads sot158-1
1997 feb 25 3 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagram handbook, full pagewidth mgd866 lcd voltage selector 12 5 timing blinker oscillator input filters i c-bus controller 2 power- on reset clk 4 sync 3 osc 6 11 scl 2 sda 1 sa0 10 display controller command decoder backplane outputs 13 bp0 14 bp2 15 bp1 16 bp3 input bank selector display ram 24 4 bits output bank selector data pointer sub- address counter display segment outputs display latch shift register 17 to 40 s0 to s23 a0 7 a1 8 a2 9 OM4085 lcd bias generator v ss v lcd v dd r r r fig.1 block diagram.
1997 feb 25 4 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 pinning symbol pin description sda 1 i 2 c-bus data input/output scl 2 i 2 c-bus clock input/output sync 3 cascade synchronization input/output clk 4 external clock input/output v dd 5 positive supply voltage osc 6 oscillator input a0 7 i 2 c-bus subaddress inputs a1 8 a2 9 sa0 10 i 2 c-bus slave address bit 0 input v ss 11 logic ground v lcd 12 lcd supply voltage bp0 13 lcd backplane outputs bp2 14 bp1 15 bp3 16 s0 to s23 17 to 40 lcd segment outputs fig.2 pin configuration. handbook, halfpage OM4085 mgd865 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 sda scl sync clk v dd osc a0 a1 a2 sa0 v ss v lcd bp0 bp2 bp1 bp3 s0 s1 s2 s3
1997 feb 25 5 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 functional description the OM4085 is a versatile peripheral device designed to interface any microprocessor to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to 4 backplanes and up to 24 segments. the display configurations possible with the OM4085 depend on the number of active backplane outputs required; a selection of display configurations is given in table 1. all of the display configurations given in table 1 can be implemented in the typical system shown in fig.3. the host microprocessor/microcontroller maintains the two-line i 2 c-bus communication channel with the OM4085. the internal oscillator is selected by tying osc (pin 6) to v ss . the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connections required to complete the system are to the power supplies (v dd , v ss and v lcd ) and to the lcd panel chosen for the application. table 1 selection of display con?gurations active backplane outputs number of segments 7-segment numeric 14-segment alphanumeric dot matrix 4 96 12 digits + 12 indicator symbols 6 characters + 12 indicator symbols 96 dots (4 24) 3 72 9 digits + 9 indicator symbols 4 characters + 16 indicator symbols 72 dots (3 24) 2 48 6 digits + 6 indicator symbols 3 characters + 6 indicator symbols 48 dots (2 24) 1 24 3 digits + 3 indicator symbols 1 character + 10 indicator symbols 24 dots fig.3 typical system configuration. handbook, full pagewidth host micro- processor/ micro- controller sda scl osc 1 17 to 40 13 to 16 2 6 78 512 91011 24 segment drives 4 backplanes lcd panel (up to 96 elements) OM4085 a0 a1 a2 sa0 v dd v dd v lcd v ss v ss mbh951 r t rise 2 c bus
1997 feb 25 6 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 power-on reset at power-on the OM4085 resets to a defined starting condition as follows: 1. all backplane outputs are set to v dd 2. all segment outputs are set to v dd 3. the drive mode 1 : 4 multiplex with 1 3 bias is selected 4. blinking is switched off 5. input and output bank selectors are reset (as defined in table 5) 6. the i 2 c-bus interface is initialized 7. the data pointer and the subaddress counter are cleared. data transfers on the i 2 c-bus should be avoided for 1 ms following power-on to allow completion of the reset action. lcd bias generator the full-scale lcd voltage (v op ) is obtained from v dd - v lcd . the lcd voltage may be temperature compensated externally through the v lcd supply to pin 12. fractional lcd biasing voltages are obtained from an internal voltage divider of three series resistors connected between v dd and v lcd . the centre resistor can be switched out of circuit to provide a 1 2 bias voltage level for the 1 : 2 multiplex configuration. lcd voltage selector the lcd voltage selector coordinates the multiplexing of the lcd according to the selected lcd drive configuration. the operation of the voltage selector is controlled by mode set commands from the command decoder. the biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of v op =v dd - v lcd and the resulting discrimination ratios (d), are given in table 2. a practical value of v op is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10% contrast. in the static drive mode a suitable choice is v op 3 3v th . multiplex drive ratios of 1 : 3 and 1 : 4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller ( for 1 : 3 multiplex or for 1 : 4 multiplex). the advantage of these modes is a reduction of the lcd full scale voltage v op as follows: 1 : 3 multiplex ( 1 2 bias): 1 : 4 multiplex ( 1 2 bias): these compare with v op =3v off(rms) when 1 3 bias is used. 3 1.732 = 21 3 1.528 = v op 6v op(mrs) 2.449v off rms () = = v op 3 4 3 v off rms () 2.309v off rms () == table 2 preferred lcd drive modes: summary of characteristics lcd drive mode lcd bias configuration static (1 bp) static (2 levels) 0 1 1 : 2 mux (2 bp) 1 2 (3 levels) 1 : 2 mux (2 bp) 1 3 (4 levels) 1 3 = 0.333 1 : 3 mux (3 bp) 1 3 (4 levels) 1 3 = 0.333 1 : 4 mux (4 bp) 1 3 (4 levels) 1 3 = 0.333 v off rms () v op ----------------------- v on rms () v op ---------------------- - d v on rms () v off rms () ----------------------- = 2 4 0.354 = 10 4 0.791 = 52.236 = 53 0.745 = 52.236 = 33 9 0.638 = 33 3 1.915 = 33 0.577 = 31.732 =
1997 feb 25 7 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 lcd drive mode waveforms the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in fig.4. when two backplanes are provided in the lcd the 1 : 2 multiplex drive mode applies. the OM4085 allows use of 1 2 or 1 3 bias in this mode as shown in figs 5 and 6. the backplane and segment drive waveforms for the 1 : 3 multiplex drive mode (three lcd backplanes) and for the 1 : 4 multiplex drive mode (four lcd backplanes) are shown in figs 7 and 8 respectively. fig.4 static drive mode waveforms: v op =v dd - v lcd . handbook, full pagewidth mgg392 state 1 at any instant (t): v state 1 (t) = v s n (t) - v bp0 (t) v on(rms) = v op v state 2 (t) = v s n + 1 (t) - v bp0 (t) v off(rms) = 0 v 0 bp0 state 2 0 (a) waveforms at driver (b) resultant waveforms at lcd segment lcd segments state 1 (on) state 2 (off) v dd v lcd v dd v lcd v dd v lcd v op - v op v op - v op t frame s n s n + 1
1997 feb 25 8 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.5 waveforms for 1 : 2 multiplex drive mode with 1 2 bias: v op =v dd - v lcd . handbook, full pagewidth mgg394 state 1 bp0 s n + 1 (a) waveforms at driver (b) resultant waveforms at lcd segment lcd segments state 2 bp1 s n state 2 state 1 v dd (v dd + v lcd )/2 v lcd v dd (v dd + v lcd )/2 v lcd v dd v lcd v dd v lcd v op v op /2 0 - v op /2 - v op v op v op /2 0 - v op /2 - v op t frame at any instant (t): v state 1 (t) = v s n (t) - v bp0 (t) v on(rms) = v op ? 10 = 0.791v op 4 v state 2 (t) = v s n (t) - v bp1 (t) v off(rms) = v op ? 2 = 0.354v op 4
1997 feb 25 9 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.6 waveforms for 1 : 2 multiplex drive mode with 1 3 bias: v op =v dd - v lcd . h andbook, full pagewidth mgg393 state 1 0 bp0 (a) waveforms at driver (b) resultant waveforms at lcd segment lcd segments state 2 bp1 state 1 state 2 0 v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v op - v op 2v op /3 - 2v op /3 v op /3 - v op /3 v op - v op 2v op /3 - 2v op /3 v op /3 - v op /3 s n + 1 s n t frame at any instant (t): v state 1 (t) = v s n (t) - v bp0 (t) v on(rms) = v op ? 5 = 0.745v op 3 v state 2 (t) = v s n (t) - v bp1 (t) v off(rms) = v op = 0.333v op 3
1997 feb 25 10 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.7 waveforms for 1 : 3 multiplex drive mode: v op =v dd - v lcd . handbook, full pagewidth mgg395 state 1 0 bp0 (b) resultant waveforms at lcd segment lcd segments state 2 bp1 state 1 state 2 0 (a) waveforms at driver bp2 v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v op - v op 2v op /3 - 2v op /3 v op /3 - v op /3 v op - v op 2v op /3 - 2v op /3 v op /3 - v op /3 s n s n + 1 s n + 2 t frame at any instant (t): v state 1 (t) = v s n (t) - v bp0 (t) v on(rms) = v op ? 33 = 0.638v op 9 v state 2 (t) = v s n (t) - v bp1 (t) v off(rms) = v op = 0.333v op 3
1997 feb 25 11 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.8 waveforms for 1 : 4 multiplex drive mode: v op =v dd - v lcd. handbook, full pagewidth mgg396 state 1 0 bp0 (b) resultant waveforms at lcd segment lcd segments state 2 bp1 state 1 state 2 0 bp2 (a) waveforms at driver bp3 v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v dd v dd - v op /3 v dd - 2v op /3 v lcd v op - v op 2v op /3 - 2v op /3 v op /3 - v op /3 v op - v op 2v op /3 - 2v op /3 v op /3 - v op /3 s n s n + 1 sn + 2 s n + 3 t frame at any instant (t): v state 1 (t) = v s n (t) - v bp0 (t) v on(rms) = v op ? 3 = 0.577v op 3 v state 2 (t) = v s n (t) - v bp1 (t) v off(rms) = v op = 0.333v op 3
1997 feb 25 12 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 oscillator the internal logic and the lcd drive signals of the OM4085 or pcf8576 are timed either by the built-in oscillator or from an external clock. the clock frequency (f clk ) determines the lcd frame frequency and the maximum rate for data reception from the i 2 c-bus. to allow i 2 c-bus transmissions at their maximum data rate of 100 khz, f clk should be chosen to be above 125 khz. a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state. internal clock when the internal oscillator is used, osc (pin 6) should be tied to v ss . in this case, the output from clk (pin 4) provides the clock signal for cascaded OM4085s and pcf8576s in the system. external clock the condition for external clock is made by tying osc (pin 6) to v dd ; clk (pin 4) then becomes the external clock input. timing the timing of the OM4085 organizes the internal data flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the synchronization signal sync maintains the correct timing relationship between the OM4085s in the system. the timing also generates the lcd frame frequency which it derives as an integer multiple of the clock frequency (table 3). the frame frequency is set by mode set commands when internal clock is used, or by the frequency applied to pin 4 when external clock is used. table 3 lcd frame frequencies the ratio between the clock frequency and the lcd frame frequency depends on the mode in which the device is operating. in the power saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. the reduced clock frequency results in a significant reduction in power dissipation. OM4085 mode f frame nominal f frame (hz) normal mode f clk /2880 64 power saving mode f clk /480 64 the lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the i 2 c-bus. when a device is unable to digest a display data byte before the next one arrives, it holds the scl line low until the first display data byte is stored. this slows down the transmission rate of the i 2 c-bus but no data loss occurs. display latch the display latch holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship between the data in the display latch, the lcd segment outputs and one column of the display ram. shift register the shift register serves to transfer display information from the display ram to the display latch while previous data are displayed. segment outputs the lcd drive section includes 24 segment outputs s0 to s23 (pins 17 to 40) which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with the data resident in the display latch. when less than 24 segment outputs are required the unused segment outputs should be left open-circuit. backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which should be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required the unused outputs can be left open. in the 1 : 3 multiplex drive mode bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. in the 1 : 2 multiplex drive mode bp0 and bp2, bp1 and bp3 respectively carry the same signals and may also be paired to increase the drive capabilities. in the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. display ram the display ram is a static 24 4-bit ram which stores lcd data. a logic 1 in the ram bit-map indicates the on state of the corresponding lcd segment; similarly, a logic 0 indicates the off state.
1997 feb 25 13 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 there is a one-to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. the first ram column corresponds to the 24 segments operated with respect to backplane bp0 (see fig.9). in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with bp1, bp2 and bp3 respectively. when display data are transmitted to the OM4085 the display bytes received are stored in the display ram according to the selected lcd drive mode. to illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in fig.10; the ram filling organization depicted applies equally to other lcd types. with reference to fig.10, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display ram addresses. in the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display ram addresses. in the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. this last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. in the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display ram addresses. data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the data pointer by the load data pointer command. following this, an arriving data byte is stored starting at the display ram address indicated by the data pointer thereby observing the filling order shown in fig.10. the data pointer is automatically incremented according to the lcd configuration chosen. that is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode), by three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex drive mode). subaddress counter the storage of display data is conditioned by the contents of the subaddress counter. storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to a0, a1 and a2 (pins 7, 8, and 9). a0, a1 and a2 should be tied to v ss or v dd . the subaddress counter value is defined by the device select command. if the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. the subaddress counter is also incremented when the data pointer overflows. the storage arrangements described lead to extremely efficient data loading in cascaded applications. when a series of display bytes are being sent to the display ram, automatic wrap-over to the next OM4085 occurs when the last ram address is exceeded. subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character. fig.9 display ram bit-map showing direct relationship between display ram addresses and segment outputs, and between bits in a ram word and backplane outputs. handbook, full pagewidth 0 0 1 2 3 1234 1920212223 display ram addresses (rows)/segment outputs (s) display ram bits (columns) / backplane outputs (bp) mgg389
1997 feb 25 14 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mbe534 s 2 n s 1 n s 7 n s n s n s 3 n s 5 n s 2 n s 3 n s 1 n s 1 n s 1 n s 2 n s n s 6 n s n s 4 n dp dp dp dp a f b g e c d a f b g e c d a f b g e c d a f b g e c d bp0 bp0 bp0 bp1 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n1 n2 n3 n4 n5 n6 n7 bit/ bp n a b x x 0 1 2 3 f g x x e c x x d dp x x n1 n2 n3 bit/ bp n b dp c x 0 1 2 3 a d g x f e x x n1 n2 bit/ bp n a c b dp 0 1 2 3 f e g d n1 bit/ bp cbaf geddp abf gecddp bdpcadgf e ac bdpf egd msb lsb msb lsb msb lsb msb lsb drive mode static 1 : 2 multiplex 1 : 3 multiplex 1 : 4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte fig.10 relationships between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c-bus (x = data bit unchanged).
1997 feb 25 15 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 output bank selector this selects one of the four bits per display ram address for transfer to the display latch. the actual bit chosen depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. in 1 : 4 multiplex, all ram addresses of bit 0 are the first to be selected, these are followed by the contents of bit 1, bit 2 and then bit 3. similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. in 1 : 2 multiplex, bits 0 then 1 are selected and, in the static mode, bit 0 is selected. the OM4085 includes a ram bank switching feature in the static and 1 : 2 multiplex drive modes. in the static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of bit 0 contents. in the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. input bank selector the input bank selector loads display data into the display ram according to the selected lcd drive configuration. display data can be loaded in bit 2 in static drive mode or in bits2and3in1:2 drive mode by using the bank select command. the input bank selector functions independently of the output bank selector. blinker the display blinking capabilities of the OM4085 are very versatile. the whole display can be blinked at frequencies selected by the blink command. the blinking frequencies are integer multiples of the clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which the device is operating, as shown in table 4. an additional feature is for an arbitrary selection of lcd segments to be blinked. this applies to the static and 1 : 2 lcd drive modes and can be implemented without any communication overheads. by means of the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blinking frequency. this mode can also be specified by the blink command. in the 1 : 3 and 1 : 4 multiplex modes, where no alternate ram bank is available, groups of lcd segments can be blinked by selectively changing the display ram data at fixed time intervals. if the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode set command. table 4 blinking frequencies blinking mode normal operating mode ratio power-saving mode ratio nominal blinking frequency f blink (hz) off -- blinking off 2hz f clk /92160 f clk /15360 2 1hz f clk /184320 f clk /30720 1 0.5 hz f clk /368640 f clk /61440 0.5
1997 feb 25 16 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 i 2 c-bus description the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). system con?guration a device generating a message is a transmitter, a device receiving a message is a receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited. each byte is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse, set up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. fig.11 bit transfer. mba607 data line stable; data valid change of data allowed sda scl
1997 feb 25 17 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.12 definition of start and stop conditions. mba608 sda scl p stop condition sda scl s start condition fig.13 system configuration. mba605 master transmitter / receiver slave receiver slave transmitter / receiver master transmitter master transmitter / receiver sda scl fig.14 acknowledgement on the i 2 c-bus. handbook, full pagewidth mba606 - 1 start condition s scl from master data output by transmitter data output by receiver clock pulse for acknowledgement 1 2 8 9
1997 feb 25 18 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 OM4085 i 2 c-bus controller the OM4085 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the OM4085 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferred command data and on the hardware subaddress. in single device applications, the hardware subaddress inputs a0, a1 and a2 are normally left open-circuit or tied to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1 and a2 are left open-circuit or tied to v ss or v dd according to a binary coding scheme such that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. in the power-saving mode it is possible that the OM4085 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. if this situation occurs, the OM4085 forces the scl line low until its internal operations are completed. this is known as the clock synchronization feature of the i 2 c-bus and serves to slow down fast transmitters. data loss does not occur. input ?lters to enhance noise immunity in electrically adverse environments, rc low-pass filters are provided on the sda and scl lines. i 2 c-bus protocol two i 2 c-bus slave addresses (0111110 and 0111111) are reserved for OM4085. the least-significant bit of the slave address that a OM4085 will respond to is defined by the level tied at its input sa0 (pin 10). therefore, two types of OM4085 can be distinguished on the same i 2 c-bus which allows: 1. up to 16 OM4085s on the same i 2 c-bus for very large lcd applications 2. the use of two types of lcd multiplex on the same i 2 c-bus. the i 2 c-bus protocol is shown in fig.15. the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the two OM4085 slave addresses available. all OM4085s with the corresponding sa0 level acknowledge in parallel the slave address but all OM4085s with the alternative sa0 level ignore the whole i 2 c-bus transfer. after acknowledgement, one or more command bytes (m) follow which define the status of the addressed OM4085s. the last command byte is tagged with a cleared most-significant bit, the continuation bit c. the command bytes are also acknowledged by all addressed OM4085s on the bus. after the last command byte, a series of display data bytes (n) may follow. these display data bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated and the data are directed to the intended OM4085 device. the acknowledgement after each byte is made only by the (a0, a1, a2) addressed OM4085. after the last display byte, the i 2 c-bus master issues a stop condition (p). command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. all available commands carry a continuation bit c in their most-significant bit position (see fig.16). when this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. if the bit is reset, it indicates the last command byte of the transfer. further bytes will be regarded as display data. the five commands available to the OM4085 are defined in table 5.
1997 feb 25 19 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.15 i 2 c-bus protocol. handbook, full pagewidth mbh953 s a 0 s 011111 0ac command a p a display data slave address / rw acknowledge by all addressed OM4085s acknowledge by a0, a1 and a2 selected OM4085 only m 3 1 byte(s) n 3 0 byte(s) 1 byte update data pointers and if necessary, subaddress counter fig.16 general format of command byte. mgg388 rest of opcode c msb lsb 0 = last command 1 = commands continue
1997 feb 25 20 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 table 5 de?nition of OM4085 commands table 6 lcd drive mode command/opcode options description mode set c 1 0 lp e b m1 m0 see table 6 de?nes lcd drive mode see table 7 de?nes lcd bias con?guration see table 8 de?nes display status; the possibility to disable the display allows implementation of blinking under external control see table 9 de?nes power dissipation mode load data pointer c 0 0 p4 p3 p2 p1 p0 see table 10 ?ve bits of immediate data, bits p4 to p0, are transferred to the data pointer to de?ne one of twenty-four display ram addresses device select c1100a2a1a0 see table 11 three bits of immediate data, bits a0 to a2, are transferred to the subaddress counter to de?ne one of eight hardware subaddresses bank select c11110 io see table 12 de?nes input bank selection (storage of arriving display data) see table 13 de?nes output bank selection (retrieval of lcd display data) the bank select command has no effect in 1 : 3 and 1 : 4 multiplex drive modes blink c1110abf1bf0 see table 14 de?nes the blinking frequency see table 15 selects the blinking mode; normal operation with frequency set by bits bf1 and bf0, or blinking by alternation of display ram banks. alternation blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes lcd drive mode bit m1 bit m0 static (1 bp) 0 1 1 : 2 mux (2 bp) 1 0 1 : 3 mux (3 bp) 1 1 1 : 4 mux (4 bp) 0 0
1997 feb 25 21 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 table 7 lcd bias con?guration table 8 display status table 9 power dissipation mode table 10 load data pointer table 11 device select table 12 input bank selection table 13 output bank selection table 14 blinking frequency lcd bias bit b 1 3 bias 0 1 2 bias 1 display status bit e disabled (blank) 0 enabled 1 mode bit lp normal mode 0 power-saving mode 1 bits p4 p3 p2 p1 p0 5-bit binary value of 0 to 23 bits a0 a1 a2 3-bit binary value of 0 to 7 static 1 : 2 mux bit 1 ram bit 0 ram bits 0, 1 0 ram bit 2 ram bits 2, 3 1 static 1 : 2 mux bit 0 ram bit 0 ram bits 0, 1 0 ram bit 2 ram bits 2, 3 1 blink frequency bit bf1 bit bf0 off 0 0 2hz 0 1 1hz 1 0 0.5 hz 1 1 table 15 blink mode selection display controller the display controller executes the commands identified by the command decoder. it contains the status registers of the OM4085 and coordinates their effects. the controller is also responsible for loading display data into the display ram as required by the filling order. cascaded operation in large display configurations, up to 16 OM4085s can be distinguished on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1 and a2) and the programmable i 2 c-bus slave address (sa0). it is also possible to cascade up to 16 OM4085s. when cascaded, several OM4085s are synchronized so that they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the outputs of only one device need to be through-plated to the backplane electrodes of the display. the other OM4085s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (fig.17). the sync line is provided to maintain the correct synchronization between all cascaded OM4085s. this synchronization is guaranteed after the power-on reset. the only time that sync is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the definition of a multiplex mode when OM4085s with differing sa0 levels are cascaded). sync is organized as an input/output pin; the output section being realized as an open-drain driver with an internal pull-up resistor. a OM4085 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. should synchronization in the cascade be lost, it will be restored by the first OM4085 to assert sync. the timing relationships between the backplane waveforms and the sync signal for the various drive modes of the pcf8576 are shown in fig.18. the waveforms are identical with the parent device pcf8576. cascade ability between OM4085s and pcf8576s is possible, giving cost effective lcd applications. blink mode bit a normal blinking 0 alternation blinking 1
1997 feb 25 22 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.17 cascaded OM4085 configuration. handbook, full pagewidth host micro- processor/ micro- controller sda scl clk osc sync 1 17 to 40 13 to 16 13 to 16 2 3 4 6 78 512 91011 7 8 9 10 11 24 segment drives 4 backplanes 24 segment drives lcd panel (up to 1536 elements) OM4085 OM4085 a0 a1 a2 sa0 mbh950 sda scl sync clk osc 1 512 2 3 4 6 17 to 40 bp0 to bp3 (open-circuit) a0 a1 a2 sa0 bp0 to bp3 v dd v lcd v ss v dd v lcd v ss v lcd v dd v ss r t rise 2 c bus
1997 feb 25 23 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 for single plane wiring of OM4085s, see chapter application information. fig.18 synchronization of the cascade for the various OM4085 drive modes. handbook, full pagewidth t= frame f frame 1 bp0 sync bp1 (1/2 bias) sync bp2 (a) static drive mode. (b) 1 : 2 multiplex drive mode. (c) 1 : 3 multiplex drive mode. (d) 1 : 4 multiplex drive mode. bp3 sync sync bp1 (1/3 bias) mbe535
1997 feb 25 24 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 limiting values in accordance with the absolute maximum rating system (iec 134). handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is advised to take handling precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.5 +7 v v lcd lcd supply voltage v dd - 7v dd v v i input voltage (scl, sda, a0 to a2, osc, clk, sync and sa0) v ss - 0.5 v dd + 0.5 v v o output voltage (s0 to s23 and bp0 to bp3) v lcd - 0.5 v dd + 0.5 v i i dc input current - 20 ma i o dc output current - 25 ma i dd , i ss , i lcd v dd , v ss or v lcd current - 50 ma p tot power dissipation per package - 400 mw p o power dissipation per output - 100 mw t stg storage temperature - 65 +150 c
1997 feb 25 25 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 dc characteristics v ss =0v; v dd = 2.0 to 6 v; v lcd =v dd - 2.0 to v dd - 6 v; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. outputs open; inputs at v ss or v dd ; external clock with 50% duty factor; i 2 c-bus inactive. 2. resets all logic when v dd 1997 feb 25 26 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 ac characteristics v ss =0v; v dd = 2.0 to 6 v; v lcd =v dd - 2.0 to v dd - 6 v; t amb = - 40 to +85 c; unless otherwise speci?ed; note 1. notes 1. all timing values referred to v ih and v il levels with an input voltage swing of v ss to v dd . 2. at f clk < 125 khz, i 2 c-bus maximum transmission speed is derated. symbol parameter conditions min. typ. max. unit f clk oscillator frequency (normal mode) v dd = 5 v; note 2 125 200 315 khz f clklp oscillator frequency (power saving mode) v dd = 3.5 v 21 31 48 khz t clkh clk high time 1 --m s t clkl clk low time 1 --m s t psync sync propagation delay -- 400 ns t syncl sync low time 1 --m s t plcd driver delays with test loads v lcd =v dd - 5v -- 30 m s i 2 c-bus t buf bus free time 4.7 --m s t hd; sta start condition hold time 4 --m s t low scl low time 4.7 --m s t high scl high time 4 --m s t su; sta start condition set-up time (repeated start code only) 4.7 --m s t hd; dat data hold time 0 --m s t su; dat data set-up time 250 -- ns t r rise time -- 1 m s t f fall time -- 300 ns t su; sto stop condition set-up time 4.7 --m s fig.19 test loads. handbook, full pagewidth mgg387 3.3 k w 1.5 k w 6.8 k w (2%) (2%) (2%) clk (pin 4) sda, scl (pins 1, 2) sync (pin 3) 0.5v dd v dd v dd s0 to s23 (pins 17 to 40) i load ? 15 m a i load ? 25 m a bp0 to bp3 (pins 13 to 16)
1997 feb 25 27 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.20 driver timing waveforms. handbook, full pagewidth mgg391 1 f clk t clkh t clkl t psync t syncl t plcd 0.5 v 0.5 v (v dd = 5 v) 0.3v dd 0.7v dd 0.3v dd 0.7v dd clk sync bp0 to bp3 s0 to s23 fig.21 i 2 c-bus timing waveforms. handbook, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
1997 feb 25 28 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 fig.22 typical supply current characteristics. a. normal mode; v lcd =0v; external clock = 200 khz. b. low power mode; v lcd =0v; external clock = 35 khz. handbook, halfpage 40 30 10 20 mgg397 0 0 24 8 6 v dd (v) i dd ( m a) + 85 c - 40 c handbook, halfpage 0 24 16 8 0 24 8 6 mgg398 v dd (v) i dd ( m a) - 40 c + 85 c fig.23 typical characteristics of lcd outputs. a. backplane output impedance bp0 to bp3 (r bp ); v dd = 5 v; t amb = - 40 to +85 c. b. segment output impedance s0 to s23 (r s ); v dd =5v. handbook, halfpage 0 6 4 2 0 24 8 6 mgg399 v dd (v) r bp (k w ) handbook, halfpage 0 12 8 4 0 24 8 6 mgg400 v dd (v) r s (k w ) + 25 c + 85 c - 40 c
1997 feb 25 29 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... application information fig.24 single plane wiring of package OM4085s. handbook, full pagewidth mbh952 OM4085 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 s23 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 sda scl sync clk v dd osc a0 a1 a2 sa0 v ss v lcd v ss v lcd bp0 bp2 bp1 bp3 s0 s0 s1 s2 s3 sda scl sync clk v dd OM4085 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 s47 s47 s46 s45 s44 s43 s42 s41 s40 s39 s38 s37 s36 s35 s34 s33 s32 s31 s30 s29 s28 bp0 bp2 bp1 bp3 s24 s24 s25 s26 s27 open-circuit backplanes segments
1997 feb 25 30 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 chip dimensions and bonding pad locations fig.25 bonding pad locations. (1) typical value. pad size: 120 120 m m chip area: 7.27 mm. the numbers given in the small squares refer to the pad numbers. handbook, full pagewidth mbh949 y 2.5 mm (1) x 0 0 OM4085 36 37 38 39 40 5 4 3 2 1 25 24 23 22 21 16 15 14 2.91 (1) mm 13 12 11 10 17 18 19 20 9 8 7 6 30 31 32 33 34 35 26 27 28 29 s23 s22 s21 s20 s19 v dd clk sync scl sda s5 s7 s8 s6 sa0 a2 a1 a0 osc s16 s17 s18 v ss v lcd bp0 bp2 bp1 s11 s10 s9 s12 s14 s13 s15 bp3 s0 s1 s2 s3 s4
1997 feb 25 31 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 table 16 bonding pad locations (dimensions in mm) all x/y coordinates are referenced to centre of chip, (see fig.25) pad number symbol x y pin 1 sda 200 - 1235 1 2 scl 400 - 1235 2 3 sync 605 - 1235 3 4 clk 856 - 1235 4 5v dd 1062 - 1235 5 6 osc 1080 - 1025 6 7 a0 1080 - 825 7 8 a1 1080 - 625 8 9 a2 1080 - 425 9 10 sa0 1080 - 225 10 11 v ss 1080 - 25 11 12 v lcd 1080 347 12 13 bp0 1080 547 13 14 bp2 1080 747 14 15 bp1 1080 947 15 16 bp3 1074 1235 16 17 s0 674 1235 17 18 s1 674 1235 18 19 s2 474 1235 19 20 s3 274 1235 20 21 s4 - 274 1235 21 22 s5 - 474 1235 22 23 s6 - 674 1235 23 24 s7 - 874 1235 24 25 s8 - 1074 1235 25 26 s9 - 1080 765 26 27 s10 - 1080 565 27 28 s11 - 1080 365 28 29 s12 - 1080 165 29 30 s13 - 1080 - 35 30 31 s14 - 1080 - 235 31 32 s15 - 1080 - 435 32 33 s16 - 1080 - 635 33 34 s17 - 1080 - 835 34 35 s18 - 1080 - 1035 35 36 s19 - 1056 - 1235 36 37 s20 - 830 - 1235 37 38 s21 - 630 - 1235 38 39 s22 - 430 - 1235 39 40 s23 - 230 - 1235 40
1997 feb 25 32 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 package outline unit a 1 a 2 a 3 b p cd (1) e (2) z (1) eh e ll p qy w v q references outline version european projection issue date iec jedec eiaj mm inches 0.3 0.1 2.45 2.25 0.25 0.42 0.30 0.22 0.14 15.6 15.2 7.6 7.5 0.762 2.25 12.3 11.8 1.15 1.05 0.6 0.3 7 0 o o 0.1 0.1 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 1.7 1.5 sot158-1 92-11-17 95-01-24 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a y 40 20 21 1 pin 1 index 0.012 0.004 0.096 0.089 0.017 0.012 0.0087 0.0055 0.61 0.60 0.30 0.29 0.03 0.089 0.48 0.46 0.045 0.041 0.024 0.012 0.004 0.2 0.008 0.004 0.067 0.059 0.010 0 5 10 mm scale vso40: plastic very small outline package; 40 leads sot158-1 a max. 2.70 0.11
1997 feb 25 33 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all vso packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all vso packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 feb 25 34 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 feb 25 35 philips semiconductors product speci?cation universal lcd driver for low multiplex rates OM4085 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2870, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417067/25/02/pp36 date of release: 1997 feb 25 document order number: 9397 750 01676

▲Up To Search▲

Price & Availability of OM4085

	To Download OM4085 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .