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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 7 1 publication order number: CS5305/d CS5305 three?phase synchronous switching step?down controller with single wire current sharing the CS5305 provides a low ? cost, single ? controller solution for the low ? voltage, high ? current power needs of next ? generation workstation and server processors. this ic provides high accuracy and the industry?s fastest transient response, reducing the need for large banks of output capacitors and providing the most compact, reliable, and economical power supply. since each phase?s output voltage and current feed back to develop the pwm ramp signal (enhanced v 2 ? control), the CS5305 shares output current accurately between phases. accurate current sharing means that the power supply design does not need to use power components rated to handle mismatched current per phase. the enhanced v 2 control compensates for variations in both line and load. the ic?s built ? in single wire current sharing capability allows easy paralleling of multiple voltage regulator modules (vrms) based on the CS5305. the paralleled vrms use a shared bus to provide high current and high reliability to multiple microprocessor workstations or servers. the CS5305 meets vrm 9.x specifications with its power good, enable, differential remote sense, and single ? wire current share features. the product fits server and workstation vrms, and can be used to power embedded processors. the ic provides the simplest, lowest ? cost solution for any low voltage, high current power supply. features ? enhanced v 2 control method ? vrm 9.x compatible vid codes ? lossless inductor current sensing ? single wire active current sharing between converters ? auto master ? slave current share control method ? programmable 200 to 800 khz switching frequency ? programmable adaptive voltage positioning ? differential remote sense ? pulse ? by ? pulse current limit ? master hiccup overcurrent protection through single wire share bus ? 5 ? bit dac with 1% tolerance ? enabl input ? vrm 9.x ? compliant power good output ? active current sharing during soft start http://onsemi.com device package shipping ordering information so ? 28l 27 units/rail so ? 28l 1000 tape & reel so ? 28l dw suffix case 751f 1 28 1 28 pwrgds i fb sgnd cs ref v cc cs3 drvon cs2 gate3 cs1 gate2 enabl gate1 r osc gnd ocset v id0 i out v id1 share v id3 v drp v id2 scomp v id4 v fb pwrgd comp pin connections CS5305gdw28 CS5305gdwr28 marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week 1 CS5305 awlyyww 28
CS5305 http://onsemi.com 2 application diagrams gh gh gh gnd gate1 gate2 gate3 drvon v cc sgnd pwrgds v id0 v id1 v id2 v id3 v id4 pwrgd ocset r osc enabl cs1 cs2 cs3 cs ref i fb i out share scomp v drp v fb comp CS5305 3.9 k 47 nf 12 k 3 k .01 f 22 nf 91 k 17 k 220 0.1 f 220 12 k 3 47 nf 3 gnd sense powergood v out sense share v id4 v id3 v id2 v id1 v id0 60.4 k ncp5351 enable v cc gl pgnd in bst swn 1 f .47 nf ntd 4302 2 ntd 4302 2 bas40lt1 ncp5351 enable v cc gl pgnd in bst swn 1 f ntd 4302 2 bas40lt1 ncp5351 enable v cc gl pgnd in bst swn 1 f ntd 4302 2 bas40lt1 ntd 4302 2 ntd 4302 2 v out 100 f 5 270 nh 470 nh 20 k enable 28.7 k +12 v 2.2 f 220 k 0.1 f 6.2 v gnd 5.6 v .47 f .47 f figure 1. vrm 9.0, 60 a converter 10 f 3 20
CS5305 http://onsemi.com 3 12 v enable v id0 v id1 v id2 v id3 v id4 v out sense v out gnd gnd sense powergood share 12 v enable v id0 v id1 v id2 v id3 v id4 v out sense v out gnd gnd sense powergood share enable v id0 v id1 v id2 v id3 v id4 12 v 5.0 v gnd v out powergood 1.5 k inductors & resistors represent distribution impedances. * figure 2. two ? converter system with sharing maximum ratings* rating value unit operating junction temperature 150 c storage temperature range ? 65 to 150 c esd susceptibility (human body model) 2.0 kv thermal resistance, junction ? to ? case, r jc 15 c/w thermal resistance, junction ? to ? ambient, r ja 75 c/w jedec moisture sensitivity level 5 ? lead temperature soldering: reflow: (smd styles only) note 1. 230 peak c 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. maximum ratings pin number pin symbol v max v min i source i sink 1 ocset 7.0 v ? 0.3 v 1.0 ma 1.0 ma 2 r osc 7.0 v ? 0.3 v 1.0 ma 1.0 ma 3 enabl 16 v ? 0.3 v 1.0 ma 1.0 ma 4 ? 6 cs1 ? 3 7.0 v ? 0.3 v 1.0 ma 1.0 ma 7 cs ref 7.0 v ? 0.3 v 1.0 ma 1.0 ma 8 i fb 7.0 v ? 0.3 v 1.0 ma 1.0 ma 9 i out 7.0 v ? 0.3 v 10 ma 10 ma 10 share 16 v ? 0.3 v 50 ma 1.0 ma 11 scomp 7.0 v ? 0.3 v 1.0 ma 1.0 ma 12 v drp 7.0 v ? 0.3 v 1.0 ma 1.0 ma 13 v fb 7.0 v ? 0.3 v 1.0 ma 1.0 ma 14 comp 7.0 v ? 0.3 v 10 ma 1.0 ma 15 pwrgd 16 v ? 0.3 v 1.0 ma 20 ma
CS5305 http://onsemi.com 4 maximum ratings (continued) pin number i sink i source v min v max pin symbol 16 ? 20 v id4 ? v id0 16 v ? 0.3 v 1.0 ma 1.0 ma 21 pwrgds 7.0 v ? 0.3 v 1.0 ma 1.0 ma 22 sgnd 0.3 v ? 0.3 v 1.0 ma 1.0 ma 23 v cc 16 v ? 0.3 v n/a 0.4 a, 1.0 s 100 ma dc 24 drvon 7.0 v ? 0.3 v 10 ma 1.0 ma 25 ? 27 gate 3 ? 1 16 v ? 0.3 v 0.1 a, 1.0 s; 25 ma dc 0.1 a, 1.0 s 25 ma dc 28 gnd n/a n/a 0.4 a, 1.0 s; 100 ma dc n/a electrical characteristics (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c scomp = 0.01 f, c vcc = 0.1 f, r rosc = 32.4 k , r share = 60.4 k , v(ocset) = 0.54 v, dac code 01110; unless otherwise stated.) parameter test conditions min typ max unit voltage identification dac (0 = connected to gnd, 1 = open (pulled ? up to internal 3.3 v) or pulled ? up to external voltage 13 v) accuracy (all codes) vid code ? 125 mv connect vfb to comp, sgnd < 55 mv, measure comp ? sgnd 1.0 % v id4 v id3 v id2 v id1 v id0 v id maximum voltage 1 1 1 1 1 drvon < 1.0 v, gate x < 1.0 v fault mode v 1 1 1 1 0 1.100 0.965 0.975 0.985 v 1 1 1 0 1 1.125 0.990 1.000 1.010 v 1 1 1 0 0 1.150 1.015 1.025 1.035 v 1 1 0 1 1 1.175 1.040 1.050 1.061 v 1 1 0 1 0 1.200 1.064 1.075 1.086 v 1 1 0 0 1 1.225 1.089 1.100 1.111 v 1 1 0 0 0 1.250 1.114 1.125 1.136 v 1 0 1 1 1 1.275 1.139 1.150 1.162 v 1 0 1 1 0 1.300 1.163 1.175 1.187 v 1 0 1 0 1 1.325 1.188 1.200 1.212 v 1 0 1 0 0 1.350 1.213 1.225 1.237 v 1 0 0 1 1 1.375 1.238 1.250 1.263 v 1 0 0 1 0 1.400 1.263 1.275 1.288 v 1 0 0 0 1 1.425 1.287 1.300 1.313 v 1 0 0 0 0 1.450 1.312 1.325 1.338 v 0 1 1 1 1 1.475 1.337 1.350 1.364 v 0 1 1 1 0 1.500 1.361 1.375 1.389 v 0 1 1 0 1 1.525 1.386 1.400 1.414 v 0 1 1 0 0 1.550 1.411 1.425 1.439 v 0 1 0 1 1 1.575 1.436 1.450 1.465 v 0 1 0 1 0 1.600 1.460 1.475 1.490 v 0 1 0 0 1 1.625 1.485 1.500 1.515 v 0 1 0 0 0 1.650 1.510 1.525 1.540 v
CS5305 http://onsemi.com 5 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c scomp = 0.01 f, c vcc = 0.1 f, r rosc = 32.4 k , r share = 60.4 k , v(ocset) = 0.54 v, dac code 01110; unless otherwise stated.) parameter unit max typ min test conditions voltage identification dac (0 = connected to gnd, 1 = open (pulled ? up to internal 3.3 v) or pulled ? up to external voltage 13 v) 0 0 1 1 1 1.675 1.535 1.550 1.566 v 0 0 1 1 0 1.700 1.560 1.575 1.591 v 0 0 1 0 1 1.725 1.584 1.600 1.616 v 0 0 1 0 0 1.750 1.609 1.625 1.641 v 0 0 0 1 1 1.775 1.634 1.650 1.667 v 0 0 0 1 0 1.800 1.658 1.675 1.692 v 0 0 0 0 1 1.825 1.683 1.700 1.717 v 0 0 0 0 0 1.850 1.708 1.725 1.742 v input threshold v id4 , v id3 , v id2 , v id1 , v id0 1.00 1.25 1.5 v input pull ? up resistance 0 v < v id4 , v id3 , v id2 ,v id1 , v id0 < 3.3 v 25 50 100 k pull ? up voltage 1.0 m to gnd 2.5 2.7 3.0 v sgnd bias current sgnd < 55 mv, all dac codes 10 20 40 a power good output upper threshold force pwrgds ? sgnd sgnd < 55 mv 1.876 ( ? 5%) 1.975 2.074 (+5%) v lower threshold force pwrgds ? sgnd sgnd < 55 mv 0.95 (v id ? 125 mv) or ? 2.6% from nominal pwrgd threshold 0.975 (v id ? 125 mv) v id ? 125 mv or +2.6% from nominal pwrgd threshold v v id4 v id3 v id2 v id1 v id0 1 1 1 1 0 0.926 0.951 0.975 v 1 1 1 0 1 0.950 0.975 1.000 v 1 1 1 0 0 0.974 1.000 1.025 v 1 1 0 1 1 0.998 1.024 1.050 v 1 1 0 1 0 1.021 1.048 1.075 v 1 1 0 0 1 1.045 1.073 1.100 v 1 1 0 0 0 1.069 1.097 1.125 v 1 0 1 1 1 1.093 1.122 1.150 v 1 0 1 1 0 1.116 1.146 1.175 v 1 0 1 0 1 1.140 1.170 1.200 v 1 0 1 0 0 1.164 1.195 1.225 v 1 0 0 1 1 1.188 1.219 1.250 v 1 0 0 1 0 1.211 1.243 1.275 v 1 0 0 0 1 1.235 1.268 1.300 v 1 0 0 0 0 1.259 1.292 1.325 v 0 1 1 1 1 1.283 1.316 1.350 v 0 1 1 1 0 1.306 1.341 1.375 v
CS5305 http://onsemi.com 6 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c scomp = 0.01 f, c vcc = 0.1 f, r rosc = 32.4 k , r share = 60.4 k , v(ocset) = 0.54 v, dac code 01110; unless otherwise stated.) parameter unit max typ min test conditions power good output 0 1 1 0 1 1.330 1.365 1.400 v 0 1 1 0 0 1.354 1.389 1.425 v 0 1 0 1 1 1.378 1.414 1.450 v 0 1 0 1 0 1.401 1.438 1.475 v 0 1 0 0 1 1.425 1.463 1.500 v 0 1 0 0 0 1.449 1.487 1.525 v 0 0 1 1 1 1.473 1.511 1.550 v 0 0 1 1 0 1.496 1.536 1.575 v 0 0 1 0 1 1.520 1.560 1.600 v 0 0 1 0 0 1.544 1.584 1.625 v 0 0 0 1 1 1.568 1.609 1.650 v 0 0 0 1 0 1.591 1.633 1.675 v 0 0 0 0 1 1.615 1.658 1.700 v 0 0 0 0 0 1.639 1.682 1.725 v switch leakage current v cc = 14 v, pwrgds = 1.4 v ? ? 1.0 a delay pwrgds low to pwrgd low 50 250 600 s output low voltage pwrgds = 1.0 v, i pwrgood = 4.0 ma ? 0.15 0.4 v voltage feedback error amplifier v fb bias current note 2. 9.5 10.3 11.5 a comp source current comp = 0.5 v to 2.0 v, v fb = 1.6 v 15 30 60 a comp sink current comp = 0.5 v to 2.0 v, v fb = 1.0 v 15 30 60 a transconductance ? 10 a < i comp < +10 a, note 3. ? 32.0 ? mmho output impedance note 3. ? 2.5 ? m open loop dc gain note 3. 60 95 ? db unity gain bandwidth comp = 0.01 f, note 3. ? 50 ? khz psrr @ 1.0 khz note 3. ? 70 ? db comp max voltage v fb = 0 v 2.4 2.7 ? v comp min voltage v fb = 1.6 v ? 0.1 0.2 v comp discharge threshold ? 0.15 0.2 0.25 v hiccup latch discharge current csx ? cs ref = .05 v, ocset = 0.1 v, comp = 0.5 v 2.0 5.0 10 a hiccup charge / discharge ratio ? 4.5 6.0 7.5 ? 2. the v fb bias current changes with the value of r osc per figure 5. 3. guaranteed by design. not tested in production.
CS5305 http://onsemi.com 7 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c scomp = 0.01 f, c vcc = 0.1 f, r rosc = 32.4 k , r share = 60.4 k , v(ocset) = 0.54 v, dac code 01110; unless otherwise stated.) parameter unit max typ min test conditions voltage feedback error amplifier share fault discharge current share = 3.5 v, comp = 0.5 v, csx = cs ref = 0 v, ocset = 0.5 v 0.3 2.5 5.0 ma enable input threshold voltage monitor drvon 1.12 1.25 1.38 v pull ? up voltage 1 m to gnd 2.5 2.7 3.0 v input pull ? up resistance ? 25 50 100 k pwm comparators minimum pulse width measured from csx to gatex, v fb = cs ref = 0.5 v, comp = 0.5 v, 60 mv step on csx; measure at gatex = 1.0 v ? 75 220 ns transient response time measured from cs ref to gatex, comp = 2.1 v, csx = cs ref = 0.5 v, cs ref stepped from 1.2 v ? 2.0 v ? 100 150 ns channel start ? up offset csx = cs ref = v fb = 0 v, measure v(comp) when gatex switch high 0.34 0.6 0.75 v channel start ? up offset mismatch csx = cs ref = v fb = 0 v, measure v(comp) when gatex switch high, note 4. ? 5.0 ? 5.0 mv gates high voltage i gatex = 1.0 ma 2.25 2.5 3.0 v low voltage i gatex = 1.0 ma ? 0.2 0.4 v rise time gate 0.8 v < gate < 2.0 v, v cc = 10 v ? 15 30 ns fall time gate 2.0 v > gate > 0.8 v, v cc = 10 v ? 15 30 ns oscillator switching frequency r osc = 32.4 k 300 400 500 khz switching frequency r osc = 63.4 k , note 4. 150 200 250 khz switching frequency r osc = 16.2 k , note 4. 600 800 1000 khz r osc voltage note 4. 0.90 1.00 1.10 v phase delay ? 90 120 150 deg 4. guaranteed by design. not tested in production.
CS5305 http://onsemi.com 8 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c scomp = 0.01 f, c vcc = 0.1 f, r rosc = 32.4 k , r share = 60.4 k , v(ocset) = 0.54 v, dac code 01110; unless otherwise stated.) parameter unit max typ min test conditions current sense amplifiers cs ref input bias current cs ref = csx = 0 v ? 0.3 3.0 a csx input bias current cs ref = csx = 0 v ? 0.1 1.0 a sense amp gain cs ref = 0 v, csx = 0.05 v, measure v(comp) when gatex switches high .95 1.06 1.17 v / v mismatch 0 (csx ? cs ref ) 50 mv, note 5. ? 3.0 ? 3.0 mv common mode input range note 5. 0 ? 2.0 v bandwidth note 5. ? 7.0 ? mhz single phase pulse by pulse current limit v fb = cs ref = 0.5 v, comp = 2.0 v, measure csx ? cs ref when gatex goes low 80 90 100 mv ocset input bias current ocset = 0 v ? 0.1 1.0 a current sense input to ocset gain ocset / r (csx ? cs ref ), ocset = 0.6 v, monitor drvon < 1.0 v 3.4 3.7 4.0 v / v current limit filter slew rate cs ref = 1.1 v, csx = 1.0 v, pulse csx to 1.16 v, note 5. 2.0 5.0 13 mv / s adaptive voltage positioning v drp output voltage to dac out offset csx = cs ref , v fb = comp, measure v drp ? comp ? 30 2.0 60 mv maximum v drp voltage csx ? cs ref = 50 mv, v fb = comp, measure v drp ? comp 500 560 620 mv current sense amp to v drp gain csx ? cs ref = 50 mv, v fb = comp, measure v drp ? comp 3.4 3.7 4.0 v / v v drp source current csx ? cs ref = 50 mv, v fb = comp, v drp = 1.5 v 1.0 7.0 14 ma share current sense amplifier i fb input bias current i fb = 0 v ? 0.2 1.0 a input offset voltage note 5. ? 5.0 0 5.0 mv common mode input range note 5. 0 ? 2.0 v output current i out = 0 v, csx = 0.667 v, cs ref = 0.5 v 1.0 10 22 ma gain note 5. ? 120 ? db output unity gain bw note 5. ? 5.0 ? mhz 5. guaranteed by design. not tested in production.
CS5305 http://onsemi.com 9 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c scomp = 0.01 f, c vcc = 0.1 f, r rosc = 32.4 k , r share = 60.4 k , v(ocset) = 0.54 v, dac code 01110; unless otherwise stated.) parameter unit max typ min test conditions share bus share amplifier offset voltage measure v(share) ? v(i out ), 0 < i out < 2.0 v 20 40 60 mv share amplifier source current i out = 2.1 v, share = 2.0 v 1.0 7.5 24 ma share amplifier max voltage i out = 3.5 v, t a = 25 c 2.65 2.80 3.20 v share fault threshold drvon < 1.0 v, t a = 25 c 3.2 3.4 3.7 v share ok threshold drvon > 1.0 v 2.0 2.3 2.5 v share fault hysteresis ? 1.0 1.15 1.3 v share fault output voltage ? 3.8 4.25 4.7 v share fault output current share = 3.8 v 1.2 2.0 2.5 ma share full load accuracy cs ref = 0.5 v, csx = 0.52 v, i out / fb divider = 22 k /3.0 k 1.7 1.95 2.2 v share short circuit current v(i out ) = 2.0 v, share = gnd 1.0 17 28 ma share fault short circuit current cs ref = 0.5 v, csx = 0.6 v 2.0 19 30 ma current share adjust amplifier transconductance from i out to scomp 0 < i out < 2.0 v, 0 < scomp < 2.0 v 23 40 53 a / v gain from i out to comp note 6. 30 50 140 ma / v maximum scomp source current scomp = 1.5 v 15 30 60 a maximum scomp sink current scomp = 1.5 v 15 30 60 a unity gain bw c(scomp) = tbd, note 6. 30 56 100 hz mosfet driver enable pull ? up voltage drvon floating 4.5 5.5 6.0 v drvon source current drvon = 1.5 v .5 3.0 6.5 ma drvon pull down resistor drvon = 1.5 v, enabl = 0 v, r = 1.5 v / i(1.5 v) 35 70 140 k general electrical specifications v cc disable current enable = 0 v (no switching) ? 30 60 ma uvlo start threshold comp charging, drvon > 1.0 v 8.5 9.0 9.5 v uvlo stop threshold gates not switching, comp discharging, drvon < 1.0 v 7.5 8.0 8.5 v uvlo hysteresis start ? stop 0.8 1.0 1.2 v v cc operating current enable open ? 22 30 ma 6. guaranteed by design. not tested in production.
CS5305 http://onsemi.com 10 package pin description package pin number pin symbol pin name function so ? 28l 1 ocset over ? current set resistor divider from r osc to gnd programs the threshold of the hiccup over ? current protection. 2 r osc oscillator frequency adjust resistance to gnd programs the oscillator frequency. it also programs the v fb bias current shown in figure 5. 3 enabl enable input ttl ? compatible logic input with 50 k internal pull ? up resistor to 3.3 v. a logic low puts the ic in fault mode. 4 ? 6 cs1 ? 3 current sense inputs non ? inverting inputs to the current sense amplifiers. 7 cs ref current sense reference inverting input to the current sense amplifiers, and fast feedback input to the pwm comparator. 8 i fb share current amp inverting input inverting input to share current amp. connect resistor divider between i out , i fb , and ic gnd pin 28 to program share current amp gain. 9 i out share current amp output share current amplifier output and input to share adjust amplifier. 10 share share bus connect with other modules for single ? wire current sharing. 11 scomp share compensation connect compensation network to stabilize share loop. 12 v drp current sense output for avp the offset of this pin above the dac voltage is proportional to the output current. connect a resistor from this pin to v fb to program the avp voltage or leave this pin open for no avp. 13 v fb voltage feedback error amp inverting input. input bias current used to program avp light load offset via resistor connected to converter output voltage. short v fb to the converter output voltage for no avp. 14 comp error amp output and pwm comparator input provides loop compensation. also used to control softstart and fault timing. 15 pwrgd power good output open collector output goes low when v fb is out of regulation. user must externally limit current into this pin to less than 20 ma. 16 ? 20 v id4 ? v id0 voltage id dac inputs programs output voltage. 50 k internal pull ? up resistors to 3.3 v. 21 pwrgds power good sense provides remote output voltage sensing. 22 sgnd reference ground ground connection for the dac. provides remote sensing of ground at the load. 23 v cc supply input ic power supply input. 24 drvon driver enable logic high enables outputs of compatible mosfet driver ics. low turns all mosfets off. pin driven from internal 5.5 v; 70 k internal resistor to gnd. 25 ? 27 gate 3 ? 1 fet driver outputs pwm signal input to external mosfet gate driver ics. 28 gnd ground ic power supply return; connected to ic substrate.
CS5305 http://onsemi.com 11 v id0 v id1 v id2 v id3 v id4 dac sgnd 50 k ? + 3.3 v ocset dac output vid = 1 1111 ? oc filter ? + ? + 1.25 v enabl enable comparator ? + ? + 50 k 3.3 v start stop ? + v cc 9.0 v 8.0 v uvlo comparator ? + ? + ? + 0.2 v discharge comparator reset dominant s r share fault * 0.975 v ? + ? + v drp comp reset ? + ? + pwm1 comparator ilim1 comparator ? + 0.33 v co1 co1f ? + ? + pwm2 comparator ilim2 comparator ? + 0.33 v co2 co2f ? + ? + pwm3 comparator ilim3 comparator ? + 0.33 v co3 co3f reset dominant r s reset dominant r s reset dominant r s v cc pgnd pgnd v cc gate2 gate1 gate3 latch pwm1 latch pwm2 latch pwm3 ? + avp amp delay ? + ? + 1.975 v pwrgds pwrgd ? 3.7 co1 1 co1f 3.7 co2 1 co2f 3.7 co3 1 co3f ? + ? + ? + ? + ? + cs ref cs1 cs2 cs3 ? + ? + share current sense amp ? + 30 mv i fb i out share bus amp ? + share adjust amp share scomp start stop ? + ? + 3.1 v 2.1 v share fault comparator error amp fault ? + v fb ? + 0.6 v ? + 3.3 v ? + 3.8 v share fault ibias idischg fault comp current source generator ? + 1.0 v ? + r osc pulseout1 pulseout2 pulseout3 iosc oscillator gnd fault 5.5 v drvon 70 k oc comparator figure 3. block diagram v cc pgnd pgnd
CS5305 http://onsemi.com 12 typical performance characteristics figure 4. oscillator frequency 0 i cc (ma) 33 temperature ( c) 34 35 36 37 38 39 40 25 50 75 100 125 enabl = low enabl = floating gates switching 0 threshold voltage (v) 8.0 temperature ( c) 8.2 8.4 8.6 8.8 9.0 9.2 9.4 25 50 75 100 125 start threshold stop threshold 0 oscillator frequency (khz) 400 temperature ( c) 405 410 25 50 75 100 125 0 dac output (v) 1.348 temperature ( c) 1.349 1.350 1.351 1.352 1.353 1.354 25 50 75 100 125 frequency (khz) 100 r osc value (k ) 300 400 500 600 700 800 900 200 10 20 30 40 50 60 70 10 v fb bias current ( a) 0 r osc value 5 10 15 20 25 20 30 40 50 60 70 80 figure 5. v fb bias current vs. r osc value figure 6. i cc vs. temperature figure 7. uvlo start and stop thresholds vs. temperature figure 8. oscillator frequency vs. temperature for r osc = 32.4 k figure 9. dac output for vid = 01111 (1.475 v)
CS5305 http://onsemi.com 13 typical performance characteristics figure 10. dac output for vid = 00110 (1.700 v) figure 11. gate phase delay vs. temperature figure 12. gate rise and fall time vs. temperature figure 13. pwm comparator minimum pulse width vs. temperature figure 14. pwm transient response time vs. temperature figure 15. current sense amp channel start ? up offset voltage vs. temperature 0 dac output (v) 1.572 temperature ( c) 1.574 1.576 1.578 1.580 1.582 25 50 75 100 125 0 phase delay (degrees) 100 temperature ( c) 110 115 120 125 130 135 140 25 50 75 100 125 105 gate3 to gate1 gate2 to gate3 gate1 to gate2 0 rise/fall times (ns) 4.0 temperature ( c) 6.0 8.0 10 25 50 75 100 125 rise time fall time 0 minimum pulse width (ns) 70 temperature ( c) 75 80 85 90 95 25 50 75 100 125 0 transient response time (ns) 80 temperature ( c) 100 120 140 160 25 50 75 100 125 0 start ? up offset voltage (mv) 400 temperature ( c) 450 500 550 600 650 700 25 50 75 100 125 c load = 100 pf
CS5305 http://onsemi.com 14 typical performance characteristics figure 16. current sense amplifier gain vs. temperature figure 17. v fb bias current vs. temperature for r osc = 32.4 k figure 18. v drp source current vs. temperature figure 19. v drp to dac output offset voltage vs. temperature figure 20. share bus voltages vs. temperature figure 21. i out output current vs. temperature 0 current sense gain (v/v) 1.0 temperature ( c) 1.5 2.0 2.5 3.0 3.5 4.0 25 50 75 100 125 current sense amp to v drp gain current sense amp to oscetgain current sense amp to pwm comparator gain 0 v fb bias current ( a) 10.55 temperature ( c) 10.60 10.65 10.70 10.75 10.80 10.85 10.90 25 50 75 100 125 v(v fb ) = 1.9 v v(v fb ) = 1.0 v 0 v drp source current (ma) 6.0 temperature ( c) 6.5 7.0 7.5 8.0 8.5 25 50 75 100 125 0 v drp to dac output offset voltage (mv) 0.8 temperature ( c) 1.0 1.2 1.4 1.6 25 50 75 100 125 0 share bus voltages (v) 1.5 temperature ( c) 2.0 2.5 3.0 3.5 4.0 4.5 25 50 75 100 125 share fault output voltage share fault threshold share max output voltage share ok threshold share full load accuracy 0 i out output current (ma) 13.0 temperature ( c) 13.5 14.0 14.5 15.0 15.5 16.0 25 50 75 100 125
CS5305 http://onsemi.com 15 typical performance characteristics figure 22. share offset voltage vs. temperature figure 23. i out to s comp transconductance vs. temperature figure 24. power good lower threshold voltage vs. temperature figure 25. power good upper threshold voltage vs. temperature figure 26. power good delay vs. temperature 0 share offset voltage (mv) 38 temperature ( c) 39 40 41 42 43 44 45 25 50 75 100 125 0 i out to s comp transconductance ( a/v) 15 temperature ( c) 20 25 30 35 40 45 25 50 75 100 125 0 percentage change over nominal (%) ? 0.06 temperature ( c) ? 0.04 ? 0.02 0 0.02 0.04 0.06 25 50 75 100 125 vid = 11110 vid = 01110 vid = 00000 0 power good upper threshold voltage (v) 1.975 temperature ( c) 1.985 1.990 1.995 2.000 2.005 2.010 2.015 25 50 75 100 125 1.980 0 power good delay ( s) 210 temperature ( c) 215 220 225 230 235 25 50 75 100 125
CS5305 http://onsemi.com 16 applications information theory of operation fixed frequency multi ? phase control multi ? phase cpu controllers include the necessary control circuitry to implement several buck converters in parallel. these converters are configured to turn on at different times. this allows much higher output current than could be provided by a single converter. the apparent ripple frequency is increased and so output current can ramp up or down faster than a single converter with the same value of output inductor. heat is also spread among multiple components. the CS5305 uses a fixed frequency, enhanced v 2 architecture. each phase is delayed by approximately 120 from the previous phase. the ga te output for each channel changes to a logic high at the beginning of its oscillator cycle. inductor current ramps up until the combination of the current sense signal and the output ripple trip the pwm comparator, at which time the gate output changes to a logic low. once low, the gate output remains low until the next oscillator cycle begins, and the control loop will not respond until that time. the enhanced v 2 control loop will respond to line and load transients while the gate output is high. enhanced v 2 control will respond within the off time of the converter. pwm comp + ? offset cs amp + ? error amp ? + csx cs ref comp v fb r csx c csx c comp l esr l switch v out node figure 27. the enhanced v 2 architecture measures and adjusts current in each phase. an additional input (csx pin) provides current information for each output phase to the control loop as shown in figure 27. inductor current is measured across capacitor ccsx. the voltage across this capacitor is equal to the product of the output current and the inductor esr if these components are chosen such that (ccsx)(rcsx) = (l)/esr l . this signal is buffered by the current sense amplifier (unity gain in the CS5305) and summed with an of fset voltage before it is presented as input to non ? inverting input of the pwm comparator. inductor current provides the pwm ramp. as inductor current increases, the voltage at the positive input to the pwm comparator rises and terminates the pwm cycle. if the inductor starts the next cycle with higher current, the pwm cycle terminates earlier, thus providing negative feedback. a csx input is provided for each channel, but the cs ref , v fb and comp inputs are common to all phases. current sharing between phases is accomplished by referencing all phases to the same error amplifier. any phase with a larger current signal will turn off earlier than the channels with a lower current signal. including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. in the absence of any load current, the comp pin voltage will be equal to the sum of the output voltage, the offset voltage and half of the steady ? state ramp voltage. (at no load, the output ripple current?s positive and negative contributions are equal, and the dc averaged voltage is equal to half the ripple voltage.) if the comp pin is held steady and the inductor current is forced to change, the output voltage will also change. in a closed ? loop situation, changing the inductor current will force the comp voltage to change so the output voltage can remain the same. the change in comp voltage depends on the scaling of the current feedback signal, and can be defined as: v comp ( esr l )( current sense gain )( i phase ) since the current sense gain for this loop is unity, this equation reduces to: v comp ( esr l )( i phase ) and so the single ? phase power stage output impedance is: v comp i phase esr l the CS5305 has three phases, so the total power stage output impedance is then esr l /3. lossless inductive current sensing current can be sensed across the inductor as shown in figure 27. the output inductor is designated l and the inductor?s equivalent series resistance is designated esr l . in the ideal case, the values of rcsx and ccsx are chosen such that (l/esr l ) = (rcsx)(ccsx). if this criterion is met, the current sense signal will have the same shape as the inductor cur rent, and the circuit can be analyzed as if a sense resistor with value equal to esr l was placed in series with the inductor. however, these components also determine the ramp signal that is used to prevent pulse skipping and duty cycle jitter. choosing (rcsx)(ccsx) < (l/esr l ) will result in the ac portion of the current sense signal being scaled more than the dc portion. this results in a larger ramp signal, but the current signal will overshoot during transients. this will affect transient response, adaptive voltage positioning and current limit. the comp pin voltage will overshoot along with the current signal in order to maintain the output voltage. the comp voltage will eventually find the correct level for regulation, but the error
CS5305 http://onsemi.com 17 will decay with the time constant (rcsx)(ccsx). the v drp voltage will also overshoot and response will be slowed, since the current signal is a component of that voltage. the single phase current limit will trip earlier since the current signal appears larger than it should be, and the module current limit will have a lower threshold for fast transients than it will for slow tr ansients. additional external components in the droop circuit and in the error amp compensation will correct this condition. details are provided in the data sheet section on choosing external components. adaptive voltage positioning adaptive voltage positioning is a technique used to reduce peak ? to ? peak output deviations during output current transients. the output voltage is set higher than nominal at light loads to reduce output voltage sag when load current is suddenly increased. similarly, output voltage is set lower than nominal at heavy loads to reduce overshoot when load current suddenly decreases. the CS5305 implements adaptive voltage positioning by placing a resistor divider between v drp and v out . the center tap of the divider connects to v fb . these resistors, along with two or three other external components, implement a lossless droop voltage function. past implementations of adaptive voltage positioning used a droop resistor. this resistor was placed in series between the regulation point of the output voltage and the load. increasing the current to the load caused the voltage at the load to droop below the regulation point. the amount of droop was equal to the change in current multiplied by the droop resistor value. this method was acceptable for low values of output current, where the droop resistor provided a minimal change in voltage without dissipating a great deal of power. higher output current levels and tighter droop voltage requirements in today?s microprocessors have rendered this droop resistor technique unusable. the lossless technique solves these problems. the avp function addresses dc and slow transient output voltage positioning. response during the first few hundreds of nanoseconds of a transient are addressed primarily by the power stage output impedance, and the esr and esl of the output filter. the ramp size and the error amplifier compensation control the transition between these two regions. if ramp size is too large or the error amp is too slow, there will be a long transition to the final voltage after a transient. this will be most apparent if the output capacitance is low. figure 28 shows how adaptive positioning works. the waveform labeled ?normal? shows output voltage for a converter without adaptive voltage positioning. the voltage sags when current steps up, returns to its nominal value and then overshoots when the current load is decreased. using a slow adaptive positioning circuit can actually worsen performance. the slow adaptive positioning waveform above shows the output voltage sag, but the voltage recovers to its initial value before the adaptive positioning circuit becomes active. when the load decreases, the overshoot causes the output voltage to exceed the upper limit. the fast adaptive positioning waveform shows how avp can reduce transient voltage requirements by about one half compared to a ?normal? converter. adaptive positioning adaptive positioning normal fast slow limits figure 28. adaptive positioning current limit the CS5305 features two separate current limit circuits. first, the per ? phase current limit terminates topside switch conduction in a phase if the voltage between any csx pin and cs ref exceeds a typical value of 90 mv. this provides fast peak current protection for individual phases. in addition, the output current signals for all three phases are summed and filtered to provide an average module current signal. this signal is compared to a voltage that is user ? programmable. if this volta ge is exceeded, the fault latch is set and the comp capacitor is discharged by a 5 a current sink until the comp vo ltage falls below 0.2 v. the soft ? start cycle begins when this threshold is reached, and the converter will operate in hiccup ? mode until the overcurrent condition is cleared. error amplifier the CS5305 uses the enhanced v 2 control method to offer the fastest and most accurate regulation available. one of the features of this control method is ease of error amplifier compensation. a single capacitor placed from the comp pin to ground is suf ficient to adequately stabilize the error amplifier.
CS5305 http://onsemi.com 18 200 160 120 80 40 100 60 20 ? 20 ? 60 v db (vy2) in db(volts) phase(vy2) in deg 100 1.0 k 10 k 100 k frequency in hz 2 21 1 figure 29. error amplifier frequency response with no compensation 80 40 0 ? 40 ? 80 170 150 130 110 90 phase(vy1) in deg +result of v db (vy1) 10 100 1.0 k 10 k frequency in hz figure 30. error amplifier frequency response with 0.1 f capacitor 2 21 1 soft start/hiccup mode at initial power ? up, the comp voltage is zero. the total comp capacitance will begin to charge with a typical current of 30 a. (there may be more than one capacitor connected between comp and ground depending on the adaptive voltage positioning compensation.) all gate outputs are held low until the comp voltage reaches 0.6 v. once this threshold is reached, the gate outputs are released to operate normally. in hiccup ? mode, this will result in gate pulses being generated until the module overcurrent condition reoccurs, and the discharge/soft start cycle begins anew. undervoltage lockout the CS5305 includes an under ? voltage lockout circuit. this circuit disables the output drivers until v cc applied to the ic reaches a typical value of 9 v. the gate outputs are disabled when v cc drops below 8 v typical. enable the CS5305 has a dedicated enable pin, in accordance with the latest vrm specifications. this pin is internally pulled up to a 3.3 v rail through a blocking diode and a 50 k resistor. the blocking diode allows external pull up to a bias voltage greater than 3.3 v but below 13 v. fault protection logic the CS5305 is equipped with sophisticated fault ? detection and protection circuitry to ensure proper operation in a paralleled vrm environment. in such an environment, any one of several distinct failures could not only destroy the vrm that sees the fault, but also those vrms that are connected in parallel with the faulted vrm. table 1 describes the fault logic circuitry, shown below in figure 31. vid fault enable uvlo s r comp dischg?d? s r ovc local fault latch share fault latch share bus high? fault share fault figure 31. fault logic circuitry
CS5305 http://onsemi.com 19 table 1. description of fault logic fault modes stop switching drvon level pwrgd level share controller off comp pin characteristics reset method under voltage lockout yes low low via power good window comparator n/a no ? 5.0 a comp < 0.2 v vid = 1 1111 yes low low via power good window comparator n/a no ? 5.0 a comp < 0.2 v enable low yes low low n/a no ? 5.0 a comp < 0.2 v module over current (set by ocset) yes low low via power good window comparator > 3.8 v no ? 5.0 a comp < 0.2 v phase over current (0.33 v limit) terminate pulse high n/a n/a no not affected not affected external share fault (share > 3.8 v) yes low low via power good window comparator n/a no ? 2.5 ma remove external 3.8 v from share pwrgds out of win- dow range no high low n/a no not affected not affected gate outputs the CS5305 is designed to operate with external gate drivers. accordingly, the gate outputs are capable of driving a 100 pf load with typical rise and fall time of 15 ns. drvon when the CS5305 is used with drvon ? compatible gate drivers, the ability of the system to survive a fault in a paralleled environment is greatly increased. the drvon signal tells the gate drivers to shut off both fets while entering a fault condition. this action takes the faulted vrm ?out of the picture,? allowing the system to operate until the bad module can be replaced. digital to analog converter (dac) the output voltage of the CS5305 module is set by means of a 5 ? bit, 1% dac. the dac pins are internally pulled up to a 3.3 v rail through a blocking diode and a set of 50 k resistors. the blocking diode allows external pull up to a bias voltage greater than 3.3 v and less than 13 v. the output of the dac is described in the electrical characteristics section of the datasheet. these outputs are consistent with the latest vrm specifications. the dac produces an output voltage 125 mv lower than the vid code would indicate in order to produce an accurate pwrgd output. the relationship between the vid code and the dac code is described by figure 32 shown below. the shaded area shows the acceptable range of output voltages. in order to produce a workable vrm using the CS5305, the designer is expected to use avp as described earlier to position the output voltage above the dac output, resulting in an output voltage somewhere in the middle of the acceptable range. 125 mv vid code dac output max v out min v out v out figure 32. vrm 9.0 output voltage accuracy requirements the latest vrm specifications require a module to turn its output off in the event of a 1 1111 vid code. when the dac sees such a code, the gate pins stop switching and go low. the drvon signal also goes low, which turns off all fets on the module if the fet driver has an enable input. this condition is described in table 1. pwrgd according to the latest vrm specifications, the pwrgd signal is to be asserted when the output voltage is within a window defined by the vid code, as shown in figure 33.
CS5305 http://onsemi.com 20 pwrgd ??? ??? ??? ??? ??? ??? ??? ??? (vid ? 125 mv) 1.975 v v out high low pwrgd ? 2.6% +2.6% ? 5.0% +5.0% figure 33. pwrgd assertion window low pwrgd low pwrgd high in addition, certain fault modes must cause pwrgd to go low to signal the system board that a vrm fault has occurred. in that sense, the pwrgd signal operates as a ?vrm bad? signal. these fault modes, as shown in t able 1 above, are enabl low and csx out of window. when the enabl pin is pulled low, pwrgd is pulled low to indicate that the vrm is off. drvon is pulled low to turn both fets off if the fet driver has an enable input. the logic circuitry inside the chip sets pwrgd low only after a delay period has been passed. a ?power bad? event does not cause pwrgd to go low unless it is sustained through the delay time, typically 200 s. if the anomaly disappears before the end of the delay, the pwrgd output will never be set low. in order to use the pwrgd pin as specified, the user is advised to connect external resistors as necessary to limit the current into this pin to 4 ma or less. share bus vrm 9.x specifications require that a single ? wire share bus be provided from each module. this bus allows output current information to be communicated between modules such that the total load current is shared equally by each module. the CS5305 employs a proprietary share algorithm called direct duty cycle control. a block diagram is provided in figure 34. pwm latch reset set gatex gate driver + ? pwm comparator + ? + ? share bus amp ? + 30 mv + ? share adjust amp share current sense amp from oscillator comp scomp share i out i fb 3.7 current sense input 3.3 v v out + v offset + 1 current sense input figure 34. direct duty cycle control utilizes a master ? slave approach to current sharing. at any given current load, one module will have a higher share bus voltage than the other modules. this module acts as the master. it conveys output current information to the other modules via the share bus. this information is buffered and provided to the pwm comparators, thus directly controlling duty cycle for the slave modules. the share current sense amplifier allows the user to customize the share bus transconductance. current sense information is provided to the non ? inverting input from the 3.7 current sense amplifier from each phase. this provides a representation of the total module current. an external resistor divider between i out and ground, center ? tapped at i fb programs the share bus voltage for a particular current level. the share bus amplifier serves as a buffer and places the i out voltage on the share pin. note there is a diode in the schematic between the share bus amplifier and the share pin. this is an ?ideal? diode, and indicates that the share bus amplifier does not have current sink capability. this allows the share bus to be driven by the module with the highest share bus voltage. a 30 mv offset voltage provides noise immunity to ensure that any given module does not cycle between master and slave in a random fashion. it also guarantees that the master module is not driving duty cycle from the share bus. for the master module, the i out and share voltages will be equal. in this case, the 30 mv of fset holds the share adjust amplifier inactive, and the pwm channel is controlled in the normal manner. the offset voltage results in a current error between the master and slave modules, but this error is small compared to the current share tolerance found in the vrm 9.x specifications. the share adjust amplifier takes the share bus voltage and directly drives the pwm comparators of all slave modules as previously described. the scomp pin provides a
CS5305 http://onsemi.com 21 connection point for a compensation capacitor for the share adjust amplifier. choosing external components for the CS5305 r ocset and r osc the r osc lead of the CS5305 provides a fixed 1 v reference to the user. a resistive divider is connected from r osc to ground as shown in figure 35. the center tap of the divider is connected to the ocset lead. the total resistance from the r osc lead to ground programs the oscillator frequency for the converter according to the chart in figure 36. the resistive divider also sets a voltage on the ocset lead. this voltage programs the module overcurrent trip point. the module overcurrent comparator, or oc comparator, uses the ocset lead voltage as the reference against which the module output current signal is compared. the output current of each phase is given as (v csx ? v csref ) divided by the equivalent series resistance of the inductor. the voltage information (v csx ? v csref ) is gained up by a factor of 3.7 and summed for all three phases at the non ? inverting input of the oc comparator. the fault latch is set if the module overcurrent limit is exceeded. this results in ?hiccup ? mode? operation until the overcurrent condition is cleared. r1 r ocset r osc ocset r osc = r1 + r ocset figure 35. figure 36. f osc vs. r1 + r ocset f osc (khz) 100 r1 + r oscset (k ) 300 400 500 600 700 800 900 200 10 20 30 40 50 60 70 additionally, the total value of resistance between r osc and ground also programs the v fb pin bias current. v fb bias current is equal to 0.333 v divided by the total resistance from r osc to ground. this current is used to generate the droop function in the adaptive voltage positioning circuitry and is discussed further in that section. current sense components current sense components are chosen for two reasons. first, the value of r csx and c csx should be chosen to meet the criterion: ( r csx )( c csx ) ( l ) ( esr l ) where l is the inductor value and esr l is the inductor equivalent series resistance. meeting this criterion will ensure that the module overcurrent limit is not exceeded during current transients. second, r csx and c csx should be chosen to add a small amount of ramp to the system. this will provide stable, jitter ? free operation. the amount of ramp voltage required depends on several factors: supply voltage, output voltage (dac code), switching frequency and board layout all affect the amount of artificial ramp required to some degree. the power supply designer should be aware that choosing the value of artificial ramp is a trade ? off. as artificial ramp amplitude increases, the system becomes less prone to duty cycle jitter, but transient response will suffer. adding 20 mv of artificial ramp is a good compromise and can be used to start design. the current sense ramp is generated from the square wave obtained at the switching node of each phase by using an rc filter. the rc filter components for the csx leads should be chosen to satisfy the following formula: r csx c csx ( v out ) 1 v out v cc ( f osc )( v ramp ) choose a conv enient standard value for c csx and solve for the value of r csx . each of the three output phases requires its own rc combination. an rc filter is also required for the cs ref connection. this filter may use the same value of capacitance identified for the cs1, cs2 and cs3 leads, but the value of resistance should be one third that of r csx : r csref r csx 3 this change is necessary to compensate for the dif ference in bias current between the cs ref lead and each csx lead. the schematic in figure 37 shows the connection of these components. r csx c csx c csref r csref = r csx /3 cs ref v out switch node x l1 csx figure 37.
CS5305 http://onsemi.com 22 share bus components five external components are required to implement the module ? to ? module current share function. these components set the current sense load line, provide the share bus pull ? down and compensate the share adjust amplifier. the share current sense amplifier monitors the total module current and provides a dc voltage output proportional to that current. the share sense amplifier gain is programmable and allows the user to set the share bus transconductance. it is important that all modules in a system have a share current load line that approximates that of all the other modules to ensure accurate module ? to ? module current sharing. let us arbitrarily set the share bus maximum voltage for full load at 2 v. if a module is designed to provide 81 a at full load, the module share transconductance should be 81 a/2 v or 40.5 a/v. two resistors and a capacitor set the share current sense amplifier gain. the resistors set the dc gain while the capacitor provides a zero to minimize errors due to noise. the total module current is measured as described in the section dealing with the ocset current limit function. that is, each phase within a module generates a voltage between the csx and cs ref leads that is proportional to the current flow in the output inductor and the inductor?s esr: v csx v csref ( i l )( esr l ) this signal is amplified by a factor of 3.7 for each phase and then summed for all three phases. this signal is provided as input to the share current sense amplifier. if we assume that all three phases are sharing current equally within a single module, the input to the share current sense amplifier can be expressed as: v in ( sense ) 11.1 ( v csx v csref ) 11.1 ( i l )( esr l ) 3.7 ( i out )( esr l ) if we set i l equal to the maximum per phase current at full load, and if we know the value of esr for our inductors, we can calculate the required sh are current sense amplifier gain as: a v ( sharesense ) share maximimum voltage v in ( sense ) as an example, let us again consider the case for a module providing full load current of 81 a. each output phase is conducting 27 a. if we assume esr = 1.5 m then input to the share current sense amplifier is (11.1)(27 a)(1.5 m ) = 0.45 v. the required share current sense amplifier gain is then 2 v/0.45 v = 4.44. + ? r iout c iout i fb r ifb v in(sense) i out figure 38. from the schematic in figure 38, we derive the dc gain as: a v ( sharesense ) 4.44 r iout r ifb 1 this specifies that r iout should be 3.44 times greater than r ifb . another important consideration is the type of resistor selected for r ifb . the thermal performance of r ifb must match that of whatever sense element is being used to monitor module current. inductive sensing has been shown to be reasonably accurate, but copper?s thermal coefficient of resistivity is approximately +4000 parts per million per c (0.4% per c). in order to maintain accurate control of the share bus over temperature, r ifb must have a similar thermal coefficient. this requires a positive temperature coefficient element such as the koa ? speer lt73. if a standard sense resistor is used in series be tween the inductor and the load, there is no need to use special resistors for sensing, but efficiency will suffer due to power dissipation in the sense resistor. as regards the value of c iout , it should be noted that the complete transfer function for the share current sense amplifier in figure 38 is: a v ( sharesense ) r iout r ifb ( 1 sc iout r iout ) 1 c iout causes the gain for high frequency noise to decrease, thus quieting the share bus. the share resistor provides a passive pull ? down on the share lead. this allows the share bus voltage to be pulled all the way down to ground. the share resistor is selected to satisfy a number of criteria. first, the resistor cannot be made too small. the share lead source current is guaranteed to be above 1 ma and must be capable of driving the share lead voltage to 3 v. the share bus of one module serves as master to all and drives the total resistance of all share leads. thus, the total impedance of all share resistors should be made greater than or equal to 3 k . that is,
CS5305 http://onsemi.com 23 3k r share n where n is the maximum numb er of modules that can be placed in parallel as defined by the designer. as an example, if ten is the maxi mum number of modules that may be paralleled, then the minimum value of r share should be 30 k . the share resistor should also not be made too lar ge, since this is the only pull ? down on the share lead. transient response of the share bus is limited by the rc time constant of the share resistance and any parasitic capacitance found on the share line between modules. droop components the CS5305 offers adaptive voltage positioning. this feature allows the output voltage to be set at different levels according to the amount of current being provided by the module. the output voltage is somewhat higher than nominal under no load or light load conditions and somewhat lower than nominal under heavy load conditions. both set points must fall within the power good window. the adaptive positioning allows for overshoot and undershoot conditions that occur during load current transients and results in a reduction in the peak ? to ? peak v out voltage excursion during load current transients. three components are required to implement dc adaptive voltage positioning. resistor r fb is connected between the module v out(sense)+ lead and the v fb lead. resistor r drp is connected between the v drp lead and v fb lead. resistor r vsense is connected between the v out(sense)+ lead and the module v out lead. these connections are shown in figure 39. figure 39. r drp r fb r vsense v out v out(sense)+ v fb v drp the first step in choosing these components is to select the appropriate no ? load and full ? load output voltage set points for the particular dac code being used. additionally, the values of r osc and r ocset should be known, as should esr of the output inductors and the full ? load output current.
CS5305 http://onsemi.com 24 figure 40. + ? r fb v drp v(dac) v out output stage r drp i(v fb ) v fb as was previously noted, the total value of resistance between the r osc pin and ground sets the v fb lead bias current according to: i ( v fb ) 0.333 v ( r osc r ocset ) referring to figure 40, the v drp lead voltage is equal to the dac voltage plus the current sense information. under no load conditions, the v drp and v fb pin voltages are equal, and the entire v fb bias current flows between v out(sense)+ and v fb through r fb . because the v fb bias current sinks into v fb , the output voltage is forced to be higher than the dac voltage, and so the value of r fb can be calculated as: r fb ( v out no load set point v dac ) i ( v fb ) with r fb chosen, we can now se lect the value of r drp . if we again refer to figure 40, we can use kirchoff?s current law at the v fb node to find that the value of r drp is defined as: r drp ( full load current )( 3.7 )( esr l )( r fb ) ( r fb )( i ( v fb )) v ( dac ) v out full load set point r vsense is used to ensure that a connection between v out and v out(sense) always exists. this ensures that the module will operate correctly in the event that the v out(sense) connection is broken. the module ? to ? load interface and the number of modules placed in parallel determine the value of r vsense . the CS5305 is specified to operate correctly with up to 55 mv dropped across the module connector. it is assumed that the maximum current allowed to flow in this connection to the load is 1 ma. r vsense 55 mv (1 ma n) where: n = the number of modules to be paralleled. if four modules are to be paralleled, each contributes a maximum of 250 a to this connection, and so r vsense = 55 mv/250 a = 220 . this component is placed to ensure the vrm module will regulate correctly if the module v out(sense)+ connection to the load is opened. the transient droop performance should be checked next. performance should be verified using the transient test tool typically provided in a microprocessor development kit. true transient performance can be masked even at test frequencies as low as 2 khz. it should be possible to modify the test tool so a function generator can drive it. using lower frequency (approximately 100 hz) and lower duty cycle (10%) allow the designer to better observe the true settling behavior of the vrm module. it may be necessary to add some filtering components to the droop voltage divider. these components cause the ac and dc gain from the current sense circuitry to match and allow the user to tailor the droop output voltage performance. there are two methods for tuning droop performance. the first is illustrated in figure 41. in this case, capacitors c drp and c fb are placed in parallel with r drp and r fb . a third capacitor c drcmp is connected between the comp and v drp leads. the first two capacitors correct any gain errors introduced in the selection of current sense components rcsx and ccsx. v alues for these components are defined as: c fb l (( r fb )( esr l )) and c drp (( c csx )( r csx )) r drp the capacitor between v drp and comp allows the user to fine ? tune the transition between ?fast? avp and the slower positioning set by resistors r drp and r fb . this capacitor may or may not be required and is empirically chosen based on the fine ? tuning procedure described below. a value of 1 nf is recommended as an initial value. figure 41. r drp r fb r vsense v out v out(sense)+ v fb v drp c drp c fb c drcmp comp set up the circuit to be tested with a dvm and oscilloscope to the output. have the scope set to dc input and set its offset so a resolution of at least 100 mv/div is used and the output is visible on the screen. using a dvm, measure the output voltage with no load. if this value differs from the expected value, adjust r fb until the nominal value is reached. once this is set, mark this dc level on the scope with a cursor. next, measure the output voltage with full dc load. if this value deviates from the expected value, adjust r drp until the nominal value is reached. once this is set, mark this dc level on the scope with another cursor.
CS5305 http://onsemi.com 25 figure 42. no load cursor marker full load cursor marker trace 1: optimal trace 2: c fb too large trace 3: c fb too small trace 4: c drcmp too large, c comp too small trace 5: c drcmp too small, c comp too large using the transient test tool, set up a current load step from low current (1 a) to maximum load at the slew rate being designed for. set the current step at about 100 hz with a duty cycle of 10%. converter response should be similar to that shown in figure 42. next, determine if there is a ?bump? (trace 4 or trace 5) in the output. adjust c comp and c drcmp to flatten out this bump. if the ?bump? is negative (trace 5), make c drcmp slightly larger and c comp slightly smaller. if you see a positive ?bump? (trace 4), make c drcmp slightly smaller and c comp slightly larger. if performance is better without c drcmp , just make c1 larger. once the bump is removed, look to see if the ?pulse step? magnitude is larger or smaller than the dc level (trace 2 or trace 3). make c fb slightly lar ger if the ac gain (trace 3) is too large or slightly smaller if the ac gain (trace 2) is too small. once the output response resembles the ?optimal? trace (trace 1), the controller has been optimized for the design from a static and dynamic response. if the output appears to be jittering slightly prior to optimizing transient response, make the previous adjustments first, since they may solve the problem. if the problem persists, decreasing the value of rcsx across the inductor will increase ramp amplitude, and jitter performance should improve with increased ramp. the second method uses a capacitor to ?square up? the comp waveform and a series resistor and capacitor to tune the v drp waveform. these components are chosen empirically based on observations of comp and v drp performance. first, set the test tool for a load current transient from no load (1 a) to full load and observe the comp waveform. the comp waveform should ideally be flat, or at worst decrease slightly during a current increase transient. the principle at work here is that the increase in current sense information will generate a voltage that should exactly cancel the droop voltage, and thus the comp capacitor voltage should not change. in reality, it is unlikely that every manufactured module can be built to perfectly compensate the droop voltage, and so the comp voltage should exhibit a small amplitude square wave during transient conditions. if the comp voltage is decreasing gradually, the current sense information is too small to fully compensate for the droop voltage, and the designer should add a capacitor between v out and comp. this capacitor is chosen empirically, with 1 nf a good starting point. this capacitor will pull the comp pin down initially and ?square up? the comp waveform as shown in figure 43. figure 43. current transient comp ideal waveform comp uncorrected waveform v out uncorrected waveform comp corrected waveform v out corrected waveform
CS5305 http://onsemi.com 26 in a similar manner, if the current information is too large, the comp voltage will rise to compensate. again, a square wave is preferable to a slow change in the comp voltage, and placing a capacitor between v drp and comp will ?square up? the comp waveform as shown in figure 44. figure 44. current transient comp ideal waveform comp uncorrected waveform v out uncorrected waveform comp corrected waveform v out corrected waveform once the comp waveform has been squared up, it is necessary to check the v drp waveform. the v drp waveform is dependent on the choice of ramp components. if these components have been chosen such that (r csx )(c csx ) = l / esr l , the v drp waveform should be a square wave that matc hes the current step. at this point, the v out waveform should also be a square wave and transient performance should be optimized. if (r csx )(c csx ) < l / esr l , the v drp waveform will be faster than current step. the v drp voltage will exhibit a fast rise followed by an exponential droop down to a dc level, as shown in figure 45. this waveform has the effect of telling the system that transient current signals are larger than the true current. response will be slowed, and v out will overshoot until the error amplifier ?catches up?. in this case, it is desirable to push the v fb pin down, so that comp voltage is forced up and duty cycle is reduced slightly. this is done by placing a series rc filter across resistor r fb . figure 45. current step v drp (r csx )(c csx ) < l/esr l if (r csx )(c csx ) > l / esr l , the v drp waveform will be slower than the current step. v drp will exhibit an initial spike, but the voltage will then exponentially rise toward its correct dc level, as shown in figure 46. this waveform effectively tells the system that the current signal is smaller than the true current, and response will be faster than optimal. v out will then undershoot. in this case, forcing v fb up so comp voltage decreases results in increasing output duty cycle. the series rc filter is now located in parallel with r drp . figure 46. current step v drp (r csx )(c csx ) > l/esr l these components are chosen empirically. the fastest way to optimize the design is to start with a 1 nf capacitor and a 500 k potentiometer and ?dial in? performance. error amplifier compensation error amplifier compensation is very simple using the enhanced v 2 control architecture. a single 0.1 f capacitor from the comp lead to ground is usually sufficient. as an alternative, a resistor and capacitor in series between comp and ground may improve output voltage positioning during current transients. the resistance will speed up the ef fective slew rate of the error amplifier output. the comp capacitor also provides soft start and hiccup ? mode timing. at start ? up, the comp capacitance must charge from ground through a typical channel start ? up offset of 0.6 v before the gate outputs are allowed to begin switching. the comp capacitance includes both the comp capacitor and any droop compensation capacitance that may be connected to the comp pin. the typical soft start time can then be approximated as: t soft ? start ( ms ) 20 c comp(total) ( f ) hiccup timing has a similar equation. during hiccup ? mode, the comp voltage traverses between the fault reset threshold (approximately 0.2 v) and the channel start ? up offset voltage. when the fault circuitry becomes active, the comp capacitor is discharged with a 5 a current until the fault reset threshold is reached. the time this initial discharge takes is variable depending on the comp voltage when the fault occurred. once the reset threshold is reached, the comp capacitor is charged with the 30 a current until the start ? up offset voltage is reached. the gate outputs will begin to pulse, quickly ramping the inductor current. the fault circuitry can then re ? detect the fault condition some number of gate pulses later if it is still present. thus, the period of the fault hiccup mode is approximately defined as: t hiccup ( ms ) 93.3 c comp(total) ( f ) period is only approximately defined since the number of gate pulses between restart and redetection of a fault condition is unpredictable.
CS5305 http://onsemi.com 27 inductors there are many factors to consider when choosing the output inductors. maximum load current, core and winding losses, ripple current, short circuit current, saturation characteristics, component height and cost are all variables that the designer should consider. however, the most important consideration in designing for the vrm 9.x specifications may be the effect inductor value has on transient response. the amount of overshoot or undershoot exhibited during a current transient is defined as the product of the current step and the output filter capacitor esr. to some degree, adaptive voltage positioning is used to ?pre ? position? the output voltage so the voltage step during a current transient will not cause the output voltage to exceed the power good window. however, adaptive positioning will not completely eliminate the overshoot or undershoot conditions, and choosing the inductor value appropriately can minimize the amount of energy that must be transferred from the inductor to the capacitor or vice ? versa. in the subsequent paragraphs, we will determine the minimum value of inductance required for our system and consider the trade ? off of ripple current vs. transient response. in order to choose the minimum value of inductance, input voltage, output voltage and output current must be known. most computer applications use reasonably well regulated bulk power supplies so that, while the equations below specify v in(max) or v in(min) , it is possible to use the nominal value of v in in these calculations with little error. current in the inductor while operating in the continuous current mode is defined as the load current plus ripple current. i l i load i ripple the ripple current waveform is triangular, and the current is a function of voltage across the inductor, switch fet on ? time and the inductor value. fet on ? time can be defined as the product of duty cycle and switch frequency, and duty cycle can be defined as a ratio of v out to v in . thus, i ripple ( v in v out ) v out ( f osc )( l )( v in ) peak inductor current is defined as the load current plus half of the peak current. peak current must be less than the maximum rated fet switch current, and must also be less than the inductor saturation current. thus, the maximum output current for a single phase can be defined as: i out(max) i switch(max) v in(max) v out v out 2 f osc l v in(max) since the maximum output current must be less than the maximum switch current, the minimum inductance required for a single phase can be determined. l (min) ( v in(min) v out ) v out ( f osc )( i switch(max) )( v in(min) ) this equation identifies the value of inductor that will provide the full rated switch current as inductor ripple current, and will usually result in inefficient system operation. the system will sink current away from the load during some portion of the duty cycle unless load current is greater than half of the rated switch current. some value larger than the minimum inductance must be used to ensure the converter does not sink current. choosing larger values of inductor will reduce the ripple current, and inductor value can be designed to accommodate a particular value of ripple current by replacing i switch(max) with a desired value of i ripple : l (ripple) ( v in(min) v out ) v out ( f osc )( i ripple )( v in(min) ) however, reducing the ripple current will cause transient response times to increase. the response times for both increasing and decreasing current steps are shown below. t response(increasing) ( l )( i out ) ( v in v out ) t response(decreasing) ( l )( i out ) ( v out ) inductor value selection also depends on how much output ripple voltage the system can tolerate. output ripple voltage is defined as the product of the output ripple current and the output filter capacitor esr. however, since the CS5305 has three paralleled phases, the net effect is that the switching frequency as seen by the output capacitance is tripled relative to the CS5305 operating freque ncy. this is because each phase switches in sequence an d the ripple currents in each phase are superimposed on the output capacitance. this is illustrated graphically in figures 45 and 46. thus, output ripple voltage can be calculated as: v ripple esr c i ripple esr c v in v out v out 3 f osc l v in it is also important to note that the maximum value of inductor esr is limited by the single ? phase pulse ? by ? pulse current limit. the specified minimum value for this parameter is 80 mv, so the maximum inductor esr is: esr l(max) ( in ohms ) ( 0.08 v ) single phase current limit value in amps
CS5305 http://onsemi.com 28 figure 47. phase 1 switch node phase 2 switch node phase 3 switch node superimposed phase inductor currents phase 1 current phase 2 current phase 3 current output ripple current finally, we should consider power dissipation in the output inductors. power dissipation is proportional to the square of inductor current: p d i 2 phase ) ( esr l ) the temperature rise of the inductor relative to the air surrounding it is defined as the product of power dissipation and thermal resistance to ambient: t(inductor) (ra)(p d) ra for an inductor designed to conduct 20 a to 30 a is approximately 45 c/w. the inductor temperature is given as: t(inductor) t(inductor) tambient output filter capacitors each microprocessor manufacturer specifies output filter capacitors for the motherboards. in addition, the designer may need to add some output capacitance on the vrm module. these added output capacitors would serve to reduce the noise floor and help ensure jitter ? free operation. if needed, one or two ceramic capacitors should be sufficient. they should have a 4 wvdc rating. large amounts of bulk capacitance placed on the vrm module are not useful, since the impedance of the vrm connector exists between the module and the load. low equivalent series resistance is important since output ripple voltage and response to output current transients are largely dependent on this parasitic parameter. v cc bypass filtering a small rc filter should be added between module v cc and the v cc input to the CS5305. a 10 resistor and a 0.1 f capacitor should be sufficient to ensure the controller ic does not operate erratically due to injected noise. module input filter capacitors the input filter capacitors for the vrm module provide a charge reservoir that minimizes supply voltage variations due to changes in current flowing through the switch fets. these capacitors must be chosen primarily for ripple current rating. figure 48. v in v out i in(ave) i rms(cin) c in control input l in l out c out consider the schematic shown in figure 48. the average current flowing in the input inductor l in for any given output current is: i in(ave) (i out )(v out v in ) (i out per phase)(n)(d) where: d = duty cycle, n = number of phases. input capacitor current is positive into the capacitor when the switch fets are off, and negative out of the capacitor when the switch fets are on. when the switches are off, i in(ave) flows into the capacitor. when the switches are on, capacitor current is equal to the per ? phase output current minus i in(ave) . if we ignore the small current variation due to the output ripple current, we can approximate the input capacitor current waveform as a square wave. we can then calculate the rms input capacitor ripple current: i rms(cin) i 2 in(ave) d
n
i out per phase i in(ave) 2 i 2 in(ave)
CS5305 http://onsemi.com 29 the input capacitance must be designed to conduct the worst case input ripple current. this will require several capacitors in parallel. in addition to the worst case current, attention must be paid to the capacitor manufacturer?s derating for operation over temperature. as an example, let us define the input capacitance for a 12 v to 1.7v conversion at 81 a, or 27 a per phase at an ambient temperature of 60 c. a droop voltage of 90 mv to 1.61 v and efficiency of 80% is assumed. average input current in the input filter inductor is: i in(ave) (27 a)(3 phases)(1.61 v 12 v) 80% 10.868 a input capacitor rms ripple current is then i in(rms) 10.868 2 1.61 v 12 v
3
27 a 10.868 a 2 10.868 a 2 13.347 a if we consider a sanyo sp series capacitor, the ripple current rating for a 16sps100m capacitor is 2820 ma at 100 khz and 45 c. the derating factor is 0.85 for operation up to 65 c, resulting in an effective ripple current rating of 2397 ma. we determine the number of input capacitors by dividing the ripple current by the per ? capacitor current rating: number of capacitors 13.347 a 2.397 a 5.52 a total of at least 6 capacitors in parallel must be used to meet the input capacitor ripple current requirements. output switch fets output switch fets must be chosen carefully, since their properties vary widely from manufacturer to manufacturer. the CS5305 system is designed assuming that a fet driver ic and n ? channel fets will be used. the fet characteristics of most concern are the gate charge/gate ? source threshold voltage, gate capacitance, on ? resistance, current rating and the thermal capability of the package. fet driver ics have a limited drive capability. if the switch fet has a high gate charge, the amount of time the fet stays in its ohmic region during the turn ? on and turn ? off transitions is larger than that of a low gate charge fet, with the result that the high gate charge fet will consume more power. similarly, a low on ? resistance fet will dissipate less power than will a higher on ? resistance fet at a given current. thus, low gate charge and low r ds(on) will result in higher module efficiency and will reduce heat being generated by the vrm module. it can be advantageous to use multiple switch fets to reduce power consumption. by placing a number of fets in parallel, the ef fective r ds(on) is reduced, thus reducing the ohmic power loss. however, placing fets in parallel increases the gate capacitance so that switching losses increase. as long as adding another parallel fet reduces the ohmic power loss more than the switching losses increase, there is some advantage to doing so. however, at some point the law of diminishing returns will take hold, and a mar ginal increase in efficiency may not be worth the board area required to add the extra fet. additionally, as more fets are used, the limited drive capability of the fet driver will have to charge a larger gate capacitance, resulting in increased gate voltage rise and fall times. this will affect the amount of time the fet operates in its ohmic region and will increase power dissipation. the following equations can be used to calculate power dissipation in the switch fets. for ohmic power losses due to r ds(on) : p on(top) ( r ds(on)(top) )( i rms(top) ) 2 ( n) ( number of topside fets per phase ) p on(bottom) r ds(on)(bottom) i rms(bottom) 2 n) number of bottom ? side fets per phase where: n = number of phases. note that r ds(on) increases with temperature. it is good practice to use the value of r ds(on) at the f et?s maximum junction temperature in the calculations shown above. i rms(top) i 2 pk (i pk )(i ripple ) d 3 i 2 ripple i rms(bottom) i 2 pk (i pk i ripple ) (1 d) 3 i 2 ripple i ripple (v in v out )(v out ) (f osc )(l)(v in ) i peak i load i ripple 2 i out 3 i ripple 2 where: d = duty cycle. for switching power losses: p d ncv 2 (f osc ) where: n = number of switch fets (either top or bottom) per phase, c = fet gate capacitance, v = maximum gate drive voltage (usually v cc ), f osc = switching frequency.
CS5305 http://onsemi.com 30 external fet driver the CS5305 is designed such that an external fet driver ic is required. the gate pin outputs are designed to drive a 100 pf load, and do not have suf ficient drive capability to directly drive the gates of switch fets. the gate outputs have a typical output high voltage of 2.5 v, so the turn ? on threshold of the fet driver should be approximately 2 v. the gate outputs are also phased such that the fet driver ic should turn on the topside n ? channel fet when the gate output goes high. the bottom ? side n ? channel fet should be on when the ga te output is below the fet driver ic turn ? on threshold. additionally, the CS5305 provides a signal called drvon that can be connected to the enable pin of fet drivers that offer an enable feature. if the fet driver?s enable input is high, the fet driver output is determined by the gate input, and the switch fets are driven according to the conditions described above. if the fet driver?s enable input is low, all switch fets are turned off and no current is conducted to the load. this drvon signal is a logic output from the CS5305. drvon goes high when all internal functions of the CS5305 are operating correctly and the ic is not in fault mode. a table of the drvon logic may be found in the theory of operation section. choosing a fet driver ic with an enable feature significantly improves system reliability, since a faulty module is essentially disconnected from the load. sgnd resistor the module ? to ? load interface and the number of modules placed in parallel determine the value of r sgnd . the CS5305 is specified to operate correctly with up to 55 mv dropped across the module connector. it is assumed that the maximum current allowed to flow in this connection to the load is 1 ma. r sgnd 55 mv (1 ma n) where: n = the number of vrm modules to be paralleled. if four modules are to be paralleled, each contributes a maximum of 250 a to this connection, and so, r sgnd 55 mv 250 a 220 this component is placed to ensure the vrm module will regulate correctly if the module v out(sense) ? connection to the load is opened. layout considerations enhanced v 2 performs best under dynamic load conditions if current ramp is kept small. however, this may lead to pulse ? width jitter or pulse skipping, particularly as the ambient noise level at the control circuit increases. this is a complicated design trade ? off that can not be mathematically characterized, and it is crucial to have a ?quiet? layout. following the design/layout guidelines below will provide the best system performance. refer to figure 50 for a layout example and to page 2 for the associated schematic. numbers in parentheses refer to ic pin numbers. component names refer to the reference designators for the application schematic. 1.noise across the pwm comparator inputs needs to be low or pulse width jitter will occur. referring to the block diagram, the cs ref pin (7) and the comp pin (14) present external information to the pwm comparator. any differential signal across these pins is expressed directly across the pwm comparator, which may cause pulse ? width jitter or pulse skipping. the solution is to provide a dedicated kelvin connection for sensing the vrm?s v out ? . the ic?s gnd pin (28) and comp capacitance need a dedicated sense line to v out ? , in effect making the ic and comp capacitance v out ? ground ? referenced. this is desirable since the fast feedback path through cs ref is connected to v out+ and is therefore also v out ? ground ? referenced. furthermore, a ground strip under the ic is desirable since the comp pin is located at the opposite corner of the ic from the gnd pin. this ground strip further reduces the ambient noise level of the CS5305 along with providing a good connection from comp return to gnd and v out ? . following this guideline will provide the most system improvement from a layout standpoint.
CS5305 http://onsemi.com 31 figure 49. v out+ sense v out ? sense v out+ sense v out ? sense or 2.differential noise across the pwm comparator can be further reduced if the v out+ and v out ? sense lines going to cs ref and gnd are paralleled to minimize loop area. v out+ ripple information provided to the pwm comparator via the cs ref pin needs to be symmetric for all three phases or poor current sharing between phases will occur. this can be accomplished by placing the v out+ and v out ? sense locations symmetrically with respect to the three output inductors. see figure 49. 3.frequency jitter could occur if the r osc pin (2) and ocset pin (1) components are not properly located. most layouts will have two resistors in series from r osc to gnd. keep these two components as close as possible to the ic and ensure a short ground connection to the ic gnd. provision for a small cap (1000 pf or less) from r osc to gnd can be placed although this is rarely needed. if the r osc capacitor value is too large, the r osc voltage reference will oscillate. 4.the v cc (23) bypass capacitor (0.1 f or greater) should be located as close as possible to the ic. this capacitor?s connection to gnd must be as short as possible. the most effective way to implement this tight component placement is to via the gate1, 2, 3 and drvon runs to internal layers right at the ic pins. 5.the switch nodes of all three phases must be sensed for inductive current sensing. care should be given to how this information is brought to the CS5305. switch node voltages should not be routed underneath or near the ic; however, the resistors in the rc filter of cs1, 2, 3 must be reasonably close to their associated capacitors so noise pick ? up on the cs1, 2, 3 pins is minimized. the best solution is to locate the rc filter capacitors close to the cs1, 2, 3 pins and to place the respective resistors off to the side of the ic. 6.a positive temperature coefficient thermistor can be used for r11 (see share bus section) to compensate for thermal variation in the inductor esr. this component should be placed near the one of the inductors to achieve the best thermal coupling, and so the best current sharing performance. remote placement with respect to the ic requires dedicated parallel runs of gnd and i fb to reduce share bus noise sensitivity. thermal considerations typically, the controller ic and the fet gate drivers do not dissipate significant amounts of power, and do not contribute greatly to module power dissipation. the main components of concern are the switch fets and the inductors. we have already reviewed the power calculations for these components, but we haven?t related them to a thermal solution. standards exist limiting the maximum vrm printed circuit board temperature (105 c is common), and thus power dissipation becomes a thermal consideration in addition to playing a part in overall module efficiency. power dissipation on the vrm results in heat radiation to the surrounding air. power dissipated by the components is conducted to the pcb. the pcb acts as a heat sink and provides a larger surface area for heat exchange to the surrounding air. the pcb temperature is dependent on total pcb power dissipation, the surface area of the pcb available to act as a heat si nk, the ambient temperature of the surrounding air and the thermal resistance to ambient of the pcb. while it is possible to model power dissipation on the pcb for efficiency purposes, it is very difficult to accurately model thermal performance. in particular, thermal resistance to ambient of the pcb varies widely. this parameter depends on many factors: board shape, size and material; copper weight; amount of exposed copper; insulating characteristics of the solder mask layers; air flow properties (amount, direction, pcb orientation to the airflow); and even whether a particular component is ?hidden? behind others. in reality, modeling pcb resistance to ambient is highly complex and the best way to guarantee thermal performance is to actually build prototypes and measure it directly.
CS5305 http://onsemi.com 32 figure 50. sample layout additional information several additional resources are available to make system design with the CS5305 a simpler task. the power supply designer is invited to obtain the following documents and files from on semiconductor. 1.and8045/d, ?enhanced v 2 multiphase smps for microprocessor.? this application note provides details on the theory of operation, selection of components, layout practices and thermal management strategies necessary to design power supplies with the CS5305 controller. 2.?excel spreadsheet method for choosing CS5305 external components?. this excel spreadsheet that can be used to generate a first ? pass schematic design for vrm 9.x designs based on user input, and is available from the factory. 3.?excel spreadsheet method for CS5305 power budget optimization?. this excel spreadsheet that can be used to calculate power dissipation in all the high ? power dissipation components (including metal traces). this allows the design to be optimized for power/thermal management, and is available from the factory.
CS5305 http://onsemi.com 33 package dimensions a1 1 15 14 28 b s a m 0.025 b s c m 0.25 b m seating plane a notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusions. 4. maximum mold protrusion 0.015 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.13 0.29 b 0.35 0.49 c 0.23 0.32 d 17.80 18.05 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 l 0.41 0.90 0 8 l c pin 1 ident a b d e h e 0.10 c so ? 28l dw suffix case 751f ? 05 issue f on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 CS5305/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative patents pending. v 2 is a trademark of switch power, inc.

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