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1 features ? one of a family of devices with user memories from 1 kbit to 1 mbit 1-kbit eeprom user memory ? four 32 x 8 (256 bit) zones ? self-timed write cycle (5 ms) ? single byte or 16-byte page write mode ? programmable access rights for each zone 2-kbit configuration zone ? 37-byte otp area for user-defined codes ? 160-byte area for user-defined keys and passwords low voltage operation: 2.7v to 5.5v dual protocol ? iso 7816-3 asynchronous t = 0 protocol ? synchronous two-wire protocol high security features ? 64-bit patented dynamic symetric mutual authentication protocol (under exclusive patent license from elva ) ? encrypted checksum ? stream encryption ? four key sets for authentication and encryption ? eight sets of two 24-bit passwords ? anti-tearing function ? voltage and frequency monitor high reliability ? endurance: 100,000 cycles ? data retention: 10 years ? esd protection: 4,000v min iso-compliant bond pad locations and package options table 1. pin configuration card module contact 8-lead soic, pdip or lap pad description iso module contact standard package pin vcc supply voltage c1 8 gnd ground c5 4 scl/clk serial clock input c3 6 sda/io serial data input/output c7 5 rst reset input c2 nc vcc = c1 rst = c2 scl/clk = c3 nc = c4 c5 = gnd c6 = nc c7 = sda/io c8 = nc 1 2 3 4 8 7 6 5 nc nc nc gnd vcc nc scl sda 8 x 32 x 4 cryptomemory ? at88sc0104c summary rev. 2021bs?smem?10/02 note: this is a summary document. a complete document is available under nda. for more in formation, please contact your local atmel sales office.
2 at88sc0104c 2021bs?smem?10/02 description the at88sc0104c member of the cryptomemory family is a high-performance secure memory providing 1 kbit of user memory with advanced security and cryptographic fea- tures built in. the user memory is divided into 4 zones, each of which may be individually set with different security access rights or combined together to provide space for 1 to 4 data files. the at88sc0104c provides high security, low cost and ease of implementation for smart card applicat ions without the need for a microprocessor operating system. the embedded cryptographic engine provides for a dynamic, sym- metric-mutual authentication between the device and host, as well as performing stream encryption for all data and passwords ex changed between the device and host. up to four unique key sets may be used for these operations. the at88sc0104c offers the ability to communicate with virtually any smart card reader using the asynchronous t = 0 protocol defined in iso 7816-3. for closed systems or applications using the device on a circuit board, the at88sc0104c will also communicate using a synchronous two-wire protocol at clock speeds up to 1.5 mhz. in this communication mode, up to 15 devices may be connected and individually addressed on the same serial data bus. the two-wire protocol may also be used for high-speed personalization of the device in card form. figure 1. block diagram pin descriptions supply voltage (v cc ) the v cc input is a 2.7v to 5.5v positive voltage supplied by the host. clock (scl/clk) in the asynchronous t = 0 protocol, the scl/clk input is used to provide the device with a carrier frequency f . the nominal length of one bit emitted on i/o is defined as an ?elementary time unit? (etu) and is equal to 372/ f . when the synchronous protocol is used, the scl/clk input is used to positive edge clock data into the device and negative edge clock data out of the device. serial data (sda/io) the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wired with any number of other open drain or open collector devices. an exter- nal pull-up resistor should be connected between sda and v cc . the value of this resistor and the system capacitance loading the sda bus will determine the rise time of sda. this rise time will determine the maximum frequency during read operations. low value pull-up resistors will allow higher frequency operations while drawing higher aver- age power supply current. reset (rst) the at88sc0104c provides an iso 7816-3 compliant asynchronous answer to reset sequence. when the reset sequence is activated, the device will output the data pro- random generator authentication, encryption and certification unit eeprom answer to reset data transfer password verification reset block asynchronous iso interface synchronous interface power management vcc gnd scl/clk sda/io rst
3 at88sc0104c 2021bs?smem?10/02 grammed into the 64-bit answer-to-reset register. an internal pull-up on the rst input pad allows the device to be used in syn chronous mode without bonding rst. the at88sc0104c does not support the synchronous answer-to-reset sequence. device architecture user zones the eeprom user memory is divided into 4 zones of 256 bits each. multiple zones allow for different types of data or files to be stored in different zones. access to the user zones is allowed only after security requirements have been met. these security requirements are defined by the user during the personalization of the device in the con- figuration zone. if the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone. control logic access to the user zones occurs only through the control logic built into the device. this logic is configurable through access registers, key registers and keys programmed into the configuration zone during device personalization. also implemented in the control logic is a cryptographic engine for performing the various higher-level security functions of the device. table 2. user zones zone $0 $1 $2 $3 $4 $5 $6 $7 user 0 $000 32 bytes ? ? $018 user 1 $000 32 bytes ? ? $018 user 2 $000 32 bytes ? ? $018 user 3 $000 32 bytes ? ? $018
4 at88sc0104c 2021bs?smem?10/02 configuration zone the configuration zone consists of 2048 bits of eeprom memory used for storing pass- words, keys and codes and defining security levels to be used for each user zone. access rights to the configuration zone are defined in the control logic and may not be altered by the user. security fuses there are three fuses on the device that must be blown during the device personaliza- tion process. each fuse locks certain por tions of the configuration zone as otp memory. fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be performed at one final step. table 3. configuration zone component address answer to reset $00 fab code memory test zone card manufacturers code lot history code device configuration register $18 identification number access registers password/key registers issuer code authentication attempts counters $50 cryptograms session encryption keys secret seeds password attempts counters $b0 write passwords read passwords reserved
5 at88sc0104c 2021bs?smem?10/02 protocol selection the at88sc0104c is compatible with two different communication protocols: asynchro- nous t = 0 as defined by iso 7816-3 or synchronous two-wire protocol. the power-up sequence determines which of the two protocols will be used. asynchronous t = 0 protocol the power-up sequence complies with iso 7816-3 for a cold reset. v cc goes high; rst, i/o-sda and clk-scl are low. set i/o-sda in receive mode. provide a clock signal to clk-scl. rst goes high after 400 clock cycles. the device will respond with a 64-bit atr code, including historical bytes to indicate the memory density within the cryptomemory family. once the asynchronous mode has been selected, it is not possible to switch to the synchronous mode without powering off the device. figure 2. asynchronous t = 0 protocol synchronous two-wire protocol the synchronous mode is the default after powering up v cc due to the internal pull-up on rst. power-up v cc , rst goes high also. after stable v cc , clk-scl and i/o-sda may be driven. figure 3. synchronous two-wire protocol note: four clock pulses must be sent before the first command is issued. v cc i/o-sda rst clk-scl at r v cc i/o-sda rst clk-scl 1234
6 at88sc0104c 2021bs?smem?10/02 communication security modes communications between the device and host operate in three basic modes. standard mode is the default mode for the device after power-up. authentication mode is acti- vated by a successful authentication sequence. encryption mode is activated by a successful encryption activation following a successful authentication. note: 1. configuration data include viewable areas of the configuration zone except the passwords: mdc: modification detection code. mac: message authentication code. security options anti-tearing in the event of a power loss during a write cycle, the integrity of the device?s stored data may be recovered. this function is optional: the host may choose to activate the anti- tearing function, depending on application requirements. when anti-tearing is active, write commands take longer to execute, since more write cycles are required to com- plete them, and data are limited to eight bytes. data are written first to a buffer zone in eeprom instead of the intended destination address, but with the same access conditions. the data are then written in the required location. if this second write cycle is interrupted due to a power loss, the device will automatically recover the data from the system buffer zone at the next power-up. in two-wire mode, the host is required to perform ack polling for up to 20 ms after write commands when anti-tearing is active. at power-up, the host is required to perform ack polling, in some cases for up to 10 ms, in the event that the device needs to carry out the data recovery process. write lock if a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte for the bytes of that page. example : the write lock byte at $080 controls the bytes from $080 to $087. the write lock byte may also be locked by wr iting its least significant (rightmost) bit to ?0?. moreover, when write lock mode is activated, the write lock byte can only be pro- grammed ? that is, bits written to ?0? cannot return to ?1?. in the write lock configuration, only one byte can be written at a time. even if several bytes are received, only the first byte will be taken into account by the device. table 4. communication security modes (1) mode configuration data user data passwords data integrity check standard clear clear clear mdc (1) authentication clear clear encrypted mac (1) encryption clear encrypted encrypted mac (1) $080 $081 $082 $083 $084 $085 $086 $087 @ 11011001 xxxx xxxx locked xxxx xxxx locked xxxx xxxx xxxx xxxx xxxx xxxx locked xxxx xxxx xxxx xxxx $80
7 at88sc0104c 2021bs?smem?10/02 password verification passwords may be used to protect read and/or write access of any user zone. when a valid password is presented, it is memorized and active until power is turned off, unless a new password is presented or rst becom es active. there are eight password sets that may be used to protect any user zone. only one password is active at a time, but write passwords give read access also. authentication protocol the access to a user zone may be protected by an authentication protocol. any one of four keys may be selected to use with a user zone. the authentication success is memorized and active as long as the chip is powered, unless a new authentication is initialized or rst becomes active. if the new authentica- tion request is not validated, the card loses its previous authentication and it should be presented again. only the last request is memorized. note: password and authentication may be presented at any time and in any order. if the trials limit has been reached (after four consecutive incorrect attempts), the password verifica- tion or authentication process will not be taken into account. figure 4. password and authentication operations checksum the at88sc0104c implements a data validity check function in the form of a check- sum, which may function in standard, authentication or encryption modes. in the standard mode, the checksum is implemented as a modification detection code (mdc), in which the host may read a mdc from the device in order to verify that the data sent was received correctly. in the authentication and encryption modes, the checksum becomes more powerful since it provides a bidirectional data integrity check and data origin authentication capa- bility in the form of a message authentication code (mac). only the host/device that carried out a valid authentication is capable of computing a valid mac. while operating in the authentication or encryption modes, the use of a mac is required. for an ingoing command, if the device calculates a mac di fferent from the mac transmitted by the host, not only is the command abandoned but the mode is also reset. a new authentica- tion and/or encryption activation will be required to reactivate the mac. cs verify cs write data verify rpw data checksum (cs) verify cs
8 at88sc0104c 2021bs?smem?10/02 encryption the data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. the issuer may choose to require encryption for a user zone by settings made in the configuration zone. any one of four keys ma y be selected for use with a user zone. in this case, activation of the encryption mode is required in order to read/write data in the zone and only encrypted data will be transmitte d. even if not required, the host may elect to activate encryption provided the proper keys are known. supervisor mode enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including the ability to change passwords. modify forbidden no write access is allowed in a user zone protected with this feature at any time. the user zone must be written during device personalization prior to blowing the security fuses. program only for a user zone protected by this feature, data within the zone may be changed from a ?1? to a ?0?, but never from a ?0? to a ?1?.
9 at88sc0104c 2021bs?smem?10/02 packaging information module size: m2 dimension*: 12.6 x 11.4 [mm] glob top: square - 8.8 x 8.8 [mm] thickness: 0.58 [mm] pitch: 14.25 mm ordering code: 09nt module size: m2 dimension*: 12.6 x 11.4 [mm] glob top: square - 8.8 x 8.8 [mm] thickness: 0.58 [mm] pitch: 14.25 mm ordering code: 09pt module size: m4 dimension*: 12.6 x 12.6 [mm] glob top: square - 9.0 x 9.0 [mm] thickness: 0.58 [mm] pitch: 14.25 mm ordering code: 09ct module size: m4 dimension*: 12.6 x 12.6 [mm] glob top: square - 9.0 x 9.0 [mm] thickness: 0.58 [mm] pitch: 14.25 mm ordering code: 09dt module size: m2 dimension*: 12.6 x 11.4 [mm] glob top: round - 8.0 [mm] thickness: 0.58 [mm] pitch: 14.25 mm ? ordering code: 09et *note: the module dimensions listed refer to the dimensions of the exposed metal contact area. the actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm greated in both directions (i.e., a punched m2 module will yield 13.0 x 11.8 mm).
10 at88sc0104c 2021bs?smem?10/02 ordering code: iosc 8-lead soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. note: 10/10/01 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 a common dimensions (unit of measure = mm) symbol min nom max note these drawings are for general information only. refer to jedec drawing ms-012 for proper dimensions, tolerances, datums, etc. h 1 2 n 3 top view c e end view a b l a2 e d side view a ? ? 1.75 b ? ? 0.51 c ? ? 0.25 d ? ? 5.00 e ? ? 4.00 e 1.27 bsc h ? ? 6.20 l ? ? 1.27
11 at88sc0104c 2021bs?smem?10/02 ordering code: iopc 8-lead pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view
12 at88sc0104c 2021bs?smem?10/02 ordering code: iocc 8-lead lap 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8cn1 , 8-lead (8 x 5 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) a 8cn1 11/13/01 common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.36 0.41 0.46 1 d 7.90 8.00 8.10 e 4.90 5.00 5.10 e 1.27 bsc e1 0.60 ref l 0.62 .0.67 0.72 1 l1 0.92 0.97 1.02 1 note: 1. metal pad dimensions. pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d
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