spice device model sup/sub75n08-10 siliconix 1 9/14/98 document: 70936 n-channel enhancement-mode transistors characteristics ? n-channel vertical dmos ? macro-model (subcircuit) ? level 3 mos ? applicable for both linear and switch mode ? applicable over a -55 to 125 c temperature range ? models gate charge, transient, and diode reverse recovery characteristics description the attached spice model describes typical electrical characteristics of the n-channel vertical dmos. the subcircuit model was extracted and optimized over a 25 c to 125 c temperature range under pulse conditions for 0 to 10 volt gate drives. saturated output impedance model accuracy has been maximized for gate biases near threshold. a novel gate-to-drain feedback capacitance network is used to model gate charge characteristics while avoiding convergence problems of switched c gd model. model parameter values are optimized to provide a best fit to measured electrical data and are not intended as an exact physical description of a device. model subcircuit this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number for guaranteed specification limits. g c gs d 2 4 3 m1 dbd m2 1 r1 s
spice device model sup/sub75n08-10 siliconix 2 9/14/98 document: 70936 model evaluation n-channel device (t j =25 c unless otherwise noted) parameter symbol test conditions typ unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 3.12 v on-state drain current b i d(on) v ds = 5 v, v gs = 10 v 416 a drain-source on-state resistance b r ds(on) v gs = 10 v, i d = 30 a 0.011 v gs = 10 v, i d = 30 a, t j = 125 c 0.018 ? v gs = 10 v, i d = 30 a, t j = 175 c 0.022 forward transconductance b g fs v ds = 15 v, i d = 30 a 60 s forward voltage b v sd i f = 75 a, v gs = 0v 0.92 v dynamic a input capacitance c iss 4890 output capacitance c oss v gs = 0v, v ds = 25v, f = 1mhz 963 pf reverse transfer capacitance c rss 221 total gate charge c q g 83 gate-source charge c q gs v ds = 30 v, v gs = 10 v, i d = 75 a 31 nc gate-drain charge c q gd 24 turn-on delay time c t d(on) 57 rise time c t r v dd = 30 v, r l = 0.47 ? 31 turn-off delay time c t d(off) i d ? 75 a, v gen = 10 v, r g = 2.5 ? 62 ns fall time c t f 20 reverse recovery time t rr i f = 75 a, di/dt =100a/ s 100 ns notes: a) guaranteed by design, not subject to production testing b) pulse test: pulse width 300 sec, duty cycle 2% c) independent of operating temperature
spice device model sup/sub75n08-10 siliconix 3 9/14/98 document: 70936 comparison of model with measured data (t j =25 c unless otherwise noted) 0 50 100 150 200 250 id - drain current (a) 0 2 4 6 8 10 vds - drain-to-source voltage (v) vgs= 10, 9, 8v vgs=5v vgs=6v vgs=7v 0 50 100 150 200 id - drain current (a) 0 2 4 6 8 10 vgs - gate-to-source (v) 25c 150c -55c 0 2 4 6 8 10 sqrt (idsat) (a) 0 0.02 0.04 0.06 0.08 0.1 rds(on) - on-resistance (ohm) 0 2 4 6 8 10 vgs - gate-to-source voltage (v) sqrt( idsat) rds(on) 0 0.004 0.008 0.012 0.016 0.02 rds(on) - on-resistance (ohm) 0 20 40 60 80 100 id - drain current (a) vgs = 10v vgs = 20v 0 1000 2000 3000 4000 5000 6000 7000 capacitance (pf) 0 10 20 30 40 50 60 vds - drain-to-source voltage ( v ) ciss coss crss 0 6 12 18 24 30 vds (v) 0 4 8 12 16 20 vgs (v) 0 25 50 75 100 125 150 175 qg (nc) vgs vds
|
