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1 white electronic designs corporation ? (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX fast clock speed: 150, 133, and 100mhz fast access times: 3.8ns, 4.2ns, and 5.0ns fast oe access times: 3.8ns, 4.2ns, and 5.0ns high performance 3-1-1-1 access rate 2.5v 5% power supply common data inputs and data outputs byte write enable and global write control six chip enables for depth expansion and address pipeline internally self-timed write cycle burst control pin (interleaved or linear burst sequence) automatic power-down for portable applications commercial, industrial and military temperature ranges packaging: ?152 pbga package 17 x 23mm 512k x 72 synchronous pipeline burst zbl sram november 2003 rev. 6 f unctional b lock d iagram *preliminary features description benefits 30% space savings compared to equivalent tqfp solution reduced part count 24% i/o reduction laminate interposer for optimum tce match low profile reduce layer count for board routing suitable for hi-reliability applications user configurable as 1m x 36 or 2m x 18 upgradable to 1m x 72 (contact factory for availability) the wedc syncburst - sram employs high-speed, low- power cmos design that is fabricated using an advanced cmos process. wedc?s 32mb syncburst srams integrate two 512k x 36 ssrams into a single bga package to pro- vide 512k x 72 configuration. all synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (clk). the zbl or zero bus latency memory utilizes all the bandwidth in any combination of operating cycles. address, data inputs, and all control sig- nals except output enable and linear burst order are syn- chronized to input clock. burst order control must be tied ?high or low.? asynchronous inputs include the sleep mode enable (zz). output enable controls the outputs at any given time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and pro- vides increased timing flexibility for incoming signals. *preliminary product that is not fully characterized, non-qualified and is subject to change without notice. a 0-18 bwa bwb bwc bwd we 0 oe 0 clk 0 cke 0 cs1 0 cs2 0 cs2 0 adv 0 lbo zz sa bwa bwb bwc bwd we 0 oe 0 clk cke cs1 cs2 cs2 adv lbo zz dqpa dqa 0-7 dqpb dqb 0-7 dqpc dqc 0-7 dqpd dqd 0-7 dqpa dqa 0-7 dqpb dqb 0-7 dqpc dqc 0-7 dqpd dqd 0-7 512k x 36 ssram bwe bwf bwg bwh we1 oe1 clk1 cke1 cs1 1 cs2 1 cs2 1 adv1 sa bwa bwb bwc bwd weo oeo clk cke cs1 cs2 cs2 adv lbo zz 512k x 36 ssram dqpa dqa 0-7 dqpb dqb 0-7 dqpc dqc 0-7 dqph dqd 0-7 dqpe dqe 0-7 dqpf dqf 0-7 dqpg dqg 0-7 dqph dqh 0-7
2 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX p in c onfiguration (top view) note: dnu means do not use and are reserved for future use. * pin f 8 reserved for a 19 upgrade to 1m x 72. 12 3456789 a - adv 0 oe 0 dqb 2 dqb 4 dqb 6 dnu dqa 6 dqa 2 b cke 0 we 0 dqb 7 dqb 5 dqb 3 dqb 0 dqa 7 dqa 3 dqa 1 c clk 0 cs2 0 dqc 2 dqpc dqpb dqb 1 dqd 7 dqa 4 dqa 0 d b w a b w b dqc 3 v ss v ss v ss dqd 6 dqa 5 dqpa e b w c b w d dqc 4 v ddq v ddq v ddq dqd 5 dqpd z z f cs1 0 cs2 0 dqc 5 v ddq v ddq v ss dqd 4 dnu* a 0 g a 7 dqc 0 dqc 7 v ss v dd v dd dqd 3 a 1 a 3 h a 18 dqc 1 dqc 6 v dd v dd v dd ` dqd 2 a 2 a 5 j a 9 a 6 dqf 2 v ss v ss v ss dqd 1 a 4 a 16 k a 8 dqf 4 fqf 3 v dd v dd v dd dqd 0 a 14 a 15 l a 17 dqf 5 dqf 6 v dd v dd v ss dqe 6 a 12 a 13 m adv 1 oe 1 dqf 7 v ss v ddq v ddq dqe 7 a 10 a 11 n cke 1 we 1 dqpf v ddq v ddq v ddq dqe 5 dqe 3 lbo p clk 1 cs2 1 dqf 1 v ss v ss v ss dqe 4 dqe 2 dqe 0 r b w e b w f dqf 0 dqg 1 dqg 4 dqh 1 dqh 2 dqe 1 dqpe t b w g b w h dqg 0 dqg 2 dqg 5 dqh 0 dqh 4 dqh 7 dqph u cs1 1 cs2 1 dqg 3 dqpg dqg 6 dqg 7 dqh 3 dqh 5 dqh 6
3 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX burst sequence table note 1: lbo pin must be tied to high or low, and floating state must not be allowed. write operation occurs when we is driven low at the rising edge of the clock. bw[h:a] can be used for byte write operation. the pipe-lined zbl ssram uses a late-late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are registered, and the data associated with that address is required two cycles later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst seguence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is deter- mined by the state of the lbo pin. when this pin is low, linear burst sequence is selected. and when this pin is high, interleaved burst sequence is selected. during normal operation, zz must be driven low. when zz is driven high, the sram will enter a power sleep mode after two cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram operates after two cycles of wake up time. (interleaved burst, lbo = high) case 1 case 2 case 3 case 4 lbo pin high a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 11011 01001110 10110001 fourth address 1 1 1 00100 (linear burst, lbo = low) case 1 case 2 case 3 case 4 lbo pin high a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 11011 01101100 10110001 fourth address 1 1 0 00110 the WEDPZ512K72S-XBX is an zbl ssram designed to sustain 100% bus bandwidth by eliminating turn- around cycle when there is transition from read to write, or vice versa. all inputs (with the exception of oe, lbo and zz) are synchronized to rising clock edges. all read, write and deselect cycles are initiated by the adv input. subsequent burst addresses can be inter- nally generated by the burst advance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for next operation. clock enable (cke) pin allows the operation of the chip to be suspended as long as necessary. when cke is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. nbl ssram latches external address and ini- tiates a cycle when cke and adv are driven low at the rising edge of the clock. output enable (oe) can be used to disable the output at any given time. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, cke is driven low, the write enable input signals we are driven high, and adv driven low. the internal array is read between the first rising edge and the second ris- ing edge of the clock and the data is latched in the out- put register. at the second clock edge the data is driven out of the sram. during read operation oe must be driven low for the device to drive out the requested data. function description
4 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX truth tables s ynchronous t ruth t able w rite t ruth t able we bwa bwb bwc bwd operation hxxxx read l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d lllll write all bytes l hhhh write abort/nop cex adv we bwx oe cke clk address accessed operation hlxxx l n/a deselect xhxxx l n/a continue deselect llhxll external address begin burst read cycle xhxx l l next address continue burst read cycle llhxhl external address nop/dummy read xhxxh l next address dummy read llllxl external address begin burst write cycle xhxlxl next address continue burst write cycle lllhxl n/a nop/write abort xhxhx l next address write abort xxxxxh current address ignore clock notes: 1. x means ?don?t care.? 2. the rising edge of clock is symbolized by ( ). 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table. 5. operation finally depends on status of asynchronous input pins (zz and oe). 6. cex refers to the combination of cs 1 , cs 2 and cs 2 . notes: 1. x means ?don?t care.? 2. all inputs in this table must meet setup and hold time around the rising edge of clk ( ). 3. replace bw a with bw e , bw b , with bw f , bw c with bw g and bw d with bw h for operation of ic 2 .
5 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX 150 133 100 description symbol conditions mhz mhz mhz units notes (max) (max) (max) power supply i dd device selected; all inputs v il or v ih ; cycle 700 650 600 ma 1 current: operating time t cyc min; v dd = max; output open power supply i sb2 device deselected; v dd = max; all inputs v il or v ih current: standby all inputs static; clk frequency = max 120 120 120 ma output open, zz v dd - 0.2v clock running i sb device deselected; v dd = max; all inputs 180 180 160 ma standby current v ss + 0.2 or v dd - 0.2; f = max ; zz v il a bsolute m aximum r atings * v in voltage or any other pin relative to v ss -0.3v to +3.6v voltage on v dd supply relative to v ss -0.3v to +3.6v storage temperature (bga) -55c to +150c e lectrical c haracteristics (-55c - ta - +125c) *stress greater than those listed under ?absolute maximum ratings: may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condtions for extended periods may affect reliability. description symbol conditions min max units notes input high (logic 1) voltage v ih 1.7 v dd +0.3 v 1 input low (logic 0) voltage v il -0.3 0.7 v 1 input leakage current i il v dd = m ax, 0v - v in - v dd -4 +4 a 2 output leakage current i lo output(s) disabled, v out = v ss to v ddq -2 +2 a output high voltage v oh i oh = -1.0ma 2.0 --- v 1 output low voltage v ol i ol = 1.0ma --- 0.4 v 1 supply voltage v dd 2.375 2.625 v 1 i/o power suply v ddq 2.375 2.625 v 1 notes: 1. all voltages referenced to v ss (gnd) 2. zz pin has an internal pull-up, and input leakage = 20 a. dc c haracteristics (-55c - ta - + 125c) bga c apacitance (t a = + 25c, f = 1mh z ) notes: 1. this parameter is not tested but guaranteed by design. description symbol max units notes control input capacitance (lbo, zz) c ic 16 pf 1 control input capacitance c i 8pf 1 input/output capacitance (dq) c o 10 pf 1 address capacitance c a 16 pf 1 clock capacitance c ck 6pf 1 notes: 1. i dd is specified with no output current and increases with faster cycle times. i dd increases with faster cycle times and greater output loading. t hermal r esist ance parameter symbol max unit thermal resistance: die junction to ambient ja 28.7 c/w thermal resistance: die junction to ball jb 16.0 c/w thermal resistance: die junction to case jc 7.1 c/w note: refer to application note ?pbga thermal resistance corrleation? for further information regarding wedc?s thermal modeling.
6 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX ac c haracteristics (-55c - t a - +125c) notes: notes: notes: notes: notes: 1. all address inputs must meet the specified setup and hold times for all rising clock (clk) edges when adv is sampled low and csx is sampled valid. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. chip enable must be valid at each rising edge of clk (when adv is low) to remain enabled. 3. a write cycle is defined by we low having been registered into the device at adv low. a read cycle is defined by we high with adv low. both cases must meet setup and hold times. o utput l oad (a) o utput l oad (b) (for t lzc , t lzoe , t hzoe , and t hzc ) dout zo=50 ? rl=50 ? vl=1.25 v 50pf* dout 1538 ? 5pf* +2.5v 1667 ? *including scope and jig capacitance ac t est c onditions parameter v alue input pulse level 0 to 2.5v input rise and fall time 1.0v/ns input and output timing reference levels 1.25v output load see output load (a & b) symbol 150mhz 133mhz 100mhz parameter min max min max min max units clock time t cyc 6.7 7.5 10.0 ns clock access time t cd -- 3.8 -- 4.2 -- 5.0 ns output enable to data valid t oe -- 3.8 -- 4.2 -- 5.0 ns clock high to output low-z t lzc 1.5 -- 1.5 -- 1.5 -- ns output hold from clock high t oh 1.5 -- 1.5 -- 1.5 -- ns output enable low to output low-z t lzoe 0.0 -- 0.0 -- 0.0 -- ns output enable high to output high-z t hzoe -- 3.0 -- 3.5 -- 3.5 ns clock high to output high-z t hzc -- 3.0 -- 3.5 -- 3.5 ns clock high pulse width t ch 2.5 -- 2.5 -- 3.0 -- ns clock low pulse width t cl 2.5 -- 2.5 -- 3.0 -- ns address setup to clock high t as 1.5 -- 1.5 -- 1.5 -- ns cke setup to clock high t ces 1.5 -- 1.5 -- 1.5 -- ns data setup to clock high t ds 1.5 -- 1.5 -- 1.5 -- ns write setup to clock high t ws 1.5 -- 1.5 -- 1.5 -- ns address advance to clock high t advs 1.5 1.5 1.5 ns chip select setup to clock high t css 1.5 1.5 1.5 ns address hold to clock high t ah 0.5 -- 0.5 -- 0.5 -- ns cke hold to clock high t ceh 0.5 -- 0.5 -- 0.5 -- ns data hold to clock high t dh 0.5 -- 0.5 -- 0.5 -- ns write hold to clock high t wh 0.5 -- 0.5 -- 0.5 -- ns address advance to clock high t advh 0.5 -- 0.5 -- 0.5 -- ns chip select hold to clock high t csh 0.5 -- 0.5 --- 0.5 -- ns
7 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX snooze mode is a low-current, ?power-down? mode in which the device is deselected and current is re- duced to isb 2 z . the duration of snooze mode is dictated by the length of time z is in a high state. after the device enters snooze mode, all inputs except zz become gated inputs and are ignored. zz is an asyn- chronous, active high input that causes the device to enter snooze mode. when zz becomes a logic high, isb 2 z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending operations are completed. s nooze m ode description conditions symbol min max units current during snooze mode zz v ih i sb2z 20 ma zz active to input ignored tzz 2 cycle zz inactive to input sampled trzz 2 cycle zz active to snooze current t zzi 2 cycle zz inactive to exit snooze current t rzzi o ns fig. 2 snooze mode s nooze m ode t iming d iagram zz i supply clock a ll inputs (except zz) output (q) t zz t zzi t rzz t rzzi high-z deselect or read only i isb2z don't care deselect or read only normal operation cycle
8 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX fig. 3 t iming w aveform of r ead c ycle clk x ck e x address w rite adv x oe data ou t t ch t cl t ces t ce h t as t ah a1 a2 a 3 t ws t wh t css t csh t oe t hz oe t lzoe t cd t o h t hzc q3-4 q3-3 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 q1-1 don t care undefined t cyc t advs t a dvh csx notes: write = l means wex = l, and bwx = l csx refers to the combination of cs1 0 , cs2 0 and cs2 0 , or cs1 1, cs2 1 and cs2 1.
9 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX fig. 4 t iming w aveform of w rite c ycle clk x address write adv x data i n t ch t cl a2 a3 d2-1 d1-1 d2-2 d2-3 d2-4 d3-1 d3-2 d3-3 oe data ou t t ds t dh don t care undefined t cyc ck e x a1 d3 -4 t ces t ceh q0-4 t hzoe q0-3 csx notes: write = l means wex = l, and bwx = l csx refers to the combination of cs1 0 , cs2 0 and cs2 0 , or cs1 1, cs2 1 and cs2 1.
10 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX clk x a ddress wri te a dv x oe data i n t ch t cl t ds t dh data ou t a2 a4 a5 d 2 t oe t lzoe q1 don t care undefined t cyc ck e x t ces t ceh a1 a3 a7 a6 q3 q4 q7 q6 d5 a9 a8 csx notes: write = l means we x = l, and bwx = l csx refers to the combination of cs1 0 , cs2 0 and cs2 0 , or cs1 1, cs2 1 and cs2 1. fig. 5 t iming w aveform of s ingle r ead /w rite
11 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX fig. 6 t iming w aveform of cke o pera tion clkx a ddress writ e adv x oe data in t ch t cl data ou t a1 a2 a3 a4 a 5 t ces t ceh don t care undefined t cyc ck e x t ds t dh d2 q4 q1 t cd t lzc t hzc q3 a6 csx notes: write = l means we = l, and bwx = l csx refers to the combination of cs1 0 , cs2 0 and cs2 0 , or cs1 1 , cs2 1 and cs2 1 .
12 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX fig. 7 t iming w aveform of ce o pera tion clk x a ddress writ e adv x oe data in t ch t cl data ou t a1 a2 a3 a4 a 5 don t care undefined t cyc ck e x d5 q4 t ces t ce h q1 q2 t oe t lz oe d3 t cd t lzc t hz c t dh t ds cs x notes: write = l means we = l, and bwx = l csx refers to the combination of cs1 0 , cs2 0 and cs2 0 , or cs1 1 , and cs2 1 .
13 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX 0.61 (0.024) nom 1.27 (0.050) nom a b c d e f g h j k l m n p r t u 20.32 (0.800) nom 9 8 7 6 5 4 3 2 1 23.1 (0.909) max 17.1 (0.673) max 10.16 (0.400) nom 1.27 (0.050) nom 2.03 (0.080) max bottom view ? 0.762 (0.030) nom device grade: m = military -55c to +125c i = industrial -40c to +85c c =commercial 0c to +70c package: b = 152 plastic ball grid array (pbga) frequency (mhz) 100 = 100mhz 133 = 133mhz 150 = 150mhz 2.5 v voltage configuration, 512k x 72 ssram zbl plastic white electronic designs corp. all linear dimensions are in millimeters and parenthetically in inches wed p z 512k 72 s - xxx b x ordering information package dimension: 152 bump pbga
14 white electronic designs corporation (602) 437-1520 www.whiteedc.com WEDPZ512K72S-XBX document title 512k x 72 synchronous sram ? nbl revision history rev # history release date s t atus rev 0 initial release february 2001 advanced rev 1 changes (pg. 1, 5, 6, 13) april 2001 advanced 1.1 block diagram: change dqd to dqpd, font consistency 1.2 electrical characteristics note 2: change reference to ma instead of ma. 1.3 dc characteristics: adjust location of units & notes for isb2. 1.4 ac characteristics: change temperature range to (-55c t a +125c) 1.5 package dimension: adjust length line to end of package 1.6 block diagram: adjust look for consistency 1.7 dc characteristics: isb2 condition should read all inputs v il or v ih instead of > v ih 1.8 figure 2: inputs transition should not be shown fully connected. 1.9 figure 6: unknown text deleted from timing diagram 1.10 package dimension: ball diameter arrow corrected to point to ball. rev 2 change (pg. 1) november 2001 preliminary 1.1 change status from advanced to preliminary rev 3 changes (pg. 1, 2) november 2001 preliminary 1.1 block diagram: address lines should be a0-18 1.2 pin configuration: add note *pin f8 reserved for a19 upgrade to 1mx72. rev 4 changes (pg. 1, 5) november 2002 preliminary 1.1 bga capacitance: remove references to temperature in individual conditions 1.2 change c i from 10pf to 8pf 1.3 change c a from 20pf to 16pf 1.4 change c ck from 7pf to 6pf 1.5 add control input capacitance (c ic ) 16pf rev 5 changes (pg. 5) may 2003 preliminary 1.1 add thermal resistance table 1.2 update current values 1.3 update package mechanical drawing rev 6 changes (pg. 1, 13, 14, 15) november 2003 preliminary 1.1 change mechanical drawing to new style

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