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p-dso-36-12 multi-voltage processor power supply tle 6361 g data sheet, rev. 2.0 1 2005-03-01 data sheet 1overview 1.1 features ? high efficiency regulator system wide input voltage range, up to 60v stand-by mode with low current consumption suitable for standard 12v, 24v and 42v powernets step down converter as pre-regulator: 5.5v / 1.5a step down slope control for lowest eme switching loss minimization three high current linear post-regulators with selectable output voltages: 5v / 800ma 3.3v or 2.6v / 500ma 5v or 3.3v / 350ma six independent voltage trackers (followers): 5v / 17ma each stand-by regulator with 1ma current capability three independent undervoltage detection circuits (e.g. reset, early warning) for each linear post-regulator power on reset functionality window watchdog triggered by spi tracker control and diagnosis by spi all outputs protected against short-circuit power-dso-36 package smd = surface mounted device type ordering code package tle 6361 g q 67007-a9466 p-dso-36-12
tle 6361 g data sheet, rev. 2.0 2 2005-03-01 1.2 short functional description the tle 6361 g is a multi voltage power supply system especially designed for automotive applications using a standard 12v or 24v battery as well as the new 42v powernet. the device is intended to supply 32 bit micro-controller systems which require different supply voltage rails such as 5v, 3.3v and 2.6v. the regulators for external sensors are also provided. the tle 6361 g cascades a buck converter block with a linear regulator and tracker block on a single chip to achieve lowest power dissipation thus being able to power the application even at very high ambient temperatures. the step-down converter delivers a pre-regu lated voltage of 5.5v with a minimum current capability of 1.5a. supplied by this step down converter three low drop linear post-regulators offer 5v, 3.3v, or 2.6v of output voltages depending on the configuration of the device with current capabilities of 800ma, 500ma and 350ma. in addition the inputs of six voltage trackers are connected to the 5.5v bus voltage. their outputs follow the main 5v linear regulator (q_ldo1) with high accuracy and are able to drive a current of 17ma each. the trackers can be turned on and off individually by a 16 bit serial peripheral interface (spi). through this interface also the status information of each tracker (i.e. short circuit) can be read out. to monitor the output voltage levels of each of the linear regulators three independent undervoltage detection circuits are available which can be used to implement the reset or an early warning function. the supervision of the c is managed by the spi-triggered window watchdog. for energy saving reasons while the motor is turned off, the tle 6361 g offers a stand- by mode, where the quiescent current does not exceed 30a typically. in this stand-by mode just the stand-by regulator remains active. the tle 6361 g is based on infineon power technology spt ? which allows bipolar , cmos and power dmos circuitry to be integrated on the same monolithic circuitry.
tle 6361 g data sheet, rev. 2.0 3 2005-03-01 1.3 pin configuration figure 1 pin configuration (top view), bottom heatslug and gnd corner pins are connected err do di q_stb q_t1 q_ldo3 r1 clk gnd cs q_t2 r3 r2 gnd q_t3 q_t4 q_t5 q_t6 gnd in wake boost slew sw bootstrap fb/l_in c+ sel q_ldo2 ccp c- gnd q_ldo1 in sw fb/l_in 6 32 31 4 33 34 35 36 30 5 7 3 2 1 9 8 29 28 27 15 23 22 13 24 25 26 21 14 16 12 11 10 18 17 20 19 p-dso-36-12
tle 6361 g data sheet, rev. 2.0 4 2005-03-01 1.4 pin definitions and functions pin no. symbol function 1,18,19, 36 gnd ground ; to reduce thermal resistance place cooling areas on pcb close to this pins. those pins are connected internally to the heatslug at the bottom. 2 clk spi interface clock input ; clocks the shiftregister; clk has an internal active pull down and requires cmos logic level inputs;see also chapter spi 3 cs spi interface chip select input ; cs is an active low input; serial communication is enabled by pulling the cs terminal low; cs input should only be switched when clk is low; cs has an internal active pull up and requires cmos logic level inputs ;see also chapter spi 4 di spi interface date input; receives serial data from the control device; serial data transmitted to di is a 16 bit control word with the least significant bit (lsb) being transferred first; the input has an active pull down and requires cmos logic level inputs; di will accept data on the falling edge of clk-signal; see also chapter spi 5 do spi interface data output; this tristate output transfers diagnosis data to the controlling device; the output will remain 3- stated unless the device is selected by a low on chip-select cs ; see also the chapter spi 6 err error output ; push-pull output. monitors failures in parallel to the spi diagnosis word, reset via spi. err is a latched output. 7 q_stb standby regulator output ; the output is active even when the buck regulator and all other circuitry is in off mode 8 q_t1 voltage tracker output t1 tracked to q_ldo1; bypass with a 1f ceramic capacitor for stability. it is switched on and off by spi command. keep open, if not needed. 9 q_t2 voltage tracker output t2 tracked to q_ldo1; bypass with a 1f ceramic capacitor for stability. it is switched on and off by spi command. keep open, if not needed. 10 q_t3 voltage tracker output t3 tracked to q_ldo1; bypass with a 1f ceramic capacitor for stability. it is switched on and off by spi command. keep open, if not needed.
tle 6361 g data sheet, rev. 2.0 5 2005-03-01 11 q_t4 voltage tracker output t4 tracked to q_ldo1; bypass with a 1f ceramic capacitor for stability. it is switched on and off by spi command. keep open, if not needed. 12 q_t5 voltage tracker output t5 tracked to q_ldo1; bypass with a 1f ceramic capacitor for stability. it is switched on and off by spi command. keep open, if not needed. 13 q_t6 voltage tracker output t6 tracked to q_ldo1; bypass with a 1f ceramic capacitor for stability. it is switched on and off by spi command. keep open, if not needed. 14 q_ldo3 voltage regulator output 3; 5v or 3.3v output; ouput voltage is selected by pin sel (see also 3.4.2); for stability a ceramic capacitor of 470nf to gnd is sufficient. 15 r3 reset output 3 , undervoltage detection for output q_ldo3; open collector output; an external pullup resistor of 10k ? is required 16 r2 reset output 2 , undervoltage detection for output q_ldo2; open collector output; an external pullup resistor of 10k ? is required 17 r1 reset output 1 , undervoltage detection for output q_ldo1 and watchdog failure reset; open collector output ; an external pullup resistor of 10k ? is required 20 c- charge pump capacitor connection ; add the fly-capacitor of 100nf between c+ and c- 21 c+ charge pump capacitor connection ; add the fly-capacitor of 100nf between c+ and c- 22 ccp charge pump storage capacitor output ; add the storage capacitor of 220nf between pin ccp and gnd. 23 sel select pin for output voltage adjust of q_ldo2 and q_ldo3 (see also 2.2.2) 24 q_ldo2 voltage regulator output 2; 3.3v or 2.6v output; output voltage is selected by pin sel (see also 3.4.2); for stability a ceramic capacitor of 470nf to gnd is sufficient. 25, 26 fb/l_in feedback and linear regulator input ; input connection for the buck converter output 1.4 pin definitions and functions (cont?d) pin no. symbol function
tle 6361 g data sheet, rev. 2.0 6 2005-03-01 27 q_ldo1 voltage regulator output 1; 5v output; acts as the reference for the voltage trackers.the spi and window watchdog logic is supplied from this voltage. for stability a ceramic capacitor of 470nf to gnd is sufficient. 28 bootstrap bootstrap input ; add the bootstrap capacitor between pin sw and pin bootstrap, the capcitance value should be not lower than 2% of the buck converter output capacitance 29, 31 sw switch output; connect both pins externally through short lines directly to the cathode of the catch diode and the buck circuit inductance. 30, 32 in supply voltage input; connect both pins externally through short lines to the input filter/the input capacitors. 33 boost boost input ; for switching loss minimization connect a diode (cathode directly to boost pin) in series with a 100nf ceramic capacitor to the in pin and from the anode of the diode to the buck converter output a 22 ? resistor. recommended for 42v applications, in 12/24v applications connect boost directly to in 34 wake wake up input ; a positive voltage applied to this pin turns on the device 35 slew slew control input ; a resistor to gnd defines the current slope in the buck switch for reduced eme 1.4 pin definitions and functions (cont?d) pin no. symbol function
tle 6361 g data sheet, rev. 2.0 7 2005-03-01 1.5 basic block diagram figure 2 block diagram r1 linear reg. 1 linear reg. 2 tracker 5v reset logic window watchdog spi 16 bit -controller / memory supply sensor supplies (off board supplies) power down logic tracker 5v tracker 5v tracker 5v tracker 5v tracker 5v tle 6361 standby regulator 2.5v osz pwm driver error- amplifier internal reference feedback 2* 2* 2* ref ref ref ref ref ref protection 4* buck regulator boost in slew wake r2 r3 clk cs di do err gnd q_stb sw bootstrap fb/l_in c+ c- ccp sel q_ldo1 q_ldo2 q_ldo3 q_t1 q_t2 q_t3 q_t4 q_t5 q_t6 charge pump linear reg. 3
tle 6361 g data sheet, rev. 2.0 8 2005-03-01 2 detailed circuit description in the following major buck regulator blocks, the linear voltage regulators and trackers, the undervoltage reset function, the watchdog and the spi are described in more detail. for applications information e.g. choice of external components, please refer to section . 2.1 buck regulator the diagram below shows the internal implemented circuit of the buck converter, i. e. the internal dmos devices, the regulation loop and the other major blocks. figure 3 detailed buck regulator diagram the 1.5a buck regulator consists of two internal dmos power stages including a current mode regulation scheme to avoid external compensation components plus additional blocks for low eme and reduced switching loss. figure 3 indicates also the principle how int. voltage regulator int. charge pump zero cross detection divider oscillator 1.4mhz slope logic under- voltage lockout gate driver delay unit 5v 14v 150a vref=6v voltage feedback amplifier current sense amplifier + current comparator pwm logic gate off signal from overtemp or sleep command trigger for gate on trigger for gate off slope compensation lowpass lowpass switching frequency 330khz slope control from current sensing to current sense amplifier fb/l_in c+ c- ccp slew sw boot- strap boost sw in in external components main switch on/off slope switch charge signal slope switch discharge signal 8 to 10v main dmos slope dmos pins
tle 6361 g data sheet, rev. 2.0 9 2005-03-01 the gate driver supply is managed by the combination of internal charge pump, external charge pump and bootstrap capacitor. 2.1.1 current mode control scheme the regulation loop is located at the left lower corner in the schematic, there you find the voltage feedback amplifier which gives the actual information of the actual output voltage level and the current sense amplifier for the load current information to form finally the regulation signal. to avoid subharmonic oscillations at duty cycles higher than 50% the slope compensation block is necessary. the control signal formed out of those three blocks is finally the input of the pwm regulator for the dmos gate turn off command, which means this signal determines the duty cycle. the gate turn on signal is set by the oscillator periodically every 3s which leads to a buck converter switching frequency around 330khz. with decreasing input voltage the device changes to the so called pulse skipping mode which means basically that some of the oscillator gate turn off signals are ignored. when the input voltage is still reduced the dmos is turned on statically (100% duty cycle) and its gate is supplied by the internal charge pump. below typical 4.5v at the feedback pin the device is turned off.during normal switching operation the gate driver is supplied by the bootstrap capacitor. 2.1.2 start-up procedure to guarantee a device startup even under full load condition at the linear regulator outputs a special start up procedure is implemented. at first the bootstrap capacitor is charged by the internal charge pump. afterwards the outpuput capacitor is charged where the driver supply in that case is maintained only by the bootstrap capacitor. once the output capacitor of the buck converter is charged the external charge pump is activated being able to supply the linear regulators and finally the linear regulators are released to supply the loads. 2.1.3 reduction of electromagnetic emission in figure 3 it is recognized that two internal dmos switches are used, a main switch and an auxiliary switch. the second implemented switch is used to adjust the current slope of the switching current. the slope adjustment is done by a controlled charge and discharge of the gate of this dmos. by choosing the external slew resistor appropriate the current transition time can be adjusted between 20ns and 100ns. 2.1.4 reducing the switching losses the second purpose of the slope dmos is to minimise the switching losses. once being in freewheeling mode of the buck regulator the output voltage level is sufficient to force the load current to flow, the input voltage level is not needed in the first moment. by a feedback network consisting of a resistor and a diode to the boost pin (connection see
tle 6361 g data sheet, rev. 2.0 10 2005-03-01 section ) the output voltage level is present at the drain of the switch. as soon as the voltage at the sw pin passes zero volts the handover to the main switch occurs and the traditional switching behaviour of the buck switch can be observed. 2.2 linear voltage regulators the linear regulators offer voltage rails of 5v, 3.3v and 2.6v which can be determined by a hardware connection (see table at 2.2.2 ) for proper power up procedure. being supplied by the output of the buck pre-regulator the power loss within the three linear regulators is minimized. all voltage regulators are short circuit protected which means that each regulator provides a maximum current according to its current limit when shorted. together with the external charge pump the npn pass elements of the regulators allow low dropout voltage operation. by using this structure the linear regulators work stable even with a minimum of 470nf ceramic capacitors at their output. q_ldo1 has 5v nominal output voltage, q_ldo2 has a hardware programmable output voltage of 3.3v or 2.6v and q_ldo3 is programmable to 5v or 3.3v (see 2.2.2 ). all three regulators are on all the time, if one regulator is not needed a base load resistor in parallel to the output capacitance for controlled power down is recommended. 2.2.1 startup sequence linear regulators when acting as 32 bit c supply the so-called power sequencing (the dependency of the different voltage reails to each other) is important. within the tle 6361 g the following startup-sequence is defined (see also figure 4 ): v q_ldo2 v q_ldo1; v q_ldo3 v q_ldo1 with v q_ldo1 =5v, v q_ldo2 = 2.6v and v q_ldo3 = 3.3v and v q_ldo2 v q_ldo1 with v q_ldo1 =5v, v q_ldo2 = 2.6v/3.3v and v q_ldo3 = 5v the power sequencing refers to the regulator itself, externally voltages applied at q_ldo2 and q_ldo3 are not pulled down actively by the device if q_ldo1 is lower than those outputs. that means for the power down sequencing if different output capacitors and different loads at the three outputs of the linear regulators are used the voltages at q_ldo2 and q_ldo3 might be higher than at q_ldo1 due to slower discharging. to avoid this behaviour three schottky diodes have to be connected between the three outputs of the linear regulators in that way that the cathodes of the diodes are always connected to the higher nominal rail.
tle 6361 g data sheet, rev. 2.0 11 2005-03-01 figure 4 power-up and -down sequencing of the regulators 2.2.2 q_ldo2 and q_ldo3 output voltage selection* to determine the output voltage levels of the three linear regulators, the selection pin (sel, pin 23) has to be connected according to the matrix given in the table below. * for different output voltages please refer to the multi voltage supply tle6368 definition of output voltage q_ldo2 and q_ldo3 select pin sel connected to q_ldo2 output voltage q_ldo3 output voltage gnd 3.3 v 5 v q_ldo1 2.6 v 3.3 v q_ldo2 2.6 v 5 v v ldo_en t v fb/l_in power sequencing 0.7v 5v 3.3v 2.6v v rth5 t 2.6v v rth2.6 t 0.7v v q_ldo1 +/- 50mv v q_ldo3 (3.3v mode) 3.3v v rth3.3 t +/- 50mv v q_ldo2 (2.6v mode) 5v ldo 5v ldo 5v ldo 5v ldo
tle 6361 g data sheet, rev. 2.0 12 2005-03-01 2.3 voltage trackers for off board supplies i.e. sensors six voltage trackers q_t1 to q_t6 with 17ma output current capability each are available. the output voltages match q_ldo1 within +5 / -15mv. they can be individually turned on and off by the appropriate spi command word sent by the microcontroller. a ceramic capacitor with the value of 1f at the output of each tracker is sufficient for stable operation without oscillation. the tracker outputs can be connected in parallel to obtain a higher output current capability, no matter if only two or up to all six trackers are tied together. for uniformly distributed current density in each tracker internal balance resistors at each output are foreseen internally. by connecting twice three trackers in parallel two sensors with more than 50ma each can be supplied, all six in parallel give more than 100ma. the tracker outputs can withstand short circuits to gnd or battery in a range from -4 to +40v. a short circuit to gnd at is detected and indicated individually for each tracker in the spi status word. also an open load condition might be recognised and indicated as a failure condition in the spi status word. a minimum load current of 2ma is required to avoid open load failure indication. in case of connecting several trackers to a common branch balancing currents can prevent proper operation of the failure indication. 2.4 standby regulator the standby regulator is an ultra low power 2.5v linear voltage regulator with 1ma output current which is on all the time. it is intended to supply the microcontroller in stop mode and requires then only a minimum of quiescent current (<30a) to extend the battery lifetime. 2.5 charge pump the 1.6 mhz charge pump with the two external capacitors will serve to supply the base of the npn linear regulators q_ldo1 and q_ldo3 as well as the gate of the buck dmos transistor in 100% duty cycle operation at low battery condition. the charge pump voltage in the range of 8 to 10v can be measured at pin 22 (ccp) but is not intended to be used as a supply for additional circuitry. 2.6 power on reset a power on reset is available for each linear voltage regulator output. the reset output lines r1, r2 and r3 are active (low) during start up and turn inactive with a reset delay time after q_ldo1, q_ldo2 and q_ldo3 have reached their reset threshold. the reset outputs are open collector, three pull up resistors of 10k ? each have to be connected to the i/o rail (e.g. q_ldo1) of the c. all three reset outputs can be linked in parallel to obtain a wired-or. the reset delay time is 64 ms by default and can be set to lower values as 8 ms, 16 ms or 32 ms by spi command. at each power up of the device when the output voltage at
tle 6361 g data sheet, rev. 2.0 13 2005-03-01 q_ldo1 has decreased below 3.3v (max.) the default settings are valid, means the 64ms delay time. if the voltage on q_ldo1 during sleep or power off mode was kept above 3.3v the delay time set by the last spi command is valid. figure 5 undervoltage reset timing 2.7 ram good flag a ram good flag will be set within the spi status word when the q_ldo1 voltage drops below 2.3v. a second one will be set if q_ldo2 drops below typical 1.4v. both ram good flags can be read after power up to determine if a cold or warm start needs to be processed. both ram good flags will be reset after each spi cycle. 2.8 err pin an hardware error pin indicates any fault conditions on the chip. it should be connected to an interrupt input of the microcontroller. a low signal indicates an error condition. the microcontroller can read the root cause of the error by reading the spi register. 2.9 window watchdog the on board window watchdog for supervision of the c works in combination with the spi. the window watchdog logic is triggered when cs is low and bit wd-trig in the spi command word is set to ?1?. the watchdog trigger is recognized with the low to high transition of the cs signal. to allow reading the spi at any time without getting a reset due to misinterpretation the wd-trig bit has to be set to ?0? to avoid false trigger conditions. to disable the window watchdog the wd-off bits need to be set to ?010?. v fb/l_in t v q_ldox t v rx t v rth,q_ldox t res t rr < t rr thermal shutdown under voltage over load t res t res t res
tle 6361 g data sheet, rev. 2.0 14 2005-03-01 figure 6 window watchdog timing definition figure 6 shows some guidelines for designing the watchdog trigger timing taking the oscillator deviation of different devices into account. of importance is the maximum (w.c.) of the closed window and the minimum of the open window in which the trigger has to occur. the length of the ow and cw can be modified by spi command. if a change of the window length is desired during the watchdog function is operating please send the spi command with the new timing with a ?watchdog trigger bit? d15=1.in this case the next cw will directly start with the new length. a minimum time gap of > 1/48 of the actual ow/cw time between a ?watchdog disable? and ?watchdog enable? spi-command should be maintained. this allows the internal watchdog counters to be resetted. thus after the enable command the watchdog will start properly with a full cw of the adjusted length. t ecw, w.c. = t cw (1+ ? ) closed window open window t cw =t cw definition f osc =f oscmax reset start delay time after wi ndow watchdog timeout reset delay time wit hout trigger reset duration time after wi ndow watchdog time-out t sr = t ow /2 t ow =t cw t wdr = t res t owmin f osc =f oscmin definition worst cases t eow, w.c. = ( t cw +t ow )(1- ? ) example with: t cw =128ms ? =25% (oscillator deviation) t ecw, w.c. = 128(1.25) = 160ms t eow, w.c = (128+128)(0.75) = 192ms t owmin = 32ms (not the same scale) t eow = end of open window t ecw (not the same scale) t owmin = t ow - ? * ( t ow + 2* t cw ) minimum open window time:
tle 6361 g data sheet, rev. 2.0 15 2005-03-01 figure 7 window watchdog timing figure 7 gives some timing information about the window watchdog. looking at the upper signals the perfect triggering of the watchdog is shown. when the 5v linear regulator q_ldo1 reaches its reset threshold, the reset delay time has to run off before v rth1 t res r1 t t v q_ldo1 1v t watchdog window t cs t err cw ow cw ow cw cw ow perfect triggering after power on reset incorrect triggering t watchdog window cw ow t cs 1) 2) 1) pretrigger 2) missing trigger legend: ow = open window cw = closed window t cw t sr with wd- trig=1 with wd- trig=1
tle 6361 g data sheet, rev. 2.0 16 2005-03-01 the closed window (cw) starts. then three valid watchdog triggers are shown, no effect on the reset line and/or error pin is observed. with the missing watchdog trigger signal the error signal turns low immediately where the reset is asserted after another delay of half the closed window time. also shown in the figure are two typical failure modes, one pretrigger and one missing signal. in both cases the error signal will go low immediately the failure is detected with the reset following after the half closed window time. 2.10 overtemperature protection at a chip temperature of more than 130 an error and temperature flag is set and can be read through the spi. the device is switched off if the device reaches the overtemperature threshold of 170c. the over temperature shutdown has a hysteresis to avoid thermal pumping. 2.11 power down mode the tle 6361 g is started by a static high signal at the wake input or a high pulse with a minimum of 50s duration at the wake input (pin 34). voltages in the range between the turn on and turn off thresholds for a few 100s must be avoided! by spi command (?sleep?-bit, d8, equals zero) all voltage regulators including the switching regulator except the standby regulator can be turned off completely only if the wake input is low. in the case the wake input is permanently connected to battery the device cannot be turned off by spi command, it will always turn on again. for stable ?on? operation of the device the ?sleep?-bit, d8 has to be set to high at each spi cycle! when powering the device again after power down the status of the spi controlled devices (e.g. trackers, watchdog etc.) depends on the output voltage on q_ldo1. did the voltage at q_ldo1 decrease below 3.3v t he default status (given in the next section) is set otherwise the last spi command defines the status. 2.12 serial peripheral interface a standard 16bit spi is available for control and diagnostics. it is capable to operate in a daisy chain. it can be written or read by a 16 bit spi interface as well as by an 8 bit spi interface. the 16-bit control word (write bit assignment, see figure 8) is read in via the data input di, synchronous to the clock input clk supplied by the c. the diagnosis word appears in the same way synchronously at the data output do (read bit assignment, see figure 9 ), so with the first bit shifted on the di line the first bit appears on the do line. the transmission cycle begins when the tle 6361 g is selected by the ?not chip select? input cs (h to l). after the cs input returns from l to h, the word that has been read in at the di line becomes the new control word. the do output switches to tristate status at
tle 6361 g data sheet, rev. 2.0 17 2005-03-01 this point, thereby releasing the do bus circuit for other uses. for details of the spi timing please refer to figures 10 to 13 . the spi will be reset to default values given in the following table ?write bit meaning? if the ram good flag of q_ldo1 indicates a cold start (lower output voltage than 3.3v). the reset will be active as long as the power on reset is present so during the reset delay time at power up no spi commands are acceptable. the register content of the spi - including watchdog timings and reset delay timings - is maintained if the ram good flag of q_ldo1 indicates a warm start (i.e. q_ldo1 did not decrease below 3.3v). 2.12.1 write mode the following tables show the bit assignment to the different control functions, how to change settings with the right bit combination and also the default status at power up. 2.12.2 write mode bit assignment figure 8 write bit assignment write bit meaning function bit combination default not assigned d1 x x tracker 1 to 6 - control: turn on/off the individual trackers d2 d3 d4 d5 d6 d7 0: off 1: on 0 power down: send device to sleep d8 0: sleep 1: normal 1 wd_of f1 t6- control t5- control t4- control t6- control t2- control t1- control not assigned sleep wd-trig wd_of f3 wd 2 wd 1 reset 2 reset 1 wd_of f2 1 0 0 0 0 0 0 x 1 0 1 0 0 0 0 1 bit default name d 15 d8 d9 d10 d11 d12 d13 d14 d7 do d1 d2 d3 d4 d5 d6
tle 6361 g data sheet, rev. 2.0 18 2005-03-01 2.12.3 read mode below the status information word and the bit assignments for diagnosis are shown. 2.12.3.1 read mode bit assignment figure 9 read bit assignment error bit d0: the error bit indicates fail function and turns high if the temperature prewarning, the watchdog error is active, further if one ram good indicates a cold start or if a voltage tracker does not settle within 1ms when it is turned on. in addition to the error indication by software the err pin atcs as a hardware error flag. reset timing: reset delay time t res valid at warm start d10d11 00: 64ms 10: 32ms 01: 16ms 11: 8ms 00 window watchdog timing: open window time t ow and closed window time t cw valid at warm start d12d13 00: 128ms 10: 64ms 01: 32ms 11: 16ms 00 window watchdog function: enable /disable window watchdog d0d9d14 010: off 1xx: on x0x: on xx1: on 111 window watchdog trigger: enable / disable window watchdog trigger d15 0: not triggered 1: triggered 1 write bit meaning function bit combination default error t6- status t5- status t4- status t3- status t2- status t1- status temp_ warn ram good 1 dc/dc status wd error r-error3 r-error2 r-error1 wd window ram good 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 bit default name d 15 d8 d9 d10 d11 d12 d13 d14 d7 do d1 d2 d3 d4 d5 d6
tle 6361 g data sheet, rev. 2.0 19 2005-03-01 read bit meaning function type bit combination default error indication, explanation see below this table latched d0 0: normal operation 1: fail function 0 overtemperature warning not latched d1 0: normal operation 1: prewarning 0 status of tracker output q_t[1:6],only if output is on not latched d2 d3 d4 d5 d6 d7 1: settled output voltage 0:tracker turned off or shorted output. also open load may possibly be indicated as 0. 1) 0 indication of cold start/ warm start, q_ldo1 latched d8 0: cold start 1: warm start 0 indication of cold start/ warm start, q_ldo2 latched d9 0: cold start 1: warm start 0 indication for open or closed window not latched d10 0: open window 1: closed window 0 reset condition at output q_ldo1 not latched d11 0: normal operation 1: reset r1 0 reset condition at output q_ldo2 not latched d12 0: normal operation 1: reset r2 0 reset condition at output q_ldo3 not latched d13 0: normal operation 1: reset r3 0 watchdog error latched d14 0: normal operation 1: wd error 0 dc/dc converter status not latched d15 0: off 1: on 1 1) min. load current to avoid ?0? signal caused by open load is 2ma.
tle 6361 g data sheet, rev. 2.0 20 2005-03-01 2.12.4 spi timings figure 10 spi data transfer timing di clk c s do data out (n-1) data in (n) di: data will be accepted on the falling edge of clk-signal do: state will change on the rising edge of clk-signal time data in (n+1) data out (n) t r a c k e r - c o n t r o l setting (n) setting (n-1) 0 d1 d0 15 14 13 3 2 1 + d1 d0 d0 d15 d14 d13 d2 d3 d0 + d15 d14 d13 d3 d2 d1 d1 01 cs high to low & rising edge of clk: do is enabled. status information is transferred to output shift register cs low to high: data from register are transferred to e.g. trackers e.g. status (n) status (n-1) e.g. t r a c k e r - s t a t u s
tle 6361 g data sheet, rev. 2.0 21 2005-03-01 figure 11 spi-input timing figure 12 do valid data delay time and valid time clk 0.7 v q_ldo1 0.2 v q_ldo1 50% do 90% 10% do 90% 10% (low to high) (high to low) t rin t fin <10ns t rdo t fdo t vado
tle 6361 g data sheet, rev. 2.0 22 2005-03-01 figure 13 do enable and disable time cs 0.7 v q_ldo1 0.2 v q_ldo1 50% do do t fin t rin <10ns t endo t disdo 50% 50% 10k ? pullup to v q_ldo1 10k ? pulldown to gnd
tle 6361 g data sheet, rev. 2.0 23 2005-03-01 3 characteristics 3.1 absolute maximum ratings item parameter symbol limit values unit test condition min. max. 3.1.1 supply voltage input in voltage v vs -0.5 60 v ? current i vs ? ? ? 3.1.2 buck-switch output sw voltage v sw -2 v s +0.5 v ? current i sw ? ? ? 3.1.3 feedback and linear voltage regulator input voltage v fb/l_in -0.5 8 v ? current i fb/l_in ? ? ? 3.1.4 bootstrap connector bootstrap voltage v bootstrap v sw - 0.5v v sw + 10v v voltage v bootstrap -0.5 70 v current i bootstrap ? ? ? internally limited 3.1.5 boost input voltage v boost -0.5 60 v ? current i boost ? ? ? internally limited 3.1.6 slope control input slew voltage v slew -0.5 6 v ? current i slew ? ? ? internally limited 3.1.7 charge pump capacitor connector c- voltage v cl -0.5 v fb/l_in +0.5 v current i cl -150 +150 ma
tle 6361 g data sheet, rev. 2.0 24 2005-03-01 3.1.8 charge pump capacitor connector c+ voltage v ch -0.5 13 v current i ch -150 +150 ma 3.1.9 charge pump storage capacitor ccp voltage v ccp -0.5 12 v current i ccp -150 ? ma 3.1.10 standby voltage regulator output q_stb voltage v q_stb -0.5 6 v ? current i q_stb ? ? ? internally limited 3.1.11 voltage regulator output voltage q_ldo1 voltage v q_ldo1 -0.5 6 v ? current i q_ldo1 ? ? ? internally limited 3.1.12 voltage regulator output voltage q_ldo2 voltage v q_ldo2 -0.5 6 v ? current i q_ldo2 ? ? ? internally limited 3.1.13 voltage regulator output voltage q_ldo3 voltage v q_ldo3 -0.5 6 v ? current i q_ldo3 ? ? ? internally limited 3.1.14 voltage tracker output voltage q_t1 voltage v q_t1 -4 40 v ? current i q_t1 ? ? ma internally limited 3.1.15 voltage tracker output voltage q_t2 voltage v q_t2 -4 40 v ? current i q_t2 ? ? ma internally limited 3.1.16 voltage tracker output voltage q_t3 voltage v q_t3 -4 40 v ? current i q_t3 ? ? ma internally limited 3.1.17 voltage tracker output voltage q_t4 voltage v q_t4 -4 40 v ? current i q_t4 ? ? ma internally limited
tle 6361 g data sheet, rev. 2.0 25 2005-03-01 3.1.18 voltage tracker output voltage q_t5 voltage v q_t5 -4 40 v ? current i q_t5 ? ? ma internally limited 3.1.19 voltage tracker output voltage q_t6 voltage v q_t6 -4 40 v ? current i q_t6 ? ? ma internally limited 3.1.20 select input sel voltage v sel -0.5 6 v ? current i sel ? ? ? internally limited 3.1.21 wake up input wake voltage v wake -0.5 60 v ? current i wake ? ? ? 3.1.22 reset output r1 voltage v r1 -0.5 6 v ? current i r1 ? ? ? 3.1.23 reset output r2 voltage v r2 -0.5 6 v ? current i r2 ? ? ? 3.1.24 reset output r3 voltage v r3 -0.5 6 v ? current i r3 ? ? ? 3.1.25 spi data input di voltage v di -0.5 6 v ? current i di ? ? ? 3.1.26 spi data output do voltage v do -0.5 6 v ? current i do ? ? ? internally limited 3.1.27 spi clock input clk voltage v clk -0.5 6 v ? current i clk ? ? ?
tle 6361 g data sheet, rev. 2.0 26 2005-03-01 1) package mounted on fr4 47x50x1.5mm 3 ; 70 cu, zero airflow note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.1.28 spi chip select not input cs voltage v cs -0.5 6 v ? current i cs ? ? ? 3.1.29 error output pin voltage v error -0.5 6 v ? current i error ? ? ? internally limited 3.1.30 thermal resistance junction- ambient r thja 37 k/w 1) pcb heat sink area 300mm 2 junction- ambient r thja 29 k/w 1) pcb heat sink area 600mm 2 junction- case r thjc ? 2 k/w 3.1.31 temperature junction temperature t j -40 150 c junction temperature transient t jt 175 c lifetime=tbd storage temperature t stg -50 150 c 3.1.32 esd - protection (human body model; 1.5k ? ; c=100pf) electrostatic discharge voltage v esd -1 1 kv all pins
tle 6361 g data sheet, rev. 2.0 27 2005-03-01 3.2 functional range note: within the functional range the ic can be operated . the electrical characteristics, however, are not guaranteed over this full functional range -40c < t j < 150 c item parameter symbol limit values unit condition min. max. supply voltage v in 5.5 v to achieve v in,min an initial startup with v in >8v is required; supply voltage v in 60 v ripple at fb/l_in v fb/l_in ripple 0 150 mv pp
tle 6361 g data sheet, rev. 2.0 28 2005-03-01 3.3 recommended operation range -40c < t j < 150 c item parameter symbol limit values unit condition min. typ. max. buck inductor l b 18 100 h 1) 1) c b, min needs a buck inductance l b =47h to avoid instabilities buck capacitor c b 10 f esr <0.15 ? , ceramic capacitor (x7r) recommended 1) bootstrap capacitor c btp 2 % of c b slew resistor r slew 0 20 k ? linear regulator capacitors c q_ldo1-3 470 nf ceramic capacitor (x7r) tracker bypass capacitors c q_t1-6 1 f ceramic capacitor (x7r) spi rise and fall timings, cs , di, clk t r,f 200 ns
tle 6361 g data sheet, rev. 2.0 29 2005-03-01 3.4 electrical characteristics the electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. typical values represent the median values at room temperature, which are related to production processes. -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max. buck regulator 3.4.1 switching frequency f sw 280 370 425 khz 3.4.2 current transition time, min., rising edge t r_i_sw 20 ns r sl =0 ? 1) 3.4.3 current transition time, max., rising edge t r_i_sw 100 ns r sl =20k ? 1) 3.4.4 current transition time, min., falling edge t f_i_sw 20 ns r sl =0 ? 1) 3.4.5 current transition time, max., falling edge t f_i_sw 100 ns r sl =20k ? 1) 3.4.6 voltage rise / fall time t f_v_sw 25 ns 1) 3.4.7 static on resistance r on 160 m ? t j =25c in static operation 3.4.8 static on resistance r on 280 400 m ? t j =150c in static operation 3.4.9 current limit i max 1.5 3.2 a v fb/l_in =5.4v 3.4.10 output voltage v out 5.4 6.3 v i out =0.1a v in =13.5 v 3.4.11 output voltage v out 5.4 6.05 v i out =1.5a v in =13.5 v
tle 6361 g data sheet, rev. 2.0 30 2005-03-01 3.4.12 bootstrap charging current at start-up i btstr 80 160 220 a 3.4.13 bootstrap voltage (internal charge pump) v btstr 10 17 v v fb/l_in =6.5v, buck converter off 3.4.14 bootstrap undervoltage lockout, buck turn on threshold v btstr, turn on 5 9 v 3.4.15 bootstrap undervoltage lockout, hysteresis v btstr, turn on - v btstr, turn off 2.5 v 3.4.16 charge pump voltage v ccp 7.9 11.0 v i q_ldo1 = 800ma, v fb/l_in =6.0v, c fly =100nf, c ccp =220nf 3.4.17 max. duty cycle duty max 95 % switching operation 3.4.18 min. duty cycle duty min 0 % static-off operation voltage regulator q_ldo1 3.4.19 output voltage v q1 4.9 5.1 v 100ma < i q_ldo1 < 800ma 3.4.20 output voltage v q1 5.0 v i q_ldo1 = 800ma 3.4.21 load regulation ? v q_ldo1 40 mv 100ma< i q_ldo1 <800ma; v fb/l_in =5,5v 3.4.22 current limit i q_ldo1limit 800 1050 1400 ma v q_ldo1 =4v -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 31 2005-03-01 3.4.23 ripple rejection psrr1 26 40 db f=330khz; 1) 3.4.24 output capacitor c q_ldo1 470 nf ceramic type, value for stability voltage regulator q_ldo2 3.4.25 output voltage 3.3v v q_ldo2 3.14 3.46 v 50ma < i q_ldo2 < 400ma; 3.3v mode 3.4.26 output voltage 3.3v v q_ldo2 3.32 v i q_ldo2 =400ma; 3.3v mode 3.4.27 output voltage 2.6v v q_ldo2 2.500 2.750 v 50ma < i q_ldo2 < 400ma; 2.6v mode 3.4.28 output voltage 2.6v v q_ldo2 2.62 v i q_ldo2 =400ma; 2.6v mode 3.4.29 load regulation ? v q_ldo2 50 mv 50ma< i q_ldo3 <400ma; v fb/l_in =5.5v 3.3v mode 3.4.30 load regulation ? v q_ldo2 50 mv 50ma< i q_ldo2 <400ma; v fb/l_in =5.5v 2.6v mode 3.4.31 current limit i q_ldo2limit 500 650 850 ma v q_ldo2 = 2.8v; 3.3v mode 3.4.32 current limit i q_ldo2limit 500 650 850 ma v q_ldo2 = 2v; 2.6v mode 3.4.33 ripple rejection psrr2 26 40 db f=330khz; 1) 3.4.34 output capacitor c q_ldo2 470 nf ceramic type, value for stability voltage regulator q_ldo3 -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 32 2005-03-01 3.4.35 output voltage 5v v q_ldo3 4.8 5.2 v 20ma < i q_ldo3 < 300ma; 5v mode 3.4.36 output voltage 5v v q_ldo3 5.0 v i q_ldo3 =300ma; 5v mode 3.4.37 output voltage 3.3v v q_ldo3 3.14 3.46 v 20ma < i q_ldo3 < 300ma; 3.3v mode 3.4.38 output voltage 3.3v v q_ldo3 3.32 v i q_ldo3 =300ma; 3.3v mode 3.4.39 load regulation ? v q_ldo3 100 mv 20ma< i q_ldo3 <300ma; v fb/l_in =5,5v 5v mode 3.4.40 load regulation ? v q_ldo3 50 mv 20ma< i q_ldo3 <300ma; v fb/l_in =5,5v 3.3v mode 3.4.41 current limit i q_ldo3 limit 350 500 600 ma v q_ldo3 =4v; 5v mode 3.4.42 current limit i q_ldo3 limit 350 500 600 ma v q_ldo3 =2.8v; 3.3v mode 3.4.43 ripple rejection psrr3 26 40 db f=330khz; 1) 3.4.44 output capacitor c q_ldo3 470 nf ceramic type, value for stability voltage tracker q_t1 3.4.45 output voltage tracking accuracy ? v q_t1 -15 5 mv v q_t1 -v q_ldo1 ; 1ma < i q_t1 < 17ma 3.4.46 output voltage tracking accuracy ? v q_t1 -10 mv v q_t1 -v q_ldo1 ; i q_t1 = 17ma -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 33 2005-03-01 3.4.47 overvoltage threshold v ovq_t1 v q_t1, nom mv i q_t1 = 0ma; 1) 3.4.48 undervoltage threshold v uvq_t1 v q_t1 - 15mv mv 1) 3.4.49 current limit i q_t1 limit 17 30 ma v q_t1 =4v 3.4.50 ripple rejection psrr 26 db f=330khz; 1) 3.4.51 tracker load capacitor c q_t1 1 f ceramic type, minimum for stability voltage tracker q_t2 3.4.52 output voltage tracking accuracy ? v q_t2 -15 5 mv v q_t2 -v q_ldo1 ; 1ma < i q_t2 < 17ma 3.4.53 output voltage tracking accuracy ? v q_t2 -10 mv v q_t2 -v q_ldo2 ; i q_t2 = 17ma 3.4.54 overvoltage threshold v ovq_t2 v q_t2, nom mv i q_t2 = 0ma; 1) 3.4.55 undervoltage threshold v uvq_t2 v q_t2 - 15mv mv 1) 3.4.56 current limit i q_t2 limit 17 30 ma v q_t2 =4v 3.4.57 ripple rejection psrr 26 db f=330khz; 1) 3.4.58 tracker load capacitor c q_t2 1 f ceramic type, minimum for stability voltage tracker q_t3 -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 34 2005-03-01 3.4.59 output voltage tracking accuracy ? v q_t3 -15 5 mv v q_t3 -v q_ldo1 ; 1ma < i q_t3 < 17ma 3.4.60 output voltage tracking accuracy ? v q_t3 -10 mv v q_t3 -v q_ldo3 ; i q_t3 = 17ma 3.4.61 overvoltage threshold v ovq_t3 v q_t3, nom mv i q_t3 = 0ma; 1) 3.4.62 undervoltage threshold v uvq_t3 v q_t3 - 15mv mv 1) 3.4.63 current limit i q_t3 limit 17 30 ma v q_t3 =4v 3.4.64 ripple rejection psrr 26 db f=330khz; 1) 3.4.65 tracker load capacitor c q_t3 1 f ceramic type, minimum for stability voltage tracker q_t4 3.4.66 output voltage tracking accuracy ? v q_t4 -15 5 mv v q_t4 -v q_ldo1 ; 1ma < i q_t4 < 17ma 3.4.67 output voltage tracking accuracy ? v q_t4 -10 mv v q_t4 -v q_ldo4 ; i q_t4 = 17ma 3.4.68 overvoltage threshold v ovq_t4 v q_t4, nom mv i q_t4 = 0ma; 1) 3.4.69 undervoltage threshold v uvq_t4 v q_t4 - 15mv mv 1) 3.4.70 current limit i q_t4 limit 17 30 ma v q_t4 =4v 3.4.71 ripple rejection pssr 26 db f=330khz; 1) -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 35 2005-03-01 3.4.72 tracker load capacitor c q_t4 1 f ceramic type, minimum for stability voltage tracker q_t5 3.4.73 output voltage tracking accuracy ? v q_t5 -15 5 mv v q_t5 -v q_ldo1 ; 1ma < i q_t5 < 17ma 3.4.74 output voltage tracking accuracy ? v q_t5 -10 mv v q_t5 -v q_ldo5 ; i q_t5 = 17ma 3.4.75 overvoltage threshold v ovq_t5 v q_t5, nom mv i q_t5 = 0ma; 1) 3.4.76 undervoltage threshold v uvq_t5 v q_t5 - 15mv mv 1) 3.4.77 current limit i q_t5 limit 17 30 ma v q_t5 =4v 3.4.78 ripple rejection psrr 26 db f=330khz; 1) 3.4.79 tracker load capacitor c q_t5 1 f ceramic type, minimum for stability voltage tracker q_t6 3.4.80 output voltage tracking accuracy ? v q_t6 -15 5 mv v q_t6 -v q_ldo1 ; 1ma < i q_t6 < 17ma 3.4.81 output voltage tracking accuracy ? v q_t6 -10 mv v q_t6 -v q_ldo6 ; i q_t6 = 17ma 3.4.82 overvoltage threshold v ovq_t6 v q_t6, nom mv i q_t6 = 0ma; 1) -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 36 2005-03-01 3.4.83 undervoltage threshold v uvq_t6 v q_t6 - 15mv mv 1) 3.4.84 current limit i q_t6 limit 17 30 ma v q_t6 =4v 3.4.85 ripple rejection psrr 26 db f=330khz; 1) 3.4.86 tracker load capacitor c q_t6 1 f ceramic type, minimum for stability standby regulator 3.4.87 output voltage v q_stb 2.2 2.4 2.6 v 0a v wake th, on max ; 1) reset r1 -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 37 2005-03-01 3.4.96 reset threshold q_ldo1 v rth q_ldo1, de 4.5 4.65 4.8 v v q_ldo1 decreasing 3.4.97 reset threshold q_ldo1 v rth q_ldo1, in 4.55 4.70 4.9 v v q_ldo1 increasing 3.4.98 reset output low voltage v r1 l 0.4 v i r1 =1.6ma; v q_ldo1 =5v 3.4.99 reset output low voltage v r1 l 0.3 v i r1 =0.3ma; v q_ldo1 =1v 3.4.100 reset high leakage current i r1 h 1 a reset r2 3.4.101 reset threshold q_ldo2 v rth q_ldo2, de 2.6 2.8 3.0 v 3.3v mode; v q_ldo2 decreasing 3.4.102 reset threshold hysteresis q_ldo2 v rth q_ldo2, in - v rth q_ldo2, de 40 mv 3.3v mode 3.4.103 reset threshold q_ldo2 v rth q_ldo2, de 2.3 2.4 2.5 v 2.6v mode; v q_ldo2 decreasing 3.4.104 reset threshold hysteresis q_ldo2 v rth q_ldo2, in - v rth q_ldo2, de 40 mv 2.6v mode 3.4.105 reset output low voltage v r2 l 0.4 v i r2 =1.6ma; v q_ldo2 =2.5v 3.4.106 reset output low voltage v r2 l 0.3 v i r2 =0.3ma; v q_ldo2 =1v 3.4.107 reset high leakage current i r2 h 1 a -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 38 2005-03-01 reset r3 3.4.108 reset threshold q_ldo3 v rth q_ldo3, de 2.7 2.85 3.0 v 3.3v mode; v q_ldo3 decreasing 3.4.109 reset threshold hysteresis q_ldo3 v rth q_ldo3, in - v rth q_ldo3, de 40 mv 3.3v mode 3.4.110 reset threshold q_ldo3 v rth q_ldo3, de 4.0 4.2 4.5 v 5v mode; v q_ldo3 decreasing 3.4.111 reset threshold hysteresis q_ldo3 v rth q_ldo3, in - v rth q_ldo3, de 40 mv 5v mode 3.4.112 reset output low voltage v r3 l 0.4 v i r3 =1.6ma; v q_ldo3 =3.3v 3.4.113 reset output low voltage v r3 l 0.3 v i r3 =0.3ma; v q_ldo3 =1v 3.4.114 reset high leakage current i r3 h 1 a 3.4.115 reset reaction time t rr 1 2 10 s 1) valid for r1, r2 and r3 3.4.116 reset delay norm factor t norm,res 0.75 1 1.25 1 3.4.117 reset delay time t res 0.75 1 1.25 t res(spi) valid for r1, r2 and r3; t res (spi) is defined by the spi word (see section 2.12) ram good 3.4.118 v q1 threshold v th q1 2.3 2.8 3.3 v -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 39 2005-03-01 3.4.119 v q2 threshold v th q2 1.2 1.4 1.7 v 3.3v mode 3.4.120 v q2 threshold v th q2 1.2 1.4 1.7 v 2.6v mode; 1) window watchdog 3.4.121 closed window time tolerance t cw_tol 0.75 1 1.25 multiply with watchdog window time set by spi to obtain the limits (2.12) 3.4.122 open window time tolerance t ow_tol 0.75 1 1.25 multiply with watchdog window time set by spi to obtain the limits (2.12) 3.4.123 watchdog reset low time t wrl t res 3.4.124 watchdog reset delay time t sr t cw /2 error output err 3.4.125 h-output voltage level v err ,h v q_ldo1 ? 2.0 v q_ldo1 ? 0.7 ? v i err , h = 1 ma 3.4.126 l-output voltage level v err ,l ? 0.3 0.5 v i err , l = ? 1.6 ma spi 3.4.127 spi clock frequency f clk 0 2.5 mhz production test up to 1mhz; 2.5mhz 1) spi input di -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 40 2005-03-01 3.4.128 h-input voltage threshold v ih ? 40 70 % of v q_ldo1 ? 3.4.129 l-input voltage threshold v il 20 36 ? % of v q_ldo1 ? 3.4.130 hysteresis of input voltage v ihy 50 200 500 mv 1) 3.4.131 pull down current i i 5 25 100 a v di = 0.2 * v q_ldo1 3.4.132 input capacitance c i ? 10 15 pf 0 v < v q_ldo1 < 5.25 v 3.4.133 input signal rise time t r ? ? 200 ns 1) 3.4.134 input signal fall time t f ? ? 200 ns 1) spi clock input clk 3.4.135 h-input voltage threshold v ih ? 40 70 % of v q_ldo1 ? 3.4.136 l-input voltage threshold v il 20 36 ? % of v q_ldo1 ? 3.4.137 hysteresis of input voltage v ihy 50 200 500 mv 1) 3.4.138 pull down current i i 5 25 100 a v clk = 0.2 * v q_ldo1 3.4.139 input capacitance c i ? 10 15 pf 0 v < v q_ldo1 < 5.25 v 3.4.140 input signal rise time t r ? ? 200 ns 1) 3.4.141 input signal fall time t f ? ? 200 ns 1) spi chip select input cs -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 41 2005-03-01 3.4.142 h-input voltage threshold v ih ? 39 70 % of v q_ldo1 ? 3.4.143 l-input voltage threshold v il 20 35 ? % of v q_ldo1 ? 3.4.144 hysteresis of input voltage v ihy 50 200 500 mv 1) 3.4.145 pull up current at pin cs i i, cs ? 100 ? 25 ? 5 a v cs = 0.2 * v q_ldo1 3.4.146 input capacitance c i ? 10 15 pf 0 v < v q_ldo1 < 5.25 v 3.4.147 input signal rise time t r ? ? 200 ns 1) 3.4.148 input signal fall time t f ? ? 200 ns 1) logic output do 3.4.149 h-output voltage level v doh v q_ldo1 ? 1.0 v q_ldo1 ? 0.8 ? v i doh = 1 ma 3.4.150 l-output voltage level v dol ? 0.2 0.4 v i dol = ? 1.6 ma 3.4.151 tri-state leakage current i do_tri ? 10 ? 10 a v cs = v q_ldo1 ; 0 v < v do < v q_ldo1 3.4.152 tri-state input capacitance c do ? 10 15 pf v cs = v q_ldo1 0 v < v q_ldo1 < 5.25 v data input timing 3.4.153 clock period t pclk 1000 ? ? ns 1) -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 42 2005-03-01 3.4.154 clock high time t clkh 500 ? ? ns 1) 3.4.155 clock low time t clkl 500 ? ? ns 1) 3.4.156 clock low before cs low t bef 500 ? ? ns 1) 3.4.157 cs setup time t lead 500 ? ? ns 1) 3.4.158 clk setup time t lag 500 ? ? ns 1) 3.4.159 clock low after cs high t beh 500 ? ? ns 1) 3.4.160 di setup time t disu 250 ? ? ns 1) 3.4.161 di hold time t diho 250 ? ? ns 1) data output timing 3.4.162 do rise time t rdo ? 50 100 ns c l = 100 pf 3.4.163 do fall time t fdo ? 50 100 ns c l = 100 pf 3.4.164 do enable time t endo ? ? 250 ns low impedance 3.4.165 do disable time t disdo ? ? 250 ns high impedance 3.4.166 do valid time t vado ? 100 250 ns v do < 10% v do > 90% c l = 100 pf general 3.4.167 temperature warning flag t j,flag 140 c 2) 3.4.168 over temperature shutdown t j,shutdown 150 170 200 c 2) -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max.
tle 6361 g data sheet, rev. 2.0 43 2005-03-01 4 typical performance charcteristics buck converter switching frequency vs. junction temperature 3.4.169 over- temperature shutdown hysteresis ? t sd_hys 30 k 3.4.170 deltatw to tsd t j,shutdown - t j,flag 20 k 1) specified by design, not subject to production test 2) simulated at wafer test only, not absolutely measured -40 < t j <150 c; v in =13.5v unless otherwise specified item parameter symbol limit values unit test conditions min. typ. max. -50 -20 10 40 70 100 130 160 t j c f sw khz 280 300 420 320 340 360 380 400
tle 6361 g data sheet, rev. 2.0 44 2005-03-01 buck converter output voltage at 1.5a load vs. junction temperature buck converter dmos on-resistance vs. junction temperature buck converter current limit vs. junction temperature start-up bootstrap charging current vs. junction temperature -50 -20 10 40 70 100 130 160 t j c v fb/l_in v 5.3 5.4 6.0 5.5 5.6 5.7 5.8 5.9 -50 -20 10 40 70 100 130 160 t j c r on m ? 50 100 400 150 200 250 300 350 -50 -20 10 40 70 100 130 160 t j c i max a 0.5 1.0 4.0 1.5 2.0 2.5 3.0 3.5 -50 -20 10 40 70 100 130 160 t j c i btstr a 0 40 280 80 120 160 200 240
tle 6361 g data sheet, rev. 2.0 45 2005-03-01 bootstrap uv lockout, turn on threshold vs. junction temperature device wake up thresholds vs. junction temperature q_ldo1 output voltage at 800ma load vs. junction temperature reset1 threshold at drecreasing v_ldo1 vs. junction temperature -50 -20 10 40 70 100 130 16 0 t j c v btstr, tu rn o n v 5.0 5.5 8.5 6.0 6.5 7.0 7.5 8.0 -50 -20 10 40 70 100 130 160 t j c v w a k e th v 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 v w a k e th , o n v w a k e th , o ff -50 -20 10 40 70 100 130 160 t j c v q_ldo1 v 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 -50 -20 10 40 70 100 130 160 t j c v rth q_ldo1, de v 4.45 4.50 4.55 4.60 4.65 4.70 4.75 4.80
tle 6361 g data sheet, rev. 2.0 46 2005-03-01 q_ldo1 current limit vs. junction temperature q_ldo2 output voltage at 400ma load (2.6v mode) vs. junction temperature q_ldo2 current limit (2.6v mode) vs. junction temperature q_ldo3 output voltage at 300ma load (3.3v mode) vs. junction temperature -50 -20 10 40 70 100 130 160 t j c i q_ldo1 v 1400 1300 700 800 900 1000 1100 1200 -50 -20 10 40 70 100 130 160 t j c v q _ld o 2 v 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 -50 -20 10 40 70 100 130 160 t j c i q_ldo2 v 850 500 550 600 650 700 750 800 -50 -20 10 40 70 100 130 160 t j c v q_ldo3 v 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50
tle 6361 g data sheet, rev. 2.0 47 2005-03-01 reset2 threshold at decreasing v_ldo2 (2.6v mode) vs. junction temperature q_ldo3 current limit (3.3v mode) vs. junction temperature reset3 threshold at decreasing v_ldo3 (3.3v mode) vs. junction temperature tracker current limit vs. junction temperature -50 -20 10 40 70 100 130 160 t j c v rth q_ldo2, de v 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 -50 -20 10 40 70 100 130 160 t j c i q_ldo3 v 600 250 300 350 400 450 500 550 -50 -20 10 40 70 100 130 160 t j c v rth q_ldo3, de v 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 -50 -20 10 40 70 100 130 160 t j c i q_tx ma 32 30 18 20 22 24 26 28
tle 6361 g data sheet, rev. 2.0 48 2005-03-01 tracker accuracy with respect to v_ldo1 vs. junction temperature q_stb output voltage at 500a load vs. junction temperature q_stb current limit vs. junction temperature device current consumption in off mode vs. junction temperature -50 -20 10 40 70 100 130 160 t j c dv q_tx mv 4 2 -1 0 -8 -6 -4 -2 0 -50 -20 10 40 70 100 130 160 t j c v q_stb v 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 -50 -20 10 40 70 100 130 16 0 t j c i q_stb ma 4.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 -50 -20 10 40 70 100 130 160 t j c i q, off a 35 30 0 5 10 15 20 25
tle 6361 g data sheet, rev. 2.0 49 2005-03-01 5 application information 5.1 application diagram figure 14 application diagram tle 6361 aea03380_6361zr .vsd buck regulator standby regulator 2.5 v driver pw m osz bootstrap q_stb buck output in boost slew c i3 1 0 to 100 nf r slew 0 to 20 k ? + c i2 47 f l i u p to 47 h c i1 100 nf b a tte ry c boost 100 nf dboost fb/l_in charge pump c fly 100 nf c ccp 220 nf c+ c- ccp protection to ig n wake lin. reg. 5 v lin. reg. 3.3/2.6 v lin. reg. 5/3.3 v tracker 5 v ref c ldo1,1 470 nf + c ldo1,2 4.7 f sel q_ldo1 c ldo2,1 470 nf + c ldo2,2 4.7 f q_ldo2 c ldo3,1 470 nf + c ldo3,2 4.7 f q_ldo3 c t1 1 f q_t1 tracker 5 v ref c t2 1 f q_t2 tracker 5 v ref c t3 1 f q_t3 tracker 5 v ref c t4 1 f q_t4 tracker 5 v ref c t5 1 f q_t5 tracker 5 v ref c t6 1 f q_t6 spi 16 bit 1 k ? do 10 k ? di cs 10 k ? clk 10 k ? power down logic reset logic r1 r2 q_ldo1 r3 w indow w atchdog 4* gnd sensor supplies (off board supplies) -controller/ memory supply 2* c stb 100 nf r boost 22 ? sw 2* l b 47 h c btstr 680 nf db 3 a, 60 v + c b > 10 f ceram ic or > 20 f low esr tantalum 2* err t o c t o c 10 k ? 10 k ? e rro r- amplifier in te rn a l reference feedback 10 k ? 10 k ?
tle 6361 g data sheet, rev. 2.0 50 2005-03-01 5.2 buck converter circuit a typical choice of external components for the buck converter is given in figure 14. for basic operation of the buck converter the input capacitor c i2 , the bootstrap capacitor c btp , the catch diode d b , the induuctance l b , the output capacitor c b and the charge pump capacitors c fly and c ccp are necessary. the additional components shown on top of the circuit lower the electromagnetic emission (l i , c i1 , c i3 , r slew ) and the switching losses (r boost , c boost , d boost ). for 12v battery systems the switching loss minimization feature might not be used. in that case the boost pin (33) is connected directly to the in pins (32, 30) and the components r boost , c boost and d boost are left away 5.2.1 buck inductance (l b ) selection: the inductance value determines together wi th the input voltage, the output voltage and the switching frequency the current ripple which occurs during normal operation of the step down converter. this current ripple is important for the all over ripple at the output of the switching converter. as a rule of thumb this current ripple ? i is chosen between 10% and 50% of the load current. for optimum operation of the control loop of the buck converter the inductance value should be in the range indicated in section 3.3, recommended operation range. when picking finally the inductance of a certain supplier (epcos, coilcraft etc.) the saturation current has to be considered. with a maximum current limit of the buck converter of 3.2a an inductance with a minimum saturation current of 3.2a has to be chosen. l v i v out ? () v out ? f sw v i ? i ?? -------------------------------------------------- - =
tle 6361 g data sheet, rev. 2.0 51 2005-03-01 5.2.2 buck output capacitor (c b ) selection: the choice of the output capacitor effects straight to the minimum achievable ripple which is seen at the output of the buck converter. in continuous conduction mode the ripple of the output voltage equals: from the formula it is recognized that the esr has a big influence in the total ripple at the output, so ceramic types or low esr tantalum capacitors are recommended for the application. one other important thing to note are the requirements for the resonant frequency of the output lc-combination. the choice of the components l and c have to meet also the specified range given in section 3.3 otherwise instabilities of the regulation loop might occur. 5.2.3 input capacitor (c i2 ) selection: at high load currents, where the current through the inductance flows continuously, the input capacitor is exposed to a square wave current with its duty cycle v out /v i . to prevent a high ripple to the battery line a capacitor with low esr should be used. the maximum rms current which the capacitor has to withstand is calculated to: 5.2.4 freewheeling diode / catch diode (d b ) for lowest power loss in the freewheeling path schottky diodes are recommended. with those types the reverse recovery charge is negligible and a fast handover from freewheeling to forward conduction mode is possible. depending on the application (12v battery systems) 40v types could be also used instead of the 60v diodes. a fast recovery diode with recovery times in the range of 30ns can be also used if smaller junction capacitance values (smaller spikes) are desired, the slew resistor should be set in this case between 10 and 20k ? . v ripple ? ir esrcb 1 8f sw c b ?? ---------------------------- + ?? ?? ? = i rms i load v out v in -------------- 1 1 3 -- - ? i 2i load ? ----------------------- ?? ?? 2 ? + ?? =
tle 6361 g data sheet, rev. 2.0 52 2005-03-01 5.2.5 bootstrap capacitor (c btp ) the voltage at the bootstrap capacitor does not exceed 15v, a ceramic type with a minimum of 2% of the buck output capacitance and voltage class 16v would be sufficient. 5.2.6 external charge pump capacitors (c fly , c ccp ) out of the feedback voltage the charge pump generates a voltage between 8 and 10v. the fly capacitor connected between c+ and c- is charged with the feedback voltage level and discharged to achieve the (almost) double voltage level at ccp. c fly is chosen to 100nf and c ccp to 220nf, both ceramic types. the connection of ccp to a voltage source of e.g. 7v (take care of the maximum ratings!) via a diode improves the start-up behavior at very low battery voltage. the diode with the cathode on ccp has to be used in order to avoid any influence of the voltage source to the device?s operation and vice versa. 5.2.7 input filter components for reduced eme (c i1 , c i2 , c i3 , l i , r slew ) at the input of buck converters a square wave current is observed causing electromagnetical interference on the battery line. the emission to the battery line consists on one hand of components of the switching frequency (fundamental wave) and its harmonics and on the other hand of the high frequency components derived from the current slope. for proper attenuation of those interferers a -type input filter structure is recommended which is built up with inductive (l i ) and capacitive components (c i1 , c i2 , c i3 ). the inductance can be chosen up to the value of the buck converter inductance, higher values might not be necessary, c i1 and c i3 should be ceramic types and for c i2 an input capacitance with very low esr should be chosen and placed as close to the input of the buck converter as possible. inexpensive input filters show due to their parasitrics a notch filter characteristic, which means basically that the lowpass filter acts from a certain frequency as a highpass filter and means further that the high frequency components are not attenuated properly. for that reason the tle 6361 g offers the possibility of current slope adjustment. the current transistion time can be set by the external slew resistor to times between 20ns and 80ns by varying the resistor value bewteen 0 ? (fastest transition) and 20k ? (slowest transistion). 5.2.8 feedback circuit for minimum switching loss (r boost , c boost , d boost ) to decrease the switching losses to a mininum the external components r boost , c boost and d boost are needed. the current through the feedback resistor r boost is about a few ma where the diode d boost and the capacitor c boost run a part of the load current. if this feature is not needed the three components are not needed and the boost pin (33) can be connected directly to the in pins(32, 30).
tle 6361 g data sheet, rev. 2.0 53 2005-03-01 5.3 reverse polarity protection the buck converter is due to the parasitic source drain diode of the dmos not reverse polarity protected. therefore, as an example, the reverse polarity diode is shown in the application circuit, in general the reverse polarity protection can be done in different ways. 5.4 linear voltage regulators (c ldo1, 2, 3 ) as indicated before the linear regulators show stable operation with a minimum of 470nf ceramic capacitors. to avoid a high ripple at the output due to load steps this output cap might have to be increased to some few f capacitors. 5.5 linear voltage trackers (c t1,2,3,4,5,6 ) the voltage trackers require at their outputs 1f ceramic capacitors each to avoid some oscillation at the output. if needed the tracker outputs can be connected in parallel, in that the output capacitor increases linear according to the number of parallel outputs. 5.6 reset outputs (r1,2,3) the undervoltage/watchdog reset outputs are open drain structures and require external pull up resistors in the range of 10k ? to the c i/o voltage rail.
tle 6361 g data sheet, rev. 2.0 54 2005-03-01 5.7 components recommendation - overview device type supplier remark l i b82479 series epcos 10-1000 h; 4.3-0.56a b82464-a4 series epcos 1-1000 h; 6.8-0.3a do3340p series coilcraft 10-1000 h; 8.0-0.8a do5022p series coilcraft 1-1000 h; 20.0-1.0a ds5022p series coilcraft 10-1000 h; 8.0-0.8a slf1275t-330m3r2 tdk 33h, 3.2a c i1 ceramic various 100nf, 60v c i2 low esr tantalum various 47 f, 60v c i3 ceramic various 10nf to 100nf, 60v d boost s3b various l b b82479 series epcos 10-1000 h; 4.3-0.56a b82464-a4 series epcos 1-1000 h; 6.8-0.3a do3340p series coilcraft 10-1000 h; 8.0-0.8a do5022p series coilcraft 1-1000 h; 20.0-1.0a ds5022p series coilcraft 10-1000 h; 8.0-0.8a c btp ceramic various 100nf, 10v d b mbrd360 motorola schottky, 60v, 3a mbrd340 motorola schottky, 40v, 3a ss34 various schottky, 40v, 3a c b b45197-a2226 epcos low esr tantalum, 22 f, 10v, c-case 2 * lmk316bj475ml taiyo yuden ceramic x7r, 4.7 f, 10v c3216x7r1c106m tdk ceramic x7r, 10f, 16v tpsc476k010r350 avx low esr tantalum, 47 f, 10v, c-case c ldox ceramic various 470nf, 10v c tx ceramic various 1f, 60v
tle 6361 g data sheet, rev. 2.0 55 2005-03-01 5.8 layout recommendation the most sensitive points for buck converters - when considering the layout - are the nodes at the input and the output of the buck switch, the dmos transistor. for proper operation the external catch diode and buck inductance have to be connected as close as possible to the sw pins (29, 31). best suitable for the connection of the cathode of the schottky diode and one terminal of the inductance would be a small plain located next to the sw pins. the gnd connection of the catch diode must be also as short as possible. in general the gnd level should be implemented as surface area over the whole pcb as second layer, if necessary as third layer. the pin fb/l_in is sensitive to noise. with an appropriate layout the buck output capacitor helps to avoid noise coupling to this pin. also filtering of steep edges at the supply voltage pin e.g. as shown in the application diagram is mandatory. c i2 may either be a low esr tantalum capacitor or a ceramic capacitor. a minimum capacitance of 10f is recommended for c i2 . to obtain the optimum filter capability of the input -filter it has to be located also as close as possible to the in pins, at least the ceramic capacitor c i3 should be next to those pins.
tle 6361 g data sheet, rev. 2.0 56 2005-03-01 package outlines bottom view does not include plastic or metal protrusion of 0.15 max. per side 1 18 0.25 0.1 1.1 36 +0.13 0.25 36x 19 m (heatslug) 15.74 0.65 0.1 c ab 19 c 3.25 3.5 max. +0.1 0 0.1 0.1 36 2.8 b 11 0.15 1) 1.3 5? 0.25 3? -0.02 +0.07 6.3 14.2 (mold) 0.3 b 0.15 0.25 heatslug 0.95 heatslug 0.1 5.9 3.2 (metal) 0.1 (metal) 13.7 (metal) 10 1 -0.2 index marking (mold) 15.9 1) 0.1 a 1 x 45? 1) p-dso-36-12 smd = surface mounted device dimensions in mm see also: http://www.infineon.com -> products -> packages
tle 6361 g data sheet, rev. 2.0 57 2005-03-01 edition 2004-09 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2/28/05. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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