LSI403Z digital signal processor overview the LSI403Z is a low power 16-bit fixed-point digital signal processor (dsp) based on the lsi logic zsp400 dsp core. the device has been designed for applications requiring high throughput and flexibility coupled with a high speed i/o, such as voice over networks cpe/iad devices and audio applications. the LSI403Z is capable of a maximum clock rate of 150 mhz for 600 mips peak performance and sustained effective throughput of 300 dsp mips (macs). the device is also software compatible with all other products in the zsp architecture, and offers an unrivalled combination of code density, performance and ease of use. memory the internal memory structure of the LSI403Z comprises of 16k words of on-chip instruction memory, 16k words of on-chip data memory, 2k words on- chip boot rom, and on-chip peripherals. additionally, the boot rom provides start-up and self-test capabilities. both synchronous and asynchronous devices are supported including sync-burst sram. the external memory is logically segmented into instruction, data, and peripheral spaces. dma the dma controller of the LSI403Z supports zero-overhead instruction or data transfers to or from the entire 32k words of internal ram to the memory interface unit, host processor interface, or serial ports. the eight dma channels are segmented between four ?indexed? and four ?non-indexed? channels. indexed channels have the ability to multiplex and de-multiplex data. indexed channels can also operate in non-indexed mode. features 150 mhz operation at 1.8v 2 high-speed serial/tdm ports (t1/e1 framer, h.100/h.110 bit stream compatible) low power modes 32k words on-chip ram, 2k words on-chip rom 8-channel dma controller on-board pll for clock generation 32-/16-bit external memory interface 2 on-board timers ieee 1149.1-compliant jtag port for real-time emulation benefits 300 mmac sustained dsp performance at 150 mhz direct interfacing to standard telecommunications interfaces, reducing system cost high data throughput without processor overhead low power per channel flexibility to optimize power consumption high data bandwidth to off-chip devices rtos support and increased system integration low overhead on chip debug ideal for voice over dsl iad designs the communications company tm mac 1 mac 2 alu 2 alu 1 register file ppl boot rom program memory 16kx16 data memory 16kx16 dma mxu load/store buffer xbus serial port 0 serial port 1 hpi pio pipeline control unit data unit d-cache instruction unit i-cache bus i/f unit icu deu jtag dsp core 64b 32b 64b 32b 64b 64b 32b figure 1. LSI403Z functional block diagram zsp tm architecture performance with high-end integration
LSI403Z digital signal processor timers the LSI403Z has two identical 16-bit on board timers for real-time interrupt generation. each timer is fully programmable, and has a 6-bit prescaler and interrupt capability. the timers can automatically reload with the initial count so that periodic interrupts can be generated. tdm serial ports the LSI403Z provides two identical synchronous serial ports that support 8- or 16-bit active or passive transfers, which can be either burst or continuous. it a maximum transfer rate in either active or passive mode of one-half the processor clock rate. both serial ports provide the programmable feature of a tdm (time division multiplex) mode that is compatible with t1/e1 framers or the local serial bus of h.100/h.110 interface devices. the tdm mode can also be used to establish a serial multiprocessor communication link with only three signals. host processor interface (hpi) the host processor interface, or hpi, is an asynchronous 8-bit parallel port that is used to interface with off-chip devices. it is compatible with both motorola and intel style memory interfaces, and supports word transfers. the maximum transfer rate for the hpi is one-forth of the processor clock frequency. development tools the LSI403Z is fully supported by both lsi logic and third party commercial tools. lsi logic provides a gnu-based compiler, linker and assembler available for windows and solaris platforms. the compiler supports c fixed-point data types and employs a variety of c intrinsic functions. also supported is a full commercial tool chain from greenhills software and corelis jtag debug tools. the zsp architecture enables the c compiler to produce code unrivaled in code density and execution speed by any dsp in its class, offering a fast time to market with optimal performance and cost. an LSI403Z evaluation board, the eb403, is available offering the following features: ? 32-bit pci interface provides jtag debug capabilities 16-bit a/d converter on board reference board with the ability to handle multiple voice channels programmable gain amplifier for more information please call: lsi logic corporation north american headquarters milpitas, ca tel: 800 574 4286 lsi logic europe ltd. european headquarters united kingdom tel: 44 1344 426544 fax: 44 1344 481039 lsi logic kk headquarters tokyo, japan tel: 81 3 5463 7165 fax: 81 3 5463 7820 lsi logic web site www.lsilogic.com lsi logic logo design, is a registered trademark of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. copyright ?2001 by lsi logic corporation. all rights reserved. order no. r20034 301.1k.sr.lt - printed in usa the communications company tm
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