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cym9288/cym9289 512k/1m x 72 flowthrough nobl sram module cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05062 rev. ** revised september 4, 2001 87 features ? operates at 66 mhz uses 256k/512k x 18 high performance flowthrough nobl synchronous srams 3.3v data inputs/outputs functional description the cym9288/9289 are high-performance synchronous flowthrough nobl memory modules organized as 512k/1m by 72 bits. these modules are constructed from 256k/512k x 18 nobl sram ? s in plastic surface mount packages on an epoxy laminate board with pins. the modules are designed to be incorporated into large memory arrays. modules are configured as either one or two banks, where each bank has separate chip select controls. separate clocks are provided for every pair of srams. multiple ground pins and on-board decoupling capacitors en- sure high performance with maximum noise immunity. all components on the cache modules are surface mounted on a multi-layer epoxy laminate (fr-4) substrate. the contact pins are plated with 200 micro-inches (minimum) of 90/10 tin/lead over 50 micro-inches of nickel. logic block diagram- cym9288/9289 d[63:0] dp[7:0] a[17:0] clk[0:3] pd 1 pd 0 9288/9289 a 17:0 oe cs oe 9288 nc nc (4) 256k/512k x 18 sram ? s a 17:0 oe cs clk (4) 256k/512k x 18 sram ? s bw[0] bw[1] bw[0] bw[1] bwe[7:0] clk[0] clk[1] clk[1] clk[3] clk[0] clk[2] clk[2] clk[3] ce[0:1] d[15:0] dp[1:0] d[15:0] dp[1:0] adv/ld adv/ld adv/ld clk bank 0 bank 1 bank 0 & 1 ce0 ce1 oe oe we we we mode mode mode 9289 gnd gnd bank 0 & 1
cym9288/cym9289 document #: 38-05062 rev. ** page 2 of 11 selection guide nobl synchronous module part number cym9288-60 cym9288-66 cym9289-60 cym9289-66 cache size 512 k x 72 512 k x 72 1m x 72 1m x 72 srams used 8 of 256k x 18 8 of 256k x 18 8 of 512k x 18 8 of 512k x 18 system clock (mhz) 60 66 60 66 data t cdv 12 ns 10.5 ns 12 ns 10.5 ns
cym9288/cym9289 document #: 38-05062 rev. ** page 3 of 11 pin configuration top view dual read-out zip 10 9 5 6 7 8 4 1 2 gnd 3 90 89 85 86 87 88 20 19 15 16 17 18 14 11 12 13 30 29 25 26 27 28 24 21 22 23 39 35 36 37 38 34 31 32 33 40 41 42 52 51 47 48 49 50 46 43 44 45 57 58 59 60 56 53 54 gnd 55 69 65 66 67 68 64 61 62 gnd 63 70 71 72 100 99 95 96 97 98 94 91 92 93 110 109 105 106 107 108 104 101 102 103 120 119 115 116 117 118 114 111 112 113 121 122 127 128 129 130 126 123 124 125 gnd 140 139 135 136 137 138 134 131 132 133 144 141 142 143 gnd 9288/9289 gnd clk1 clk3 gnd gnd gnd 77 73 74 75 75 160 78 79 80 145 155 154 150 151 152 153 149 146 147 148 159 156 157 158 gnd gnd gnd gnd gnd gnd 81 161 162 163 164 82 83 84 adv/ld 165 166 167 168 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd clk2 gnd d63 d62 dp7 d59 d61 gnd gnd clk0 gnd bwe 6 ce1 bwe 1 bwe 5 bwe 3 bwe 7 gnd bwe 4 bwe 2 bwe 0 oe ce0 pd1 we vcc3 d57 d54 d17 d52 d10 d50 dp6 d19 d45 d34 d47 d48 vcc3 vcc3 d36 d38 dp4 d41 d43 d27 d29 d31 d32 d58 d60 d20 d22 dp2 d25 vcc3 vcc3 vcc3 d11 d13 d15 d16 d18 d0 d9 dp0 d2 d4 d6 a19 a13 a15 a17 vcc3 vcc3 a7 a9 a11 a1 a3 a5 d51 d53 d55 d56 d35 d37 d39 d49 dp1 dp3 dp5 vcc3 vcc3 vcc3 d40 d42 d44 d46 d26 d28 d30 d33 d21 d23 d24 d12 d14 d5 d7 d8 pd0 d1 d3 mode a18 a12 a14 a16 a0 a2 a10 a6 a8 a4 a20
cym9288/cym9289 document #: 38-05062 rev. ** page 4 of 11 pin definitions signal description v cc3 3.3v supply gnd ground a[20:0] addresses from processor oe output enable we write enable bwe[7:0] byte write enables cs [1:0] chip select for the two banks pd 0 ? pd 1 presence detect output pins d[63:0] data lines from processor dp[7:0] data parity lines from processor clk[0:3] clock lines to the module adv/ld advance load signal from processor mode mode pin for burst selection nc signal not connected on module rsvd reserved presence detect pins pd 1 pd 0 cym9288 - 512k x 72 nc nc cym9289 - 1m x 72 gnd gnd
cym9288/cym9289 document #: 38-05062 rev. ** page 5 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ? 55 c to +125 c ambient temperature with power applied 0 c to +70 c supply voltage to ground potential ? 0.5v to +4.5v dc voltage applied to outputs in high z state ? 0.5v to +4.6v dc input voltage ? 0.5v to +4.6v output current into outputs (low)20 ma ................................................................. operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 5% electrical characteristics over the operating range parameter description test condition min. max. unit v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ? 0.3 0.8 v v oh output high voltage v cc = min. i oh = ? 4 ma 2.4 v v ol output low voltage v cc = min. i ol = 8 ma 0.4 v i cc (9288) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 2400 ma i cc (9289) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 2400 ma capacitance [1] parameter description test conditions max. unit c a address input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 48 pf c i control input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 48 pf c o input/output capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 16 pf c clk clock capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 12 pf note: 1. tested initially and after any design or process changes that may affect these parameters. 3.0v gnd output r=317 ? r=351 ? 5pf including jig and scope (a) (b) all input pulses output r l =50 ? z 0 =50 ? v l = 1.5v 3.3v ac test loads and waveforms
cym9288/cym9289 document #: 38-05062 rev. ** page 6 of 11 switching characteristics over the operating range [2] 60 66 parameter description min. max. min. max. unit clock t cyc clock cycle time 16.6 15.0 ns f max maximum operating frequency 60 66 mhz t ch clock high 6.0 5.0 ns t cl clock low 6.0 5.0 ns output times t cdv data output valid after clk rise 12 10.5 ns t eov oe low to output valid [3, 5] 6 6 ns t doh data output hold after clk rise 1.5 1.5 ns t chz clock to high-z [3, 4, 5] 5.0 5.0 ns t clz clock to low-z [3, 4, 5] 3.0 2.0 ns t eohz oe high to output high-z [3, 4, 5] 6.0 6.0 ns t eolz oe low to output low-z [3, 4, 5] 0 0 ns setup times t as address set-up before clk rise 2.5 2.0 ns t ds data input set-up before clk rise 2.5 2.0 ns t wes we , bwe [7:0] set-up before clk rise 2.5 2.0 ns t als adv/ld set-up before clk rise 2.5 2.0 ns t ces chip selects set-up 2.5 2.0 ns hold times t ah address hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t weh we , bwe [7:0] hold after clk rise 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 ns t ceh chip selects hold after clk rise 0.5 0.5 ns notes: 2. ac test conditions assume signal transition time of 2 ns or less, timing reference levels, input pulse levels and output load ing shown in part (a) of ac test load for 3.3v devices and (c) for 2.5v devices. 3. t chz , t clz , t oev , t eolz , and t eohz are specified with ac test conditions shown in part (a) of ac test loads. transition is measured 200 mv from steady-state voltage. 4. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 5. this parameter is sampled and not 100% tested.
cym9288/cym9289 document #: 38-05062 rev. ** page 7 of 11 switching waveforms read/write/deselect timing cen clk[0:3] address ce[0:1] we & 1a data- in/out t cyc t ch t cl t cens t cenh ra1 t ah t as t ws t wh t ces t ceh t cdv q4 q1 = don ? t care = undefined we is the combination of we & bwe x to define a write cycle (see write cycle description table). out d2 in d5 in out read write deselect write read read read ignore read deselect deselect wa2 ra3 ra4 wa5 ra6 ra7 t clz t doh 1a q3 out t chz rax stands for read address x, wax stands for device originally deselected write address x, dx stands for data-in x, qx stands for data-out x. q7 out t chz t cens t cenh t doh q6 out bwe[7:0]
cym9288/cym9289 document #: 38-05062 rev. ** page 8 of 11 read/write/deselect timing switching waveforms (continued) adv/ld clk[0:3] address ce[1:0] 1a data- in/out t cyc t ch t cl t als t alh ra1 t ah t as t ces t ceh t cdv q1 = don ? t care = undefined the combination of we & bwe [7:0] define a write cycle. out begin read burst read t clz t doh rax stands for read address x, wax stands for device originally deselected write address x, dx stands for data-in for location x, qx stands for data-out for location x. cen held wa2 q1+1 out q1+2 out q1+3 out ra3 t clz t chz d2+1 in d2+2 in d2+3 in d2 in t cdv q3 out t ds t dh burst read burst read begin write burst write burst write burst write begin read burst read burst read burst sequences bwe [7:0] t ws t wh we t ws t wh low. during burst writes, byte writes can be conducted by asserting the appropriate bwe [7:0] input signals. burst order determined by the state of the mode input. cen held low. oe held low. out q1+1
cym9288/cym9289 document #: 38-05062 rev. ** page 9 of 11 switching waveforms (continued) oe three-state i/o ? s oe timing t eohz t eov t eolz ordering information speed (mhz) ordering code package name package type description operating range 60 CYM9288Apz-60c pz12 168-pin quad-row zip flowthrough nobl 512k x 72 commercial 66 CYM9288Apz-66c flowthrough nobl 512k x 72 60 cym9289bpz-60c pz12 168-pin quad-row zip flowthrough nobl 1m x 72 commercial 66 cym9289bpz-66c flowthrough nobl 1m x 72
cym9288/cym9289 document #: 38-05062 rev. ** page 10 of 11 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams pz12: 168 pin quad row zip module
cym9288/cym9289 document #: 38-05062 rev. ** page 11 of 11 document title: cym9288, cym9289 512k/ 1m x 72 flowthrough nobl sram module document number: 38-05062 rev. ecn no. issue date orig. of change description of change ** 107254 09/15/01 szv change from spec number: 38-m-00092 to 38-05062

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