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| it8152f / IT8152G advanced risc - to - pci companion chip preliminary specification v0.3.4
copyright ? 2001 ite, inc. this is preliminary document release. all specifications are subject to change without notice. the material containe d in this document supersedes all previous documentation issued for the related products included herein. please contact ite, inc. for the latest document(s). all sales are subject to ite?s standard terms and conditions, a copy of which is included in the back of this document. ite, it8152f/IT8152G is a trademark of ite, inc. intel strongarm is a trademark claimed by intel corporation. all other trademarks are claimed by their respective owners. all specifications are subject to change without notice. add itional copies of this manual or other ite literature may be obtained from: ite, inc. phone: (02) 2657 - 9896 marketing department fax: (02) 2657 - 8561, 2657 - 8576 7f, no. 435, nei hu district, jui kuang rd., taipei 114, taiwan, r.o.c. ite (usa) inc. phone: (408) 530 - 8860 marketing department fax: (408) 530 - 8861 1235 midas way sunnyvale, ca 94086 u.s.a. ite (usa) inc. phone: (512) 388 - 7880 eastern u.s.a. sales office fax: (512) 388 - 3108 896 summit st., #105 round rock, tx 78664 u.s.a. if you have any marketing or sales questions, please contact: lawrence liu, at ite taiwan: e - mail: lawrence.liu@ite.com.tw , tel: 886 - 2 - 26579896 x6071, fax: 886 - 2 - 26578561 david lin , at ite u.s.a: e - mail: david.lin@iteusa.com , tel: (408) 530 - 8860 x238, fax: (408) 530 - 8861 don gardenhire , at ite eastern usa office: e - mail: don.gardenhire@iteusa. com tel: (512) 388 - 7880, fax: (512) 388 - 3108 to find out more about ite, visit our world wide web at: http://www.ite.com.tw http://www.iteusa.com or e - mail itesupport@ite.com.tw for more product information/ services. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 1 revision history revision history section revision page no. 1, 2 l remove the next generation xscale cpu support. 1, 3 5 l the sdclk attribute was revised from od12 to ot24 in table 5 - 2. 17 l the ot24 description was added in i/o cell section. 22 7 l the pcicr d efault was revised to 00000168h in table 7 - 1. 32 l bit 0 description was revised in section 7.2.1 sdram control register. 33 l the default value of bit 7 was revised to 0 in section 7.2.2 pci slave control register. l the default value of bit 3 was revised t o 1000 in section 7.2.2 pci slave control register. 34 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com i contents contents 1. features ................................ ................................ ................................ ................................ ................................ 1 2. general description ................................ ................................ ................................ ................................ ............. 3 3. system block diagram ................................ ................................ ................................ ................................ ........ 5 3.1 block diagra m ................................ ................................ ................................ ................................ ....... 5 3.2 system address space ................................ ................................ ................................ ........................ 6 3.3 internal registers address map ................................ ................................ ................................ ........... 7 3.4 pci memory space and configuration space map ................................ ................................ ............ 8 3.5 pci io space map ................................ ................................ ................................ ................................ 9 4. pin configuration ................................ ................................ ................................ ................................ ................ 11 4.1 208 - pin pqfp ................................ ................................ ................................ ................................ ...... 11 4.2 208 - pin lbga (top view) ................................ ................................ ................................ .................. 12 4.3 208 - pinlbga (bottom view) ................................ ................................ ................................ .............. 13 5. it8152f/IT8152G pin descriptions ................................ ................................ ................................ .................. 17 6. power management ................................ ................................ ................................ ................................ ........... 23 6.1 overview ................................ ................................ ................................ ................................ .............. 23 6.2 features ................................ ................................ ................................ ................................ ............... 23 6.3 clock tree block diagram ................................ ................................ ................................ .................. 23 6.4 register descriptions ................................ ................................ ................................ .......................... 24 6.4.1 device standby register (dsr) ? offset 0x00 ................................ ................................ .. 25 6.4.2 device software reset register (dsrr) ? offset 0x04 ................................ ................... 25 6.4.3 device test mode register (dtmr) ? offset 0x08 ................................ ........................... 26 6.4.4 pci clkrun option register (pcor) ? offset 0x0c ................................ ...................... 27 6.4.5 pll control register (pllcr) ? offset 0x20 ................................ ................................ .... 28 6.4.6 mclk frequency select register (mfsr) ? offset 0x24 ................................ ................. 29 6.4.7 debug port register (dpr) ? offset 0x40 ................................ ................................ ......... 29 6.4.8 software interrupt port register (sipr) ? offset 0x44 ................................ ..................... 29 7. memory controller ................................ ................................ ................................ ................................ .............. 31 7.1 overview ................................ ................................ ................................ ................................ .............. 31 7.1.1 features ................................ ................................ ................................ ................................ . 31 7.1.2 block diagram ................................ ................................ ................................ ........................ 31 7.1.3 register configuration ................................ ................................ ................................ ........... 32 7.2 register descriptions ................................ ................................ ................................ .......................... 33 7.2.1 sdram control register (sdcr) ? offset 0x00 ................................ ................................ 33 7.2.2 pci slave control register (pcicr) ? offset 0x04 ................................ .......................... 34 7.3 opera tions ................................ ................................ ................................ ................................ ........... 34 7.3.1 pci to memory interface (p2m) ................................ ................................ ............................ 34 7.3.2 dma arbiter ................................ ................................ ................................ ............................ 35 7.3.3 shared sdram controller ................................ ................................ ................................ .... 35 7.3.4 pci to internal rab bus inte rface ................................ ................................ ........................ 35 7.3.5 rab bus arbiter ................................ ................................ ................................ ..................... 35 8. cpu to pci bridge ................................ ................................ ................................ ................................ ............. 37 8.1 overview ................................ ................................ ................................ ................................ .............. 37 8.2 features ................................ ................................ ................................ ................................ ............... 37 8.3 block diagra m ................................ ................................ ................................ ................................ ..... 37 8.4 register description ................................ ................................ ................................ ............................ 38 8.4.1 pci configuration registers ................................ ................................ ................................ . 40 8.4.1.1 configuration address register (confaddr) ? address 0x43f00800 ............. 41 8.4.1.2 configuration data register (confdata) ? address 0x43f00804 .................... 41 8.4.2 pci command registers ................................ ................................ ................................ ...... 41 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com ii it81 52f/IT8152G 8.4.2.1 pci interrupt acknowledge cycle (piac) ? address 0x43f00808 ....................... 41 8.4.2.2 pci special cycle (psc) ? address 0x43f0080c ................................ ................. 42 8.4.3 cpu/pci bridge configuration registers (function 0) ................................ ....................... 42 8.4.3.1 vendor identification register (vid) ? offset 0x00 - 01 ................................ ........... 42 8.4.3.2 device identification register (did) ? offset 0x02 - 0x03 ................................ ....... 42 8.4.3.3 pci command register (pcicmd) ? offset 0x04 - 0x05 ................................ ........ 43 8.4.3.4 pci status register (pcists) ? offset 0x06 - 0x07 ................................ ................ 44 8.4.3.5 revision id register (rid) ? offset 0x08 ................................ ............................... 44 8.4.3.6 class code register (classc) ? offset 0x09 - 0x0b ................................ ............ 44 8.4.3.7 header type register (head t) ? offset 0x0e ................................ ...................... 45 8.4.3.8 pci memory base address register (pmbar) ? offset 0x10 .............................. 45 8.4.3.9 pci i/o base address register (piobar) ? offset 0x14 ................................ ...... 45 8.4.3.10 pci mem ory address prefix register for bank 4 (pmapr4) ? offset 0x40 ........ 4 5 8.4.3.11 pci memory address prefix register for bank 5 (pmapr5) ? offset 0x44 ........ 45 8.4.3.12 pci i/o address prefix register (pioapr) ? offset 0x48 ................................ ..... 46 8.4.3.13 prefetch control register (pcr) ? offset 0x4c ................................ ..................... 46 8.4.3.14 partial read base address register n (prbarn) ................................ .................. 46 8.4.3.15 partial read control reg ister n (prcrn) ................................ ................................ 47 9. pci - to - lpc bridge ................................ ................................ ................................ ................................ ............. 49 9.1 overview ................................ ................................ ................................ ................................ .............. 49 9.2 features ................................ ................................ ................................ ................................ ............... 49 9.3 configuration register description ................................ ................................ ................................ .... 50 9.3.1 vendor identification register (vid) ? offset 0x00 - 0x01 ................................ .................. 50 9.3.2 device identification register (did) ? offset 0x02 - 0x03 ................................ ................... 50 9.3.3 pci command register (pcicmd) ? offset 0x04 - 0x05 ................................ ................... 51 9.3.4 pci status register (pcists) ? offset 0x06 - 0x07 ................................ ........................... 52 9.3.5 revision id register (rid) ? offset 0x08 ................................ ................................ .......... 52 9.3.6 class code register (classc) ? offset 0x09 - 0x0b ................................ ........................ 52 9.3.7 header type register (headt) ? offset 0x0e ................................ ................................ . 53 9.3.8 base address register (bar) ? offset 0x10 ................................ ................................ ..... 53 9.3.9 serial irq control register (serirqc) ? offset 0x49 ................................ .................... 53 9.3.10 bridge control register (bcr) ? offset 0x4c ................................ ................................ .... 54 9.3.11 bridge status register (bsr) ? offset 0x4d ................................ ................................ ..... 55 9.3.12 discard timer register (dtr) ? offset 0x4f ................................ ................................ ..... 55 9.3.13 lpc i/o space base address register (lisbar) ? offset 0x50 ................................ ..... 55 10. chaining dma controller ................................ ................................ ................................ ................................ ... 57 10.1 overview ................................ ................................ ................................ ................................ .............. 57 10.2 features ................................ ................................ ................................ ................................ ............... 57 10.3 block diagram ................................ ................................ ................................ ................................ ..... 57 10.4 dma operation ................................ ................................ ................................ ................................ .... 58 10.4.1 non - chaining mode dma ................................ ................................ ................................ ..... 58 10.4.2 chaining mode dma ................................ ................................ ................................ ............. 59 10.5 regist er description ................................ ................................ ................................ ............................ 60 10.5.1 cdma configuration registers (function 1) ................................ ................................ ....... 62 10.5.1.1 vendor identification register (vid) ? vid, offset 0x00 - 0x11 .............................. 62 10.5.1.2 device identif ication register (did) ? did, offset 0x02 - 0x03 .............................. 62 10.5.1.3 pci command register (pcicmd) ? pcicmd, offset 0x04 - 0x05 ....................... 62 10.5.1.4 pci status register (pcists) ? pcists, offset 0x06 - 0x07 ................................ 63 10.5.1.5 revision id register (rid) ? rid, offset 0x08 ................................ ...................... 63 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com iii contents 10.5.1.6 class code register (classc) ? classc, offset 0x09 - 0x0b ........................... 63 10.5.1.7 latency timer register (lt) ? lt, offset 0x0d ................................ ..................... 64 10.5.1.8 base address register (bar) ? bar, offset 0x10 ................................ ................ 64 10.5.2 cdma operation registers ................................ ................................ ................................ .. 64 10.5.2.1 memory address register of channel n (marn) ................................ ..................... 64 10.5.2.2 device address register of channel n (darn) ................................ ....................... 64 10.5.2.3 byte count register of channel n (bcrn) ................................ ............................... 65 10.5.2.4 descriptor pointer register of channel n (dprn) ................................ ................... 65 10.5.2.5 mode register of channel n (mrn) ................................ ................................ .......... 66 10.5.2.6 command/status register of channel n (csrn) ................................ .................... 67 10.5.2.7 priority type register (ptr) ? ptr, i/o offset 0x60 ................................ ............ 67 11. audio digital controller ................................ ................................ ................................ ................................ ...... 69 11.1 overview ................................ ................................ ................................ ................................ .............. 69 11.2 features ................................ ................................ ................................ ................................ ............... 69 11.3 block diagram ................................ ................................ ................................ ................................ ..... 69 11.4 configuration regis ter descriptions ................................ ................................ ................................ .. 70 11.4.1 device/vendor identification register (did/vid) ................................ ................................ . 71 11.4.2 pci status/command register (pcists/pcicmd) ................................ ........................... 71 11.4.3 class code/revision id regi sters (classc/rid) ................................ ............................. 72 11.4.4 bist/header type/latency timer/cache line size registers (bist/headt/lt/cals) 72 11.4.5 base address register (bar) ? offset 0x10 ................................ ................................ ..... 73 11.4 .6 sub - system vendor id register (svid) ? offset 0x2c ................................ ..................... 73 11.4.7 sub - system id register (sid) ? offset 0x2e ................................ ................................ ..... 73 11.4.8 capability pointer register (cp) ? offset 0x34 ................................ ................................ . 73 11.4.9 interrupt line register (ilr) ? offset 0x3c ................................ ................................ ........ 73 11.4.10 interrupt pin register (ipr) ? offset 0x3d ................................ ................................ ......... 73 11.4.11 min grant period for pci burst period register (mgpbp) ? offset 0x3e ....................... 73 11.4.12 max latency for pci grant period register (mlpgp) ? offset 0x3f .............................. 74 11.4.13 vendor id writeable register (vidw) ? offset 0x98 ................................ ........................ 74 11.4.14 device id writeable register (didw) ? offset 0x9a ................................ ........................ 74 11.4.15 sub - system vendor id writeable register (svidw) ? offset 0x9c ................................ 74 11.4.16 sub - system id writeable register (sidw) ? offset 0x9e ................................ ................ 74 11.4 .17 dfc reset control register (drc) ? offset 0xa0 ................................ ............................ 74 11.4.18 capability id register (cid) ? offset 0xdc ................................ ................................ ....... 74 11.4.19 next item pointer register (nip) ? offset 0xdd ................................ ................................ 75 11.4.20 power management capability register (pmc) ? offset 0xde ................................ ....... 75 11.4.21 power management control/status register (pmcs) ? offset 0xe0 .............................. 75 11.5 operation register description ................................ ................................ ................................ .......... 76 11.5.1 playback channel control register (pcc) ? offset 0x08 ................................ ................. 77 11.5.2 playback channel data length/current count register (pcdl/cc) ? offset 0x0a ...... 78 11.5.3 playback channel buffer i system starting address register (pcb1sta) ? offset 0x0c ................................ ................................ ................................ ................................ ................ 78 11.5.4 playback channel buffer ii system starting address register (pcb2sta) ? offset 0x10 ................................ ................................ ................................ ................................ ................ 78 11.5.5 capture channel control registe r (capcc) ? offset 0x14 ................................ ............. 78 11.5.6 capture channel data length/current count register (capcdl/cc) ? offset 0x16 ... 79 11.5.7 capture channel buffer i system starting address register (capb1sta) ? offs et 0x18 ................................ ................................ ................................ ................................ ................ 79 11.5.8 capture channel buffer ii system starting address register (capb2sta) ? offset 0x1c www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com iv it81 52f/IT8152G ................................ ................................ ................................ ................................ ................ 79 11.5.9 codec control register (codecc) ? offset 0x22 ................................ ............................ 79 11. 5.10 codec index register command port (circp) ? offset 0x2a ................................ ........ 80 11.5.11 codec index register data port (cirdp) ? offset 0x2c ................................ .................. 80 11.5.12 pci fifo data port register (pfdp) ? offset 0x4c ................................ ......................... 80 11.5.13 general control register (gc) ? offset 0x54 ................................ ................................ .... 80 11.5.14 interrupt mask control register (imc) ? offset 0x56 ................................ ........................ 80 11.5.15 interrupt status/clear register (isc) ? offset 0 x5b ................................ .......................... 81 11.5.16 blocks power down control register (bpdc) ? offset 0x70 - 0x71 ................................ . 81 11.6 protocol and data flow ................................ ................................ ................................ ...................... 81 11.6.1 codec dac and adc data access ................................ ................................ ...................... 81 11.6.2 codec control register access ................................ ................................ ............................ 81 11.6.3 directsound playback ................................ ................................ ................................ ........... 82 11.6.4 directsound recording ................................ ................................ ................................ ......... 82 12. usb host controller ................................ ................................ ................................ ................................ ........... 83 12.1 introduction ................................ ................................ ................................ ................................ .......... 83 12.1.1 device description/purpose ................................ ................................ ................................ .. 83 12.1.2 reference information ................................ ................................ ................................ ........... 83 12.2 function description ................................ ................................ ................................ ........................... 83 12.2.1 us b block diagram ................................ ................................ ................................ ............... 83 12.2.2 usb host controller ................................ ................................ ................................ .............. 84 12.2.2.1 usb states ................................ ................................ ................................ ................. 84 12.2.2.1.1 usb operational ................................ ................................ .................. 85 12.2.2.1.2 usb reset ................................ ................................ ............................ 85 12.2.2.1.3 usb suspend ................................ ................................ ...................... 85 12.2.2.1.4 usb resume ................................ ................................ ....................... 86 12.2.2.2 list processing ................................ ................................ ................................ ........... 86 12.2.2.2.1 list control block ................................ ................................ ................. 86 12.2 .2.2.1.1 priority ................................ ................................ ....................... 86 12.2.2.2.1.1.1 list priority ................................ ................................ ... 87 12.2.2.2.1.2 interface to ed block ................................ ............................... 88 12.2.2.2.2 ed block ................................ ................................ ............................... 88 12.2.2.2.2.1 list serv ice flow ................................ ................................ ...... 88 12.2.2.2.2.2 endpoint descriptor processing ................................ .............. 91 12.2.2.2.2.3 interface to the td block ................................ ......................... 92 12.2.2.2.2.4 operational registers ................................ .............................. 92 12.2.2.2.2.5 descriptor registers ................................ ................................ . 93 12.2.2.2.3 td block ................................ ................................ ............................... 93 12.2.2.2.3.1 transfer descriptor processing ................................ ............... 93 12.2.2.2.3.1.1 isochronous relative frame number calcula tion .... 95 12.2.2.2.3.1.2 isochronous packet begin and end address calculation ................................ ................................ ... 96 12.2.2.2.3.1.3 general last packet calculation ................................ 96 12.2.2.2.3.1.4 general packet begin a nd end address calculation 97 12.2.2.2.3.1.5 transfer descriptor size calculation ......................... 97 12.2.2.2.3.1.6 status writeback ................................ ......................... 97 12.2.2.2.3.1.7 transfer descriptor retirement ................................ 100 12.2.2.2.3.1.8 done queue ................................ .............................. 101 12.2.2.2.3.2 operational registers ................................ ............................ 101 12.2.2.2.3.3 descriptor registers ................................ ............................... 101 12.2.2.2.3.3.1 dword0 ................................ ................................ ....... 102 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com v contents 12.2.2.2.3.3.2 dword1 ................................ ................................ ....... 103 12.2.2.2.3.3.3 dword2 ................................ ................................ ....... 104 12.2.2.2.3.3.4 dword3 ................................ ................................ ....... 104 12.2.2.2.3.3.5 offset0 ................................ ................................ ....... 105 12.2.2.2.4 request block ................................ ................................ .................... 105 12.2.2.2.4.1 master arbitration ................................ ................................ ... 105 12.2.2.2.4.2 data and control muxing ................................ ....................... 106 12.2.2.3 frame management ................................ ................................ ................................ . 106 12.2.2.3.1 operational registers ................................ ................................ ........ 106 12.2.2.3.1.1 hcfmlnterval register ................................ ........................... 107 12.2.2.3.1.2 hcfmremaining register ................................ ...................... 107 12.2.2.3.1.3 hcfmnumber register ................................ .......................... 107 12.2.2.3.1.4 hcperiodicstart register ................................ ....................... 107 12.2.2.3.1.5 hclsthreshold register ................................ ........................ 108 12.2.2.3.2 packet size check ................................ ................................ ............ 108 12.2.2.3.2.1 full speed check ................................ ................................ .... 108 12.2.2.3.2.2 low speed check ................................ ................................ .. 108 12.2.2.3.3 transaction requests ................................ ................................ ....... 109 12.2.2.4 interrupt processing ................................ ................................ ................................ . 109 12.2.2.4.1 schedulingoverrun even t ................................ ................................ . 109 12.2.2.4.2 writebackdonehead event ................................ ............................... 109 12.2.2.4.3 startofframe event ................................ ................................ ........... 109 12.2.2.4.4 resumedetected event ................................ ................................ .... 110 12.2.2.4.5 unrecovera bleerror event ................................ ................................ 110 12.2.2.4.6 framenumberoverflow event ................................ .......................... 110 12.2.2.4.7 roothubstatuschange event ................................ ........................... 110 12.2.2.5 host controller bus master ................................ ................................ ..................... 110 12.2.2.5.1 bus master controller ................................ ................................ ........ 111 12.2.2.5.2 data buffer engine ................................ ................................ ............ 112 12.2.2.5.3 page crossing controller ................................ ................................ .. 112 12.2.2.6 data buffer (db) ................................ ................................ ................................ ....... 113 12.2.3 usb interface ................................ ................................ ................................ ....................... 113 12.2.3.1 serial interface engine (sie) ................................ ................................ ................... 113 12.2.3.1.1 sie control ................................ ................................ ......................... 114 12.2.3.1.2 packet control ................................ ................................ ................... 114 1 2.2.3.1.2.1 sync pattern ................................ ................................ ........... 114 12.2.3.1.2.2 end of packet (eop) ................................ .............................. 114 12.2.3.1.2.3 packet identifier (pid) ................................ ............................ 114 12.2.3.1.2.4 token packet ................................ ................................ .......... 116 12.2.3.1.2.5 data packet ................................ ................................ ............ 117 12.2.3.1.2.6 handshake packet ................................ ................................ . 117 12.2.3.1.2.7 preamble packet ................................ ................................ .... 118 12.2.3.1.3 serializer ................................ ................................ ............................ 118 12.2.3.1.3.1 data ................................ ................................ ......................... 119 12.2.3.1.3.2 crc generator/checker ................................ ....................... 120 12.2.3.1.3.3 bit stuffing ................................ ................................ ............... 121 12.2.3.1.3.4 data encoding/decoding (nrzi) ................................ ........... 121 12.2.3.1.3. 5 receiver ................................ ................................ .................. 122 12.2.3.1.4 bus protocol ................................ ................................ ....................... 123 12.2.3.1.4.1 non - isochronous transactions ................................ ............. 123 12.2.3.1.4.2 isochronous transfers ................................ ........................... 124 12.2.3.1 .4.3 packet to packet timing ................................ ........................ 124 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com vi it81 52f/IT8152G 12.2.3.1.4.3.1 back to back host packets ................................ ...... 124 12.2.3.1.4.3.2 response turnaround ................................ .............. 125 12.2.3.1.4.3.3 host response time - out ................................ .......... 125 12.2.3.1.4.3.4 packet error time - out ................................ ............... 125 12.2.3.1.4.4 frame timing (sof, eof) ................................ .................... 125 12.2.3.1.4.5 data toggle synchronization ................................ ................ 125 12.2.3.1.4.6 fal se eop ................................ ................................ ............... 126 12.2.3.1.4.7 packet error ................................ ................................ ............ 126 12.2.3.1.4.8 internal buffer errors ................................ .............................. 126 12.2.3.1.4.9 logical buffer errors ................................ .............................. 126 12.2.3.1.4.10 tr ansaction completion status ................................ ............. 127 12.2.3.2 root hub ................................ ................................ ................................ ................... 129 12.2.3.2.1 hub control ................................ ................................ ........................ 130 12.2.3.2.1.1 power switching ................................ ................................ ..... 130 12.2.3.2.1.2 over - curr ent protection ................................ ......................... 130 12.2.3.2.1.3 reset ................................ ................................ ....................... 130 12.2.3.2.1.4 suspend ................................ ................................ .................. 130 12.2.3.2.1.5 resume ................................ ................................ ................... 131 12.2.3.2.1.6 wakeup events ................................ ................................ ...... 131 12.2.3.2.1.7 low speed eop ................................ ................................ ..... 131 12.2.3.2.2 port control ................................ ................................ ........................ 131 12.2.3.2.2.1.1 connect/disconnect ................................ .................. 131 12.2.3.2.2.2 reset ................................ ................................ ....................... 132 12.2.3.2.2.3 enabled/disabled ................................ ................................ ... 132 12.2.3.2.2.4 suspend/resume ................................ ................................ ... 132 12.2.3.2.3 interrupts ................................ ................................ ............................ 132 12.2.3.3 clock generation ................................ ................................ ................................ ...... 133 12.2.3.3.1 sta tic sof clock ................................ ................................ ............... 133 12.2.3.3.2 data rate clock ................................ ................................ ................. 133 12.2.4 power down mode ................................ ................................ ................................ .............. 1 33 12.2.5 register/address summary ................................ ................................ ................................ 133 12.2.5.1 openhci registe rs description ................................ ................................ .............. 133 12.2.5.1.1 hc register summary ................................ ................................ ...... 134 12.2.5.1.2 hcrevision (hr) ? offset 0x00 ................................ ...................... 136 12.2.5.1.3 hccontrol (hc) ? offset 0x04 ................................ ........................ 136 12.2.5.1.4 hccommandstatus (hcs) ? offset 0x08 ................................ ....... 137 12.2.5.1.5 hcinterruptstatus (his) ? offset 0x0c ................................ ........... 137 12.2.5.1.6 hcinterruptenable (hie) ? offset 0x10 ................................ ........... 138 12.2.5.1.7 hcinteruptdisable (hid) ? offset 0x14 ................................ ........... 139 12.2.5.1.8 hchcca (hhcca) ? offset 0x18 ................................ ................... 139 12.2.5.1.9 hcperiodcurrnted (hpced) ? offset 0x1c ................................ .. 139 12.2.5.1.10 hcc ontrolheaded (hched) ? offset 0x20 ................................ ... 140 12.2.5.1.11 hccontrolcurrented (hcced) ? offset 0x24 ............................... 140 12.2.5.1.12 hcbulkheaded (hbhed) ? offset 0x28 ................................ ........ 140 12.2.5.1.13 hcbulkc urrented (hbced) ? offset 0x2c ................................ .... 140 12.2.5.1.14 hcdonehead (hdh) ? offset 0x30 ................................ ................. 140 12.2.5.1.15 hcfminterval (hfi) ? offset 0x34 ................................ ................... 141 12.2.5.1.16 hcframeremaining (hfr) ? offset 0x38 ................................ ...... 141 12.2.5.1.17 hcfmnumber (hfn) ? offset 0x3c ................................ ............... 141 12.2.5.1.18 hcperiodicstart (hps) ? offset 0x40 ................................ ............. 141 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com vii contents 12.2.5.1.19 hclsthreshold (hlst) ? offset 0x44 ................................ ............ 142 12.2.5.1.20 hcrhdescriptora (hrda) ? offset 0x48 ................................ ....... 142 12.2.5.1.21 hcrhdescriptorb (hrdb) ? offset 0x4c ................................ ....... 143 12.2.5.1.22 hcrhstatus (hrs) ? offset 0x50 ................................ ................... 144 12.2.5.1.23 hcrhportstatus (hrps) ? offset 0x54, 0x58 ............................... 145 13. uart ................................ ................................ ................................ ................................ ................................ 147 13.1 overview ................................ ................................ ................................ ................................ ............ 147 13.2 features ................................ ................................ ................................ ................................ ............. 147 13.3 seria l channel register descriptions ................................ ................................ .............................. 148 13.3.1 data registers ................................ ................................ ................................ ..................... 149 13.3.2 control registers (uier, uiir, ufcr, udll, udlm, ulcr) ................................ ......... 149 13.3.3 status registers ................................ ................................ ................................ ................... 155 13.4 reset ................................ ................................ ................................ ................................ .................. 156 13.5 programming ................................ ................................ ................................ ................................ ..... 157 13.5.1 programming sequence ................................ ................................ ................................ ...... 157 13.6 software reset ................................ ................................ ................................ ................................ .. 157 13.7 clock input operati on ................................ ................................ ................................ ....................... 157 13.8 fifo interrupt mode operation ................................ ................................ ................................ ........ 157 14. intc ................................ ................................ ................................ ................................ ................................ .. 159 14.1 overview ................................ ................................ ................................ ................................ ............ 159 14.2 features ................................ ................................ ................................ ................................ ............. 159 14.3 regist er descriptions ................................ ................................ ................................ ........................ 159 14.3.1 local device interrupt request registers (ldxnirr) ................................ ..................... 160 14.3.2 serial irq interrupt request registers (lpxnirr) ................................ .......................... 161 14.3.3 pci device interr upt request registers (pdxnirr) ................................ ....................... 162 14.3.4 local device interrupt mask registers (ldxnimr) ................................ .......................... 163 14.3.5 serial irq interrupt mask registers (lpxnimr) ................................ .............................. 164 14.3.6 pci dev ice interrupt mask registers (pdxnimr) ................................ ............................ 166 14.3.7 local device interrupt trigger mode register (ldnitr) ? offset 0x10 ........................ 167 14.3.8 serial irq interrupt trigger mode register (lpnitr) ? offset 0x30 ............................. 168 14.3.9 pci device interrupt trigger mode register (pdnitr) ? offset 0x50 ........................... 170 14.3.10 local device interrupt active level register (ldniar) ? offset 0x14 .......................... 172 14.3.1 1 serial irq interrupt active level register (lpniar) ? offset 0x34 ............................... 173 14.3.12 pci interrupt active level register (pdniar) ? offset 0x54 ................................ ......... 175 14.3.13 interrupt request type register (intc_typer) ? offset 0xfc ................................ ... 177 14.4 interrupt exception processing and priority ................................ ................................ .................... 178 15. timer ................................ ................................ ................................ ................................ ................................ . 179 15.1 overview ................................ ................................ ................................ ................................ ............ 179 15.2 features ................................ ................................ ................................ ................................ ............. 179 15.3 register configuration ................................ ................................ ................................ ...................... 179 15.4 register descriptions ................................ ................................ ................................ ........................ 180 15.4.1 timer n load register (tnldr) ................................ ................................ ........................ 180 15.4.2 timer n value register (tnvlr) ................................ ................................ ....................... 180 15.4.3 timer n control register (tnctr) ................................ ................................ .................... 181 15.4.4 timer n clear register (tnclr) ................................ ................................ ....................... 182 16. general purpose i/o port ................................ ................................ ................................ ................................ 183 16.1 overview ................................ ................................ ................................ ................................ ............ 183 16.2 features ................................ ................................ ................................ ................................ ............. 183 16.3 register configuration ................................ ................................ ................................ ...................... 183 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com viii it81 52f/IT8152G 16.4 register descriptions ................................ ................................ ................................ ........................ 184 16.4.1 port data registers (gpdr) ? gpdr offset 0x00 ................................ .......................... 184 16.4.2 general control register (gcr) ? gcr offset 0x02 ................................ ...................... 184 16.4.3 port control n registers (gpcnr) ................................ ................................ ..................... 185 16.4.4 port interrupt control registers (gpicr) ? gpicr offset 0 x0c ................................ ... 186 16.4.5 port interrupt status registers (gpisr) ? gpisr offset 0x0e ................................ ...... 188 17. dc characteristics ................................ ................................ ................................ ................................ ........... 189 18. ac characteristics ................................ ................................ ................................ ................................ ........... 191 19. package information ................................ ................................ ................................ ................................ ........ 197 19.1 qfp 208l outline dimensions ................................ ................................ ................................ ........ 197 19.2 lbga 208l outline dimensions ................................ ................................ ................................ ...... 198 20. ordering information ................................ ................................ ................................ ................................ ........ 199 timin g diagrams figure 18 - 1. cpu read cycle: read data timing ................................ ................................ .............................. 191 figure 18 - 2. cpu write cycle: write data timing ................................ ................................ .............................. 191 figure 18 - 3. smc address, control and read data timing ................................ ................................ .............. 192 figure 18 - 4. smc dqm, write data timing ................................ ................................ ................................ ........ 193 figure 18 - 5. cold reset timing ................................ ................................ ................................ ............................ 194 figur e 18 - 6. warm reset timing ................................ ................................ ................................ .......................... 194 figure 18 - 7. ac?97 sync and data timing ................................ ................................ ................................ .......... 195 figure 18 - 8. uart rx timing ................................ ................................ ................................ ............................... 196 figure 18 - 9. gpio interrupt timing (falling edge trigger) ................................ ................................ ................ 196 figure 18 - 10. gpio interrupt timing (rising edge trigger) ................................ ................................ ............... 196 figures figure 6 - 1. it8152 clock tree block diagram ................................ ................................ ................................ ...... 23 figure 7 - 1. memory controller block diagram ................................ ................................ ................................ ...... 31 figure 8 - 1. cpu to pci bridge block diagram ................................ ................................ ................................ ...... 37 figure 10 - 1. cdma syste m architecture ................................ ................................ ................................ ............... 57 figure 12 - 1 . usb states ................................ ................................ ................................ ................................ ......... 84 figure 12 - 2 . list priority within a usb frame ................................ ................................ ................................ ........ 8 6 figure 12 - 3 . control bulk service ratio of 4:1 ................................ ................................ ................................ ...... 87 figure 12 - 4 . list service flow ................................ ................................ ................................ ................................ 89 figure 12 - 5 . endpoint descriptor service flow ................................ ................................ ................................ ..... 91 figure 12 - 6 . endpoint descriptor ................................ ................................ ................................ ............................ 93 figure 12 - 7 . transfer descriptor servic e flow ................................ ................................ ................................ ...... 94 figure 12 - 8 . standard token packet format ................................ ................................ ................................ ...... 116 figure 12 - 9 . sof token packet format ................................ ................................ ................................ .............. 116 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com ix contents figure 12 - 10 . data packet format ................................ ................................ ................................ ....................... 117 fi gure 12 - 11 . handshake packet format ................................ ................................ ................................ ............ 117 figure 12 - 12 . preamble packet format ................................ ................................ ................................ ............... 118 figure 12 - 13 . serializer ................................ ................................ ................................ ................................ ......... 118 figure 12 - 14 . crc logic ................................ ................................ ................................ ................................ ....... 120 figure 12 - 15 . non - isochronous bus transaction ................................ ................................ ................................ 123 figure 12 - 16 . isochronous bus transaction ................................ ................................ ................................ ........ 124 tables table 4 - 1. pins listed in numeric order for 208 - pin pqfp (it8152f) ................................ ................................ 14 table 4 - 2. pins lis ted in numeric order for 208 - pin lbga (IT8152G) ................................ ............................... 15 table 5 - 1. pin descriptions of test mode select ................................ ................................ ................................ .. 17 table 5 - 2. pin descriptions of host bus interface ................................ ................................ ................................ . 17 table 5 - 3. pin descript ions of pci bus interface ................................ ................................ ................................ .. 18 table 5 - 4. pin descriptions of lpc host controller/gpio interface ................................ ................................ .... 19 table 5 - 5. pin descriptions of uart port interface ................................ ................................ .............................. 20 table 5 - 6. pin descriptions of digital ac link interface ................................ ................................ ....................... 20 table 5 - 7. pin descriptions of usb host controller interface ................................ ................................ .............. 21 table 5 - 8. pin descriptions of miscellaneous signals ................................ ................................ .......................... 21 table 5 - 9. pin descriptions of jtag interface signals ................................ ................................ ......................... 21 table 5 - 10. pin descriptions of power/ground signals ................................ ................................ ........................ 21 table 6 - 1. register list of system registers ................................ ................................ ................................ ........ 24 table 7 - 1. shared memory controller registers ................................ ................................ ................................ ... 32 table 8 - 1. list of pci configuration registers ................................ ................................ ................................ ...... 38 table 8 - 2 . list of pci command registers ................................ ................................ ................................ ........... 38 table 8 - 3 . list of cpu/pci b ridge configuration registers ................................ ................................ ................. 38 table 10 - 1. configuration register list of cdma controller ................................ ................................ ................ 60 table 10 - 2 . operation register list of cdma controller ................................ ................................ ...................... 60 table 12 - 1 . e xample calculation of r and host controller action ................................ ................................ ....... 95 table 12 - 2. itd packet offset location ................................ ................................ ................................ ................. 96 table 12 - 3 . completion codes ................................ ................................ ................................ ............................... 99 table 12 - 4 . dword0 gtd fields ................................ ................................ ................................ ........................... 102 table 12 - 5 . dword0 itd fields ................................ ................................ ................................ ............................. 102 table 12 - 6 . dword1 gtd fields ................................ ................................ ................................ ........................... 103 table 12 - 7 . dword1 itd fields ................................ ................................ ................................ ............................. 103 table 12 - 8 . dword2 fields ................................ ................................ ................................ ................................ .... 104 table 12 - 9 . dword3 gtd fields ................................ ................................ ................................ ........................... 104 table 12 - 10 . dword3 itd fields ................................ ................................ ................................ ........................... 104 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com x it81 52f/IT8152G table 12 - 11 . offset0 field description ................................ ................................ ................................ ................. 105 table 12 - 12 . list processor cont rol signals ................................ ................................ ................................ ....... 106 table 12 - 13 . transaction control information ................................ ................................ ................................ ..... 114 table 12 - 14 . pid encoding ................................ ................................ ................................ ................................ ... 115 table 12 - 15 . bus time - out periods ................................ ................................ ................................ ...................... 124 tab le 12 - 16 . sie eof timing requirements ................................ ................................ ................................ ...... 125 table 12 - 17 . sie completion status ................................ ................................ ................................ .................... 127 table 12 - 18 . in transaction error response ................................ ................................ ................................ ...... 128 table 12 - 19 . out transaction error res ponse ................................ ................................ ................................ .. 128 table 12 - 20 . hub/port commands ................................ ................................ ................................ ....................... 129 table 12 - 21 . power switching configurations ................................ ................................ ................................ ..... 130 table 12 - 22 . hc operational register summary ................................ ................................ ................................ 134 table 13 - 1. list of uart registers ................................ ................................ ................................ ...................... 148 table 14 - 1. list of interrupt controller module registers ................................ ................................ ................... 159 table 15 - 1. list of timer registers ................................ ................................ ................................ ...................... 179 table 16 - 1. list of general purpose i/o port pin function configurations ................................ ....................... 183 table 16 - 2. list of register configurations ................................ ................................ ................................ .......... 183 table 18 - 1. cpu interface read data timing table ................................ ................................ .......................... 191 table 18 - 2. cpu write cycle: write data timing table ................................ ................................ ..................... 195 table 18 - 3. smc address, control and read data timing table ................................ ................................ ..... 196 table 18 - 4. smc dqm, write data timing table ................................ ................................ ............................... 197 table 18 - 5. cold reset ac table ................................ ................................ ................................ ......................... 198 table 18 - 6. warm reset ac table ................................ ................................ ................................ ...................... 198 table 18 - 7. ac?97 sy nc and data ac table ................................ ................................ ................................ ....... 199 table 18 - 8. uart rx ac table ................................ ................................ ................................ ........................... 200 table 18 - 9. gpio ac table ................................ ................................ ................................ ................................ .. 200 www.ite.com.tw t8152f/IT8152G v0.3.4 www.iteusa.com advanced risc - to - pci companion chip specifications subject to change without notice by joe liu, itpm - pn - 200138, 11/1 /2001 1 features 1. features n cpu interface - supports intel strongarm series sa1110 32 - bit risc microprocessor interface n shared sdram controller - supports 16mb, 64mb, 128mb, 256mb sdram - supports up to 64mb memory - 32 - bit data bus interface - supports one bank of sdram shared with sa1110 microprocessor interface sdram controller - provides deep levels of pci to sdram buffers for burst transfer - up to 96 mhz bus operation n pci bus controller - 3 2 - bit data bus interface - supports pci rev. 2.1 specification - provides cpu to pci buffers for burst transfer - pci bus arbiter built in - supports up to 4 individual external bus master devices - supports clkrun# signal function - 33 mhz bus operation n interrupt controller - supports one maskable interrupt to risc processor - interrupt order is controlled by software - registers support interrupts masking and unmasking n chaining dma controller - four independent software dma channels - supports chaining mode and non - chainin g mode - supports both pci memory address and i/o address - supports rotating and fixed priority types - supports dma transfers of unaligned address n timers - 4 - channel 24 - bit auto - reloaded timer with pre - scale (1,1/16,1/256) for dividing cpu clock - supports the i nterrupt generation whenever the timer?s count reaches 0 n low pin count (lpc) host controller - compliant with intel lpc interface specification rev. 1.0 (sept. 29, 1997) - supports serial irq protocol - shared with gpio pins n digital ac?97 controller - directly interfaced to ac?97 codec for controlling voice data to the speaker or from the microphone n usb host controller - supports two usb ports - supports device bandwidth of 12 mbps or 1.5 mbps - supports power management mode to protect usb bus power, and overcurrent detector to protect usb bus from abnormal overcurrent load - fully compatible with usb specification version 1.1 and register compatible with ohci specification version 1.0 issued by microsoft, compaq and ns n uart - supports txd and rxd signals for serial dat a transfer, it is 16550 mode compatible - - n general purpose i/o (gpio) function - gpio pins can be programmed as inputs, outputs, or as interrupt inputs - interrupt events can be independently programmed to rising edge or falling edge trigger - maximum 8 bits fo r gpio functions n clock generator and pll - provides a pll from 12 mhz to 96 mhz for sdram controller - provides a pll from 12 mhz to 33 mhz for pci bus controller - clock generator and pll support standby mode n power management - software controllable power manag ement - intelligent power management to reduce power consumption - system wake up through interrupt, gpio pins n package: 208 - pin pqfp 208 - pin lbga www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 2 - - www.ite.com.tw it8152f/g v0.3.4 www.iteusa.com 3 general description 2. general description the it8152, an advanced risc - to - pci companion chip th at supports sa1110 32 - bit risc microprocessor interface, is especially designed for the main applications in datacomm, telecomm, and internet appliances and networking devices. this companion chip interfaces directly to risc processors, and provides a bri dge to link host bus and pci bus. it also provides a shared memory (sdram) controller, low pin count (lpc) host controller, interrupt controller, dma co n troller, timers, usb host controller, digital ac?97 controller, gpio controller and power management. paired with intel?s sa1110 risc microprocessor interface , the it8152 provides a low cost, high performance host to pci bridge function for any system applications in datacomm/telecomm products. the it8152 is available in two packages: 208 - pin pqfp and 208 - pin lbga. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 4 www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 5 block diagram 3. system block diagram 3.1 block diagram sdram h2r smc rab bus dma bus pci bus pci arbiter dma p2r p2d r2p intc uart audio arb pmu gpio r2i ite bus sa-1110 sdram usb lpc arb clkgen / pll tmr host bus www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 6 it81 52f/IT8152G 3.2 system address space sa-1110 memory space pci master memory view pci master i/o view 0x00000000 0x00000000 0x00000000 0x40000000 0x40000000 0x43e00000 0x43e00000 0x43e00000 0x43f00000 0x43f00000 0x43f00800 internal registers 0x43f00800 internal registers 0x43f00810 pci config/cmd 0x44000000 not decoded 0x48000000 0x48000000 0x4c000000 0x4c000000 0xc0000000 0xc0000000 0xc4000000 0xc4000000 0xffffffff 0xffffffff reserved relocatable not decoded pci memory 62mb pci io 1mb pci io 1mb pci memory 62mb pci memory 64mb not decoded shared memory 64mb shared memory 64mb not decoded pci memory 64mb cs4# cs5# www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 7 block diagram 3.3 internal registers address map system/pmu registers 0x43f00000-0x43f000ff 0x43f00810-0x43ffffff sdram control/r2p/p2r/p2d registers uart registers reserved intc registers timer registers gpio registers 0x43f00800-0x43f00807 pci configuration registers cpu memory space pci i/o space base address + 000 - base address + 0ff base address + 100 - base address + 1ff base address + 200 - base address + 2ff base address + 300 - base address + 3ff base address + 400 - base address + 4ff base address + 500 - base address + 5ff 0x43f00808-0x43f0080f pci command registers reserved base address + 600 - base address + 7ff note : the default pci i/o base address for internal registers is 0x43f00000. 0x43f00100-0x43f001ff 0x43f00200-0x43f002ff 0x43f00300-0x43f003ff 0x43f00400-0x43f004ff 0x43f00500-0x43f005ff 0x43f00600-0x43f007ff www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 8 it81 52f/IT8152G 3.4 pci memory space and configuration space map 0x40000000 reserved for 0x40000000 pci devices 0x40100000 pci memory usb host registers 0x43dfffff (cs4#) (relocatable) 0x40100fff reserved for pci devices 0x43dfffff 0x48000000 0x48000000 pci memory reserved for 0x4bffffff (cs5#) pci devices 0x4bffffff 0x00 0x43f00800 0x43f00804 conf_addr 1 pci configuration space conf_data 2 (256 bytes/device) 0xff notes: 1. pci configuration address register 2. pci configuration data register pci configuration space view www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 9 block diagram 3.5 pci io space map 0x43e00000 lpc devices (re-locatable) 0x43e00000 (subtractive-decoded) 0x43e10800 audio registers (re-locatable) 0x43e11000 pci i/o chain-dma registers (re-locatable) 0x43e11800 0x43efffff reserved 0x43e12000 0x43efffff reserved for pci devices notes: the it8152 is a multi - function (pci) device, i.e., only one idsel is provided. therefore, for a pci configuration cycle, all functions in the pci bus must decode the function numbers in addition to idsel. the function nu m bers a re assigned as follows: 1. the internal registers (pci bridge, uart, intc, pmu, timer, gpio that are hooked in the rab bus) is function 0. 2. the cdma controller is function 1. 3. the pci - to - lpc bridge is function 2. 4. the audio digital controller is funct ion 3. 5. the usb host controller is function 4. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 10 www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 11 pin configuration 4. pin configuration 4.1 208 - pin pqfp 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vcc3 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9 10 vcc3 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 vss 53 54 60 59 57 56 55 58 62 61 64 70 69 67 66 65 68 63 72 71 74 80 79 77 76 75 78 73 82 81 84 90 89 87 86 85 88 83 92 91 94 100 99 97 96 95 98 93 102 104 101 103 sdclk avss2 mclko pciclko vss d0 avcc2 d16 vcc3 d1 d17 d2 d18 vss d3 d19 d4 d20 d5 d21 vcc3 d6 d22 d7 d23 dqm0 dqm2 vss mrclk vss dqm1 dqm3 d8 d24 d9 d25 vcc3 d10 d26 d11 d27 d12 d28 vss d13 d29 d14 d30 d15 d31 vcc3 oe# we# reseti# bat_flt int mbreq mbgnt rdy a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 vss a10 a11 a12 cs4# sdcs# sdcas# sdras# vss a13 a14 a15 vcc3 vcc3 a16 a17 vss a18 a19 a20 a21 a22 a23 a24 a25 vss pad0 pad1 pad2 vcc3 pad3 pad4 pad5 pad6 pad7 cbe0# pad8 pad9 pad10 pad11 pad12 pad13 vcc3 pad14 pad15 cbe1# par serr# lock# avcc3 pciclki avss3 stop# vss devsel# trdy# irdy# frame# pci_cf cbe2# pad16 vcc3 pad17 pad18 pad19 pad20 pad21 pad22 vss pad23 idsel cbe3# pad24 pad25 pad26 vcc3 pad27 pad28 pad29 pad30 pad31 cs5# clkrun# gnt3# vss req3# gnt2# req2# gnt1# req1# phdla#/gnt# phold#/req# reseto# inta#/int# intb# intc# intd# acrst# acsync acdout acdin bitclk lad0/gpio0 lad1/gpio1 lad2/gpio2 lad3/gpio3 vss vss lframe#/gpio4 ldrq#/gpio5 vcc3 serirq/gpio6 dple/gpio7 vcc3 txd tdo trst# tclk tms tdi endian rxd usbpen# usbovr# avcc4 ud1p ud1m ud2p ud2m avss4 tst avcc1 ck12m ck12me avss1 vss it8152f 208-pin pqfp www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 12 it81 52f/IT8152G 4.2 208 - pin lbga (top view) a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t IT8152G 208-pin lbga avss2 avss5 d0 d1 d4 d5 d22 d7 dqm0 dqm1 d8 d9 d27 d12 oe# 1 avcc1 sdclk d16 d18 d20 d6 d23 mrclk dqm3 d25 d11 d14 d30 int 2 ud1m ck12m mclko avcc2 d2 d3 d21 dqm2 d24 d28 d10 d29 d15 bat_flt mbreq 3 ud1p tst ck12me avcc5 vcc3 d17 d19 d13 d26 d31 reseti# mbgnt a0 4 ud2m usbovr# endian avss1 vcc3 vcc3 we# rdy a1 5 ud2p rxd tms vss vss vss vss vcc3 a2 a4 a5 a7 6 trst# tclk usbpen# avss4 vcc3 a3 a6 a9 a10 7 dple/ gpio7 tdo tdi avcc4 vss vss a8 vss a11 a12 cs4# 8 ldrq# /gpio5 serirq /gpio6 vcc3 txd vss sdcs# sdcas# vss a13 vcc3 9 lad1/ gpio1 lad2/ gpio2 lad3/ gpio3 vss lframe#/ gpio4 sdras# a14 a16 vss a18 10 intd# acdout bitclk lad0/ gpio0 vss a15 a17 a21 pad1 11 acrst# acsync acdin vcc3 a19 a22 pad0 12 vss gnt2# reseto# intb# intc# vss vss vss vcc3 a20 a23 pad2 13 pad6 cbe0# vcc3 par pci_cf vcc3 pad24 pad29 gnt3# req2# phold#/ req# inta#/ int# vcc3 a24 14 pad3 pad5 pad8 pad13 serr# avcc3 devsel# pad17 pad22 cbe3# pad28 pad30 clkrun# gnt1# phdla#/ gnt# a25 15 pad4 pad9 pad12 pad15 lock# avss3 trdy# cbe2# pad18 idsel pad25 pad31 cs5# req1# pad20 16 pad7 pad10 pad11 pad14 cbe1# pciclki stop# irdy# frame# pad16 pad19 pad21 pad23 pad26 pad27 req3# pciclko www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 13 pin configuration 4.3 208 - pinlbga (bottom view) a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t IT8152G 208-pin lbga avss2 avss5 d0 d1 d4 d5 d22 d7 dqm0 dqm1 d8 d9 d27 d12 oe# 1 avcc1 sdclk d16 d18 d20 d6 d23 mrclk dqm3 d25 d11 d14 d30 int 2 ud1m ck12m mclko avcc2 pciclko d2 d3 d21 dqm2 d24 d28 d10 d29 d15 bat_flt mbreq 3 ud1p tst ck12me avcc5 vcc3 d17 d19 d13 d26 d31 reseti# mbgnt a0 4 ud2m usbovr# endian avss1 vcc3 vcc3 we# rdy a1 5 ud2p rxd tms vss vss vss vss vcc3 a2 a4 a5 a7 6 trst# tclk usbpen# avss4 vcc3 a3 a6 a9 a10 7 dple/ gpio7 tdo tdi avcc4 vss vss a8 vss a11 a12 cs4# 8 ldrq# /gpio5 serirq /gpio6 vcc3 txd vss sdcs# sdcas# vss a13 vcc3 9 lad1/ gpio1 lad2/ gpio2 lad3/ gpio3 vss lframe#/ gpio4 sdras# a14 a16 vss a18 10 intd# acdout bitclk lad0/ gpio0 vss a15 a17 a21 pad1 11 acrst# acsync acdin vcc3 a19 a22 pad0 12 vss gnt2# reseto# intb# intc# vss vss vss vcc3 a20 a23 pad2 13 pad6 cbe0# vcc3 par pci_cf vcc3 pad24 pad29 gnt3# req2# phold#/ req# inta#/ int# vcc3 a24 14 pad3 pad5 pad8 pad13 serr# avcc3 devsel# pad17 pad22 cbe3# pad28 pad30 clkrun# gnt1# phdla#/ gnt# a25 15 pad4 pad9 pad12 pad15 lock# avss3 trdy# cbe2# pad18 idsel pad25 pad31 cs5# req1# pad20 16 pad7 pad10 pad11 pad14 cbe1# pciclki stop# irdy# frame# pad16 pad19 pad21 pad23 pad26 pad27 req3# www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 14 it81 52f/IT8152G table 4 - 1 . pins listed in numeric order for 208 - pin pqfp (it8152f) pin signal pin signal pin signal pin signal 1 vcc3 53 oe# 105 vss 157 vcc3 2 avcc2 54 we# 106 pad7 158 req3# 3 sdclk 55 reseti# 107 cbe0# 159 gnt2# 4 avss2 56 bat_ flt 108 pad8 160 req2# 5 mclko 57 int 109 pad9 161 gnt1# 6 pciclko 58 mbreq 110 pad10 162 req1# 7 vss 59 mbgnt 111 pad11 163 phdla#/gnt# 8 d0 60 rdy 112 pad12 164 phold#/req# 9 d16 61 a0 113 pad13 165 reseto# 10 vcc3 62 a1 114 vcc3 166 inta#int# 11 d1 63 a2 115 pad14 167 intb# 12 d17 64 a3 116 pad15 168 intc# 13 d2 65 a4 117 cbe1# 169 intd# 14 d18 66 a5 118 par 170 acrst# 15 vss 67 a6 119 serr# 171 acsync 16 d3 68 a7 120 lock# 172 acdout 17 d19 69 a8 121 avcc3 173 acdin 18 d4 70 a9 122 pciclki 174 bitclk 19 d20 71 vss 123 avss3 175 lad0/gpio0 20 d5 72 a10 124 stop# 176 lad1/gpio1 21 d21 73 a11 125 vss 177 lad2/gpio2 22 vcc3 74 a12 126 devsel# 178 lad3/gpio3 23 d6 75 cs4# 127 trdy# 179 vss 24 d22 76 sdcs# 128 irdy# 180 vss 25 d7 77 sdcas# 129 frame# 181 lframe#/gpio4 26 d23 78 sdras# 130 pci_cf 182 ldrq#/gpio5 27 dqm0 79 vss 131 cbe2# 183 vcc3 28 dqm2 80 a13 132 pad16 184 serirq/gpio6 29 vss 81 a14 133 vcc3 185 dple/gpio7 30 mrclk 82 a15 134 pad17 186 vcc3 31 vss 83 vcc3 135 pad18 18 7 txd 32 dqm1 84 vcc3 136 pad19 188 tdo 33 dqm3 85 a16 137 pad20 189 trst# 34 d8 86 a17 138 pad21 190 tclk 35 d24 87 vss 139 pad22 191 tms 36 d9 88 a18 140 vss 192 tdi 37 d25 89 a19 141 pad23 193 endian 38 vcc3 90 a20 142 idsel 194 rxd 39 d10 91 a2 1 143 cbe3# 195 usbpen# 40 d26 92 a22 144 pad24 196 usbovr# 41 d11 93 a23 145 pad25 197 avcc4 42 d27 94 a24 146 pad26 198 ud1p 43 d12 95 a25 147 vcc3 199 ud1m 44 d28 96 vss 148 pad27 200 ud2p 45 vss 97 pad0 149 pad28 201 ud2m 46 d13 98 pad1 150 pad2 9 202 avss4 47 d29 99 pad2 151 pad30 203 tst 48 d14 100 vcc3 152 pad31 204 avcc1 49 d30 101 pad3 153 cs5# 205 ck12m 50 d15 102 pad4 154 clkrun# 206 ck12me 51 d31 103 pad5 155 gnt3# 207 avss1 52 vcc3 104 pad6 156 vss 208 vss www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 15 pin configuration table 4 - 2. pins liste d in numeric order for 208 - pin lbga (IT8152G) pin signal pin signal pin signal pin signal a1 ck12me d5 vcc3 j1 d7 n13 pad6 a2 ck12m d6 avss4 j2 d23 n14 pad8 a3 ud1p d7 avcc4 j3 dqm2 n15 pad12 a4 ud2m d8 vcc3 j4 vcc3 n16 pad14 a5 ud2p d9 lad1/gpio1 j5 vss p1 d27 a6 trst# d10 intd# j12 vss p2 d14 a7 dple/gpio7 d11 vcc3 j13 pci_cf p3 d15 a8 ldrq#/gpio5 d12 gnt2# j14 devsel# p4 reseti# a9 lframe#/gpio4 d13 gnt3# j15 trdy# p5 rdy a10 lad0/gpio0 d14 pad30 j16 irdy# p6 a4 a11 acdin d15 pad25 k1 dqm0 p7 a6 a12 intc# d16 pad23 k2 dqm1 p8 a11 a13 inta#/int# e1 d1 k3 d24 p9 a13 a14 phdla#/gnt# e2 d16 k4 d26 p10 a18 a15 req1# e3 d0 k5 vss p11 a21 a16 req3# e4 avcc2 k12 vss p12 pad0 b1 mclko e7 vss k13 par p13 pad2 b2 ud1m e8 vss k14 avcc3 p14 pad5 b3 tst e9 vss k15 avss3 p15 pad9 b4 usbovr# e10 vss k16 stop# p16 pad11 b5 rxd e13 vcc3 l1 mrclk r1 d12 b6 tclk e14 pad28 l2 dqm3 r2 d30 b7 tdo e15 idsel l3 d10 r3 bat_flt b8 serirq/gpio6 e16 pad21 l4 d13 r4 mbgnt b9 lad3/gpio3 f1 d4 l13 vcc3 r5 a1 b10 bitclk f2 d18 l14 serr# r6 a5 b11 acsync f3 d2 l15 lock# r7 a9 b12 intb# f4 avcc5 l16 pciclki r8 a12 b13 phold#/req# f13 pad29 m1 d8 r9 sdcas# b14 gnt1# f14 cbe3# m2 d25 r10 a14 b15 cs5# f15 pad20 m3 d28 r11 a17 b16 pad27 f16 pad19 m4 vcc3 r12 a22 c1 pciclko g1 d5 m7 vss r13 a23 c2 avss2 g2 d20 m8 vss r14 pad3 c3 avcc1 g3 d3 m9 vss r15 pad4 c4 endian g4 d17 m10 vss r16 pad10 c5 tms g5 vss m13 cbe0# t1 oe# c6 usbpen# g12 vss m14 pad13 t2 int c7 tdi g13 pad24 m15 pad15 t3 mbreq c8 txd g14 pad22 m16 cbe1# t4 a0 c9 lad2/gpio2 g15 pad18 n1 d9 t5 a2 c10 acdout g16 pad16 n2 d11 t6 a7 c11 acrst# h1 d22 n3 d29 t7 a10 c12 reseto# h2 d6 n4 d31 t8 cs4# c13 req2# h3 d21 n5 we# t9 sdcs# c14 clkrun# h4 d19 n6 vcc3 t10 sdras# c15 pad31 h5 vss n7 a3 t11 a15 c16 pad26 h12 vss n8 a8 t12 a19 d1 sdclk h13 vcc3 n9 vcc3 t13 a20 d2 avss5 h14 pad17 n10 a16 t14 a24 d3 vcc3 h15 cbe2# n11 pad1 t15 a25 d4 avss1 h16 frame# n12 vcc3 t16 pad7 www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 16 www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 17 it8152f/IT8152G pin descriptions 5. it8152f/IT8152G pin descriptions table 5 - 1 . pin descriptions of test mode select signal pin(s) no. pqfp pin(s) no. lbga attribute description test mode select (3.3v cmos i/f) tst 203 b3 i test mode enable. 0: disabled. 1: enabled. table 5 - 2 . pin descriptions of host bus interface signal pin(s) no. pqfp pin(s) no. lbga attribute description host bus interface (3.3v cmos i/f) mrclk 30 l1 i memory read access clock reference input. sdclk 3 d1 ot24 shared memory clock output t o sdram. this clock will be floating, if the chip is not accessing sdram right now. mclko 5 b1 o12 memory clock output for adjusting clock skew. this clock is always running. reseti# 55 p4 ik power on reset. reseto# 165 c12 o8 system reset output for all system reset. a[25:0] 95 - 88, 86, 85, 82 - 80, 74 - 72, 70 - 61 t15, t14, r13, r12, p11, t13, t12, p10, r11, n10, t11, r10, p9, r8, p8, t7, r7, n8, t6, p7, r6, p6, n7, t5, r5, t4 io12 26 - bit system address bus. t he a[24:10] will be as output pins when the i nternal dma or external pci master want to access the sdram. d[31:0] 51, 49, 47, 44, 42, 40, 37, 35, 26, 24, 21, 19, 17, 14, 12, 9, 50, 48, 46, 43, 41, 39, 36, 34, 25, 23, 20, 18, 16, 13, 11, 8 n4, r2, n3, m3, p1, k4, m2, k3, j2, h1, h3, g2, h4, f2, g4, e 2, p3, p2, l4, r1, n2, l3, n1, m1, j1, h2, g1, f1, g3, f3, e1, e3 io12 32 - bit system data bus. oe# 53 t1 i memory output enable of cpu. the output enable is active when the cpu read accesses right now. we# 54 n5 io12 memory write enable. when the as ic is the slave of cpu write transfer, the pin is input signal and it pairs with dqm[3:0] to specify byte write. on the other hand, when the asic writes data to sdram, the pin is output signal and is connected to we# pin of sdram. dqm[3:0] 33, 28, 32, 27 l2, j3, k2, k1 io12 data output mask enable for sdram write transfer. cs4# 75 t8 i chip select 4 for enabling all access. cs5# 153 b15 i chip select 5 for enabling all access. rdy 60 p5 ot12 ready signal for cpu. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 18 it81 52f/IT8152G table 5 - 2. pin descriptions of host b us interface (cont?d) signal pin(s) no. pqfp pin(s) no. lbga attribute description host bus interface (3.3v cmos i/f) mbreq 58 t3 o8 bus request to cpu. mbgnt 59 r4 i bus grant from cpu. sdcs# 76 t9 ot12 sdram chip select. sdras# 78 t10 ot12 sdram row address strobe. sdcas# 77 r9 ot12 sdarm column address strobe. int 57 t2 o8 interrupt to request to cpu. endian 193 c4 i big endian enable set the addressing mode of cpu interface to either big endian or little endian. 0: little endian. 1: big endian. table 5 - 3 . pin descriptions of pci bus interface signal pin(s) no. pqfp pin(s) no. lbga attribute description pci bus interface (3.3v cmos i/f, 5v tolerant) pciclki 122 l16 pi pci clock input. pciclko 6 c1 o16 pci clock output. pad[31:0] 152 - 148, 146 - 144, 141, 139 - 134, 132, 116,115, 113 - 108, 106, 104 - 101, 99 - 97 c15, d14, f13, e14, b16, c16, d15, g13, d16, g14, e16, f15, f16, g15, h14, g16, m15, n16, m14, n15, p16, r16, p15, n14, t16, n13, p14, r15, r14, p13, n11, p12 pio pci address/data bus 31 - 0. cbe[3:0]# 143,131, 117,107 f14, h15, m16, m13 pio pci c/be[3:0]# signal. pci c/be# bus 3 - 0 signals. frame# 129 h16 pio pci bus frame# signal. lock# 120 l15 pio pci bus lock# signal. irdy# 128 j16 pio pci bu s irdy# signal. trdy# 127 j15 pio pci bus trdy# signal. stop# 124 k16 pio pci bus stop# signal. devsel# 126 j14 pio pci bus devsel# signal. idsel 142 e15 pi pci bus initialization device select. serr# 119 l14 pi pci bus serr# signal. par 118 k13 pio pci bus parity bit. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 19 it8152f/IT8152G pin descriptions table 5 - 3. pin descriptions of pci bus interface (cont?d) signal pin(s) no. pqfp pin(s) no. lbga attribute description pci bus interface (3.3v cmos i/f, 5v tolerant) phold#/ req# 164 b13 pi/ po pci hold for intel chipset/pci bus r equest. when the pci_cf is tied to high, the asic is active as pci device, the pin is the pci bus request output to pci arbiter. contrarily, the pci_cf is tied to low, the pci arbiter is in the asic, the pin is the pci hold input for bus request of inte l chipset. phdla#/ gnt# 163 a14 po/ pi pci hold acknowledge for intel chipset/pci bus grant. when the pci_cf is tied to high, the asic is active as pci device, the pin is the pci bus grant input from pci arbiter. contrarily, the pci_cf is tied to low, the pci arbiter is in the asic, the pin is the pci hold acknowledge output to intel chipset. req[3:1]# 158, 160, 162 a16, c13, a15 pi pci master request [3:1]. gnt[3:1]# 155, 159,161 d13, d12, b14 po pci master grant [3:1]. inta#/int# 166 a13 pi/ po pci bus interrupt request a/pci bus interrupt request. when the pci_cf is tied to high, the asic is active as pci device, the pin is the pci bus interrupt request output to pci master. contrarily, the pci_cf is tied to low, the pci arbiter is in the asic, t he pin is the pci interrupt request a input from external pci device. intb# 167 b12 pi pci bus interrupt request b. intc# 168 a12 pi pci bus interrupt request c. intd# 169 d10 pi pci bus interrupt request d. clkrun# 154 c14 iod8 pci bus clkrun# signal. this pin does not support 5v tolerant. it only supports 3.3v cmos i/f. pci_cf 130 j13 i pci device function enable. when the pin is tied to high, the asic is active as pci device. table 5 - 4 . pin descripti ons of lpc host controller/gpio interface signal pin(s) no. pqfp pin(s) no. lbga attribute description lpc host controller/gpio interface (3.3v cmos i/f, 5v tolerant) lad3 - 0 /gpio3 - 0 178 - 175 b9, c9, d9, a10 io12 / io12 multiplexed command, address and da ta for lpc/gpio bits 3 - 0. these are multi - function pins. they can be controlled by port control register (gpxcnr). please refer to general purpose i/o port chapter for details. when the ?function 2? is set, the corresponding lad3 - 0 function is enabled. it is used as multiplexed command, address and data signals for lpc function. otherwise, the bits 3 - 0 function of general purpose i/o port register is enabled. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 20 it81 52f/IT8152G table 5 - 4. pin descriptions of lpc host controller/gpio interface (cont?d) signal pin(s) no. pqf p pin(s) no. lbga attribute description lpc host controller/gpio interface (3.3v cmos i/f, 5v tolerant) lframe#/ gpio4 181 a9 o12/ io12 frame signal for lpc/gpio bit 4. this is a multi - function pin. it can be controlled by port control register (gpxcnr ). please refer to general purpose i/o port chapter for details. when the ?function 2? is set, the corresponding lframe# function is enabled. it is used to indicate the start of a new cycle, and the termination of a broken cycle for lpc function. otherwise , the bit 4 function of general purpose i/o port register is enabled. ldrq#/ gpio5 182 a8 i/ io12 encoded dma and bus master request for lpc/gpio bit 5. this is a multi - function pin. it can be controlled by port control register (gpxcnr). please refer t o general purpose i/o port chapter for details. when the ?function 2? is set, the corresponding ldrq# function is enabled for lpc function. otherwise, the bit 5 function of general purpose i/o port register is enabled. serirq/ gpio6 184 b8 io12/ io12 ser ialized irq for lpc/gpio bit 6. this is a multi - function pin. it can be controlled by port control register (gpxcnr). please refer to general purpose i/o port chapter for details. when the ?function 2? is set, the corresponding serirq function is enabled for lpc function. otherwise, the bit 6 function of general purpose i/o port register is enabled. dple/ gpio7 185 a7 o12/ io12 debug port latch enable/gpio bit 7. this is a multi - function pin. it can be controlled by port control register (gpxcnr). please refer to general purpose i/o port chapter for details. when the ?function 2? is set, the corresponding dple function is enabled. otherwise, the bit 7 function of general purpose i/o port register is enabled. table 5 - 5 . pin descriptions of uart port interface signal pin(s) no. pqfp pin(s) no. lbga attribute description uart port interface (3.3v cmos i/f) txd 187 c8 o8 data output for uart. rxd 194 b5 i data input for uart. table 5 - 6 . pin descriptions of digital ac link interface signal pin(s) no. pqfp pin(s) no. lbga attribute description ac - link interface (3.3v cmos i/f) bitclk 174 b10 i ac?97 codec serial interface clock. acdin 173 a11 i ac?97 codec seri al interface input data. acdout 172 c10 o8 ac?97 codec serial interface output data. acsync 171 b11 o8 ac?97 codec serial interface synchronous. acrst# 170 c11 o8 reset# for ac?97 codec. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 21 it8152f/IT8152G pin descriptions table 5 - 7 . pin d escriptions of usb host controller interface signal pin(s) no. pqfp pin(s) no. lbga attribute description usb host controller interface (3.3v cmos i/f) ud1p 198 a3 uio usb port 1 d+ line. ud1m 199 b2 uio usb port 1 d - line. ud2p 200 a5 uio usb port 2 d + line. ud2m 201 a4 uio usb port 2 data d - line. usbpen# 195 c6 o8 usb power enable. usbovr# 196 b4 i over current detection. this input is asserted when the downstream ports exceed their current limitation. this input is used to disable the usb power, and the over - current condition will be reported on the hub and port status register. table 5 - 8 . pin descriptions of miscellaneous signals signal pin(s) no. pqfp pin(s) no. lbga attribute description miscel laneous (misc) signals (3.3v cmos i/f) bat_flt 56 r3 ik battery fault. when the signal is asserted, the all functions of this asic will be forced to stand - by mode. ck12m 205 a2 osci 12 mhz crystal oscillator input. ck12me 206 a1 oscio 12 mhz crystal os cillator output. table 5 - 9 . pin descriptions of jtag interface signals signal pin(s) no. pqfp pin(s) no. lbga attribute description jtag interface signals tdi 192 c7 i test data input for jtag. tms 191 c5 i test mode select for jtag. tclk 190 b6 i test clock input for jtag. trst# 189 a6 i test reset signal for jtag. tdo 188 b7 o8 test data output for jtag. table 5 - 10 . pin descriptions of power/ground sign als signal pin(s) no. pqfp pin(s) no. lbga attribute description power ground signals vcc3 1, 10, 22, 38, 52, 83, 84, 100, 114, 133, 147, 157, 183, 186 d3, d5, d8, d11, e13, h13, j4, l13, m4, n6, n9, n12 i power supply of 3.3 v. vss 7, 15, 29, 31, 45, 7 1, 79, 87, 96, 105, 125, 140, 156, 179, 180, 208 e7 - e10, g5, g12, h5, h12, j5, j12, k5, k12, m7 - m10 i ground. avcc1 204 c3 i analog vcc for analog pll. avss1 207 d4 i analog ground for analog pll. avcc2 2 e4 i analog vcc for analog pll. avss2 4 c2 i a nalog ground for analog pll. avcc3 121 k14 i analog vcc for analog pll. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 22 it81 52f/IT8152G table 5 - 10. pin descriptions of power/ground signals (cont?d) signal pin(s) no. pqfp pin(s) no. lbga attribute description power/ground signals avss3 123 k15 i analog ground for a nalog pll. avcc4 197 d7 i analog vcc for usb transceiver. avss4 202 d6 i analog ground for usb transceiver. avcc5 - f4 i analog vcc for analog pll. (lbga version only) avss5 - d2 i analog ground for analog pll. (lbga version only) notes: io cell type s are described as below: i: input pad. ik: schmitt trigger input pad. pi: pci bus specified input pad. osci: oscillator input pad. o8: 8ma output pad. o12: 12ma output pad. o16: 16ma output pad. ot12: 12ma tri - state output pad. ot24: 24ma tri - state output pad. oscio: oscillator input/output pad po: pci bus specified output pad. io12: 12ma input/output pad. pio: pci bus specified input/output pad. uio: usb bus specified input/output pad. iod8: 8ma open - drain input/output pad. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 23 power management 6. power management 6.1 overview the it8152 power management policy is software - oriented. the power management is to provide the standby register to control the device power consumption. some other registers are included in the power management to control the peripheral devices with ease . 6.2 features n software - oriented power management n peripheral devices standby control n provides software reset mechanism for peripheral devices n provides peripheral device test control 6.3 clock tree block diagram 12mhz 33 mhz pll x8 mclk, 96 mhz usbclk, 48 mhz pll pll x4 uartclk, 24 mhz a3dclk, 24 mhz timer clk, 96 mhz pciclki gating pcic_pclk, rclk, 33 mhz 96 mhz 24 mhz 48 mhz a3d_pclk, 33 mhz usb_pclk, 33 mhz cdma_pclk, 33 mhz lpc_pclk, 33 mhz div /2 gating gating gating gating gating gating gating gating pll x11/4 pciclko test_mode test_mode test_mode clk24_tst timer_clk_stop mclk_stop uart_clk_stop a3d_clk_stop pcic_clk_stop a3d_clk_stop usb_clk_stop cdma_clk_stop lpc_clk_stop mrclk mrclk, 96 mhz sdclk mclko test_mode figure 6 - 1 . it8152 clock tree block diagram www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 24 it81 52f/IT8152G 6.4 register descriptions the following table lists all the registers in power management. the register size and access size are measured in the unit of byte. the register size is the actu al size of register. the access size defines the word or byte, which is used to access each register or part of a power management register. the default value of the base address is 0x43f00000 in pci i/o space. table 6 - 1 . register list of system registers register name r/w offset default device standby register (dsr) r/w 0x00 0000006fh device software reset register (dsrr) r/w 0x04 00000000h device test mode register (dtmr) r/w 0x08 00000000h pci clkrun op tion register (pcor) r/w 0x0c 8000003fh pll control register (pllcr) r/w 0x20 0000008fh mclk frequency select register (mfsr) r/w 0x24 00000007h debug port register (dpr) wo 0x40 - software interrupt port register (sipr) wo 0x44 - definition of r/w a ttributes: wo write only . if a register is write only, reads from this register will have no effects. r/w read/write . a register with this attribute can be read and written. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 25 power management 6.4.1 device standby register (dsr) ? offset 0x00 this register is used to cont rol the device to enter the standby mode or operation mode. bit r/w default description 31 - 7 ro 0h reserved 6 r/w 1 uart standby enable (uartsb) when this bit is set, the uart will enter the standby mode. when this bit is cleared, the uart will be in no rmal operation mode. 5 r/w 1 timer standby (tmrsb) this bit is used to force the timer to enter the standby mode. when this bit is set, the timer is in standby mode. if this bit is cleared, the timer is in normal operation mode. 4 r/w 0 pci controller st andby enable (pcicsb) when this bit is set, the pci controller will enter the standby mode. when this bit is cleared, the pci controller will be in normal operation mode. 3 r/w 1 dma bus standby enable (dmabsb) when this bit is set, the dma bus will enter the standby mode. when this bit is cleared, the dma bus will be in normal operation mode. 2 r/w 1 cdma standby enable (cdmasb) when this bit is set, the chaining dma will enter the standby mode. when this bit is cleared, the chaining dma will be in norma l operation mode. 1 r/w 1 lpc standby enable (lpcsb) when this bit is set, the lpc will enter the standby mode. when this bit is cleared, the lpc will be in normal operation mode. 0 r/w 1 audio controller standby enable (acsb) when this bit is set, the a udio controller will enter the standby mode. when this bit is cleared, the audio controller will be in normal operation mode . 6.4.2 device software reset register (dsrr) ? offset 0x04 the device software reset register can be used to reset the device by soft ware. bit r/w default description 31 - 11 ro 0h reserved 10 r/w 0 uart software reset (uartsr) when this bit is set, the uart will be reset. this reset is equivalent to the hardware reset. all uart registers are set to the reset default values. note that this software reset bit is self - clearing when the reset is done. 9 r/w 0 timer #4 software reset (tmr4sr) when this bit is set, the timer #4 will be reset. this reset is equivalent to hardware reset. all the registers of timer #4 are set to the reset def ault values. note that this software reset bit is self - clearing. 8 r/w 0 timer #3 software reset (tmr3sr) when this bit is set, the timer #3 will be reset. this reset is equivalent to hardware reset. all the registers of timer #3 are set to the reset defa ult values. note that this software reset bit is self - clearing. 7 r/w 0 timer #2 software reset (tmr2sr) when this bit is set, the timer #2 will be reset. this reset is equivalent to hardware reset. all the registers of timer #2 are set to the reset defau lt values. note that this software reset bit is self - clearing. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 26 it81 52f/IT8152G device software reset register (dsrr) [cont?d] bit r/w default description 6 r/w 0 timer #1 software reset (tmr1sr) when this bit is set, the timer #1 will be reset. this reset is equivalent to hardware reset. all the registers of timer #1 are set to the reset default values. note that this software reset bit is self - clearing. 5 r/w 0 pci controller software reset (pcicsr) when this bit is set, the pci controller will be reset. this reset is equiv a lent to the hardware reset. all the registers of pci controller are set to the reset default values. note that this software reset bit is self - clearing. 4 r/w 0 dma bus software reset (dmabsr) when this bit is set, the dma bus will be reset. this r eset is equivalent to the hardware reset. all dma bus registers are set to the reset default values. note that this software reset bit is self - clearing when the reset is done. 3 r/w 0 chaining dma software reset (cdmasr) when this bit is set, the chaining dma will be reset. this reset is equiv a lent to the hardware reset. all chaining dma registers are set to the reset default values. note that this software reset bit is self - clearing when the reset is done. 2 r/w 0 lpc software reset (lpcsr) when this bit is set, the lpc will be reset. this reset is equivalent to the hardware reset. all lpc registers are set to the reset default values. note that this software reset bit is self - clearing when the reset is done. 1 r/w 0 usb software reset (usbsr) when this bit is set, the usb will be reset. this reset is equivalent to the hardware reset. all usb registers are set to the reset default values. note that this software reset bit is self - clearing when the reset is done. 0 r/w 0 audio controller software reset (a csr) when this bit is set, the audio controller will be reset. this reset is equivalent to the hardware reset. all the registers of audio controller are set to the reset default values. note that this software reset bit is self - clearing. 6.4.3 device test mod e register (dtmr) ? offset 0x08 this register is used to control the test mode of each device. bit r/w default description 31 - 11 ro 0h reserved 10 r/w 0 uart baud rate test (uarttst) this bit is used to test the uart baud rate. 9 ro 0 rab to internal bus bridge test (r2itst) this bit is used to enable the rab to internal bus bridge test mode. 8 r/w 0 rab test (rabtst) this bit is used to enable the rab test mode. 7 r/w 0 host to pci bridge test (h2ptst) this bit is used to enable the host to pci bri dge test mode. 6 r/w 0 dma bus test (dmabtst) this bit is used to control the dma bus test pin. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 27 power management device test mode register (dtmr) [cont?d] bit r/w default description 5 r/w 0 chaining dma test (cdmatst) this bit is used to control the chaining dma test pin. 4 r/w 0 lpc test (lpctst) this bit is used to enable the lpc test mode. 3 r/w 0 usb transceiver test (usbttst) this bit is used to enable the usb transceiver test pin. 2 r/w 0 usb function test (usbftst) this bit is used to enable the usb function test pin. 1 r/w 0 usb test (usbtst) this bit is used to enable the usb test mode. 0 r/w 0 audio controller test (actst) this bit is used to enable the audio controller test pin. 6.4.4 pci clkrun option register (pcor) ? offset 0x0c this register is used to control the operation of pci clkrun#. the most significant two bits pcicr and pcics dominants the operation of pciclk and these two bits should not be set at the same time. the relative clkrun mask bits from bit 5 to bit 0 are used to control the pci clkr un# sources and valid only as pcicr and pcics are both cleared to ?0?. bit r/w default description 31 r/w 1 pciclk run (pcicr) when this bit is set, the pciclk is always running regardless the status of the signal pci clkrun#. 30 r/w 0 pciclk stop (pci cs) when this bit is set, the pciclk is forced to stop regardless the status of the signal pci clkrun#. 29 - 6 - 0h reserved 5 r/w 1 memory controller clkrun mask (memcm) when this bit is set, the clkrun# signal of the memory controller is mask and then h as no effect to the status of pci clkrun#. when this bit is cleared, the clkrun# signal of the memory controller is passed to the pci clkrun#. 4 r/w 1 host to pci bridge clkrun mask (h2pcm) when this bit is set, the clkrun# signal of the host to pci bridg e is mask and then has no effect to the status of pci clkrun#. when this bit is cleared, the clkrun# signal of the host to pci bridge is passed to the pci clkrun#. 3 r/w 1 pci to lpc bridge clkrun mask (p2lcm) when this bit is set, the clkrun# signal of t he pci to lpc bridge is mask and then has no effect to the status of pci clkrun#. when this bit is cleared, the clkrun# signal of the pci to lpc bridge is passed to the pci clkrun#. 2 r/w 1 chaining dma clkrun mask (cdmacm) when this bit is set, the clkru n# signal of the chaining dma is mask and then has no effect to the status of pci clkrun#. when this bit is cleared, the clkrun# signal of the chaining dma is passed to the pci clkrun#. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 28 it81 52f/IT8152G pci clkrun option register (pcor) [cont?d] bit r/w default descripti on 1 r/w 1 usb host controller clkrun mask (usbcm) when this bit is set, the clkrun# signal of the usb host controller is mask and then has no effect to the status of pci clkrun#. when this bit is cleared, the clkrun# signal of the usb host controller is passed to the pci clkrun#. 0 r/w 1 audio controller clkrun mask (accm) when this bit is set, the clkrun# signal of the audio controller is mask and then has no effect to the status of pci clkrun#. when this bit is cleared, the clkrun# signal of the audio controller is passed to the pci clkrun#. 6.4.5 pll control register (pllcr) ? offset 0x20 this register is used to control the pll power down and clock skew between internal and external clocks. bit r/w default description 31 - 8 r/w 0h reserved 7 r/w 1 12mh z clock oscillator power down (12pdn) this bit is used to control the power down mode of 12mhz clock?s osci l lator. when this bit is set, the oscillator is in normal operation mode. when this bit is cleared, the oscillator is in power down mode. 6 - 4 r/w 0 00b pci clock skew control (pcicsc) these bits are used to control the clock skew between the internal pci clock and external pci clock (pciclk). 3 r/w 1 48mhz clock pll power down (48pdn) this bit is used to control the power down mode of 48mhz clock?s p ll. when this bit is set, the pll is in normal operation mode. when this bit is cleared, the pll is in power down mode. note that when the pll is switched from the power down mode to the normal mode, at least 5 m i croseconds are needed to let the pll lock t he external 48mhz clock. 2 r/w 1 de - skew clock pll power down (dpdn) this bit is used to control the power down mode of de - skew clock?s pll. when this bit is set, the pll is in normal operation mode. when this bit is cleared, the pll is in power down mode . note that when the pll is switched from the power down mode to the normal mode, at least 5 m i croseconds are needed to let the pll lock the external de - skew clock. 1 r/w 1 pci clock pll power down (ppdn) this bit is used to control the power down mode of pci clock?s pll. when this bit is set, the pll is in normal operation mode. when this bit is cleared, the pll is in power down mode. note that when the pll is switched from the power down mode to the normal mode, at least 5 m i croseconds are needed to let the pll lock the external pci clock (pciclk). 0 r/w 1 memory clock pll power down (mpdn) this bit is used to control the power down mode of memory clock?s pll. when this bit is set, the pll is in normal operation mode. when this bit is cleared, the pll is in power down mode. note that when the pll is switched from the power down mode to the normal mode, at least 5 m i croseconds are needed to let the pll lock the external memory clock (mclk). www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 29 power management 6.4.6 mclk frequency select register (mfsr) ? offset 0x24 this regis ter is used to select the operating frequency of memory clock, mclk. be sure to put the mclk pll in power down mode before changing the operating frequency. bit r/w default description 31 - 3 - 0h reserved 2 - 0 r/w 111b mclk frequency select (mfs[2:0]) 000 : 12 mhz 001: 24 mhz 010: 36 mhz 011: 48 mhz 100: 60 mhz 101: 72 mhz 110: 84 mhz 111: 96 mhz 6.4.7 debug port register (dpr) ? offset 0x40 writing a data to this address will generate a data latch signal output via dple pin. this signal is used to latch the d ata value to be written into this register. 6.4.8 software interrupt port register (sipr) ? offset 0x44 writing a data to this address will generate a software interrupt pulse to the interrupt controller. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 30 www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 31 memory controller 7. memory controller 7.1 overview the memory controlle r includes pci to memory interface, internal dma bus arbiter, shared sdram controller, a pci to internal rab bus interface and the internal rab bus arbiter. 7.1.1 features n supports 96 mhz, 3.3 v sdram n 32 - bit sdram data bus width n supports16mb, 64mb, 128mb, 256m b sdram n supports up to 64mb memory n supports 2 - level 64 - byte pci to sdram post write fifo n supports 2 - level 64 - byte pci to sdram read fifo n supports pci read prefetch n supports pci delayed transactions for io cycles 7.1.2 block diagram figure 7 - 1 . memory controller block diagram sdram host bus rab bus dma bus pci bus sa-1110 sdram dma_arbiter p2m_fcu smc p2m_biu p2r_biu p2m_fifo m2p_fifo register rab arbiter h2r www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 32 it81 52f/IT8152G 7.1.3 register configuration the following table lists the registers of the memory controller. all register size and access size are double word (32 bits). the base address (from cpu memory space ) of all registers is 0x43f00100 . note that these registers can also be accessed from pci io space. the base address for the memory controller registers is 0x43f00100 (pci io space base address plus 0x100 ) and can be re - allocated by changing the pci io spa ce base address register described at the pci configuration space registers in the cpu to pci bridge section. the device number is dependent on board connection and the function number is 0. table 7 - 1 . shared memory controller registers register name r/w offset default sdram control register (sdcr) r/w note1 0x00 0e050501h pci slave control register (pcicr) r/w note2 0x04 00000168h definition of r/w attribute: r/w read/write . a register with this attribu te can be read and written. note 1: bits 27 - 24, 18 - 16, 10 - 8 and 0 in the register are read/write. other bits are reserved. note 2: bits 8 - 5, 3 - 0 in the register are read/write. other bits are reserved. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 33 memory controller 7.2 register descriptions 7.2.1 sdram control register (sd cr) ? offset 0x00 this register provides some control options to the shared memory controller, including memory clock pad driving, memory signals (control and data) pad driving, sdram type, and two timing parameters tras and tcas (or tcl) which can be adju sted to comply various sdram. bit r/w default description 31 - 26 - 000011 reserved 25 - 24 r/w 10 sdram interface pad current (sdcur[1:0]) 00: 4ma, 01: 8ma, 10: 12 ma, 11: 16ma 23 - 19 - 0 reserved 18 - 16 r/w 101 sdram type (sdtyp[2:0]) 16 mb: 00 1 1m x 16 10 x 10 011 1m x 16 12 x 8 010 2m x 8 11 x 10 011 2m x 8 12 x 9 010 4m x 4 11 x 11 011 4m x 4 12 x 10 64 mb : 010 4m x 16 11 x 11 011 4m x 16 12 x 10 100 4m x 16 13 x 9 101 4m x 16 14 x 8 011 8m x 8 12 x 11 100 8m x 8 13 x 10 101 8m x 8 14 x 9 011 16m x 4 12 x 12 100 16m x 4 13 x 11 101 16m x 4 14 x 10 128 mb: 101 8m x 16 14 x 9 101 16m x 8 14 x 10 256 mb: 110 16m x 16 15 x 9 110 32m x 8 15 x 10 15 - 11 - 0 reserved 10 - 8 r/w 101 tras (tras[2:0]) the value of the sdram timing parameter tras. 7 - 1 - 0 reserved 0 r/w 1 tcas (tcas) the value of the s dram timing parameter tcas (or tcl). when this bit is set to 1, it represents tcas=3; set to 0, represents tcas=2. note that this bit should be fixed at 1 for it8152. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 34 it81 52f/IT8152G 7.2.2 pci slave control register (pcicr) ? offset 0x04 this register provides control opti ons to the pci bus interface of the shared memory controller, including pci memory read pre - fetch control, pci delayed transaction control, pci initial latency timer control and pci mem o ry space top bound (for address decoder). bit r/w default description 31 - 9 - 0 reserved 8 r/w 1 pci memory read prefetch enable (enprf) set this bit to 1 to enable the pci slave memory read prefetch. 7 r/w 0 pci io delayed transaction enable (endly) set this bit to 1 to enable the delayed transaction for pci io cycles. note that pci memory cycles do not implement delayed transaction since memory requests are generally completed within 16 pci clocks. 6 - 5 r/w 11 pci initial latency timer period selection (itmr[1:0]) set to 11 for 32 clocks of pci initial latency timer, an d set to 10 for 16 clocks. the default value is 32 clocks as in the pci specification. set to 0x disables the initial latency timer. 4 - 0 reserved 3 - 0 r/w 1000 pci memory space top bound (topb[3:0]) this register is the register that shows the pci slav e memory space (d e coding range, pci address bit 25 to 22). software is responsible for filling the correct value depends on the sdram size that was detected. the default value is 16mb. 7.3 operations the operation of the memory controller is divided into fi ve parts, pci to memory interface, dma arbiter, shared sdram controller, pci to internal rab bus interface and rab arbiter. basic operations of each part are d e scribed below. 7.3.1 pci to memory interface (p2m) the pci interface supports pci memory read/write transactions. the supported pci commands are write, write and invalidate, read, read line and read multiple. the write and write and invalidate commands are treated the same. the read command is handled in a different manner with read line and read multipl e if read prefetch is disabled, the read command will not prefetch but read line and read multiple will prefetch in current line (32 bytes alignment). the decoding speed is always medium decoding. retry, disconnect with/without data are supported. the init ial latency and subsequent latency timer are supported. clkrun# is asserted when the pci bus is non - idle, the write fifo is not empty or when the read prefetch fifo is not empty to guarantee the o p erations of the pci bus. pci lock cycle (device lock) is al so supported. for pci write transactions, all data are posted to write fifo, then the data gathering mechanism will issue proper write commands to sdram controller. all write cycles issued to sdram controller are 32 - byte alig n ment. the write fifo is capab le of containing 64 bytes write data, once the fifo is full, the pci state machines will insert wait states until the fifo is capable of receiving more data or disconnect when subsequent latency timer is expired. for pci read transactions, if read prefet ch is enabled, the prefetch mechanism will issue proper commands to prefetch data and queued in read fifo. all read requests issued to sdram controller are 32 - byte align men t. at the end of a read transaction, the prefetch fifo will be flushed. if read data is not yet ready, wait states are inserted until data ready or the latency timers expire to retry or disconnect the current read cycle. for data consistency, pci read cycles will push all write cycles (including cpu write cycles), i.e., previously posted write cycles must be completed before current read cycles. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 35 memory controller 7.3.2 dma arbiter the dma arbiter performs the arbitration between the p2m and cdma and is a round robin arbiter. on receiving the request from p2m or cdma, the dma arbiter sends the request to sdram c ontroller and also replies grant to the higher priority master. on receiving the grant from dma arbiter, the p2m or cdma is allowed to issue cycles to the dma bus, the sdram controller will then transform the cycle to the sdram bus. 7.3.3 shared sdram controlle r the sdram interface supports one bank of 16mb, 64mb, 128mb or 256mb asymmetric sdram with memory size from 8mb to 64mb. the shared sdram controller asserts mbreq to request the host bus on receiving requests from the dma arbiter. the cpu asserts mbgnt t o release the host bus and the shared sdram controller is now allowed to issue sdram cycles to the host bus. on completion of every sdram cycle (at most a burst of eight), the mbreq is negated by the shared sdram controller so that the cpu can do refresh o r other cycles. the sdram controller do not support page mode operations, that is, every row should be pre - charged after read or write command. the mrclk input is for latching the read data from the sdram, and it should be directly connected to sdclk for o ptimum timing. to fine tune the relationship between the input data and clock, mrclk can be connected to mclko on which a capacitor is placed to control the timing. the sdram initialization process (precharge all banks, 8 auto refresh followed by a set mo de register co m mand) is executed after power - on reset by cpu. the refresh is also the responsibility of the cpu. the supported sdram types are the same with sa - 1110 cpu. the sdram type register should be pr o grammed to be the same with the cpu and the tcas parameter should be the same with which programmed to the mode register of the sdram during initialization. 7.3.4 pci to internal rab bus interface the pci to internal rab bus interface translates pci cycles targeted at internal registers that reside on the r ab bus to the rab bus cycles. a rab bus arbiter is responsible for arbitration between the cpu access and pci access to the rab bus. all pci io writes to the rab bus will be posted to one level of write fifo. delayed transaction is supported for pci io rea d cycle that accesses the rab bus. to avoid deadlock, all cpu initiated pci io cycles that targeted at internal rab bus or system memory will be terminated with target abort. 7.3.5 rab bus arbiter the rab arbiter is for arbitration between p2r (pci to rab int erface) and h2r (host to rab interface). the grant is parked at h2r when there is no request to access the rab bus. once pci side request is received, the arbiter will grant to p2r if there is no h2r request, that is, the h2r has higher priority than p2r. once the p2r cycle is completed, the grant to p2r is de - asserted and parked to h2r again. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 36 www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 37 cpu to pci bridge 8. cpu to pci bridge 8.1 overview the cpu to pci bridge provides a 32 - bit host pci bus interface, which supports pci clock up to 33 mhz. eight - level dword buffers are provided for cpu - to - pci post writes to help maximize the bandwidth for memory and i/o writes to the pci bus. it also allows concurrent transaction between cpu bus and pci bus. for increasing the pci memory access performance, memory pre - fetch function is i mplemented. 8.2 features n pci spec. version 2.1 compliant n provide 8 - level dword posted write buffers for cpu - to - pci write transactions n provide 8 - level dword prefetch buffers for pci memory pre - fetch function, n support pci clock speed up to 33 mhz n support concu rrent transaction between the cpu and pci bus 8.3 block diagram the cpu to pci bridge is composed of cpu to rab bridge (h2r) and rab to pci bridge (r2p), where the rab bus is provided as an internal 32 - bit synchronous register access bus. r2p h2p_rabif rab bus pci bus prefetch fifo post-write fifo h2p_cfg_reg pci master h2p_abort_ctl h2p_pcimaster h2p_cmd_gen h2r host bus figure 8 - 1 . cpu to pci bridge block diagram www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 38 it81 52f/IT8152G 8.4 register description table 8 - 1 . list of pci configuration registers register name r/w address default co nfiguration address register (confaddr) r/w note1 0x43f00800 00000000h configuration data register (confdata) r/w 0x43f00804 00000000h definition of r/w attribute: r/w read/write . a register with this attribute can be read and written. note 1: bits 0 - 1, 24 - 31 in the register are read only. other bits are read/write. table 8 - 2 . list of pci command registers register name r/w address default pci interrupt acknowledge cycle (piac) ro 0x43f00808 - pci special cycle (psc) wo 0x43f0080c - definition of r/w attributes: ro read only . if a register is read only, writes to this register have no effects. wo write only . if a register is written only, the data written to this register can not be read fr om this register. table 8 - 3 . list of cpu/pci bridge configuration registers register name r/w offset default vendor identification register (vid) ro 0x00 1283h device identification register (did) ro 0x02 8152h pci command register (pcicmd) r/w note1 0x04 0007h pci status register (pcists) r/wc note2 0x06 0200h revision id register (rid) ro 0x08 20h class code register (classc) ro 0x09 060000h header type register (headt) ro 0x0e 80h pci memory base address register (pmbar) r/w note3 0x10 c0000008h pci i/o base address register (piobar) r/w note4 0x14 43f00001h pci memory address prefix register for bank 4 (pmapr4) r/w note5 0x40 40000000h pci memory address prefix register for bank 5 (pmapr5) r/w note5 0x44 48000000h pci i/o address prefix register (pioapr) r/w note6 0x48 43e00000h prefetch control register (pcr) r/w note7 0x4c 0 partial read base address register 0 (prbar0) r/w note8 0x50 0 partial read control register 0 (prcr0) r/w note9 0x5 4 0 partial read base address register 1 (prbar1) r/w note8 0x58 0 partial read control register 1 (prcr1) r/w note9 0x5c 0 www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 39 cpu to pci bridge table 8 - 3 . list of cpu/pci bridge configuration registers (cont?d) register name r/w offset default partial read base address register 2 (prbar2) r/w note8 0x60 0 partial read control register 2 (prcr2) r/w note9 0x64 0 partial read base address register 3 (prbar3) r/w note8 0x68 0 partial read control register 3 (prcr3) r/w note9 0x6c 0 partial read base address register 4 (prbar4) r/w note8 0x70 0 partial read control register 4 (prcr4) r/w note9 0x74 0 partial read base address register 5 (prbar5) r/w note8 0x78 0 partial read control register 5 (prcr5) r/w note9 0x7c 0 partial read base addres s register 6 (prbar6) r/w note8 0x80 0 partial read control register 6 (prcr6) r/w note10 0x84 0 partial read base address register 7 (prbar7) r/w note8 0x88 0 partial read control register 7 (prcr7) r/w note10 0x8c 0 definition of r/w attributes: r o read only . if a register is read only, writes to this register have no effects. r/w read/write . a register with this attribute can be read and written. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write o f 1 clears the corresponding bit and a write of 0 will have no effects. note 1: bits 2 - 5, 7 - 15 in the register are read only. other bits are read/write. note 2: bits 0 - 7, 9 - 10, 14 in the register are read only. other bits are read/write clear. not e 3: bits 0 - 25 in the register are read only. other bits are read/write. note 4: bits 0 - 10 in the register are read only. other bits are read/write. note 5: bits 0 - 25 in the register are read only. other bits are read/write. note 6: bits 0 - 19 in th e register are read only. other bits are read/write. note 7: bits 1 ? 21, 27 - 31 in the register are read only. other bits are read/write. note 8: bits 27 - 31 in the register are read only. other bits are read/write. note 9: bits 10 - 29 in the register are read only. other bits are read/write. note 10: bits 26 - 29 in the register are read only. other bits are read/write. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 40 it81 52f/IT8152G 8.4.1 pci configuration registers the pci specification defines two types of bus cycles to access the pci configuration space ? configur ation read and configuration write . the pci specification defines two mechanisms to access configuration space, mechanism #1 and mechanism #2. the it8152 only supports mechanism #1 according to the pci specification. the configuration access mechanism i nvolves using the confaddr register and confdata register. to reference a configuration register, a dword write cycle is used to load a value into confaddr which specifies the pci bus, the device on that bus, the function within the device and a specific c onfiguration register of device function being accessed. confdata becomes a window into four bytes of configuration space specified by the contents of confaddr. any read or write to confdata will result in translating the co n faddr into a pci configuration cycle. type 0 configuration access ? if the bus number field of the confaddr is 0, a type 0 configuration cycle is performed on pci bus. the content of confaddr[10:2] is mapped into ad[10:2]. the device number field of confaddr is decoded into ad[31:11]. for the device selection during configuration cycle, device #0 will assert ad11, device #1 will assert ad12, device #2 will assert ad13 and so forth up to device #20 which will assert ad31. according to the pci specification, only one ad line will be asser ted at a time. all device numbers greater than 20 will cause a type 0 configuration access without idsel being asserted, and consequently result a master abort. type 1 configuration access ? if the bus number field of confaddr is not 0, a type 1 configur ation is performed on pci bus. the confaddr[23:2] is mapped directly to ad[23:2]. ad[1:0] are driven to ?01? to indicate a type 1 configuration cycle. all other ad lines are driven to 0. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 41 cpu to pci bridge 8.4.1.1 configuration address register (confaddr) ? address 0x43f00800 the confaddr register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. bit r/w default description 31 - 24 ro 0h reserved 23 - 16 r/w 0h bus number (busn) a type 0 configurati on cycle is generated on pci bus if the bus number is programmed to 0h and host/pci bridge is not the target. if the bus number is programmed to a non - zero value, a type 1 configuration cycle is generated on pci bus with the bus number mapped to pad[23:16] during the address phase. 15 - 11 r/w 0h device number (devn) this field selects one of the 21 devices on a given bus number. during a type 0 configuration cycle, this field is decoded, and one of pad[31:11] is set to 1. during a type 1 configuration cycle , this field is mapped to pad[15:11]. 10 - 8 r/w 0h function number (funn) this field is mapped to pad[10:8] during pci configuration cycles. this value is used to select one of eight possible functions on a multifunction device. 7 - 2 r/w 0h register numb er (regn) this field is mapped to pad[7:2] during pci configuration cycles. this value is used to index a dword in configuration space of the intended target. 1 - 0 ro 0h reserved 8.4.1.2 configuration data register (confdata) ? address 0x43f00804 this register provides a 32 - bit read/write window into configuration space. the address portion of the configuration space that is referenced by the confdata register is determined by the contents of the co n faddr register. bit r/w default description 31 - 0 r/w 0h confi guration data (confdata) any access to this register will generate a configuration cycle which a d dress space uses the contents of the confaddr. 8.4.2 pci command registers 8.4.2.1 pci interrupt acknowledge cycle (piac) ? address 0x43f00808 bit r/w default descripti on 31 - 0 ro - pci interrupt acknowledge cycle (piac) read this register will generate a pci interrupt acknowledge cycle on the pci bus. the pci address is undefined. the pci byte enables are d e rived from cpu byte enables. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 42 it81 52f/IT8152G 8.4.2.2 pci special cycle (psc) ? a ddress 0x43f0080c bit r/w default description 31 - 0 wo - pci special cycle (psc) write this register will generate a pci special cycle on the pci bus. the pci address is undefined. the pci byte enables are derived from cpu byte enables. 8.4.3 cpu/pci bridge c onfiguration registers (function 0) the cpu/pci bridge configuration registers are contained in it8152 function 0 and are used to specify the cpu/pci bridge configuration and operating parameters. 8.4.3.1 vendor identification register (vid) ? offset 0x00 - 01 bi t r/w default description 15 - 0 ro 1283h vendor id (vid) this is a 16 - bit value assigned to ite. 8.4.3.2 device identification register (did) ? offset 0x02 - 0x03 bit r/w default description 15 - 0 ro 8152h device id (did) this is a 16 - bit value assigned to the it 8152. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 43 cpu to pci bridge 8.4.3.3 pci command register (pcicmd) ? offset 0x04 - 0x05 bit r/w default description 15 - 10 ro 0h reserved 9 ro 0 fast back - to - back enable (fb2be) not implemented. this bit is always 0. 8 ro 0 serr # enable (serre) not implemented. this bit is always 0. 7 ro 0 address/data stepping (ads) not implemented. this bit is always 0. 6 r/w 0 parity error response (per) when this bit is set to 1, the data parity error detected can be reported. when this bit is set to 0, the data parity error detected is ignor ed. 5 ro 0 video pallet snooping (vps) not implemented. this bit is always 0. 4 ro 0 memory write and invalidate enable (mwie) not implemented. this bit is always 0. 3 ro 0 special cycle enable (sce) not implemented. this bit is always 0. 2 ro 1 bus ma ster enable (bme) this bit is always 1. disabling of bus master capability on pci bus is not supported. 1 r/w 1 memory access enable (mae) when this bit is 1, the it8152 permits other pci masters to access main memory if the pci address selects enabled m emory space. when this bit is 0, the it8152 does not respond to any pci memory cycle which a c cesses the main memory. 0 r/w 1 i/o access enable (ioae) when this bit is 1, the it8152 permits other pci masters to access internal registers of it8152. when thi s bit is 0, access to internal regi s ters of it8152 is disabled. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 44 it81 52f/IT8152G 8.4.3.4 pci status register (pcists) ? offset 0x06 - 0x07 bit r/w default description 15 r/wc 0 detected parity error (dpe) when this bit is set to 1, it indicates that a parity error has been det ected even if parity error enable ( perre ) bit is disabled. when this bit is 0, it indicates that no parity error is detected. this bit is cleared by writing a 1 to itself. 14 ro 0 signaled system error (sse) this bit is not implemented. 13 r/wc 0 receive d master abort (rma) when the it8152 terminates a cpu - to - pci transaction with a master abort, this bit is set to 1. this bit is cleared by writing a 1 to itself. 12 r/wc 0 received target abort (rta) this bit is set to 1 when an it8152 - initiated pci trans action is terminated with target - abort. this bit is cleared by writing a 1 to itself. 11 r/wc 0 signaled target abort (sta) this bit is set to 1 when it8152 terminates a pci transaction with a ta r get - abort. this bit is cleared by writing a 1 to itself. 1 0 - 9 ro 01 devsel timing (devt) these two bits are set to 01b (medium) to indicate the slowest time that devsel# is asserted. 8 r/wc 0 data parity error detected (dped) this bit is set only if the following conditions are met: 1) it8152 asserts perr# itsel f (during a read); 2) the parity error response ( per ) bit in command register is set to ?1?. this bit is cleared by writing a 1 to itself. 7 ro 0 fast back - to - back capable (fb2bc) this bit is always 0 when the fast back - to - back is not implemented. 6 ro 0 udf supported (udf) this bit is always 0 because udf is not supported. 5 ro 0 66 mhz capable (66c) the 66 mhz pci is not supported. this bit is always 0. 4 - 0 ro 0h reserved 8.4.3.5 revision id register (rid) ? offset 0x08 bit r/w default description 7 - 0 ro 20h revision id (rid) this field contains the revision number of the it8152. the current asic revision number is 2.0. 8.4.3.6 class code register (classc) ? offset 0x09 - 0x0b bit r/w default description 23 - 16 ro 06h base class code (basec) 06h = bridge device. 15 - 8 ro 00h sub - class code (scc) 00h = host bridge. 7 - 0 ro 00h programming interface (pi) 00h = host - to - pci bridge. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 45 cpu to pci bridge 8.4.3.7 header type register (headt) ? offset 0x0e bit r/w default description 7 - 0 ro 80h header type (headt) header type 80h identifies th e it8152 as a multi - function device. 8.4.3.8 pci memory base address register (pmbar) ? offset 0x10 bit r/w default description 31 - 26 r/w 30h pci memory base address (pmba) pci slave memory base address is 0xc0000000. 25 - 4 ro 0 pci memory size (pmsz) pci sl ave memory size, 64m bytes is required. these bits are hardwired to ?0?. 3 ro 1 pci prefetchable memory area (prf) a ?1? indicates that this is a prefetchable memory area. 2 - 1 ro 0 memory type (mtyp) a ?00? means that this memory could be allocated anywh ere in 32 - bit address space. 0 ro 0 memory space indicator (mem) a ?0? indicates that this is a memory space base address register. 8.4.3.9 pci i/o base address register (piobar) ? offset 0x14 bit r/w default description 31 - 11 r/w 87eh pci i/o base address (p ioba) pci i/o base address is 0x43f00000. 10 - 2 ro 0 pci i/o space size (piosz) pci i/o space size. these bits are hardwired to ?0?. 1 - 0 reserved 0 ro 1 pci i//o indicator (io) pci i/o space indicator. 8.4.3.10 pci memory address prefix register for bank 4 ( pmapr4) ? offset 0x40 bit r/w default description 31 - 26 r/w 10h pci memory address prefix (pmap) this field (6 bits) will be prefixed to cpu address (bits 25 - 0) to generate the 32 - bit pci mem address. 25 - 0 ro 0 reserved 8.4.3.11 pci memory address prefix regis ter for bank 5 (pmapr5) ? offset 0x44 bit r/w default description 31 - 26 r/w 12h pci memory address prefix (pmap) this field (6 bits) will be prefixed to cpu address (bits 25 - 0) to generate the 32 - bit pci mem address. 25 - 0 ro 0 reserved www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 46 it81 52f/IT8152G 8.4.3.12 pci i/o addr ess prefix register (pioapr) ? offset 0x48 bit r/w default description 31 - 20 r/w 43eh pci i/o address prefix (pioap) this field (12 bits) will be prefixed to cpu address (bits 19 - 0) to generate the 32 - bit pci i/o address. 19 - 0 ro 0 reserved 8.4.3.13 prefetch c ontrol register (pcr) ? offset 0x4c bit r/w default description 31 - 27 ro 0 reserved 26 r/w 0 prefetch bank select (pbs) 1: static bank 5 0: static bank 4 25 - 22 r/w 0 prefetch base address (pba) cpu base address (bit 25 - 22) of pci read prefetch functio n. 21 - 1 ro 0 reserved 0 r/w 0 prefetch enable (pen) set this bit to 1 enables the prefetch function. when prefetch function is enabled and cpu address match prefetch base address, prefetch function will be performed to pci memory read. 8.4.3.14 partial read bas e address register n (prbarn) for pci i/o device, byte enables must be consistent with address. however, sa - 1110 asserts all byte enables on any read cycle. so, it8152 has to infer accurate byte enables from the two lsbs of host address when sa - 1110 issue s a read cycle. for a[1:0] equal to 1 or 3, 8 - bit data transfer is assumed. as for a[1:0] equal to 0 or 2, the following 8 sets of partial read registers are used to determine the transfer size. each set of partial read registers are composed of a base ad dress register and a control register. set 6 and set 7 have offset size up to 64m bytes (bit 25 - 0), while others have offset size up to 1k bytes (bit 9 - 0). when more than one set are addressed and enabled, set 0 always has the highest priority and set 7 ha s the lowest priority. when none of them are addressed or enabled, 16 - bit data transfer is assumed for a[1:0] equal to 2, and 32 - bit data transfer is assumed for a[1:0] equal to 0. prbar0 ? offset 0x50 prbar1 ? offset 0x58 prbar2 ? offset 0x60 prbar3 ? of fset 0x68 prbar4 ? offset 0x70 prbar5 ? offset 0x78 prbar6 ? offset 0x80 prbar7 ? offset 0x88 bit r/w default description 31 - 27 ro 0 reserved 26 r/w 0 partial read bank select (prbs) 1: static bank 5 0: static bank 4 25 - 0 r/w 0 partial read base address (prba) cpu base address of pci partial read function. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 47 cpu to pci bridge 8.4.3.15 partial read control register n (prcrn) prcr0 ? offset 0x54 prcr1 ? offset 0x5c prcr2 ? offset 0x64 prcr3 ? offset 0x6c prcr4 ? offset 0x74 prcr5 ? offset 0x7c bit r/w default description 31 r/w 0 partial read enable (pren) 1: enabled. 0: disabled. 30 r/w 0 partial read transfer size (prts) 1: 16 - bit transfer 0: 8 - bit transfer 29 - 10 ro 0 reserved 9 - 0 r/w 0 partial read offset size (pros) offset size of pci partial read function. prcr6 ? offse t 0x84 prcr7 ? offset 0x8c bit r/w default description 31 r/w 0 partial read enable (pren) 1: enabled. 0: disabled. 30 r/w 0 partial read transfer size (prts) 1: 16 - bit transfer. 0: 8 - bit transfer. 29 - 26 ro 0 reserved 25 - 0 r/w 0 partial read offset siz e (pros) offset size of pci partial read function. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 48 www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 49 pci - to - lpc bridge 9. pci - to - lpc bridge 9.1 overview the pci - to - lpc bridge provides a bus conversion from pci bus to lpc bus so that system can access lpc devices. the pci - to - lpc bridge is pci function 2 in it8152. 9.2 featu res pci interface features: n supports 32 - bits pci bus & up to 33 mhz pci bus frequency n supports pci rev. 2.1 specification n supports programmable delayed transaction n supports pci configuration, memory and i/o cycles n supports pci master and slave lpc interf ace features: n supports lpc 1.0 specification n supports i/o read, i/o write cycles n supports sync time - out abort report n supports sync error report serial irq interface features: n supports up to 21 programmable data frames n supports quiet mode and continuous mo de n supports programmable 4 - bit, 6 - bit, 8 - bit start frame width www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 50 it81 52f/IT8152G 9.3 configuration register description register name r/w offset default vendor identification register (vid) ro 0x00 1283h device identification register (did) ro 0x02 8152h pci command regi ster (pcicmd) r/w 0x04 0007h pci status register (pcists) r/wc 0x06 0200h revision id register (rid) ro 0x08 20h class code register (classc) ro 0x09 068000h header type register (headt) ro 0x0e 00h base address register (bar) r/w 0x10 43e11801h seri al irq control register (serirqc) r/w 0x49 00h bridge control register (bcr) r/w 0x4c 06h bridge status register (bsr) r/wc 0x4d 00h discard timer register (dtr) r/w 0x4f 3fh lpc i/o space base address register (lisbar) r/w 0x50 43e0h definition of r /w attributes: ro read only . if a register is read only, writes to this register will have no effects. r/w read/write . a register with this attribute can be read and written. r/wc read/write clear . a register bit with this attribute can be read and writt en. however, a write of 1 clears the corresponding bit and a write of 0 has no effects. 9.3.1 vendor identification register (vid) ? offset 0x00 - 0x01 bit r/w default description 15 - 0 ro 1283h vendor id (vid) this is a 16 - bit value assigned to ite. 9.3.2 device id entification register (did) ? offset 0x02 - 0x03 bit r/w default description 15 - 0 ro 8152h device id (did) this is a 16 - bit value assigned to the device id. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 51 pci - to - lpc bridge 9.3.3 pci command register (pcicmd) ? offset 0x04 - 0x05 bit r/w default description 15 - 10 - - reserv ed 9 ro 0 fast back - to - back enable (fb2be) not implemented. this bit is always 0. 8 r/w 0 serr # enable (serre) when this bit is set to 1 (and the bit ioblee or lpctoe or lpcerre or dttoe in bcr register is set), the serr# signal will be asserted when th e condition is matched. when this bit is set to 0, no serr# signal will be asserted. 7 ro 0 address/data stepping (ads) not implemented. this bit is always 0. 6 ro 0 parity error response (per) not implemented. this bit is always 0. 5 ro 0 video palette snooping (vps) not implemented. this bit is always 0. 4 ro 0 memory write and invalidate enable (mwie) not implemented. this bit is always 0. 3 ro 0 special cycle enable (sce) not implemented. this bit is always 0. 2 ro 1 bus master enable (bme) this b it is hardwired to 1 so that bus master is always enabled. 1 ro 1 memory access enable (mae) this bit is hardwired to 1 so that memory access is always enabled. 0 ro 1 i/o access enable (ioae) this bit is hardwired to 1 so that i/o access is always enabl ed. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 52 it81 52f/IT8152G 9.3.4 pci status register (pcists) ? offset 0x06 - 0x07 bit r/w default description 15 ro 0 detected parity error (dpe) not implemented. this bit is always 0. 14 r/wc 0 signaled system error (sse) when pci to internal bus bridge asserts the serr# signal , this bit is set to 1. this bit can be cleared by writing a 1 to it. 13 ro 0 received master abort (rma) not implemented. this bit is always 0. 12 ro 0 received target abort (rta) not implemented. this bit is always 0. 11 r/wc 0 signaled target abort ( sta) this bit is set when pci to internal bus bridge function is targeted with a transaction that terminates with a target abort. this bit can be cleared by writing a 1 to it. 10 - 9 ro 01 devsel timing (devt) these two bits are set to 01b (medium) to indic ate the slowest time that devsel# is asserted for all positive decode i/o spaces. 8 ro 0 data parity error detected (dped) not implemented. this bit is always 0. 7 ro 0 fast back - to - back capable (fb2bc) this bit is always 0 as the fast back - to - back is no t implemented. 6 - 0 - - reserved 9.3.5 revision id register (rid) ? offset 0x08 bit r/w default description 7 - 0 ro 20h revision id (rid) this field contains the revision number of the it8152. the current asic revision number is 2.0. 9.3.6 class code register (cl assc) ? offset 0x09 - 0x0b bit r/w default description 23 - 16 ro 06h base class code (basec) 06h = bridge device. 15 - 8 ro 80h sub class code (scc) 80h = other bridge device. 7 - 0 ro 00h programming interface (pi) 00h = no register level programming interf ace defined. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 53 pci - to - lpc bridge 9.3.7 header type register (headt) ? offset 0x0e bit r/w default description 7 - 0 ro 00h header type (headt) header type 00h indicates that the device?s configuration space map follows the basic format. 9.3.8 base address register (bar) ? offset 0x 10 bit r/w default description 31 - 8 r/w 43e118 reserved 7 - 1 ro 0000000b reserved 0 ro 1 reserved 9.3.9 serial irq control register (serirqc) ? offset 0x49 bit r/w default description 7 r/w 0 serial irq enable (sirqen) this bit is used to enable the seria l irq host. when this bit is set, the serial irq host is enabled. when this bit is cleared, the serial irq host is disabled. 6 r/w 0 serial irq mode select (sirqms) this bit is used to select quiet or continuous mode. when this bit is set, the continuous mode is selected. when this bit is cleared, the quiet mode is selected. note that for system using the quiet mode, this bit should be first set to 1 (continuous mode) for at least one serial irq cycle (irq frame start to frame stop). second, this bit is cl eared to switch to the quiet mode. these two steps must be performed before the serirq pin will respond to the actual interrupt status. 5 - 4 r/w 00b serial irq frame width (sirqfw) these two bits are used to specify the number of pci clocks that serial irq host will assert serirq pin low at the start frame. note that when the serial irq host is in quiet or continuous mode, the start frame width is the same as observed at serirq pin. 00: 4 clocks, 01: 6 clocks, 10: 8 clocks, 11: reserved 3 - - reserved 2 - 0 r/w 000b serial irq frame number (sirqfn) these three bits are used to specify the number of data frame. the minimum is 17 frames. the maximum is 21 frames. 000: 17 frames, 001: 18 frames, 010: 19 frames, 011: 20 frames, 100: 21 frames, 101 - 111: r eserved www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 54 it81 52f/IT8152G 9.3.10 bridge control register (bcr) ? offset 0x4c bit r/w default description 7 r/w 0 serr# due to lpc sync time - out error enable (lpctoe) this bit is used to enable the lpc sync time - out error report to serr#. when this bit is set, the lpc sync ti me - out error report to serr# is enabled. if this bit is cleared, the lpc sync time - out error report to serr# is disabled. 6 r/w 0 serr# due to pci i/o cycle byte lane error enable (ioblee) this bit is used to enable the pci i/o cycle byte lane error repor t to serr#. when this bit is set, the pci i/o cycle byte lane error report to serr# is enabled. if this bit is cleared, the pci i/o cycle byte lane error report to serr# is disabled. 5 r/w 0 serr# due to lpc sync error report enable (lpcerre) this bit is used to enable the lpc sync error signal status report to serr#. when this bit is set, the lpc sync error signal status report to serr# is enabled. if this bit is cleared, the lpc sync error signal status report to serr# is disabled. 4 r/w 0 serr# due to delayed transaction time - out enable (dttoe) this bit is used to enable the delayed transaction time - out report to serr# if the pci master does not retry the same transaction when the discard timer is expired. when this bit is set, the delayed transaction time - out report to serr# is enabled. if this bit is cleared, the delayed transaction time - out report to serr# is disabled. 3 - - reserved 2 r/w 1 lpc i/o single byte read enable (lisbre) when this bit is set to 1, this bridge is allowed to issue a single byte read lpc i/o cycle no matter what the byte enables on pci are. if this bit is 0, this bridge issues lpc i/o read cycle based on the byte enables on pci. 1 r/w 1 lpc i/o space decode enable (liode) 1: enable. 0: disable. decoded space is limited to the 64kb i/o space which is assigned by lpc i/o space base address register. this space is subtractive decoded. 0 r/w 0 delayed transaction enable (dte) this bit is used to enable the delayed transaction. when this bit is set, the delayed transaction mech anism is enabled. if this bit is cleared, the d e layed transaction mechanism is disabled. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 55 pci - to - lpc bridge 9.3.11 bridge status register (bsr) ? offset 0x4d bit r/w default description 7 r/wc 0 lpc sync time - out error (lpcto) when this bit is set, the lpc time - out error occu rred. write a 1 to clear this bit 6 r/wc 0 pci i/o cycle byte lane error (ioble) when this bit is set, the pci i/o cycle byte lane error occurred. write a 1 to clear this bit. 5 r/wc 0 lpc sync error asserted (lpcerr) when this bit is set, the lpc sync e rror signal is asserted and latched. write a 1 to clear this bit. 4 r/wc 0 delayed transaction time - out (dtto) when this bit is set, the delayed transaction time - out occurred. write a 1 to clear this bit. 3 - 0 - - reserved 9.3.12 discard timer register (dtr) ? offset 0x4f bit r/w default description 7 - 0 r/w 3fh discard timer (dt) if the pci master does not repeat the same transaction within the discard time after the delayed transaction is finished. the delayed transaction will time out. this causes the pci t arget interface to discard the transa c tion and set the bit 4 (dtto) in bridge status register (bsr). the discard time is the discard timer value x 256 pci clocks. 00h=never expired; 01h=256t; ffh=256x256t. 9.3.13 lpc i/o space base address register (lisbar) ? o ffset 0x50 bit r/w default description 15 - 0 r/w 43e0h lpc i/o space base address (lisba) the values of this register are bits 31 - 16 of the 64k pci i/o space which is subtractive decoded by the pci - to - lpc bridge and translated to lpc i/o space. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 56 n n n n n n n n n n n n www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 57 chaining dma controller 10. cha ining dma controller 10.1 overview the chaining dma (cdma) controller is pci function 1 in it8152f. the cdma is able to support four independent dma channels which are capable of transferring data between sdram and pci devices. each channel supports both chai ning and non - chaining transfers. besides, both pci memory device address and pci i/o device address are su p ported. the chaining dma (cdma) controller also supports dma transfer when bits 0 ? 1 of the initial address of in pci space are not equal to bits 0 ? 1 of the initial address in sdram space (unaligned address). 10.2 features n four independent software dma channels n chaining mode and non - chaining mode are supported n both pci memory address and pci i/o address are supported n rotating and fixed priority types are supported n dma transfers of unaligned address are supported 10.3 block diagram pci bus smc sdram sdram chain dma controller pci memory device pci i/o device figure 10 - 1 . cdma system architecture www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 58 it81 52f/IT8152G 10.4 dma operation two dma operation modes are supported in the cdma controller: non - chaining mode dma and chaining mode dma. 10.4.1 non - chaining mode dma dma mode can be set to the non - chaining mode dma through the mode register. transfer parameters are set up through memory address register, device address register, byte count register, and descriptor pointer register (only the direction of transfer bit is needed in this mode). the transfer start bit in the co m mand/status register can be then set to initiate the transfer. the transfer done bit in the command/status registe r can be polled to indicate the status of dma transfer. besides, the cdma controller can be pr o grammed to generate the interrupt request when the dma transfer is completed. in this mode, only consecutive data are transferred. therefore, when the transfer of non - consecutive data is desired, chaining mode dma is suggested. mode register set dma mode to non-chaining command/status register set up transfer parameters initiate the dma transfer memory block to transfer memory-address space memory address register device address register byte count register descriptor pointer register device block to transfer pci-address space figure 10 - 2 . non - chaining mode dma operation n n n n n n n n n n n n www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 59 chaining dma controller 10.4.2 chaining mode dma in this mode, transfer parameters are set up through descriptors resided in memory that must be able to be accessed with pci memory address. they are composed of the contents of memory address register, device address register, byte count register, and descriptor pointer register. before the chaining mode dma transfer can begin, the address of the initial descriptor must be set up in the descriptor pointer register, and the byte count register must be cleared, otherwise the initial descriptor can not be loaded correctly. the transfer can be then initiate d by setting the transfer start bit. the cdma controller loads the initial d e scriptor and writes the content to memory address register, device address register, byte count register, and descriptor pointer register, and data is transferred until the desire d byte count is reached, then next d e scriptor is loaded if necessary. the same steps are repeated (load a descriptor and transfer data) until the end of chain bit is set in the descriptor pointer register. the cdma controller can be programmed to generate the interrupt request when the transfer of current d e scriptor is done or when the overall dma transfers are completed. mode register set dma mode to chaining descriptor pointer register command/status register set up first descriptor pointer register initiate dma transfer first device block to transfer second device block to transfer pci-address space first memory block to transfer second memory block to transfer memory-address space memory address device address transfer size next descriptor pointer memory address device address transfer size next descriptor pointer first descriptor second descriptor pci memory- address space figure 10 - 3 . chaining mode dma operation www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 60 it81 52f/IT8152G 10.5 register description tab le 10 - 1 . configuration register list of cdma controller register name r/w offset default vendor identification register (vid) ro 0x00 1283h device identification register (did) ro 0x02 8152h pci command reg ister (pcicmd) r/w note1 0x04 0005h pci status register (pcists) r/wc note2 0x06 0200h revision register (rid) ro 0x08 20h class code register (classc) ro 0x09 080103h latency timer register (lt) r/w note3 0x0d 80h base address register (bar) r/w note4 0x 10 43e11001h the default value of the b ase a ddress for the following registers is 0x43e11000 . not e that these registers can be re - allocated by changing the base address register. table 10 - 2 . operation regi ster list of cdma controller register name r/w offset default memory address register of channel 0 (mar0) r/w 0x00 0h device address register of channel 0 (dar0) r/w 0x04 0h byte count register of channel 0 (bcr0) r/w 0x08 0h descriptor pointer registe r of channel 0 (dpr0) r/w note5 0x0c 0h memory address register of channel 1 (mar1) r/w 0x10 0h device address register of channel 1 (dar1) r/w 0x14 0h byte count register of channel 1 (bcr1) r/w 0x18 0h descriptor pointer register of channel 1 (dpr1) r /w note5 0x1c 0h memory address register of channel 2 (mar2) r/w 0x20 0h device address register of channel 2 (dar2) r/w 0x24 0h byte count register of channel 2 (bcr2) r/w 0x28 0h descriptor pointer register of channel 2 (dpr2) r/w note5 0x2c 0h memory address register of channel 3 (mar3) r/w 0x30 0h device address register of channel 3 (dar3) r/w 0x34 0h byte count register of channel 3 (bcr3) r/w 0x38 0h descriptor pointer register of channel 3 (dpr3) r/w note5 0x3c 0h mode register of channel 0 (m r0) r/w note6 0x40 20h mode register of channel 1 (mr1) r/w note6 0x44 20h mode register of channel 2 (mr2) r/w note6 0x48 20h mode register of channel 3 (mr3) r/w note6 0x4c 20h command/status register of channel 0 (csr0) r/w note7 0x50 0h command/status register of channel 1 (csr1) r/w note7 0x54 0h n n n n n n n n n n n n www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 61 chaining dma controller table 10 - 2 . operation register list of cdma controller (cont?d) register name r/w offset default command/status register of channel 2 (csr2) r/w note7 0x58 0h command/status registe r of channel 3 (csr3) r/w note7 0x5c 0h priority type register (ptr) r/w note8 0x60 0h definition of r/w attributes: ro read only . if a register is read only, writes to this register will have no effects. r/w read/write . a register with this attribute c an be read and written. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of 1 clears the corresponding bit and a write of 0 has no effects. note 1: bits 0, 6 in the register are read/write. other bits are read only. note 2: bits 11 - 13 in the register are read/write clear. other bits are read only. note 3: bits 0 - 2 in the register are read only. other bits are read/write. note 4: bits 0 - 7 in the register are read only. other bits are read/write. note 5: bit 0 in the register is read only. other bits are read/write. note 6: bits 7, 16 - 31 in the register are read only. other bits are read/write. note 7: bits 3 - 5 in the register are read/write clear. bits 6 - 31 in the register are read only. other bi ts are read/write. note 8: bit 0 in the register is read/write. other bits are read only. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 62 it81 52f/IT8152G 10.5.1 cdma configuration registers (function 1) the following registers are the standard pci - specific configuration registers. 10.5.1.1 vendor identification register (vid) ? v id, offset 0x00 - 0x11 bit r/w default description 15 - 0 ro 1283h vendor id (vid) th is is a 16 - bit value assigned to ite. 10.5.1.2 device identification register (did) ? did, offset 0x02 - 0x03 bit r/w default description 15 - 0 ro 8152h device id (did) this is a 16 - bit value assigned to the it8152 . 1 10.5.1.3 pci command register (pcicmd) ? pcicmd, offset 0x04 - 0x05 bit r/w default description 15 - 10 ro 0h reserved 9 ro 0 fast back - to - back enable (fb2be) not implemented. this bit is always 0. 8 ro 0 serr # enable (serre ) not implemented. this bit is always 0. 7 ro 0 address/data stepping (ads) not implemented. this bit is always 0. 6 r/w 0 parity error response (per) when this bit is set to 1, the data parity error detected can be reported. when this bit is set to 0, t he data parity error detected is ignored. 5 ro 0 video pallet snooping (vps) not implemented. this bit is always 0. 4 ro 0 memory write and invalidate enable (mwie) not implemented. this bit is always 0. 3 ro 0 special cycle enable (sce) not implemented . this bit is always 0. 2 ro 1 bus master enable (bme) this bit is always 1. disabling of bus master capability on pci bus is not supported. 1 ro 0 memory access enable (mae) this bit is hardwired to 0 for not allowing this device to respond to memory s pace accesses. 0 r/w 1 i/o access enable (ioae) a value of 1 allows cdma to respond to pci i/o space accesses. a value of 0 disables it. n n n n n n n n n n n n www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 63 chaining dma controller 10.5.1.4 pci status register (pcists) ? pcists, offset 0x06 - 0x07 bit r/w default description 15 ro 0 detected parity erro r (dpe) this bit is not implemented. 14 ro 0 signaled system error (sse) this bit is not implemented. 13 r/wc 0 received master abort (rma) when this device terminates a pci transaction with a master abort, this bit is set to 1. this bit is cleared by writing a 1 to it. 12 r/wc 0 received target abort (rta) this bit is set to 1 when a pci transaction issued by this master device is terminated with target - abort. this bit is cleared by writing a 1 to it. 11 r/wc 0 signaled target abort (sta) this bit is set to 1 when this target terminates a transaction with target - abort. this bit is cleared by writing a 1 to it. 10 - 9 ro 01 devsel timing (devt) these two bits are set to 01b (medium) to indicate the slowest time that devsel# is asserted. 8 ro 0 data par ity error detected (dped) this bit is not implemented. 7 ro 0 fast back - to - back capable (fb2bc) this bit is always 0 when the fast back - to - back is not implemented. 6 ro 0 udf supported (udf) this bit is always 0 because udf is not supported. 5 ro 0 66 mhz capable (66c) the 66 mhz pci is not supported. this bit is always 0. 4 - 0 ro 0h reserved 10.5.1.5 revision id register (rid) ? rid, offset 0x08 bit r/w default description 7 - 0 ro 10h revision id (rid) this field contains the revision number of the device. the current asic revision number is 1.0 . 10.5.1.6 class code register (classc) ? classc, offset 0x09 - 0x0b bit r/w default description 23 - 16 ro 08h base class code (basec) 08h = base system peripherals. 15 - 8 ro 01h sub - class code (scc) 01h = dma controller. 7 - 0 ro 03h programming interface (pi) 03h = pci dma controller. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 64 it81 52f/IT8152G 10.5.1.7 latency timer register (lt) ? lt, offset 0x0d bit r/w default description 7 - 0 r/w 80h latency timer (lt) the number of clocks programmed represents the guaranteed time slice (measured in p ci clocks) allocated to this device, after which it must su r render the bus as soon as other pci masters request the bus. 10.5.1.8 base address register (bar) ? bar, offset 0x10 bit r/w default description 31 - 8 r/w 43e110h i/o base address (ioba) this field def ines the i/o base address for the cdma operation registers. the default pci i/o base address is 43e11000h. 7 - 1 ro 0 reserved 0 ro 1 i/o space indicator (iosi) this bit always reads back a ?1?, indicating that this base address register defines a pci i/o space. 10.5.2 cdma operation registers the following registers are the cdma operation registers used to control the operation of the cdma controller. address space mentioned in the following registers (except mar) is pci address space. 10.5.2.1 memory address registe r of channel n (marn) a 26 - bit address in sdram space (not in pci space) is expected in this register. mar0, i/o offset: 0x00 mar1, i/o offset: 0x10 mar2, i/o offset: 0x20 mar3, i/o offset: 0x30 bit r/w default description 31 - 26 ro 0 reserved 25 - 0 r/w 0 memory address (ma) this field indicates the starting memory address of a dma transfer. 10.5.2.2 device address register of channel n (darn) dar0, i/o offset: 0x04 dar1, i/o offset: 0x14 dar2, i/o offset: 0x24 dar3, i/o offset: 0x34 bit r/w default descriptio n 31 - 0 r/w 0 device address (da) this field indicates the starting device address of a dma transfer. n n n n n n n n n n n n www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 65 chaining dma controller 10.5.2.3 byte count register of channel n (bcrn) bcr0, i/o offset: 0x08 bcr1, i/o offset: 0x18 bcr2, i/o offset: 0x28 bcr3, i/o offset: 0x38 bit r/w default d escription 31 - 0 r/w 0 byte count (bc) this field indicates the number of bytes to be transferred during a dma transfer. it will be cleared by hardware when the transfer is finished no r mally. 10.5.2.4 descriptor pointer register of channel n (dprn) dpr0, i/o off set: 0x0c dpr1, i/o offset: 0x1c dpr2, i/o offset: 0x2c dpr3, i/o offset: 0x3c bit r/w default description 31 - 4 r/w 0 next descriptor address (nda) this field indicates the double word aligned address (bit3 - 0 = 0000) of next descriptor. 3 r/w 0 direction of transfer (dt) a value of 1 indicates transfers from memory to pci device. a value of 0 indicates transfers from pci device to memory. 1: m2d. 0: d2m. 2 r/w 0 descriptor done interrupt enable (ddie) a value of 1 causes an interrupt to be generated afte r the terminal count for this descriptor is reached. a value of 0 disables interrupts from being generated. 1 r/w 0 end of chain (ec) a value of 1 indicates the end of chain. 0 - 0 reserved www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 66 it81 52f/IT8152G 10.5.2.5 mode register of channel n (mrn) mr0, i/o offset: 0x40 mr 1, i/o offset: 0x44 mr2, i/o offset: 0x48 mr3, i/o offset: 0x4c bit r/w default description 31 - 16 ro 0 reserved 15 - 8 r/w 0 transfer limit of each pci transaction (tlpt) this field is used to limit the data phase number of each pci transaction. it is usef ul to control the time - sharing when rotating priority is selected. only the five high - order bits are implemented, resulting in a granularity of eight. a value of 0 will disable this function. 7 ro 0 reserved 6 r/w 0 transfer error interrupt enable (teie) a value of 1 enables the interrupt to be generated when a transfer error has occurred. 5 - 4 r/w 0 device transfer type (dtt) this field is only meaningful when dat is set to 1. it indicates the transfer size of each pci i/o transaction and it must be cons istent with byte count. 00: byte access. 01: word access. 1x: double word access. 3 r/w 0 device addressing type (dat) a value of 1 indicates device address is within pci i/o space. a value of 0 indicates device address is within pci memory space. 1: pci i/o. 0: pci memory. 2 r/w 0 device addressing mode (dam) a value of 1 indicates device address will be held constant. a value of 0 indicates the device address is incremented. this bit can only be set when pci i/o address is selected. 1: fixed. 0: incre mented. 1 r/w 0 transfer done interrupt enable (tdie) a value of 1 enables the interrupt to be generated when transfer is done. 0 r/w 0 chaining mode (cm) a value of 1 causes the dma controller to operate in chaining mode. 1: chaining mode. 0: non - chaini ng mode. n n n n n n n n n n n n www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 67 chaining dma controller 10.5.2.6 command/status register of channel n (csrn) csr0, i/o offset: 0x50 csr1, i/o offset: 0x54 csr2, i/o offset: 0x58 csr3, i/o offset: 0x5c bit r/w default description 31 - 6 ro 0 reserved 5 r/wc 0 transfer error (te) a value of 1 indicates the controller encounters an error in the process of transfer. the error may be due to incorrect transfer parameters or pci abort situation has happened. writing a 1 will clear this bit and the interrupt due to this event when teie is set to 1. 4 r/wc 0 descr iptor done (dd) a value of 1 indicates the transfer of current descriptor is complete. writing a 1will clear this bit and the interrupt due to this event when ddie is set to 1. 3 r/wc 0 transfer done (td) a value of 1 indicates the transfer of this channe l is complete. writing a 1 will clear this bit and the interrupt due to this event when tdie is set to 1. 2 r/w 0 transfer abort (ta) writing a 1 to this bit causes the channel to abort the current transfer. the channel enable bit must be cleared. this ch annel transfer done bit is set when the abort is complete. reading this bit always gets 0. 1 r/w 0 transfer start (ts) writing a 1 to this bit causes the channel to start transferring data if the channel is enabled. reading this bit always gets 0. 0 r/w 0 dma enable (de) a value of 1 enables this dma channel. 10.5.2.7 priority type register (ptr) ? ptr, i/o offset 0x60 bit r/w default description 31 - 1 - - reserved 0 r/w 0 priority type (pt) a value of 1 indicates the priority type is rotating type. channel wi ll be arbitrated for each normally terminated pci transaction. a value of 0 indicates the priority type is fixed type. when the fixed type is selected, channel 0 has the highest priority. 1: rotating priority. 0: fixed priority. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 68 www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 69 audio digital controller 11. audio digital contro ller 11.1 overview this module is a digital audio controller which supports full - duplex playback and recording. combined with high - performance ac?97 codec, this controller provides the most cost - effective yet high quality audio exper i ence to users. the audio digital controller is pci function 3 in it8152. 11.2 features n pci v.2.1 compliant with bus master and scatter - and - gather capability n 2 output channels and 2 input channels n support ac?97 ac - link 2.0 11.3 block diagram pci slave pci master fifo & dfc codec i/f capture data playback data pci bus ac-link www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 70 it81 52f/IT8152G 11.4 configurati on register descriptions register name r/w offset default vendor identification register (vid) ro 0x00 1283h device identification register (did) ro 0x02 0801h pci command register (pcicmd) r/w 0x04 0000h pci status register (pcists) r/wc 0x06 0200h revision id register (rid) ro 0x08 b1h class code register (classc) ro 0x09 040000h latency timer register (lt) r/w 0x0d 00h header type register (headt) ro 0x0e 00h base address register (bar) r/w 0x10 43e10801h sub - system vendor id register(svid) (s hadow of 0x9c~9d) ro 0x2c 1283h sub - system id register (sid) (shadow of 0x9e~9f) ro 0x2e 1283h capability pointer register (cp) ro 0x34 dch interrupt line register (ilr) r/w 0x3c 00h interrupt pin register (ipr) (inta#) ro 0x3d 01h min grant period pc i for burst period register (mgpbp) ro 0x3e 04h max latency for pci grant period register (mlpgp) ro 0x3f 28h vendor id writeable register (vidw) r/w 0x98 1283h device id writeable register (didw) r/w 0x9a 0801h sub - system vendor id writeable register (svidw) r/w 0x9c 1283h sub - system id writeable register (sidw) r/w 0x9e 1283h dfc reset control register (drc) r/w 0xa0 00h capability id register (cid) ro 0xdc 01h next item pointer register (nip) ro 0xdd 00h power management capability register (pmc ) ro 0xde 0421h power management control/status register (pmcs) r/w 0xe0 0000h definitions of r/w attributes: ro read only . if a register is read only, writes to this register will have no effects. r/w read/write . a register with this attribute can be read and written. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of 1 clears the corresponding bit and a write of 0 has no effects. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 71 audio digital controller 11.4.1 device/vendor identification register (did/vid) did, offset: 0 x02 - 0x03 vid, offset: 0x00 - 0x01 bit r/w default description 31 - 16 ro 0801h device id (did) this is a 16 - bit value assigned to this device. 15 - 0 ro 1283h vendor id (vid) this is a 16 - bit value assigned to ite. 11.4.2 pci status/command register (pcists/pcicmd) pcists, offset 0x06 - 0x07 pcicmd, offset: 0x04 - 0x05 bit r/w default description 31 r/wc 0 detected parity error (dpe) when this bit is set to 1, it indicates that a parity error is detected even if parity error enable ( perre ) bit is disabled. when this bit is 0, it indicates that no parity error is detected. this bit is cleared by writing a 1 to itself. 30 ro 0 reserved 29 r/wc 0 received master abort (rma) when this device terminates a pci transaction with a master abort, this bit is set to 1. this b it is cleared by writing a 1 to itself. 28 r/wc 0 received target abort (rta) this bit is set to 1 when a pci transaction issued by this master device is terminated with target - abort. this bit is cleared by writing a 1 to itself. 27 r/wc 0 reserved 26 - 2 5 ro 01 devsel timing (devt) these two bits are hardwired to 01b (medium) to indicate the slowest time that devsel# is asserted. 24 r/wc 0 reserved 23 ro 1 fast back - to - back capable (fb2bc) this bit is always ?1?. 22 ro 0 udf supported (udf) this bit is always 0 because udf is not supported. 21 ro 0 66 mhz capable (66c) the 66 mhz pci is not supported. this bit is always 0. 20 ro 1 power management features (pm) pci power management features appear in the standard configuration space header. read only . 19 - 10 - 0h reserved 9 r/w 0 fast back - to - back enable (fb2be) a value of 1 enables fast back - to - back. a value of 0 disables fast back - to - back. 8 r/w 0 serr # enable (serre) a value of 0 disables this device to generate serr#. a value of 1 enables this device to generate serr#. 7 ro 0 address/data stepping (ads) not implemented. this bit is always 0. 6 r/w 0 reserved 5 ro 0 video palette snooping (vps) not implemented. this bit is always 0. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 72 it81 52f/IT8152G pci status/command register (pcists/pcicmd) [cont?d] bit r/ w default description 4 ro 0 memory write and invalidate enable (mwie) not implemented. this bit is always 0. 3 ro 0 special cycle enable (sce) not implemented. this bit is always 0. 2 r/w 0 bus master enable (bme) a value of 0 disables this device from generating pci accesses. a value of 1 allows this device to behave as a bus master. 1 r/w 0 memory access enable (mae) a value of 0 disables this device?s response to memory access. a value of 1 enables this device?s response to memory access. 0 r/w 0 i /o access enable (ioae) a value of 0 disables this device?s response to i/o access. a value of 1 enables this device?s response to i/o access. 11.4.3 class code/revision id registers (classc/rid) classc, offset: 0x09 - 0x0bb rid, offset: 0x08 bit r/w default des cription 31 - 24 ro 04h base class code (basec) multimedia device. 23 - 16 ro 01h sub class code (scc) 01h = audio device. 15 - 8 ro 00h programming interface (pi) 00h = specific register - level programming interface. 7 - 0 ro b1h revision id (rid) this field c ontains the revision number of the device. b1h indicates the 3 rd version. 11.4.4 bist/header type/latency timer/cache line size registers (bist/headt/lt/cals) bist, offset: 0x0f headt, offset: 0x0e lt, offset: 0x0d cals, offset: 0x0c bit r/w default descript ion 31 - 24 - - bist (bist) the built in self test (bist) function is not supported by the device. 23 - 16 ro 00h header type (headt) header type 00h indicates that the device?s configuration space map follows the basic format. 15 - 8 r/w 00h latency timer (l t) the number of clocks programmed represents the guaranteed time slice (measured in pci clocks) allocated to this device, after which it must su r render the bus to the other pci masters requesting for the bus. the d e fault value is 00h. 7 - 0 - - cache line size (cals) the cache line size is not supported by this device. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 73 audio digital controller 11.4.5 base address register (bar) ? offset 0x10 bit r/w default description 31 - 8 r/w 43e108h base address (ba) this address determines the starting address of audio controller?s i/o registers . 11.4.6 sub - system vendor id register (svid) ? offset 0x2c bit r/w default description 15 - 0 ro 1283h sub - system vendor id (svid) subsystem vendor id. these bits can be written by being programmed through 0x9c~9d. 11.4.7 sub - system id register (sid) ? offset 0x2e bit r/w default description 15 - 0 ro 1283h sub - system id (sid) sub - system id. these bits can be written by being programmed through 0x9e~9f. 11.4.8 capability pointer register (cp) ? offset 0x34 bit r/w default description 7 - 0 ro dch capabilities pointer (c p) this register indicates where the pci power management features a p pear in the standard configuration space header. 11.4.9 interrupt line register (ilr) ? offset 0x3c bit r/w default description 7 - 0 r/w 00h interrupt line (il) this register is used to com municate the interrupt line routing information. 11.4.10 interrupt pin register (ipr) ? offset 0x3d bit r/w default description 7 - 0 ro 01h interrupt pin (ip) this register is hardwired to 01h, which indicates that this device uses inta# as the interrupt pin. 11.4.11 min grant period for pci burst period register (mgpbp) ? offset 0x3e bit r/w default description 7 - 0 ro 04h min grant period (mgp) this register is used to specify how long of a burst period the device needs (in 1/4 microsecond unit). this device will use 1 m s burst period. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 74 it81 52f/IT8152G 11.4.12 max latency for pci grant period register (mlpgp) ? offset 0x3f bit r/w default description 7 - 0 ro 28h max latency (ml) this register is used to specify how often the device needs (in 1/4 micr o second unit) to gain the access t o the pci bus. this device needs the pci bus grant every 10 m s. 11.4.13 vendor id writeable register (vidw) ? offset 0x98 bit r/w default description 15 - 0 r/w 1283h vendor id (vid) ite vendor id. the value of this register will also show in 00~01h. 11.4.14 device id writeable register (didw) ? offset 0x9a bit r/w default description 15 - 0 r/w 0801h device id (did) the value of this register will also show in 02~03h. 11.4.15 sub - system vendor id writeable register (svidw) ? offset 0x9c bit r/w default description 15 - 0 r/w 1283h sub - system vendor id (svid) the value of this register will also show in 2c~2dh. 11.4.16 sub - system id writeable register (sidw) ? offset 0x9e bit r/w default description 15 - 0 r/w 1283h sub - system id (sid) the value of this register will also show i n 2e~2fh. 11.4.17 dfc reset control register (drc) ? offset 0xa0 bit r/w default description 7 - 3 - - reserved 2 r/w 0 dc test enable (dte) 1 r/w 0 reset dfc pointer enable 1 (rdpe1) when receiving playback start command, dfc pointer is reset if this bit is s et to 1. 0 r/w 0 reset dfc pointer enable 0 (rdpe0) when receiving playback stop command, dfc pointer is reset if this bit is set to 1. 11.4.18 capability id register (cid) ? offset 0xdc bit r/w default description 7 - 0 ro 01h capability id (cid) a ?01? indica tes that the linked list items are the pci power management registers. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 75 audio digital controller 11.4.19 next item pointer register (nip) ? offset 0xdd bit r/w default description 7 - 0 ro 00h next item pointer (nip) a ?00? indicates that there are no additional items in the capability list. 11.4.20 power management capability register (pmc) ? offset 0xde bit r/w default description 15 - 11 ro 00000 pme support (pmes) a ?00000? indicates that there is no pme support. 10 ro 1 d2 support (d2s) 1: yes (shutdown 24 mhz clock, ac?97 dac, adc, and mixer). 0: no. 9 ro 0 d1 support (d1s) 1: yes, 0: no. 8 - 6 - - reserved 5 ro 1 device specific initialization (dsi) a ?1? indicates that the function requires that an initialization sequence specified by a device, following a transition from the non - d0 uninitialized state to the d0 uninitialized state. 4 - - reserved 3 ro 0 pme clock (pmeck) a ?0? indicates that no pci clock is required to generate pme#. 2 - 0 ro 001 version number (vn) 11.4.21 power management control/status register (pmcs) ? offset 0xe0 b it r/w default description 15 r/wc 0 pme status (pmes) writing ?1? to this bit will clear it and cause the function to stop asserting a pme#. the default value of 0 indicates the function does not support pme# generation from the d3 cold state. 14 - 13 ro 00 data scale (dsc) 12 - 9 ro 00000 data select (dsel) 8 r/w 0 pme enable (pmee) 7 - 2 - - reserved 1 - 0 r/w 00 power state (ps) the change of power state from d3 to d0 will cause the software reset. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 76 it81 52f/IT8152G 11.5 operation register description the default value of the b ase a ddress for all registers is 0x43e10800 . not e that these registers can be re - allocated by changing the base address register. register name r/w offset default playback channel control register (pcc) r/w 0x08 ca01h playback channel data length/ current count register (pcdl/cc) r/w 0x0a - playback channel buffer i system starting address register (pcb1sta) r/w 0x0c - playback channel buffer ii system starting address register (pcb2sta) r/w 0x10 - capture channel control register (capcc) r/w 0x1 4 ca00h capture channel data length/current count register (capcdl/cc) r/w 0x16 - capture channel buffer i system starting address register (capb1sta) r/w 0x18 - capture channel buffer ii system starting address register (capb2sta) r/w 0x1c - codec con trol register (codecc) r/w 0x22 0000h codec index register command port (circp) r/w 0x2a 0000h codec index register data port (cirdp) r/w 0x2c - pci fifo data port register (pfdp) r/w 0x4c - general control register (gc) r/w 0x54 00h interrupt mask co ntrol register (imc) r/w 0x56 03h interrupt status/clear register (isc) r/wc 0x5b 00h blocks power down control register (bpdc) r/w 0x70 00h definitions of r/w attributes: ro read only . if a register is read only, writes to this register will have no effects. r/w read/write . a register with this attribute can be read and written. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of 1 clears the corresponding bit and a write of 0 has no effects. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 77 audio digital controller 11.5.1 play back channel control register (pcc) ? offset 0x08 bit r/w default description 15 r/w 1 stereo/mono (sm) 0: mono, 1: stereo. 14 r/w 1 data format (df) 0: 8 - bit unsigned, 1: 16 - bit signed. 13 - 8 - - reserved 7 r/w 0 channel stop point (csp) 0: at the end of the current buffer. 1: immediately stop when receiving stop command. 6 r/w 0 channel pause (cp) 0: normal. 1: transfer pause. (to pause, bit 5 has to remain at ?1?.) 5 r/w 0 channel action (ca) 0: stop transfer. 1: start transfer. 4 - 3 - - reserved 2 r/w 0 current buffer ii transfer is the last transfer (cb2l) 0: no, 1: yes. 1 r/w 0 current buffer i transfer is the last transfer (cb1l) 0: no, 1: yes. 0 ro 1 dfc/pfifo data empty (de) 1: empty. 0: not empty. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 78 it81 52f/IT8152G 11.5.2 playback channel data length/current c ount register (pcdl/cc) ? offset 0x0a bit r/w default description 15 - 0 r/w - data length/current count (dl/cc) (write) ds channel data length for buffer i and ii (have to be the same size for both buffers). the actual transfer count will be this register value plus 1. (read) ds channel data current remaining count.(not available until playback starts.) 11.5.3 playback channel buffer i system starting address register (pcb1sta) ? offset 0x0c bit r/w default description 31 - 0 r/w - buffer 1 starting address (b1 sa) (write) ds playback channel buffer i system starting address. (read) ds playback channel buffer i current address. 11.5.4 playback channel buffer ii system starting address register (pcb2sta) ? offset 0x10 bit r/w default description 31 - 0 r/w - buffer 2 s tarting address (b2sa) (write) ds playback channel buffer ii system starting address. (read) ds playback channel buffer ii current address. 11.5.5 capture channel control register (capcc) ? offset 0x14 bit r/w default description 15 r/w 1 stereo/mono (sm) 0: mono. 1: stereo. 14 r/w 1 data format (df) 0: 8 - bit unsigned. 1: 16 - bit signed. 13 - 8 - - reserved 7 r/w 0 channel stop point (csp) 0: at the end of current buffer. 1: immediately stop when receiving stop command. 6 r/w 0 channel pause (cp) 0: normal. 1: transfer pause. (to pause, the bit 5 has to remain at ?1?.) 5 r/w 0 channel action (ca) 0: stop transfer. 1: start transfer. 4 - 3 - - reserved 2 r/w 0 current buffer ii transfer is the last transfer (cb2l) 0: no, 1: yes. 1 r/w 0 current buffer i tran sfer is the last transfer (cb1l) 0: no, 1:yes. 0 - - reserved www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 79 audio digital controller 11.5.6 capture channel data length/current count register (capcdl/cc) ? offset 0x16 bit r/w default description 15 - 0 r/w - data length/current count (dl/cc) (write) ds channel data length for bu ffer i and ii (have to be the same size for both buffers). the actual transfer count will be this register value plus 1. (read) ds channel data current remaining count.(not available until playback starts) 11.5.7 capture channel buffer i system starting address register (capb1sta) ? offset 0x18 bit r/w default description 31 - 0 r/w - buffer 1 starting address (b1sa) (write) ds capture channel buffer i system starting address. (read) ds capture channel buffer i current address. 11.5.8 capture channel buffer ii system starting address register (capb2sta) ? offset 0x1c bit r/w default description 31 - 0 r/w - buffer 2 starting address (b2sa) (write) ds capture channel buffer ii system starting address. (read) ds capture channel buffer ii current address. 11.5.9 codec control register (codecc) ? offset 0x22 bit r/w default description 15 - 9 - - reserved 8 r/w 0 ac?97 ate test mode (atm) 1: ate test mode on, 0: normal. 7 - - reserved 6 r/w 0 ac?97 warm reset (wr) 1: warm reset, 0: normal. 5 r/w 0 ac?97 cold reset (cr) 1: c old reset, 0: normal. 4 - 0 - - reserved www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 80 it81 52f/IT8152G 11.5.10 codec index register command port (circp) ? offset 0x2a bit r/w default description 15 - 10 - - reserved 9 ro 0 command port status (cps) 0: ready, 1: busy. 8 ro 0 data port valid flag (dpvf) 0: invalid, 1: va lid. 7 r/w 0 read/write command (rwc) 0: write, 1: read. 6 - 0 r/w - codec index address (cia) 11.5.11 codec index register data port (cirdp) ? offset 0x2c bit r/w default description 15 - 0 r/w - codec register data port (cdp) 11.5.12 pci fifo data port register (pf dp) ? offset 0x4c bit r/w default description 31 - 0 r/w - pci fifo data port (pfdp) playback/capture fifo data port. 11.5.13 general control register (gc) ? offset 0x54 bit r/w default description 7 - 6 r/w 00 volume division control (vdc) 00: no division, 01: all sources divided by 2, 10: divided by 4. 5 - 2 - - reserved 1 - 0 reserved 0 r/w 0 software warm reset (swr) 1: software warm reset, 0: normal. 11.5.14 interrupt mask control register (imc) ? offset 0x56 bit r/w default description 7 - - reserved note: do not write 0 to this bit. 6 - 2 - - reserved 1 r/w 1 capture channel interrupt mask (ccim) 1: mask, 0: non - mask. 0 r/w 1 playback channel interrupt mask (pcim) 1?: mask, 0: non - mask. www.i te.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 81 audio digital controller 11.5.15 interrupt status/clear register (isc) ? offset 0x5b bit r/w defaul t description 7 - 2 - - reserved 1 r/wc 0 capture channel interrupt (cci) a write of ?1? will clear the interrupt. a write of ?0? will have no effects. 0 r/wc 0 playback channel interrupt (pci) a write of ?1? will clear the interrupt. a write of ?0? will have no effects. 11.5.16 blocks power down control register (bpdc) ? offset 0x70 - 0x71 bit r/w default description 15 - 9 - - reserved 8 r/w 0 pci clock can be turn off (pctf) 1: ready, 0: not ready to power down. 7 - 0 - - reserved 11.6 protocol and data flow 11.6.1 c odec dac and adc data access codec i/f will read the dac data (left and right channels) from dfc (data format control) when slot request sent from codec is active. if the underrun condition occurs, the same dac data have to remain in the buffer of the dig ital mixer for codec i/f to access. codec i/f will write the adc data (left and right channels) to the dfc. when the overrun condition occurs, the new data will overwrite the previous data. 11.6.2 codec control register access 1. host can access the codec index r egisters through the control register (0x2a~2d). for register writes, the host has to poll the bit 9 of the codec index register command port (0x2a~2b) first until it is ready. after users make sure that hw is ready to access the codec registers, the host can program the data port (0x2c~2d) first, then it should issue the ?write command? and the index address to register 0x2a to trigger the hw to start programming codec. 2. for register reads from codec, the host has to poll the bit 9 of the codec index regi ster command port (0x2a~2b) first until it is ready. the host is then allowed to issue the ?read command? and the address to register 0x2a. to read the data, host starts to poll the bit 8 of the codec index register command port u n til it is set before it c an read the data from data port at 0x2c~2d. www.ite.com.tw it8152f/IT8152G v0.3.4 www.iteusa.com 82 it81 52f/IT8152G 11.6.3 directsound playback 1. program the playback channel data length register (0x0a~0x0b) and playback buffer i & ii system starting address registers (0x0c~0x13) with the proper value. 2. set playback wave format by setting stereo or mono, 8 - bit or 16 - bit and the sampling rate at the playback channel control register (0x08~09). 3. fill the buffer 1 and buffer 2 with the playback data. set the bit 5 of the playback channel control register (0x08~09) to ?1? to start the pc i bus - master transfer for playback. 4. playback current address can be read from the playback channel buffer address register (0x0c~0x0f or 0x10~0x13). playback current remaining count can be read from the playback channel current count register (0x0a~0x0b) t o determine where the hw pointer is. the interrupt status will be generated when the current count reaches ?0?. 5. when the current count reaches ?0?, hw will switch to buffer 2 starting address to transfer the data (ping - pong buffers scheme) and the current count will be re - loaded and start from data length again. in the meantime, the driver has to start filling the data in the buffer 1. 6. to pause the playback operations, set the bit 6 of the playback channel control register (0x08~09) to ?1?. to resume, just restore ?0? to the bit 6. 7. to stop/finish playback, set the bit 7 of the playback channel control register (0x08~09) to ?1? and the bit 5 to ?0?. 11.6.4 directsound recording 1. program the capture channel data length register (0x16~0x17) and the capture channel b uffer i & ii system starting address registers (0x18~0x1f) with the proper value. 2. set recording wave format by setting stereo or mono, 8 - bit or 16 - bit and the sampling rate at the capture channel control register (0x14~15). 3. set the bit 5 of the capture cha nnel control register (0x14~15) to ?1? to start the pci bus - master transfer for recording. 4. capture current address can be read from the capture channel buffer i or ii system starting address register (0x18~0x1b or 0x1c~0x1f). the capture current remaining count can be read from the capture channel current count register (0x16~0x17) to determine where the hw pointer is. the interrupt status will be generated when the current count reaches ?0?. 5. when the current count reaches ?0?, hw will switch to buffer 2 st arting address to transfer the data (ping - pong buffers scheme) and the current count will be re - loaded and start from the data length again. in the mean time, the driver has to move the data in the buffer 1 to the system. 6. to pause the recording, set the bi t 6 of the capture channel control register (0x14~15) to ?1?. to resume, just restore ?0? to the bit 6. 7. to stop/finish recording, set the bit 7 of the capture channel control register (0x14~15) to ?1? and the bit 5 to ?0?. |
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