1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 satellite applications flow? (saf) is a trademark of intersil corporation. hs-565arh-t radiation hardened high speed, monolithic digital-to-analog converter intersils satellite applications flow tm (saf) devices are fully tested and guaranteed to 100krad total dose. this qml class t device is processed to a standard ?ow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. the hs-565arh-t is a fast, radiation hardened 12-bit current output, digital-to-analog converter. the monolithic chip includes a precision voltage reference, thin-?lm r-2r ladder, reference control ampli?er and twelve high-speed bipolar current switches. the intersil semiconductor dielectric isolation process provides latch-up free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to code- dependent ground currents. hs-565arh-t die are laser trimmed for a maximum integral nonlinearity error of 0.25 lsb at 25 o c. in addition, the low noise buried zener reference is trimmed both for absolute value and minimum temperature coefficient. speci?cations speci?cations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed below must be used when ordering. detailed electrical speci?cations for the hs-565arh-t are contained in smd 5962-96755. a hot-link is provided from our website for downloading . www.intersil.com/spacedefense/newsafclasst.asp intersils quality management plan (qm plan), listing all class t screening operations, is also available on our website. www.intersil.com/quality/manuals.asp features ? qml class t, per mil-prf-38535 ? radiation performance - gamma dose ( g ) 1 x 10 5 rad(si) - no latch-up, dielectrically isolated device islands ? dac and reference on a single chip ? pin compatible with ad-565a and hi-565a ? very high speed: settles to 0.50 lsb in 500ns max ? monotonicity guaranteed over temperature ? 0.50 lsb max nonlinearity guaranteed over temperature ? low gain drift (max., dac plus reference) 50ppm/ o c ? 0.75 lsb accuracy guaranteed over temperature ( 0.125 lsb typical at 25 o c) pinouts HS1-565ARH-T (sbdip), cdip2-t24 top view hs9-565arh-t (flatpack), cdfp4-f24 top view ordering information ordering number part number temp. range ( o c) 5962r9675501tjc HS1-565ARH-T -55 to 125 5962r9675501txc hs9-565arh-t -55 to 125 note: minimum order quantity for -t is 150 units through distribution, or 450 units direct. 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 nc nc v cc ref out ref gnd ref in -v ee bipolar rin idac out 10v span 20v span pwr gnd bit 1 in (msb) bit 3 in bit 4 in bit 5 in bit 6 in bit 8 in bit 10 in bit 11 in bit 12 in (lsb) bit 2 in bit 7 in bit 9 in 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 nc nc v cc ref out ref gnd ref in -v ee bipolar rin idac out 10v span 20v span pwr gnd bit 1 in bit 3 in bit 4 in bit 5 in bit 6 in bit 8 in bit 10 in bit 11 in bit 12 in bit 2 in bit 7 in bit 9 in (lsb) (msb) data sheet july 1999 file number 4607.1
2 functional diagram de?nitions of speci?cations digital inputs the hs-565arh-t accepts digital input codes in binary format and may be user connected for any one of three binary codes. straight binary, twos complement (see note below), or offset binary, (see operating instructions). accuracy nonlinearity - nonlinearity of a d/a converter is an important measure of its accuracy. it describes the deviation from an ideal straight line transfer curve drawn between zero (all bits off) and full scale (all bits on). differential nonlinearity - for a d/a converter, it is the difference between the actual output voltage change and the ideal (1 lsb) voltage change for a one bit change in code. a differential nonlinearity of 1 lsb or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. settling time settling time is the time required for the output to settle to within the speci?ed error band for any input code transition. it is usually speci?ed for a full scale or major carry transition, settling to within 0.50 lsb of ?nal value. drift gain drift - the change in full scale analog output over the speci?ed temperature range expressed in parts per million of full scale range per o c (ppm of fsr/ o c). gain error is measured with respect to 25 o c at high (t h ) and low (t l ) temperatures. gain drift is calculated for both high (t l - 25 o c) and low ranges (25 o c - t l ) by dividing the gain error by the respective change in temperature. the speci?cation is the larger of the two representing worst case drift. offset drift - the change in analog output with all bits off over the speci?ed temperature range expressed in parts per million of full scale range per o c (ppm of fsr/ o c). offset error is measured with respect to 25 o c at high (t h ) and low (t l ) temperatures. offset drift is calculated for both high (t d - 25 o c) and low (25 o c-t l ) ranges by dividing the offset error by the respective change in temperature. the speci?cation given is the larger of the two, representing worst case drift. power supply sensitivity power supply sensitivity is a measure of the change in gain and offset of the d/a converter resulting from a change in -15v or +15v supplies. it is specified under dc conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of fsr/%). compliance compliance voltage is the maximum output voltage range that can be tolerated and still maintain its speci?ed accuracy. compliance limit implies functional operation only and makes no claims to accuracy. glitch a glitch on the output of a d/a converter is a transient spike resulting from unequal internal on-off switching times. worst case glitches usually occur at half scale or the major carry code transition from 011 . . . 1 to 100 . . . 0 or vice versa. for example, if turn on is greater than turn off for 011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0 exists, such that, the output momentarily glitches toward zero output. matched switching times and fast switching will reduce glitches considerably. ref out v cc 43 + - 19.95k ref 10v 6 5 ref + - 3.5k 3k i ref 0.5ma -v ee pwr gnd 712 24. . . 13 msb lsb (4x iref x code) gnd in 20v span 10v span out io dac 9.95k bip. off. 8 5k 5k 2.5k 11 10 9 digital input analog output straight binary offset binary (note) twos complement msb . lsb 000 . . . 000 zero - f s (full scale) zero 100 . . . 000 0.50 f s zero - f s 111 . . . 111 + f s - 1 lsb + f s - 1 lsb zero - 1 lsb 011 . . . 111 0.50 f s - 1 lsb zero - 1 lsb + f s - 1 lsb note: invert msb with external inverter to obtain twos complement coding. hs-565arh-t
3 applying the hs-565arh-t op amp selection the hs-565arh-ts current output may be converted to voltage using the standard connections shown in figures 1 and 2. the choice of operational ampli?er should be reviewed for each application, since a signi?cant trade-off may be made between speed and accuracy. remember settling time for the dac-ampli?er combination is: where t d , t a are settling times for the dac and ampli?er. no trim operation the hs-565arh-t will perform as speci?ed without calibration adjustments. to operate without calibration, substitute 50 w resistors for the 100 w trimming potentiometers: in figure 1 replace r2 with 50 w ; also remove the network on pin 8 and connect 50 w to ground. for bipolar operation in figure 2, replace r3 and r4 with 50 w resistors. with these changes, performance is guaranteed as shown under speci?cations, external adjustments. typical unipolar zero will be 0.50 lsb plus the op amp offset. the feedback capacitor c must be selected to minimize settling time. t d () 2 t a () 2 + figure 1. unipolar voltage output figure 2. bipolar voltage output v o - + r (see table 7) dac out 9 10 11 20v span 10v span 2.5k 5k 5k c 9.95k io 24 13 msb lsb . . . . . code input dac (4 x i ref -v ee pwr gnd 7 x code) i ref 0.5ma hs-565arh-t 3k 3.5k 19.95 k + - 10v 3 4 v cc + - 6 5 ref gnd ref in ref out r2 100 w 8 bip. off. +15v -15v r1 50k w 100k w 100 w v o - + r (see table 7) dac out 9 10 11 20v span 10v span 2.5k 5k 5k c 9.95k io 24 13 msb lsb . . . . . code input dac (4 x i ref -v ee pwr gnd 7 x code) i ref 0.5ma hs-565arh-t 3k 3.5k 19.95k + - 10v 3 4 v cc + - 6 5 ref gnd ref in ref out r4 100 w 8 bip. off. r3 100 w hs-565arh-t
4 calibration calibration provides the maximum accuracy from a converter by adjusting its gain and offset errors to zero, for the hs-565arh-t, these adjustments are similar whether the current output is used, or whether an external op amp is added to convert this current to a voltage. refer to table 7 for the voltage output case, along with figure 1 or 2. calibration is a two step process for each of the ?ve output ranges shown in table 1. first adjust the negative full scale (zero for unipolar ranges). this is an offset adjust which translates the output characteristic, i.e., affects each code by the same amount. next adjust positive f s . this is a gain error adjustment, which rotates the output characteristic about the negative f s value. for the bipolar ranges, this approach leaves an error at the zero code, whose maximum values is the same as for integral nonlinearity error. in general, only two values of output may be calibrated exactly; all others must tolerate some error. choosing the extreme end points (plus and minus full scale) minimizes this distributed error for all other codes. settling time this is a challenging measurement, in which the result depends on the method chosen, the precision and quality of test equipment and the operating con?guration of the dac (test conditions). as a result, the different techniques in use by converter manufacturers can lead to consistently different results. an engineer should understand the advantage and limitations of a given test method before using the speci?ed settling time as a basis for design. the approach used for several years at intersil calls for a strobed comparator to sense ?nal perturbations of the dac output waveform. this gives the lsb a reasonable magnitude (814mv for the hs-565arh-t, which provides the comparator with enough overdrive to establish an accurate 0.50 lsb window about the ?nal settled value. also, the required test conditions simulate the dacs environment for a common application - use in a successive approximation a/d converter. considerable experience has shown this to be a reliable and repeatable way to measure settling time. the usual speci?cation is based on a 10v step, produced by simultaneously switching all bits from off-to-on (t on ) or on- to-off (t off ). the slower of the two cases is speci?ed, as measured from 50% of the digital input transition to the ?nal entry within a window of 0.50 lsb about the settled value. four measurements characterize a given type of dac: (cases (b) and (c) may be eliminated unless the overshoot exceeds 0.50 lsb). for example, refer to figures 3a and 3b for the measurement of case (d). procedure as shown in figure 3b, settling time equals t x plus the comparator delay (t d = 15ns). to measure t x : ? adjust the delay on generator number 2 for a t x of several microseconds. this assures that the dac output has settled to its ?nal wave ? switch on the lsb (+5v) ? adjust the vlsb supply for 50% triggering at comparator out. this is indicated by traces of equal brightness on the oscilloscope display as shown in figure 3b. note dvm reading ? switch to lsb to pulse (p) ? readjust the vlsb supply for 50% triggering as before, and note dvm reading. one lsb equals one tenth the difference in the dvm readings noted above ? adjust the vlsb supply to reduce the dvm reading by 5 lsbs (dvm reads 10x, so this sets the comparator to sense the ?nal settled value minus 0.50 lsb). comparator output disappears ? reduce generator number 2 delay until comparator output reappears, and adjust for equal brightness ? measure t x from scope as shown in figure 3b. settling time equals t x + t d , i.e., t x + 15ns (a) t on , to final value +0.50 lsb (b) t on , to final value -0.50 lsb (c) t off , to final value +0.50 lsb (d) off, to final value -0.50 lsb table 1. operating modes and calibration mode circuit connections calibration output range pin 10 to pin 11 to resistor (r) apply input code adjust to set vo unipolar (see figure 1) 0 to +10v vo pin 10 1.43k all 0s all 1s r1 r2 0v +9.99756v 0 to +5v vo pin 9 1.1k all 0s all 1s r1 r2 0v +4.99878v hs-565arh-t
5 other considerations grounds the hs-565arh-t has two ground terminals, pin 5 (ref gnd) and pin 12 (pwr gnd). these should not be tied together near the package unless that point is also the system signal ground to which all returns are connected. (if such a point exists, then separate paths are required to pins 5 and 12). the current through pin 5 is near zero dc (note); but pin 12 carries up to 1.75ma of code - dependent current from bits 1, 2, and 3. the general rule is to connect pin 5 directly to the system quiet point, usually called signal or analog ground. connect pin 12 to the local digital or power ground. then, of course, a single path must connect the analog/signal and digital/power grounds. note: current cancellation is a two step process within the hs- 565arh-t in which code dependent variations are eliminated, the re- sulting dc current is supplied internally. first an auxiliary 9-bit r-2r ladder is driven by the complement of the dacs input code. together, the main and auxiliary ladders draw a continuous 2.25ma from the internal ground node, regardless of input code. part of the dc current is supplied by the zener voltage reference, and the remainder is sourced from the positive supply via a current mirror which is laser trimmed for zero current through the external terminal (pin 5). layout connections to pin 9 (i out ) on the hs-565arh-t are most critical for high speed performance. output capacitance of the dac is only 20pf, so a small change of additional capacitance may alter the op amps stability and affect settling time. connections to pin 9 should be short and few. component leads should be short on the side connecting to pin 9 (as for feedback capacitor c). see the settling time section. bypass capacitors power supply bypass capacitors on the op amp will serve the hs-565arh-t also. if no op amp is used, a 0.01mf ceramic capacitor from each supply terminal to pin 12 is suf?cient, since supply current variations are small. bipolar (see figure 2) 10v nc vo 1.69k all 0s all 1s r3 r4 -10v +9.99512v 5v vo pin 10 1.43k all 0s all 1s r3 r4 -5v +4.99756v 2.5v vo pin 9 1.1k all 0s all 1s r3 r4 -2.5v +2.49878v figure 3a. figure 3b. table 1. operating modes and calibration (continued) mode circuit connections calibration output range pin 10 to pin 11 to resistor (r) apply input code adjust to set vo vlsb supply 0.1 m f dvm comparator out b c 10 90 200k + - 5 9 10 nc 11 8 2.5k 5k 5k 20v 20% bias turn on turn off 9.95k 2ma 12 hs-565arh-t d out 14 13 23 24 . . . . . . . . . . . . . 5v p sync in trig out out a ~100 khz strobe in lsb pulse generator no. 2 pulse generator no. 2 50% digital input dac output comp. strobe comp. out equal brightness +3v 0v 0v -400mv 2v 0.8v 4v 0v (turn off) a b c d 50% t x td = comparator delay settling time -0.50lsb hs-565arh-t
6 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: (2718 m m x 4547 m m x 483 m m 25.4 m m) 107 x 179 x 19mils 1mil metallization: type: al si cu thickness: 16.0k ? 2k ? substrate potential: tie substrate to reference ground backside finish: silicon passivation: type: silox (s i o 2 ) thickness: 8k ? 1k ? worst case current density: < 2.0e5 a/cm 2 transistor count: 200 process: bipolar, dielectric isolation metallization mask layout hs-565arh-t v cc (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 (lsb) power gnd 20v span 10v span idac out bipolar r in -v ee v ref in v ref gnd v ref out 3 hs-565arh-t
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