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features ? power monitoring and switching for 3-volt battery-backup applica- tions ? write-protect control ? 3-volt primary cell inputs ? less than 10ns chip-enable propagation delay ? 5% or 10% supply operation general description the cmos bq2201 sram nonvolatile controller unit provides all necessary functions for converting a standard cmos sram into nonvolatile read/write memory. a precision comparator monitors the 5v v cc input for an out-of-tolerance condition. when out of tolerance is detected, a conditioned chip-enable output is forced inactive to write- protect any standard cmos sram. during a power failure, the external sram is switched from the v cc supply to one of two 3v backup sup- plies. on a subsequent power-up, the sram is write-protected until a power-valid condition exists. the bq2201 is footprint- and timing- compatible with industry stan- dards with the added benefit of a chip-enable propagation delay of less than 10ns. 1 sram nonvolatile controller unit bq2201 oct. 1998 d pin names v out supply output bc 1 bc 2 3-volt primary backup cell inputs ths threshold select input ce chip-enable active low input ce con conditioned chip-enable output v cc +5-volt supply input v ss ground nc no connect functional description pin connections an external cmos static ram can be battery-backed using the v out and the conditioned chip-enable output pin from the bq2201. as v cc slews down during a power failure, the conditioned chip-enable output ce con is forced inactive independent of the chip-enable input ce . this activity unconditionally write-protects external sram as v cc falls to an out-of-tolerance threshold v pfd . v pfd is selected by the threshold select input pin, ths. if ths is tied to v ss , power-fail detection occurs at 4.62v typical for 5% supply operation. if ths is tied to v cc , power-fail detection occurs at 4.37v typical for 10% sup- ply operation. the ths pin must be tied to v ss or v cc for proper operation. if a memory access is in process during power-fail detec- tion, that memory cycle continues to completion before the memory is write-protected. if the memory cycle is not ter- minated within time t wpt , the ce con output is uncondi- tionally driven high, write-protecting the memory. 1 pn220101.eps 8-pin narrow dip or soic 2 3 4 8 7 6 5 v cc bc 1 ce con ce v out bc 2 ths v ss 1 pn2201e.eps 16-pin soic 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc v cc nc bc 1 nc ce con nc ce nc v out nc bc 2 nc ths nc v ss
as the supply continues to fall past v pfd , an internal switching device forces v out to one of the two external backup energy sources. ce con is held high by the v out energy source. during power-up, v out is switched back to the v cc sup- ply as v cc rises above the backup cell input voltage sourcing v out . the ce con output is held inactive for time t cer (120 ms maximum) after the supply has reached v pfd , independent of the ce input, to allow for processor stabilization. during power-valid operation, the ce input is fed through to the ce con output with a propagation delay of less than 10ns. nonvolatility is achieved by hardware hookup, as shown in figure 1. energy cell inputsbc 1 ,bc 2 two primary backup energy source inputs are provided on the bq2201. the bc 1 and bc 2 inputs accept a 3v pri- mary battery, typically some type of lithium chemistry. if no primary cell is to be used on either bc 1 or bc 2 , the unused input should be tied to v ss . if both inputs are used, during power failure the v out output is fed only by bc 1 as long as it is greater than 2.5v. if the voltage at bc 1 falls below 2.5v, an internal isolation switch automatically switches v out from bc 1 to bc 2 . to prevent battery drain when there is no valid data to retain, v out and ce con are internally isolated from bc 1 and bc 2 by either of the following: n initial connection of a battery to bc 1 or bc 2 ,or n presentation of an isolation signal on ce . a valid isolation signal requires ce low as v cc crosses both v pfd and v so during a power-down. see figure 2. between these two points in time, ce must be brought to the point of (0.48 to 0.52) * v cc and held for at least 700ns. the isolation signal is invalid if ce exceeds 0.54 * v cc at any point between v cc crossing v pfd and v so . the appropriate battery is connected to v out and ce con immediately on subsequent application and removal of v cc . 2 fg220101.eps v cc ce bc 1 ths v ss v out ce con bc 2 bq2201 v cc ce cmos sram 5v from address decoder 3v primary cell 3v primary cell figure 1. hardware hookup (5% supply operation) oct. 1998 d td220101.eps v cc ce v pfd v so 0.5 v cc 700ns figure 2. battery isolation signal bq2201
3 absolute maximum ratings symbol parameter value unit conditions v cc dc voltage applied on v cc relative to v ss -0.3 to 7.0 v v t dc voltage applied on any pin excluding v cc relative to v ss -0.3 to 7.0 v v t v cc + 0.3 t opr operating temperature 0 to +70 c commercial -40 to +85 c industrial n t stg storage temperature -55 to +125 c t bias temperature under bias -40 to +85 c t solder soldering temperature 260 c for 10 seconds i out v out current 200 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional opera- tion should be limited to the recommended dc operating conditions detailed in this data sheet. expo- sure to conditions beyond the operational limits for extended periods of time may affect device reliability. recommended dc operating conditions (t a =t opr ) symbol parameter minimum typical maximum unit notes v cc supply voltage 4.75 5.0 5.5 v ths = v ss 4.50 5.0 5.5 v ths = v cc v ss supply voltage 0 0 0 v v il input low voltage -0.3 - 0.8 v v ih input high voltage 2.2 - v cc + 0.3 v v bc1 , v bc2 backup cell voltage 2.0 - 4.0 v ths threshold select -0.3 - v cc + 0.3 v note: typical values indicate operation at t a = 25c, v cc = 5v or v bc . oct. 1998 d bq2201
4 dc electrical characteristics (t a =t opr ,v cc = 5v 10%) symbol parameter minimum typical maximum unit conditions/notes i li input leakage current - - 1 m av in =v ss to v cc v oh output high voltage 2.4 - - v i oh = -2.0ma v ohb v oh , bc supply v bc - 0.3 - - v v bc >v cc ,i oh = -10 m a v ol output low voltage - - 0.4 v i ol = 4.0ma i cc operating supply current - 3 5 ma no load on v out and ce con . v pfd power-fail detect voltage 4.55 4.62 4.75 v ths = v ss 4.30 4.37 4.50 v ths = v cc v so supply switch-over voltage - v bc -v i ccdr data-retention mode current - - 100 na v out data-retention current to additional memory not in- cluded. v out1 v out voltage v cc - 0.2 - - v v cc >v bc ,i out = 100ma v cc - 0.3 - - v v cc >v bc ,i out = 160ma v out2 v out voltage v bc - 0.3 - - v v cc 2.5v i out1 v out current - - 160 ma v out >v cc - 0.3v i out2 v out current - 100 - m av out >v bc - 0.2v note: typical values indicate operation at t a = 25c, v cc = 5v or v bc . oct. 1998 d bq2201
5 ac test conditions parameter test conditions input pulse levels 0v to 3.0v input rise and fall times 5ns input and output timing reference levels 1.5v (unless otherwise specified) output load (including scope and jig) see figure 3 fg220102.eps 5v 960 100pf ce con 510 figure 3. output load capacitance (t a = 25c, f = 1mhz, v cc = 5.0v) symbol parameter minimum typical maximum unit conditions c in input capacitance - - 8 pf input voltage = 0v c out output capacitance - - 10 pf output voltage = 0v note: this parameter is sampled and not 100% tested. oct. 1998 d bq2201
6 td220102.eps v cc ce con t pf t fs 4.75 v pfd 4.25 v so t wpt v ohb ce power-down timing power-fail control (ta = t opr ) symbol parameter minimum typical maximum unit notes t pf v cc slew, 4.75v to 4.25v 300 - - m s t fs v cc slew, 4.25v to v so 10 - - m s t pu v cc slew, 4.25v to 4.75v 0 - - m s t ced chip-enable propagation delay - 7 10 ns t cer chip-enable recovery 40 80 120 ms time during which sram is write-protected after v cc passes v pfd on power-up. t wpt write-protect time 40 100 150 m s delay after v cc slews down past v pfd before sram is write-protected. note: typical values indicate operation at t a = 25c. caution: negative undershoots below the absolute maximum rating of -0.3v in battery-backup mode may affect data integrity. oct. 1998 d bq2201
7 oct. 1998 d td220103.eps v cc t pu ce ce con v ohb v so 4.25 v pfd 4.75 t cer t ced t ced power-up timing bq2201
8 oct. 1998 d 8-pin soic narrow (sn) dimension minimum maximum a 0.060 0.070 a1 0.004 0.010 b 0.013 0.020 c 0.007 0.010 d 0.185 0.200 e 0.150 0.160 e 0.045 0.055 h 0.225 0.245 l 0.015 0.035 all dimensions are in inches. 8-pin soic narrow (sn) 8-pin dip narrow (pn) dimension minimum maximum a 0.160 0.180 a1 0.015 0.040 b 0.015 0.022 b1 0.055 0.065 c 0.008 0.013 d 0.350 0.380 e 0.300 0.325 e1 0.230 0.280 e 0.300 0.370 g 0.090 0.110 l 0.115 0.150 s 0.020 0.040 all dimensions are in inches. 8-pin dip narrow (pn) bq2201
9 bq2201 oct. 1998 d s: 16-pin soic e d b e h a1 a c l .004 16-pin s ( soic ) dimension minimum maximum a 0.095 0.105 a1 0.004 0.012 b 0.013 0.020 c 0.008 0.013 d 0.400 0.415 e 0.290 0.305 e 0.045 0.055 h 0.395 0.415 l 0.020 0.040 all dimensions are in inches.
10 bq2201 oct. 1998 d data sheet revision history change no. page no. description nature of change 1 added industrial temperature range 2 1, 3, 4 10% supply operation was: ths tied to v out is: ths tied to v cc 3 1, 9, 11 added 16-pin package option note: change 1 = sept. 1991 b changes from sept. 1990 a. change 2 = aug. 1997 c changes from sept. 1991 b. change 3 = oct. 1998 d changes from aug. 1997 c.
11 ordering information bq2201 package option: pn = 8-pin narrow plastic dip sn = 8-pin narrow soic s = 16-pin soic device: bq2201 nonvolatile sram controller temperature range: blank = commercial (0 to +70c) n = industrial (-40 to +85c) bq2201 oct. 1998 d
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated

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