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december 2002 designing an off-line power supply involves many aspects of electrical engineering: analog and digital circuits, bipolar and mos power device characteristics, magnetics, thermal considerations, safety requirements, control loop stability, etc. this represents an enormous challenge involving complex trade-offs with a large number of design variables. as a result, new off-line power supply development has always been tedious and time consuming even for the experts in the field. this application note introduces a simple, yet highly efficient methodology for the design of topswitch-gx family based off-line power supplies. for topswitch-gx flyback designs, power integrations recommends the use of pi expert which implements this design methodology and also includes a knowledge base and optimization feature for making key design choices, further reducing design time. introduction the design of a switching power supply, by nature, is an iterative process with many variables requiring adjustment to optimize the design. the design method described in this document consists of two major sections: a design flow chart and a step-by-step design procedure. the flow chart shows the design sequence at a conceptual level for topswitch-gx flyback power supply design. the step-by-step procedure gives details within each step of the design flow chart, including empirical design guidelines and look-up tables. all key equations and guidelines are provided wherever possible to assist the readers in better understanding and/or further optimization. basic circuit configuration because of the high level integration of topswitch-gx , many power supply design issues are resolved in the chip. far fewer issues are left to be addressed externally, resulting in one common circuit configuration for all applications. different output power levels may require different values for some circuit components, but the circuit configuration stays unchanged. topswitch-gx is a feature-rich product family. advanced features like under-voltage, overvoltage, external i limit , line feed forward, and remote on/off are easily implemented with a minimal number of external components, but do involve additional design considerations. please refer to the topswitch-gx data sheet for details. other application figure 1. typical topswitch-gx flyback power supply. d s c control l f x +v d - v ac +v db - clamp zener pi-3038-091102 v o c in v b + - output capacitor output post filter l, c bias capacitor blocking diode control pin capacitor and series resistor external i limit resistor (optional) line sense resistor f s = 132 khz if connected as shown. for f s = 66 khz, connect "f" pin to "c" pin (f s option not available with p or g package) feedback circuit control control topswitch-gx + - + topswitch-gx flyback design methodology application note AN-32
AN-32 2 b 12/02 specific issues such as constant current, constant power outputs, etc. are beyond the scope of this application note. however, such requirements may be satisfied by adding additional circuitry to the basic converter configuration. the only part of the circuit configuration that may change from application to application is the feedback circuitry. depending on the power supply output specifications, one of the four feedback circuits, shown in figures 3, 4, 5 and 6, will be chosen for the application. the basic circuit configuration used in topswitch-gx flyback power supplies is shown in figure 1, which also serves as the reference circuit for component identifications used in the description throughout this application note. design flow figures 2a, 2b and 2c present a design flow chart showing the complete design procedure in 37 steps. with the basic circuit configuration shown in figure 1 as its foundation, the logic behind this design approach can be summarized as follows: 1. determine system requirements and decide on feedback circuit accordingly. 2. choose the smallest topswitch-gx capable of the required output power. 3. design the smallest transformer for the topswitch-gx chosen. 4. select all other components in figure 1 to complete the design. figure 2a. topswitch-gx design flow chart. step 1 to 11. 1. system requirements v acmin , v acmax , f l , v o , p o , , z 2. choose feedback circuit & v b 3. determine c in , v min , v max 4. determine v or , v clo 6. determine d max 5. set k p 9. choose topswitch-gx & f s using an-29 10. set i limit reduction factor k i calculate i limit (min) & i limit (max) n y 8. calculate primary rms current i rms to step 12 step 1-2 determine system level requirements and choose feedback circuit 11. i p i limit (min) step 3-11 choose the smallest topswitch-gx for the required power pi-3039-080502 7. calculate primary peak current i p from step 23
AN-32 3 b 12/02 figure 2b. topswitch-gx design flow chart. step 12 to 28. 13. choose core & bobbin determine a e , l e , a l , bw 14. set n s , l 15. calculate n p , n b y 22. n s , l iterated 17. calculate b m to step 28 step 12-28 design the smallest transformer to work with the topswitch-gx chosen 24. calculate i sp n 12. determine l p n y y y n n y 18. b m 3000 19. calculate l g , cma 20. l g 0.10 mm 16. calculate od, dia, awg n 23. b p 4200 from step 11 to step 10 pi-3040-091802 21. 200 cma 500 25. calculate i srms 26. calculate od s , dia s , awg s to step 29 28. calculate piv s , piv b 27. calculate i ripple
AN-32 4 b 12/02 figure 2c. topswitch-gx design flow chart. step 29 to 37. step 29-37 select other components from step 28 29. select clamp zener & blocking diode 31. select output capacitor 32. select output post filter l, c 33. select bias rectifier 34. select bias capacitor 35. select control pin capacitor & series resistor 36. select feedback circuit compenents according to reference feedback circuits in figures 3, 4, 5 and 6 37. select bridge rectifier design complete 30. select output rectifier pi-2584-091402 the overriding objective of this procedure is ?esign for cost effectiveness.?using smaller components usually leads to a less expensive power supply. however, for applications with stringent size or weight limitations, the designer may need to strike a compromise between cost and specific design requirements in order to achieve the optimum cost effectiveness for the end product.
AN-32 5 b 12/02 power supply efficiency, : 0.8 if no better reference data available. (refer to an-29) loss allocation factor, z: if z = 1, all losses are on the secondary side. if z = 0, all losses are on the primary side. set z = 0.5 if no better reference data is available. step 2. choose feedback circuit and bias voltage v b based on output requirements feedback v b circuit load* line total circuit (v) tolerance reg. reg. reg. pri./basic 5.8 10% 5% 1.5% 16.5% pri./enhan. 27.8 5% 2.5% 1.5% 9% opto/zener 12 5% 1% 0.5% 6.5% opto/tl431 12 1% 0.2% 0.2% 1.4% *over 10% to 100% load range. table 2. use primary feedback for lowest cost (for low power applications only). use opto/zener for low cost, good output accuracy. use opto/tl431 for best output accuracy. set bias voltage v b according to table 2. choose optocoupler from table 3. step-by-step design procedure this design procedure uses the pi expert design software (available from power integrations), which contains all the important equations required for a topswitch-gx flyback power supply design, and automates most calculations. designers are, therefore, relieved from the tedious calculations involved in the complicated and highly iterative design process. look-up tables and empirical design guidelines are provided in this procedure where appropriate to facilitate the design task. step 1. determine system requirements: v acmax , v acmin , f l , v o , p o , , z ? inimum ac input voltage, v acmin : in volts. ? aximum ac input voltage, v acmax : in volts. recommended ac input ranges: input (vac) v acmin (vac) v acmax (vac) universal 85 265 230 or 115 with doubler 195 265 table 1. line frequency, f l : 50 hz or 60 hz. output voltage, v o : in volts. output power: p o : in watts. figure 3. primary/basic feedback circuit. pi-3331-112202 d s c topswitch-gx control l + - f x v ac c in v o 15 ? feedback circuit + circuit performance circuit tolerance 10% load regulation 5% line regulation 1.5%
AN-32 6 b 12/02 figure 4. primary/enhanced feedback circuit. figure 5. opto/zener feedback circuit. pi-3330-091102 d s c topswitch-gx control l + - f x v ac c in v o 15 ? feedback circuit 1n5251d 22 v 1% 100 nf 50 v + circuit performance circuit tolerance 5% load regulation 2. 5% line regulation 1.5% pi-3328-112202 d s c topswitch-gx control l + - f x v ac c in zener, 2% ltv817a 470 ? ?? v o 47 ? ? feedback circuit + circuit performance circuit tolerance 5% load regulation 1% line regulation 0.5% ?? 470 ? is good for zeners with i zt = 5 ma. lower values are needed for zeners with higher i zt . (e.g. 150 ? for i zt = 20 ma). ? 47 ? is suitable for v o up to 7.5v. for v o > 7.5v, a higher value may be required for optimum transient response.
AN-32 7 b 12/02 figure 6. opto/tl431 feedback circuit. p/n ctr(%) bvceo manufacturer 4 pin dip pc123y6 80-160 70 v sharp pc817x1 80-160 70 v sharp sfh615a-2 63-125 70 v vishay, isocom sfh617a-2 63-125 70 v vishay, isocom sfh618a-2 63-125 55 v vishay, isocom isp817a 80-160 35 v vishay, isocom ltv817a 80-160 35 v liteon ltv816a 80-160 80 v liteon ltv123a 80-160 70 v liteon k1010a 60-160 60 v cosmo 6 pin dip ltv702fb 63-125 70 v liteon ltv703fb 63-125 70 v liteon ltv713fa 80-160 35 v liteon k2010 60-160 60 v cosmo pc702v2nszx 63-125 70 v sharp pc703v2nszx 63-125 70 v sharp pc713v1nszx 80-160 35 v sharp pc714v1nszx 80-160 35 v sharp moc8102 73-117 30 v vishay, isocom moc8103 108-173 30 v vishay, isocom moc8105 63-133 30 v vishay, isocom cny17f-2 63-125 70 v vishay, isocom, liteon table 3. optocoupler step 3. determine minimum and maximum dc input voltages v min , v max and input storage capacitance c in based on ac input voltage and p o (figure 7) choose input storage capacitor, c in per table 4. input (vac) c in ( f/watt of p o )v min (v) universal 2 ~ 3 90 230 or 115 with doubler 1 240 table 4 set bridge rectifier conduction time, t c = 3 ms. derive minimum dc input voltage v min where units are volts, watts, hz, seconds and farads calculate maximum dc input voltage v max : vv max acmax = 2 vv p f t c min acmin o l c in = ? ? ? ? ? ? ? ? () 2 2 1 2 2 pi-3329-112202 d s c topswitch-gx control l + - f x v ac c in tl431 utv817a v o 470 ? ( v o = 12 v) 1 k ? 3.3 k ? 100 nf 10 k ? r = v o - 2.5 2.5 x 10 k ? feedback circuit + 100 ? ( v o = 5 v) circuit performance circuit tolerance 1% load regulation 0.2% line regulation 0.2%
AN-32 8 b 12/02 step 4. determine reflected output voltage v or and clamp zener voltage v clo (figure 8) set reflected output voltage, v or = 100 v for multiple output, 120 v for single output. these values optimize cross-regulation and efficiency. to obtain the maximum output power from a given topswitch-gx device, set v or = 135 v. rcd (resistor/capacitor/diode) clamp may be used with topswitch-gx when and only when current limit is set externally with current limit reduction as a function of line voltage. compared to zener clamps, designs using rcd clamps usually have lower efficiency at light load. in addition, great care must be taken in rcd clamp design. because of its inherent variation in clamp voltage across load range, if not designed properly, an rcd clamp may fail to protect topswitch-gx , especially under startup or output overload conditions. figure 7. input voltage waveform. figure 8. reflected voltage v or and clamp zener voltage v clo . t c p o = output power f l = line frequency (50 or 60 hz) t c = conduction angle use 3 ms if unknown = efficiency v v acmin min 2 pi-2585-012500 v+ universal/230 vac input use v or = 120 v (100 v) and 180 v (150 v) zener clamp for single (multiple) output pi-3336-091402 bv dss v or = 120 v (100 v) margin = 53 v (95 v) blocking diode forward recovery = 20 v 700 v 495 v (475 v) 375 v 0 v 0 v v clo = 1.5 x v or = 180 v (150 v) v clm = 1.4 x v clo = 252 v (210 v) v clm v clo v max 555 v (525 v) 627 v (585 v) 647 v (605 v)
AN-32 9 b 12/02 step 5. set current waveform parameter k p for desired mode of operation and current waveform: k p k rp for k p 1.0 and k p k dp for k p 1.0 (figures 9 and 10) for k p 1.0, k p k rp , continuous mode (see figure 9) where i r is primary ripple current and i p is primary peak current . for k p 1.0, k p k dp , discontinuous mode (see figure 10) for continuous mode design, set k p = 0.4 for universal input 0.6 for 230 vac or 115 vac with doubler. for discontinuous mode design, set k p = 1.0. ? p must be kept within the range specified in table 5. figure 9. continuous mode current waveform, k p 1. i r k p k rp = i r i p (a) continuous, k p < 1 (b) borderline continuous/discontinuous, k p = 1 primary primary i r i p i p pi-2587-011400 k dp = k p (1-d) x t t (b) boarderline discontinuous/continuous, k p = 1 (a) discontinuous, k p > 1 secondary primary primary secondary pi-2578-011800 d x t d x t t (1-d) x t (1-d) x t = t t = 1/f s t = 1/f s figure 10. discontinuous mode current waveform, k p 1. kk i i prp r p = kk vd vv d pdp or max min ds max = ? ? () () 1
AN-32 10 b 12/02 step 9. choose topswitch-gx based on ac input voltage, v o , p o and using an-29 selection curves choose the smallest topswitch-gx using topswitch-gx selection curves in an-29. identify appropriate selection curves according to ac input voltage and output voltage, v o . continuous mode: use selection curves as is. discontinuous mode: use selection curves with the output power derated by 33%. this effectively makes a 10 w discontinuous design equivalent to a 15 w continuous design in topswitch-gx selection. switching frequency f s : for dip and smp packages, set f s = 132 khz. for to-220 package, choose between 66 khz and 132 khz. step 10. set i limit reduction factor k i for external i limit ? where 0.3 k i 1.0 ? i is set by the value of the resistor connected between m pin and source pin (refer to topswitch-gx data sheet). for applications demanding very high efficiency, a topswitch-gx bigger than necessary may be used by lowering i limit externally to take advantage of the lower r ds(on) . if no special requirement, set k i = 1.0. calculate i limit (min) and i limit (max) step 11. validate topswitch-gx selection by checking i p against i limit (min) for k i = 1.0, check i p 0.96 x i limit (min). for k i < 1.0, check i p 0.94 x i limit (min). choose larger topswitch-gx if necessary. step 12. calculate primary inductance l p continuous mode where units are h, watts, amps and hz discontinuous mode. where units are h, watts, amps and hz k p continuous discontinuous mode mode universal 0.4~1.0 1.0 230 0.6~1.0 1.0 table 5 step 6. determine d max based on v min and v or continuous mode discontinuous mode set topswitch-gx drain to source voltage, v ds = 10 v. step 7. calculate primary peak current i p continuous mode (k p 1.0) discontinuous mode (k p 1.0) input average current step 8. calculate primary rms current i rms continuous mode discontinuous mode input (vac) i default i k limit limit i (min) (min) = ? i default i k limit limit i (max) (max) = ? i i k d p avg p max = ? ? ? ? ? 1 2 i i d p avg max = 2 i p v avg o min = k external i default i i limit limit = d v vv v max or min ds or = ? + () d v kv v v max or p min ds or = ? + () id i rms max p = 2 3 iid k k rms p max p p = ? + ? ? ? ? ? ? 2 3 1 l p ik k f z p o pp p s = ? ? ? ? ? ? + 10 1 2 1 6 2 (min) () ? l p if z p o ps = ? + 10 1 2 1 6 2 (min) () ?
AN-32 11 b 12/02 step 14. set value for number of primary layers l and number of secondary turns n s (may need iteration) starting with l = 2 (keep 1.0 l 2.0 throughout iteration). starting with n s = 0.6 turn/volt. both l and n s may need iteration. step 15. calculate number of primary turns n p and number of bias turns n b diode forward voltages: 0.7 v for ultra-fast p/n diode and 0.5 v for schottky diode. set output rectifier forward voltage, v d . set bias rectifier forward voltage, v db . calculate number of primary turns. calculate number of bias turns n b . step 16. determine primary winding wire parameters od, dia, awg primary wire outside diameter in mm. where l is number of primary layers, bw is bobbin width in mm, m is safety margin in mm. determine primary wire bare conductor diameter dia and primary wire gauge awg. step 17 to step 22. check b m , cma and l g . iterate if necessary by changing l, n s or core/bobbin until within specified range set safety margin, m. use 3 mm (118 mils) for margin wound and zero for triple insulated secondary. ?maximum flux density: 3000 b m 2000, in gauss or 0.3 b m 0.2, in tesla. where units are gauss, amps, h and cm 2 ? is loss allocation factor and is efficiency from step 1. step 13. choose core and bobbin based on f s and p o using table 6 and determine a e, l e, a l and bw from core and bobbin catalog core effective cross-sectional area, a e : in cm 2 . core effective path length, l e : in cm. core ungapped effective inductance, a l : in nh/turn 2 . bobbin width, bw: in mm. choose core and bobbin based on f s , p o and construction type. triple triple insulated insulated wire wire ef12.6 ei22 ef12.6 ei22 ee13 ee19 ee13 ee19 ef16 ei22/19/6 ef16 e122/19/6 ee16 eel16 ee16 eel16 ee19 ef20 ei22 ei25 ei22/19/6 eel19 ef20 ei28 ee19 ef20 eel22 ei22 ei25 ef25 ei22/19/6 eel19 ef20 ef25 ei30 e128 epc30 eel25 ei28 e30/15/7 ef25 eel22 ei30 eer28 ef25 e30/15/7 etd29 ei30 eer28 ei35 epc30 ei33/29/ 13-z eer28l etd29 ef32 ei28 eel25 ei35 etd34 e30/15/7 ef32 eer28 etd34 ei40 ei30 etd29 e36/18/11 e36/18/11 e30/15/7 ei35 ei40 eer35 eer28 ei33/29/ etd29 13-z eer28l ef32 etd39 etd39 ei35 etd34 eer40 eer40 ef32 ei40 e42/21/15 etd34 e36/18/11 eer35 e42/21/15 e42/21/20 e36/18/11 etd39 e42/21/20 e55/28/21 ei40 eer40 e55/28/21 etd39 e42/21/15 eer40 e42/21/20 e42/21/15 e55/28/21 e42/21/20 e55/28/21 table 6. transformer core. 66 khz 132 khz output power 0-10 w 10 w- 20 w 20 w- 30 w 30 w- 50 w 50 w- 70 w 70 w- 100 w 100 w- 150 w >150w margin wound margin wound nn v vv ps or od = + nn vv vv bs bdb od = + + od lbw m n p = ? () 2 b il na m pp pe = 100
AN-32 12 b 12/02 gap length in mm: l g 0.1 where l g in mm, a e in cm 2 , a l in nh/turn 2 and l p in h primary winding current capacity in circular mils per amp: 500 cma 200 where dia is the bare conductor diameter in mm iterate by changing l, n s , core/bobbin according to table 7. b m l g cma l -- n s table 7. step 23. check b p 4200 . if necessary, reduce current limit by lowering i limit reduction factor k i check b p 4200 gauss (0.42 tesla) to avoid transformer saturation at startup and output over load. decrease k i , if necessary, until b p 4200. step 24. calculate secondary peak current i sp step 25. calculate secondary rms current i srms continuous mode discontinuous mode step 26. determine secondary winding wire parameters od s , dia s , awg s secondary wire outside diameter in mm secondary wire bare conductor diameter in mm where cma s is secondary winding current capacity in circular mils per amp. minimum wire diameter is calculated by using a cma s of 200. determine secondary winding wire gauge awg s based on dia s . if the bare conductor diameter of the wire is larger than that of the 27 awg for 132 khz or 25 awg for 66 khz, a parallel winding using multiple strands of thinner wire should be used to minimize skin effect. step 27. determine output capacitor ripple current i ripple output capacitor ripple current where i o is the output dc current step 28. determine maximum peak inverse voltages piv s , piv b for secondary and bias windings secondary winding maximum peak inverse voltage. bias winding maximum peak inverse voltage. step 29. select clamp zener and blocking diode per table 8 for primary clamping based on v or and the type of output table 8. core size blocking clamp diode zener byv26c mur160 p6ke150 uf4005 byv26c mur160 p6ke180 uf4005 ps output v or multiple output 100 v single output 120 v la n la ge p pl = ? ? ? ? ? ? ? 40 1000 1 2 cma dia i rms = ? ? ? ? 127 4 1000 25 4 2 2 . . b i i b p limit p m = (max) ii n n sp p p s = ii d k k srms sp max p p = ? () ? + ? ? ? ? ? ? 1 3 1 2 ii d k srms sp max p = ? 1 3 od bw m n s s = ? () 2 dia cma i s s srms = 4 127 25 4 1000 . . iii ripple srms o = ? 22 piv v v n n so max s p =+ () piv v v n n bb max b p =+ ()
AN-32 13 b 12/02 step 30. select output rectifier per table 9 ? r 1.25 x piv s ; where piv s is from step 28 and v r is the rated reverse voltage of the rectifier diode. ? d 3 x i o ; where i d is the diode rated dc current and i o = p o / v o . rec. diode v r (v) i d (a) package manufacturer schottky 1n5819 40 1 axial general semi sb140 40 1 axial general semi sb160 60 1 axial general semi mbr160 60 1 axial ir 11dq06 60 1.1 axial ir 1n5822 40 3 axial general semi sb340 40 3 axial general semi mbr340 40 3 axial ir sb360 60 3 axial general semi mbr360 60 3 axial ir sb540 40 5 axial general semi sb560 60 5 axial general semi mbr745 45 7.5 to-220 general semi ir mbr760 60 7.5 to-220 general semi mbr1045 45 10 to-220 general semi ir mbr1060 60 10 to-220 general semi mbr10100 100 10 to-220 general semi mbr1645 45 16 to-220 general semi ir mbr1660 60 16 to-220 general semi mbr2045ct 45 20(2 x 10) to-220 general semi ir mbr2060ct 60 20(2x10) to-220 general semi mbr20100 100 20(2x10) to-220 general semi ir ufr uf4002 100 1 axial general semi uf4003 200 1 axial general semi mur120 200 1 axial general semi egp20d 200 2 axial general semi byv27-200 200 2 axial general semi philips uf5401 100 3 axial general semi uf5402 200 3 axial general semi egp30d 200 3 axial general semi byv28-200 200 3.5 axial general semi philips mur420 200 4 to-220 general semi byw29-200 200 8 to-220 general semi philips byv32-200 200 18 to-220 general semi philips table 9. step 31. select output capacitor ripple current specification at 105 c, 100 khz: must be equal to or larger than i ripple, where i ripple is from step 27. esr specification: use low esr, electrolytic capacitor. output switching ripple voltage is i sp x esr , where i sp is from step 24. ? examples: output output capacitor 5 v to 24 v, 1 a 330 f, 35 v, low esr, electrolytic unitedchemicon lxz35vb331m10x16ll rubycon 35yxg330m10 x 16 panasonic eeufc1v331 5 v to 24 v, 2 a 1000 f, 35 v, low esr, electrolytic united chemicon lxz35vb102m12x25ll rubycon 35yxg1000m12.5 x 25 panasonic eeufc1v102 step 32. select output post filter l, c ?inductor l: 2.2 h to 4.7 h. use ferrite bead for low current ( 1a) output and standard off-the-shelf choke for higher current output. increase choke current rating or wire size, if necessary, to avoid significant dc voltage drop. ?capacitor c:100 f to 330 f, 35 v, electrolytic examples for 100 f, 35 v, electrolytic: united chemicon kmg35vb101m6x11ll rubycon 35yxa100m6.3 x 11 panasonic eca1vhg101 step 33. select bias rectifier from table 10 ? r 1.25 x piv b ; where piv b is from step 28 and v r is the rated reverse voltage of the rectifier diode. rectifier v r (v) manufacturer bav21 200 philips uf4003 200 general semi 1n4148 75 motorola step 34. select bias capacitor use 0.1 f, 50 v, ceramic. step 35. select control pin capacitor and series resistor control pin capacitor: 47 f, 10 v, low cost electrolytic (do not use low esr capacitor). table 10.
AN-32 14 b 12/02 series resistor: 6.8 ? , 1/4 w (not needed if k p 1, i.e. discontinuous mode). step 36. select feedback circuit components according to applicable reference feedback circuits shown in figures 3, 4, 5 and 6 applicable reference circuit: identified in step 2. step 37. select input bridge rectifier ? r 1.25 x x v acmax ; where v acmax is from step 1. ? d 2 x i ave ; where i d is the bridge rectifier rated current and i ave is average input current. note: ; where v min is from step 3 and from step 1. 2 i p v ave out min =
AN-32 15 b 12/02 customization of secondary designs for each output the turns for each secondary winding are calculated based on the respective output voltage v o (n): output rectifier maximum inverse voltage is with output rms current i srms (n), secondary number of turns n s (n) and output rectifier maximum inverse voltage piv s (n) known, the secondary side design for each output can now be carried out exactly the same way as for the single output design. secondary winding wire size the topswitch-gx design spreadsheet assumes a cma of 200 when calculating secondary winding wire diameters. this gives the minimum wire sizes required for the rms currents of each output using seperate windings. designers may wish to use larger size wire for better thermal performance. other considerations such as skin effect and bobbin coverage may suggest the use of a smaller wire by using multiple strands wound in parallel. in addition, practical considerations in transformer manufacturing may also dictate the wire size. inin i i srms o srms o () () = appendix a multiple output flyback power supply design the only difference between a multiple output flyback power supply and a single output flyback power supply of the same total output power is in the secondary side design. instead of delivering all power to one output as in the single output case, a multiple output flyback distributes its output power among several outputs. therefore, the design procedure for the primary side stays the same, while that for the secondary side demands further considerations. design with lumped output power one simple way of doing multiple output flyback design is described in detail in an-22, ?esigning multiple output flyback power supplies with topswitch ? the design method starts with a single output equivalent by lumping output power of all outputs to one main output. secondary peak current i sp and rms current i srms are derived. output average current i o corresponding to the lumped power is also calculated. assumption for simplification the current waveforms in the individual output windings are determined by the impedance in each circuit, which is a function of leakage inductance, rectifier characteristics, capacitor value and most importantly, output load. although this current waveform may not be exactly the same from output to output, it is reasonable to assume that, to the first order, all output currents have the same shape as for the single output equivalent of lumped power. output rms current vs. average current the output average current is always equal to the dc load current, while the rms value is determined by current wave shape. since the current wave shapes are assumed to be the same for all outputs, their ratio of rms to average currents must also be identical. therefore, with the output average current known, the rms current for each output winding can be calculated as where i srms (n) and i o (n) are the secondary rms current and output average current of the n th output and i srms and i o are the secondary rms current and output average current for the lumped single output equivalent design. nn n vn vn vv ss od d () () () = + + piv n v nn n vn s max s p o () () () = +
AN-32 16 b 12/02 singapore power integrations, singapore 51 goldhill plaza #16-05 republic of singapore 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com world headquarters americas power integrations, inc. 5245 hellyer avenue san jose, ca 95138 usa main: +1 408-414-9200 customer service: phone: +1 408-414-9665 fax: +1 408-414-9765 e-mail: usasales@powerint.com for the latest updates, visit our web site: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. the products and applications illustrated herein may be covered by one or more u.s. and foreign patents or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations?patents may be found at www.powerint.com. the pi logo, topswitch , tinyswitch , linkswitch and ecosmart are registered trademarks of power integrations, inc. pi expert is a trademark of power integrations, inc. ?opyright 2002, power integrations, inc. taiwan power integrations international holdings, inc. 17f-3, no. 510 chung hsiao e. rd., sec. 5, taipei, taiwan 110, r.o.c. phone: +886-2-2727-1221 fax: +886-2-2727-1223 e-mail: taiwansales@powerint.com china power integrations international holdings, inc. rm# 1705, bao hua bldg. 1016 hua qiang bei lu shenzhen guangdong, 518031 china phone: +86-755-8367-5143 fax: +86-755-8377-9610 e-mail: chinasales@powerint.com europe & africa power integrations (europe) ltd. centennial court easthampstead road bracknell berkshire, rg12 1yq united kingdom phone: +44-1344-462-300 fax: +44-1344-311-732 e-mail: eurosales@powerint.com korea power integrations international holdings, inc. 8th floor, dongsung building, 17-8 yoido-dong, youngdeungpo-gu, seoul, 150-874, korea phone: +82-2-782-2840 fax: +82-2-782-4427 e-mail: koreasales@powerint.com japan power integrations, k.k. keihin-tatemono 1st bldg. 12-20 shin-yokohama 2-chome kohoku-ku, yokohama-shi, kanagawa 222-0033, japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com india (technical support) innovatech #1, 8th main road vasanthnagar bangalore, india 560052 phone: +91-80-226-6023 fax: +91-80-228-9727 e-mail: indiasales@powerint.com applications hotline applications fax world wide +1-408-414-9660 world wide +1-408-414-9760

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