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| ? embedded amd-k6? processors bios design guide publication # 23913 rev: a amendment/ 0 issue date: november 2000 application note
trademarks amd, the amd logo, and combinations thereof, amd-k6, 3dnow!, e86, amd powernow!, and super7 are trademarks, and fusione86 is a service mark of advanced micro devices, inc. mmx is a trademark and pentium is a registered trademark of intel corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 2000 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. contents iii 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 processor models and steppings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 amd-k6?e embedded processor . . . . . . . . . . . . . . . . . . . . . . . 3 amd-k6?-2 processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 amd-k6?-2e embedded processor. . . . . . . . . . . . . . . . . . . . . . 4 amd-k6?-2e+ embedded processor. . . . . . . . . . . . . . . . . . . . . 4 amd-k6?-iii processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 amd-k6?-iiie+ embedded processor . . . . . . . . . . . . . . . . . . . 5 bios consideration checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 cpu speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . . 6 cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 smm issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 states after reset and init. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 register states after reset and init . . . . . . . . . . . . . . . . . . . 8 processor state after init. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 cpuid identification algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 system management mode (smm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 state-save map differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i/o trap dword differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 model-specific registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . 14 standard model-specific registers (all models) . . . . . . . . . . 16 model 7 and model 8/[7:0] registers. . . . . . . . . . . . . . . . . . . . . . . . . . 17 extended feature enable register (efer) . . . . . . . . . . . . . . 18 write handling control register (whcr) . . . . . . . . . . . . . . . 19 syscall/sysret target address register (star) . . . . . . 22 iv contents embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information model 8/[f:8] registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 extended feature enable register (efer) . . . . . . . . . . . . . . 24 write handling control register (whcr) . . . . . . . . . . . . . . . 27 uc/wc cacheability control register (uwccr) . . . . . . . . . 30 processor state observability register (psor) . . . . . . . . . . . 34 page flush/invalidate register (pfir) . . . . . . . . . . . . . . . . . . 36 model 9 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 extended feature enable register (efer) . . . . . . . . . . . . . . 39 level-2 cache array access register (l2aar) . . . . . . . . . . . 40 model d registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 processor state observability register (psor) (low-power versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 level-2 cache array access register (l2aar) . . . . . . . . . . . 48 enhanced power management register (epmr) (low-power versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 epm 16-byte i/o block (low-power versions only). . . . . . . . 55 embedded amd processor recognition. . . . . . . . . . . . . . . . . . . . . . . 57 cpuid instruction overview . . . . . . . . . . . . . . . . . . . . . . . . . . 57 testing for the cpuid instruction . . . . . . . . . . . . . . . . . . . . . . 58 using cpuid functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 i dentifying the processors vendor . . . . . . . . . . . . . . . . . . . . . 60 testing for extended functions . . . . . . . . . . . . . . . . . . . . . . . 61 determining the processor signature . . . . . . . . . . . . . . . . . . . 61 identifying supported features . . . . . . . . . . . . . . . . . . . . . . . . 63 determining instruction set support. . . . . . . . . . . . . . . . . . . . 64 detection algorithm for determining instruction set support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 amd processor signature (extended function). . . . . . . . . . . 66 displaying the processors name . . . . . . . . . . . . . . . . . . . . . . . 66 displaying cache information . . . . . . . . . . . . . . . . . . . . . . . . . 67 determining amd powernow!? technology information . . 67 sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 new amd-k6? processor instructions. . . . . . . . . . . . . . . . . . . . . . . . 68 additional considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 contents v 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information software timing dependencies relative to memory controller setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 pipelining support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 read-only memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 appendix a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 standard functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 extended functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 cache associativity field definitions . . . . . . . . . . . . . . . . . . . 80 appendix b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 values returned by the cpuid instruction . . . . . . . . . . . . . . 81 index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 vi contents embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information list of figures vii 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information list of figures figure 1. cpuid instruction flow chart . . . . . . . . . . . . . . . . . . . . . 12 figure 2. extended feature enable register (efer) (models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3. write handling control register (whcr) (models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. syscall/sysret target address register (star) (models 8, 9, and d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5. extended feature enable register (efer) (model 8/[f:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. write handling control register (whcr) (models 8/[f:8], 9, and d) . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7. uc/wc cacheability control register (uwccr) (models 8/[f:8], 9, and d) . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. processor state observability register (psor) (models 8/[f:8], 9, and standard-power d) . . . . . . . . . . . 34 figure 9. page flush/invalidate register (pfir) (models 8/[f:8], 9, and d) . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. extended feature enable register (efer) (models 9 and d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11. l2 cache organization (amd-k6?-iii processor) . . . . . 40 figure 12. l2 cache sector and line organization . . . . . . . . . . . . . 41 figure 13. l2 tag or data location (amd-k6?-iii processor)edx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 14. l2 dataeax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15. l2 tag information (amd-k6?-iii processor)eax . . 43 figure 16. lru byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 17. processor state observability register (psor) (model d low-power versions) . . . . . . . . . . . . . . . . . . . . 46 figure 18. l2 cache organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 19. l2 cache sector and line organization (same as figure 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 viii list of figures embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information figure 20. l2 tag or data location (amd-k6?-2e+ processor)edx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 21. l2 tag or data location (amd-k6?-iiie+ processor)edx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 22. l2 dataeax (same as figure 14) . . . . . . . . . . . . . . . . . 51 figure 23. l2 tag information (amd-k6?-2e+ processor)eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 24. l2 tag information (amd-k6?-iiie+ processor)eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 25. lru byte (same as figure 16) . . . . . . . . . . . . . . . . . . . . . 53 figure 26. enhanced power management register (epmr) (low-power model d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 27. epm 16-byte i/o block (low-power model d) . . . . . . . . 55 figure 28. bus divisor and voltage id control (bvc) field (low-power model d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 29. contents of eax register returned by function 1 . . . . 62 figure 30. contents of eax register returned by extended function 8000_0001h . . . . . . . . . . . . . . . . . . . . 66 list of tables ix 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information list of tables table 1. features of the amd-k6? processor family . . . . . . . . . . 2 table 2. amd-k6?e processor (model 7) and amd-k6? processor (model 8/[7:0]) state after reset . . . . . . . . . . . . . . . . . . . 8 table 3. amd-k6? processor (model 8/[f:8]) and amd-k6?-2e processor (model 8/[f:8]) state after reset . . . . . . . . . . 8 table 4. amd-k6?-2e+ (model d), amd-k6? - iii (model 9), and amd-k6?-iiie+ processors (model d) state after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. recommended boot strings for amd-k6? processors . 11 table 6. amd-k6? processor i/o trap dword configuration at offset ffa4h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. summary by register of msr differences within the amd-k6? family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. summary by model of msr differences within the amd-k6? family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. model-specific registers supported by models 7 and 8/[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. extended feature enable register (efer) definition (models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. syscall/sysret target address register (star) definition (models 8, 9, and d). . . . . . . . . . . . . . . . . . . . . 22 table 12. model-specific registers supported by model 8/[f:8] . . 23 table 13. extended feature enable register (efer) definition (model 8/[f:8]) . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. write ordering and performance settings for efer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. wc/uc memory type for uwccr register . . . . . . . . . . 31 table 16. valid masks and range sizes for uwccr register. . . . 32 table 17. processor-to-bus clock ratios (models 8/[f:8] and 9) . . 35 x list of tables embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information table 18. processor-to-bus clock ratios (model standard-power d) . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. model-specific registers supported by model 9 . . . . . . 38 table 20. extended feature enable register (efer) definition (models 9 and d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 21. tag versus data selector . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. model-specific registers supported by model d . . . . . . 45 table 23. processor-to-bus clock ratios (low-power model d) . . . 47 table 24. tag versus data selector (same as table 21) . . . . . . . . . . 51 table 25. enhanced power management register (epmr) definition (low-power model d) . . . . . . . . . . . . . . . . . . . 54 table 26. epm 16-byte i/o block definition (low-power model d) 55 table 27. bus divisor and voltage id control (bvc) definition (low-power model d). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 28. cpuid functions in amd-k6? processors. . . . . . . . . . . 60 table 29. processor signatures for amd-k6? processors . . . . . . . 62 table 30. standard and extended feature bits . . . . . . . . . . . . . . . . 63 table 31. standard feature flag descriptions. . . . . . . . . . . . . . . . . 74 table 32. extended feature flag descriptions . . . . . . . . . . . . . . . . 76 table 33. ebx format returned by function 8000_0005h. . . . . . . 78 table 34. ecx format returned by function 8000_0005h. . . . . . . 78 table 35. edx format returned by function 8000_0005h . . . . . . 78 table 36. ecx format returned by function 8000_0006h. . . . . . . 79 table 37. edx format returned by function 8000_0007h . . . . . . 79 table 38. associativity values for l2 cache . . . . . . . . . . . . . . . . . . 80 table 39. cpuid values returned by amd-k6? processors . . . . 81 revision history xi 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information revision history date rev description november 2000 a initial public release. xii revision history embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information introduction 1 application note embedded amd-k6? processors bios design guide introduction this document highlights the bios modifications required to fully support the amd-k6? processors used by amds embedded customers. the information in this application note pertains to the following processors in the amd-k6 family: n amd-k6e embedded processor n amd-k6-2 processor n amd-k6-2e embedded processor n amd-k6-2e+ embedded processor n amd-k6-iii processor n amd-k6-iiie+ embedded processor there can be more than one way to implement the functionality detailed in this document, and the information provided is for demonstration purposes. all referenced amd-k6 processor documents can be found on the amd website at http://www.amd.com/. audience it is assumed that the reader has a solid understanding of the x86 processors, the x86 architecture, and programming requirements. 2 processor models and steppings embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information processor models and steppings four models within the amd-k6 family of processorsmodels 7, 8, 9, and dare discussed in this document. for most models, feature and function detection can be determined by reading the standard and extended feature bits by executing the cpuid instruction. however, for certain models, it is necessary to check the steppingby executing the cpuid instructionto determine specific function support. table 1 shows the features of each model and stepping of the amd-k6 processor family. the descriptions in the remainder of this section provide more detailed information on the amd-k6 processor family members, and the models and steppings that comprise each member. table 7 on page 14 and table 8 on page 15 summarize the msr differences between the models and steppings of the amd-k6 family of processors. table 1. features of the amd-k6? processor family processor model/ stepping process (in microns) number of msrs 1 notes: 1. refer to model-specific registers overview on page 14 for more information. 3dnow!? instructions 3dnow! extensions amd powernow!? technology l2 cache amd-k6e 7 0.25 6 amd-k6-2 8/[7:0] 0.25 7 yes amd-k6-2 and amd-k6-2e 8/[f:8] 0.25 10 2 2. model 8/[f:8] defines the bits and fields in the write handling control register (whcr) and extended feature enable register (efer) differently from the models 7 and 8/[7:0]. yes amd-k6-2e+ d/[7:4] 0.18 11 3,4 3. this model implements the same ten msrs as the model 8/[f:8]. with the exception of bit 4 (l2d) in the efer register, the bit s and fields within these ten msrs are defined identically. 4. low-power versions implement one additional register to support amd powernow! ? technology. yes yes yes 5 5. amd powernow! technology is supported on low-power versions of these processors only. 128 kbytes amd-k6- iii 9/[3:0] 0.25 11 3 yes 256 kbytes amd-k6- iii e+ d/[3:0] 0.18 11 3,4 yes yes yes 5 processor models and steppings 3 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information amd-k6?e embedded processor model 7 model 7 is the first processor manufactured in the 0.25-micron process. n model 7 supports six model-specific registers (msrs). amd-k6?-2 processor some important features supported by the amd-k6-2 processor include the 3dnow!? instruction set and a 100-mhz processor bus. model 8/[7:0] model 8/[7:0] is any of eight possible model/steppingsmodels 8/0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, or 8/7. model 8/[7:0] is manufactured in the 0.25-micron process and was the original version of the amd-k6-2 available as a desktop product. n model 8/[7:0] implements the same six msrs as the model 7, and the bits and fields within these six msrs are defined identically. n model 8/[7:0] also implements the syscall/sysret target address register (star) msr for a total of seven msrs. model 8/[f:8] model 8/[f:8] is any of eight possible model/steppingsmodels 8/8, 8/9, 8/a, 8/b, 8/c, 8/d, 8/e, or 8/f. model 8/[f:8] is manufactured in the 0.25-micron process. n model 8/[f:8] implements the same six msrs as the models 7 and 8/[7:0], but the bits and fields within two of these msrswhcr and eferare not defined identically. n also, model 8/[f:8] supports the star msr and three additional msrs, for a total of ten msrs. 4 processor models and steppings embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information amd-k6?-2e embedded processor the amd-k6-2e processor also supports the 3dnow! instruction set and a 100-mhz processor bus. model 8/[f:8] model 8/[f:8] is any of eight possible model/steppingsmodels 8/8, 8/9, 8/a, 8/b, 8/c, 8/d, 8/e, or 8/f. model 8/[f:8] is manufactured in the 0.25-micron process. n model 8/[f:8] implements the same six msrs as the models 7 and 8/[7:0], but the bits and fields within two of these msrswhcr and eferare not defined identically. n also, model 8/[f:8] supports the star msr and three additional msrs, for a total of ten msrs. amd-k6?-2e+ embedded processor in addition to supporting the 3dnow! instruction set and a 100- mhz processor bus, the amd-k6-2e+ processor contains a 128- kbyte backside l2 cache. it also supports the 3dnow! dsp instructions extensions. low-power versions of the processor support amd powernow!? technology. model d/[7:4] model d/[7:4] is any of four possible model/steppingsmodels d/4, d/5, d/6, or d/7. model d/[7:4] is manufactured in the 0.18- micron process. n model d/[7:4] implements the same ten msrs as the model 8/[f:8]. with the exception of bit 4 (l2d) in the efer register, the bits and fields within these ten msrs are defined identically for standard-power versions. the psor register is defined differently for low-power versions. n model d/[7:4] supports an additional msr, the level-2 cache array access register (l2aar), for a total of eleven msrs. n low-power versions of model d/[7:4] support an additional msr, the enhanced power management register (epmr), for a total of twelve msrs. processor models and steppings 5 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information amd-k6? -iii processor in addition to supporting the 3dnow! instruction set and a 100- mhz processor bus, the amd-k6-iii processor contains a 256- kbyte backside l2 cache. model 9/[3:0] model 9/[3:0] is any of four possible model/steppingsmodels 9/0, 9/1, 9/2, or 9/3. model 9/[3:0] is manufactured in the 0.25- micron process. n model 9/[3:0] implements the same ten msrs as the model 8/[f:8]. with the exception of bit 4 (l2d) in the efer register, the bits and fields within these ten msrs are defined identically. n model 9/[3:0] supports one additional msr for a total of eleven msrs. amd-k6?- iii e+ embedded processor in addition to supporting the 3dnow! instruction set and a 100- mhz processor bus, the amd-k6-iiie+ processor contains a 256- kbyte backside l2 cache. it also supports the 3dnow! dsp instruction extensions. low-power versions of the processor support amd powernow! technology. model d/[3:0] model d/[3:0] is any of four possible model/steppingsmodels d/0, d/1, d/2, or d/3. model d/[3:0] is manufactured in the 0.18- micron process. n model d/[3:0] implements the same ten msrs as the model 8/[f:8]. with the exception of bit 4 (l2d) in the efer register, the bits and fields within these ten msrs are defined identically for standard-power versions. the psor register is defined differently for low-power versions. n model d/[7:4] supports an additional msr, the level-2 cache array access register (l2aar), for a total of eleven msrs. n low-power versions of model d/[7:4] support an additional msr, the enhanced power management register (epmr), for a total of twelve msrs. 6 bios consideration checklist embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information bios consideration checklist cpuid n use the cpuid instruction to properly identify the processor. for information on the cpuid instruction, see cpuid instruction overview on page 57. n determine the processor model, stepping, and features using functions 0000_0001h and 8000_0001h of the cpuid instruction. n display the processor name (bios boot strings) as described in cpuid identification algorithms on page 11. cpu speed detection n use speed detection algorithms that do not rely on repetitive instruction sequences. n use the time stamp counter (tsc) to clock a timed operation and compare the result to the real-time clock (rtc) to determine the operating frequency. see the cpu speed determination program available on the amd website at http://www.amd.com/products/cpg/bin/. n display the recommended bios boot string as shown in table 5 on page 11. model-specific registers (msrs) n only access msrs implemented in the processor. n enable write allocation by programming the write handling control register (whcr). see write handling control register (whcr) on page 19 and page 27, and the implementation of write allocate in the k86? processors application note , order# 21326 for more information. note: the whcr register as defined in models 7 and 8/[7:0] is implemented differently in models 8/[f:8], 9, and d. n for the amd-k6-2e, amd-k6-2e+, amd-k6-iii, and amd-k6-iiie+ processors, utilize the information provided in the processor state observability register (psor) to display the correct processor bus frequency. bios consideration checklist 7 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information cache testing n the amd-k6 family of processors does not contain msrs to allow for testing of the l1 cache. however, the amd-k6-2e+, amd-k6-iii, and amd-k6-iiie+ processors do contain an msr that allows for testing of their l2 caches. this msr is called l2aar, and it is described in level-2 cache array access register (l2aar) on page 40. smm issues n the system management mode (smm) functionality of the processor is the same as the pentium ? processor. n implement the processor smm state-save area in a similar manner as pentium processors except for the idt base and possibly pentium processor-reserved areas. see system management mode (smm) on page 13 for more information. 8 states after reset and init embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information states after reset and init register states after reset and init after the processor has completed its initialization following the recognition of an asserted reset or init signal, the states of all architecture registers and msrs are compatible with those of pentium processors. differences are listed in table 2 through table 4. table 2. amd-k6?e processor (model 7) and amd-k6? processor (model 8/[7:0]) state after reset register reset state edx 0000_05msh 1 notes: 1. m represents the model and s represents the stepping. efer 0000_0000_0000_0000h star 2 2. processor model 7 does not support the star register. 0000_0000_0000_0000h whcr 0000_0000_0000_0000h table 3. amd-k6? processor (model 8/[f:8]) and amd-k6?-2e processor (model 8/[f:8]) state after reset register reset state edx 0000_05msh 1 notes: 1. m represents the model and s represents the stepping. efer 0000_0000_0000_0002h pfir 0000_0000_0000_0000h psor 0000_0000_0000_01sbh 1,2 2. b represents psor[3:0], where psor[3] equals 0, and psor[2:0] is equal to the value of the bf[2:0] signals sampled during the falling transition of reset. star 0000_0000_0000_0000h uwccr 0000_0000_0000_0000h whcr 0000_0000_0000_0000h states after reset and init 9 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information processor state after init the assertion of init causes the processor to empty its pipelines, initialize most of its internal state, and branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the smm base, msrs, and the cd and nw bits of the cr0 register. the edge-sensitive interrupts flush# and smi# are sampled and preserved during the init process and are handled accordingly after the initialization is complete. however, the processor resets any pending nmi interrupt upon sampling init asserted. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. table 4. amd-k6?-2e+ (model d), amd-k6? -iii (model 9), and amd-k6?- iii e+ processors (model d) state after reset register reset state edx 0000_05msh 1 notes: 1. m represents the model and s represents the stepping. efer 2 2. because efer[4] equals 0 after reset, the l2 cache is enabled by default after reset. 0000_0000_0000_0002h l2aar 0000_0000_0000_0000h pfir 0000_0000_0000_0000h psor 0000_0000_0000_00sbh 1,3 3. b represents psor[3:0], where psor[3] equals 0, and psor[2:0] is equal to the value of the bf[2:0] signals sampled during the falling transition of reset. star 0000_0000_0000_0000h uwccr 0000_0000_0000_0000h whcr 0000_0000_0000_0000h epmr 4 4. supported on low-power versions only of model d processors. 0000_0000_0000_0000h 10 states after reset and init embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information built-in self-test (bist) for all models of the amd-k6 processor, bist is run unconditionally following the falling transition of reset. the results of the test are contained in the general-purpose register eax. if eax contains 0000_0000h, then bist was successful. if the contents of eax are non-zero, the bist failed. the internal resources tested during bist include the following: n l1 instruction and data caches n l2 unified cache (models 9 and d only) n instruction and data translation lookaside buffers (tlbs) cpuid identification algorithms 11 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information cpuid identification algorithms the cpuid instruction provides information about the processor (vendor, type, name, etc.) and its capabilities (features). after detecting the processor and its capabilities, software can be accurately tuned to the system for maximum performance and benefit to users. for more detailed information about using the cpuid instruction, see embedded amd processor recognition on page 57. to determine if the processor is enabled with amd powernow! technology, use cpuid function 8000_0007, as described on page 79. the recommended boot strings (or processor names) to be displayed for amd-k6 processors are shown in table 5. for example, a bios boot string for a model 9, stepping 3, 450- mhz amd-k6-iii processor would look like this: n amd-k6(tm)-iii/450 figure 1 on page 12 shows a flow chart for the cpuid instruction. use this chart to implement a cpuid algorithm. table 5. recommended boot strings for amd-k6? processors model recommended boot string display 1 notes: 1. the value for xxx is determined by calculating the core frequency of the processor. use the time stamp counter (tsc) to clock a timed operation and compare the result to the real-time clock (rtc) to determine the operating frequency. model 7 amd-k6(tm)/xxx all steppings of models 8 amd-k6(tm)-2/xxx model d/[7:4] 2 2. see functions 8000_0002h, 8000_0003h, and 8000_0004h processor name string on page 77 for more information about these steppings. amd-k6(tm)-2+/xxx model 9/[3:0] amd-k6(tm)-iii/xxx model d/[3:0] 2 amd-k6(tm)-iii+/xxx 12 cpuid identification algorithms embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information figure 1. cpuid instruction flow chart check for cpuid instruction support cpuid instruction supported no cpuid instruction-- use other means to detect cpu type no execute cpuid standard function eax=0 store vendor string eax > 1 ? execute cpuid standard function eax=1 store returned standard function feature bits and processor signature; determine mmx and, optionally, sse* support no amd processor not presentcheck for other cpu brands execute cpuid extended function eax=8000_0001h utilize vendor string and extended function feature bits to determine 3dnow!, 3dnow! extensions, and mmx? extensions support execute cpuid extended functions eax=8000_0002h, 8000_0003h, and 8000_0004h to display processor name string execute cpuid extended functions eax=8000_0005h and eax=8000_0006h (model 9 & model d) to gather processor cache and tlb information done tune software to optimize for features present yes yes execute cpuid extended function eax=8000_0000h to determine number of extended functions supported execute cpuid extended function eax=8000_0007h (model d) to gather amd powernow! technology information for the processor eax > 8000_0001h ? no yes utilize processor signature to determine msr support extended functions not supported * streaming simd extensions system management mode (smm) 13 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information system management mode (smm) this section documents the system management mode (smm) differences between specified models of the amd-k6 processor and the pentium processor. for more information on smm implementation in the k86 processors, see the appropriate amd-k6 or amd-k6e processor data sheet. state-save map differences the smm implemented in the amd-k6 processor differs from the smm implemented in the pentium? processor in one way. the interrupt descriptor table (idt) base location in the amd-k6 processors is located at offset ff90h. the pentium processor has the idt base located at offset ff94h. i/o trap dword differences the i/o trap dword is located at offset ffa4h. its amd-k6 processor bit fields are shown in table 6. this state-save area, which is reserved in pentium processors, contains information regarding an i/o instruction that may have been trapped by an smi# assertion. table 6. amd-k6? processor i/o trap dword configuration at offset ffa4h bits 31C16 bits 15C4 bit 3 bit 2 bit 1 bit 0 i/o port address reserved rep string operation i/o string operation valid i/o instruction input or output 14 model-specific registers overview embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information model-specific registers overview each of the models of the amd-k6 processor family support a different set of model-specific registers (msrs). these differences are summarized by register in table 7. the differences are summarized by model in table 8 on page 15, where an x indicates support for a register or field. the content of ecx selects the msr to be addressed by the rdmsr and wrmsr instruction. table 7. summary by register of msr differences within the amd-k6? family register mnemonic ecx value models description machine-check address register mcar 00h all page 16 machine-check type register mctr 01h all page 16 test register 12 tr12 0eh all page 16 time stamp counter tsc 10h all page 16 extended feature enable register efer c000_0080h 7, 8/[7:0] page 18 8/[f:8] page 24 9, d page 39 write handling control register whcr c000_0082h 7, 8/[7:0] page 19 8/[f:8], 9, d page 27 syscall/sysret target address register star c000_0081h 7 not supported 8, 9, d page 22 uc/wc cacheability control register uwccr c000_0085h 7, 8/[7:0] not supported 8/[f:8], 9, d page 30 processor state observability register psor c000_0087h 7, 8/[7:0] not supported 8/[f:8], 9, d 1 page 34 d 2 page 46 page flush/invalidate register pfir c000_0088h 7, 8/[7:0] not supported 8/[f:8], 9, d page 36 model-specific registers overview 15 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information level-2 cache array access register l2aar c000_0089h 7, 8 not supported 9 page 40 d page 48 enhanced power management register epmr c000_0086h 7, 8, 9, d 1 not supported d 2 page 54 notes: 1. standard-power versions only. 2. low-power versions only. table 7. summary by register of msr differences within the amd-k6? family (continued) register mnemonic ecx value models description table 8. summary by model of msr differences within the amd-k6? family model stepping standard msrs 1 efer 2 whcr 3 star uwccr psor pfir l2aar epmr l2d ewbec dpe sce 508 mb 4092 mb bf pbf vid ebf 7 all x x x 8 7:0 x x x x 8 f:8 x x x x x x x x x 9 3:0 x x x x x x x x x x x d 3:0 7:4 xxxxx xxx x 4 x 5 xx x 5 notes: 1. there are four msrs that every model and stepping of the amd-k6 family of processors support identicallymcar, mctr, tr12, and tsc. 2. l2d, ewbec, and dpe are bits/fields supported in efer for the indicated models/steppings. all models/steppings support the sy stem call extension (sce) bit in efer, even if the corresponding syscall and sysret instructions and the star register are not suppo rted. 3. indicates whether the waelim field supports 508 mbytes or 4092 mbytes of memory. the location of the wae15m bit and the waeli m field within the whcr register differs between the models/steppings that support 508 mbytes of memory and those that support 40 92 mbytes of memory. 4. supported on standard-power versions only. 5. supported on low-power versions only. 16 model-specific registers overview embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information standard model-specific registers (all models) this section describes the four standard msrs that every model and stepping of the amd-k6 family of processors support identically. see the appropriate amd-k6 or amd-k6e processor data sheet for more detail on these standard registers. machine-check address register (mcar) and machine-check type register (mctr) the processor does not support the generation of a machine check exception, but does provide a 64-bit machine check address register (mcar) and a 64-bit machine check type register (mctr) for software compatibility. because the processor does not support machine check exceptions, the contents of the mcar and mctr are only affected by the wrmsr instruction and by reset being sampled asserted (where all bits in each register are reset to 0). the processor also provides the machine check exception (mce) bit in control register 4 (cr4, bit 6) as a read-write bit. however, the state of this bit has no effect on the operation of the processor. test register 12 (tr12) the processor provides the 64-bit test register 12 (tr12), but only the cache inhibit (ci) bit (bit 3 of tr12) is supported. all other bits in tr12 have no effect on the processors operation. note: the i/o trap restart function (bit 9 of tr12) is always enabled on amd-k6 processors. time stamp counter (tsc) with each processor clock cycle, the processor increments a 64-bit time stamp counter (tsc) msr. the counter can be written or read using the wrmsr or rdmsr instructions when the ecx register contains the value 10h and current privilege level (cpl) = 0. the counter can also be read using the rdtsc instruction, but the required privilege level for this instruction is determined by the time stamp disable (tsd) bit in cr4. with either of these instructions, the edx and eax registers hold the upper and lower dwords of the 64-bit value to be written to or read from the tsc, as follows: n edxupper 32 bits of tsc n eax lower 32 bits of tsc the tsc can be loaded with any arbitrary value. this feature is compatible with the pentium processor. model 7 and model 8/[7:0] registers 17 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information model 7 and model 8/[7:0] registers the amd-k6e processor model 7 and the amd-k6-2 processor model 8/[7:0] provide the model-specific registers listed in table 9. the contents of ecx selects the msr to be addressed by the rdmsr and wrmsr instruction. table 9. model-specific registers supported by models 7 and 8/[7:0] register name mnemonic ecx value description comments machine-check address register mcar 00h page 16 identical on all models machine-check type register mctr 01h page 16 identical on all models test register 12 tr12 0eh page 16 identical on all models time stamp counter tsc 10h page 16 identical on all models extended feature enable register efer c000_0080h page 18 write handling control register whcr c000_0082h page 19 syscall/sysret target address register star c000_0081h page 22 not supported on model 7 18 model 7 and model 8/[7:0] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information extended feature enable register (efer) the extended feature enable register (efer) contains the control bits that enable the extended features of the amd-k6 processor. figure 2 shows the format of the efer register, and table 10 defines the function of each bit of the efer register. the efer register is msr c000_0080h. figure 2. extended feature enable register (efer) (models 7 and 8/[7:0]) 10 63 s c e reserved symbol description bit sce system call extension 0 table 10. extended feature enable register (efer) definition (models 7 and 8/[7:0]) bit description r/w function 63C1 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 0 system call extension (sce) 1 notes: 1. the amd-k6e processor model 7 provides the sce bit in the efer register, but this bit does not affect processor operation bec ause the syscall and sysret instructions and the star register are not supported in this models. r/w sce must be set to 1 to enable the usage of the syscall and sysret instructions. model 7 and model 8/[7:0] registers 19 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information write handling control register (whcr) the write handling control register (whcr) (see figure 3 on page 20) is an msr that contains three fieldsthe write cacheability detection enable (wcde) bit, the write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit. the whcr register is msr c000_0082h. amd-k6 processors contain a split level-1 (l1) 64-kbyte writeback cache organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes and lines are read from memory using an efficient pipelined burst read cycle. further performance gains are achieved by the implementation of a write allocation scheme. write allocation a write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the l1 cache. for more information, see the implementation of write allocate in the k86? processors application note , order# 21326, and the cache organization chapter in the appropriate amd-k6 or amd-k6e processor data sheet. this section describes two programmable mechanisms used by the processor to determine when to perform write allocate. when either of these mechanisms indicates that a pending write is to a cacheable area of memory, a write allocate is performed. before enabling write allocate or changing memory cacheability/writeability, the bios must writeback and invalidate the internal cache by using the wbinvd instruction. in addition, write allocate should be enabled only after performing any memory sizing or typing algorithms. 20 model 7 and model 8/[7:0] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information figure 3. write handling control register (whcr) (models 7 and 8/[7:0]) write cacheability detection enable bit for proper functionality, always program bit 8 of whcr to 0. see pipelining support on page 69 for more information on the wcde bit. write allocate enable limit field the waelim field is 7 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that misses the l1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector (for more information, see the cache organization chapter in the appropriate amd-k6 or amd-k6e processor data sheet. the maximum value of this limit is ((2 7 C1) 4 mbytes) = 508 mbytes. when all the bits in this field are set to 0, all memory is above this limit and the write allocate mechanism is disabled (even if all bits in the waelim field are set to 0, write allocates can still occur due to the write to a cacheable page and write to a sector mechanisms). once the bios determines the amount of ram installed in the system, this number should also be used to program the waelim field. for example, a system with 32 mbytes of ram would program the waelim field with the value 0001000b. 710 63 reserved waelim 8 0 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits wcde always program to 0 8 waelim write allocate enable limit 7C1 wae15m write allocate enable 15-to-16-mbyte 0 9 model 7 and model 8/[7:0] registers 21 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information this value (8), when multiplied by 4 mbytes, yields 32 mbytes as the write allocate limit. write allocate enable 15-to-16-mbyte field. the wae15m bit is used to enable write allocations for the memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocates in this memory area. this sub-mechanism of the waelim provides a memory hole to prevent write allocates. this memory hole is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0 (even if the wae15m bit is set to 0, write allocates can still occur between 15 mbytes and 16 mbytes due to the write to a cacheable page and write to a sector mechanisms). the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition, write allocations are not performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by means of write to a cacheable page or write to a sector. it is not safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a noncacheable region of memory. 22 model 7 and model 8/[7:0] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information syscall/sysret target address register (star) models 8, 9, and d implement the star register. this register contains the target eip address used by the syscall instruction and the 16-bit code and stack segment selector bases used by the syscall and sysret instructions. figure 4 shows the format of the star register, and table 11 defines the function of each field of the star register. the star register is msr c000_0081h. for more information about syscall/sysret, see the syscall and sysret instruction specification application note , order# 21086. figure 4. syscall/sysret target address register (star) (models 8, 9, and d) table 11. syscall/sysret target address register (star) definition (models 8, 9, and d) bit description r/w function 63C48 sysret cs and ss selector base r/w during the sysret instruction, this field is copied into the cs register and the contents of this field, plus 1000b, are copied into the ss register. 47C32 syscall cs and ss selector base r/w during the syscall instruction, this field is copied into the cs register and the contents of this field, plus 1000b, are copied into the ss register. 31C0 target eip address r/w during the syscall instruction, this address is copied into the eip and points to the new starting address. 31 0 63 target eip address 32 47 48 syscall cs selector and ss selector base sysret cs selector and ss selector base model 8/[f:8] registers 23 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information model 8/[f:8] registers the amd-k6-2 processor model 8/[f:8] and amd-k6-2e processor model 8/[f:8] provides the ten msrs listed in table 12. the contents of ecx select the msr to be addressed by the rdmsr and wrmsr instruction. table 12. model-specific registers supported by model 8/[f:8] register name mnemonic ecx value description comments machine-check address register mcar 00h page 16 identical on all models machine-check type register mctr 01h page 16 identical on all models test register 12 tr12 0eh page 16 identical on all models time stamp counter tsc 10h page 16 identical on all models extended feature enable register efer c000_0080h page 24 newly defined for model 8/[f:8] write handling control register whcr c000_0082h page 27 newly defined for model 8/[f:8] syscall/sysret target address register star c000_0081h page 22 identical to model 8/[7:0] uc/wc cacheability control register uwccr c000_0085h page 30 new for model 8/[f:8] processor state observability register psor c000_0087h page 34 new for model 8/[f:8] page flush/invalidate register pfir c000_0088h page 36 new for model 8/[f:8] 24 model 8/[f:8] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information extended feature enable register (efer) the extended feature enable register (efer) contains the control bits that enable the extended features of the processor. figure 5 shows the format of the efer register, and table 13 defines the function of each bit of the efer register. the efer register is msr c000_0080h. note: the efer register as defined in models 7 and 8/[7:0] is defined differently in model 8/[f:8]. a complete description of the newly defined register is included in this section for model 8/[f:8]. figure 5. extended feature enable register (efer) (model 8/[f:8]) external write buffer empty control field model 8/[f:8] contains an 8-byte write merge buffer that allows the processor to conditionally combine data from multiple noncacheable write cycles into this merge buffer. the merge table 13. extended feature enable register (efer) definition (model 8/[f:8]) bit description r/w function 63C4 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 3-2 ewbe# control (ewbec) r/w this 2-bit field controls the behavior of the processor with respect to the ordering of write cycles and the ewbe# signal. efer[3] and efer[2] are global ewbe# disable (gewbed) and speculative ewbe disable (sewbed), respectively. 1 data prefetch enable (dpe) r/w dpe must be set to 1 to enable data prefetching (this is the default setting following reset). if enabled, cache misses initi- ated by a memory read within a 32-byte cache line are con- ditionally followed by cache-line fetches of the other line in the 64-byte sector. 0 system call extension (sce) r/w sce must be set to 1 to enable the usage of the syscall and sysret instructions. 10 63 s c e reserved 2 3 4 d p e ewbec symbol description bit ewbec ewbe control 3-2 dpe data prefetch enable 1 sce system call extension 0 model 8/[f:8] registers 25 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information buffer operates in conjunction with the memory type range registers (mtrrs). refer to uc/wc cacheability control register (uwccr) on page 30 for a description of the mtrrs. merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. out-of-order write cycles. the presence of the merge buffer creates the potential to perform out-of-order write cycles relative to the processors cache. in general, the ordering of write cycles that are driven externally on the system bus and those that hit the processors cache can be controlled by the ewbe# signal. if ewbe# is sampled negated, the processor delays the commitment of write cycles to cache lines in the modified state or exclusive state in the processors cache. therefore, the system logic can enforce strong ordering by negating ewbe# until the external write cycle is complete, thereby ensuring that a subsequent write cycle that hits the cache does not complete ahead of the external write cycle. however, the addition of the write merge buffer introduces the potential for out-of-order write cycles to occur between writes to the merge buffer and writes to the processors cache. because these writes occur entirely within the processor and are not sent out to the processor bus, the system logic is not able to enforce strong ordering with the ewbe# signal. the ewbe# control (ewbec) bits provide a mechanism for enforcing three different levels of write ordering in the presence of the write merge buffer: best performance. efer[3] is defined as the global ewbe# disable (gewbed). when gewbed equals 1, the processor does not attempt to enforce any write ordering internally or externally (the ewbe# signal is ignored). this is the maximum performance setting. close-to-best performance. efer[2] is defined as the speculative ewbe# disable (sewbed). sewbed only affects the processor when gewbed equals 0. if gewbed equals 0 and sewbed equals 1, the processor enforces strong ordering for all internal write cycles with the exception of write cycles addressed to a range of memory defined as uncacheable (uc) or write-combining (wc) by the mtrrs. in addition, the processor 26 model 8/[f:8] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information samples the ewbe# signal. if ewbe# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until ewbe# is sampled asserted. this setting provides performance comparable to, but slightly less than, the performance obtained when gewbed equals 1 because some degree of write ordering is maintained. slowest performance. if gewbed equals 0 and sewbed equals 0, the processor enforces strong ordering for all internal and external write cycles. in this setting, the processor assumes, or speculates , that strong order must be maintained between writes to the merge buffer and writes that hit the processors cache. once the merge buffer is written out to the processors bus, the ewbe# signal is sampled. if ewbe# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until ewbe# is sampled asserted. this setting is the default after reset and provides the lowest performance of the three settings because full write ordering is maintained. write ordering and performance. table 14 summarizes the three settings of the ewbec field, along with the effect of write ordering and performance. enforcing complete write ordering in a uniprocessor system is usually not necessary. in order to achieve the highest level of performance while still maintaining support for the ewbe# signal, amd recommends that the bios set efer[3:2] to 01b (close-to-best performance). many uniprocessor systems do not support the ewbe# signal, in which case amd recommends that the bios set efer[3:2] to 10b or 11b (best performance). table 14. write ordering and performance settings for efer register efer[3] (gewbed) efer[2] (sewbed) write ordering performance 1 0 or 1 none best 01 all except uc/wc close-to-best 0 (default) 0 (default) all slowest model 8/[f:8] registers 27 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information write handling control register (whcr) the write handling control register (whcr) (see figure 6 on page 28) is an msr that contains two fieldsthe write allocate enable limit (waelim) field and the write allocate enable 15-to-16-mbyte (wae15m) bit. the whcr register is msr c000_0082h. note: the whcr register as defined in the models 7 and 8/[7:0] is defined differently in models 8/[f:8], 9, and d. a complete description of the newly defined register is included in this section for models 8/[f:8], 9, and d. amd-k6 processors contain a split level-1 (l1) 64-kbyte writeback cache organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes, and lines are read from memory using an efficient pipelined burst read cycle. further performance gains are achieved by the implementation of a write allocation scheme. write allocation a write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the l1 cache. for more information on write allocate, see the implementation of write allocate in the k86? processors application note , order# 21326 and see the cache organization chapter in the appropriate amd-k6 or amd-k6e processor data sheet. this section describes two programmable mechanisms used by the processor to determine when to perform write allocate. when either of these mechanisms indicates that a pending write is to a cacheable area of memory, a write allocate is performed. before enabling write allocate or changing memory cacheability, the bios must write back and invalidate the internal cache by using the wbinvd instruction. in addition, write allocate should be enabled only after performing any memory sizing or typing algorithms. 28 model 8/[f:8] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information figure 6. write handling control register (whcr) (models 8/[f:8], 9, and d) write allocate enable limit field the waelim field is 10 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that misses the l1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector (for more information, see the cache organization chapter in the appropriate amd-k6 or amd-k6e processor data sheet. the maximum value of this limit is ((2 10 C1) 4 mbytes) = 4092 mbytes. when all the bits in this field are set to 0, all memory is above this limit and the write allocate mechanism is disabled (even if all bits in the waelim field are set to 0, write allocates can still occur due to the write to a cacheable page and write to a sector mechanisms). once the bios determines the amount of ram installed in the system, this number should also be used to program the waelim field. for example, a system with 32 mbytes of ram would program the waelim field with the value 00_0000_1000b. this value (8), when multiplied by 4 mbytes, yields 32 mbytes as the write allocate limit. 15 22 0 63 reserved waelim 16 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits waelim write allocate enable limit 31-22 wae15m write allocate enable 15-to-16-mbyte 16 17 21 31 32 model 8/[f:8] registers 29 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information write allocate enable 15-to-16-mbyte field the wae15m bit is used to enable write allocations for the memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocates in this memory area. this sub-mechanism of the waelim provides a memory hole to prevent write allocates. this memory hole is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0 (even if the wae15m bit is set to 0, write allocates can still occur between 15 mbytes and 16 mbytes due to the write to a cacheable page and write to a sector mechanisms). the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition, write allocations are not performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by means of write to a cacheable page or write to a sector. it is not safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a noncacheable region of memory. additionally, if a memory region is defined as write-combinable or uncacheable by a mtrr, write allocates are not performed in that region. 30 model 8/[f:8] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information uc/wc cacheability control register (uwccr) models 8/[f:8], 9, and d provide two variable-range memory type range registers (mtrrs)mtrr0 and mtrr1that each specify a range of memory. each range can be defined as one of the following memory types: n uncacheable (uc) memory memory read cycles are sourced directly from the specified memory address, and the processor does not allocate a cache line. memory write cycles are targeted at the specified memory address, and a write allocation does not occur. n write-combining (wc) memory memory read cycles are sourced directly from the specified memory address, and the processor does not allocate a cache line. the processor conditionally combines data from multiple noncacheable write cycles that are addressed within this range into a merge buffer. merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. this memory type is applicable for linear video frame buffers. note: the mtrrs defined in this document are not software- compatible to the mtrrs defined by the pentium pro and pentium ii processors. the programmer accesses the mtrrs by addressing the 64-bit msr known as the uc/wc cacheability control register (uwccr). the msr address of the uwccr is c000_0085h. following reset, all bits in the uwccr register are set to 0. mtrr0 (lower 32 bits of the uwccr register) defines the size and memory type of range 0 and mtrr1 (upper 32 bits) defines the size and memory type of range 1 (see figure 7 on page 31). prior to programming write-combining or uncacheable areas of memory in the uwccr, the software must disable the processors cache, then flush the cache. this can be achieved by setting the cd bit in cr0 to 1 and executing the wbinvd instruction. following the programming of the uwccr, the processors cache must be enabled by setting the cd bit in cr0 to 0. model 8/[f:8] registers 31 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information figure 7. uc/wc cacheability control register (uwccr) (models 8/[f:8], 9, and d) physical base address n (n=0, 1) this address is the 15 most-significant bits of the physical base address of the memory range. the least-significant 17 bits of the base address are not needed because the base address is by definition always aligned on a 128-kbyte boundary. physical address mask n (n=0, 1) this value is the 15 most-significant bits of a physical address mask that is used to define the size of the memory range. this mask is logically anded with both the physical base address field of the uwccr register and the physical address generated by the processor. if the results of the two and operations are equal, then the generated physical address is considered within the range. that is, if: mask & physical base address = mask & physical address generated then, the physical address generated by the processor is in the range. wcn (n=0, 1) when set to 1, this memory range is defined as write- combinable (refer to table 15). write-combinable memory is uncacheable. ucn (n=0, 1) when set to 1, this memory range is defined as uncacheable (refer to table 15). 16 0 63 physical address mask 0 17 31 physical base address 0 1 2 physical address mask 1 physical base address 1 32 33 34 48 49 u c 0 w c 0 u c 1 w c 1 mtrr1 mtrr0 symbol description bits uc0 uncacheable memory type 0 wc0 write-combining memory type 1 symbol description bits uc1 uncacheable memory type 32 wc1 write-combining memory type 33 table 15. wc/uc memory type for uwccr register wcn ucn memory type 0 0 no effect on cacheability or write-combining 1 0 write-combining memory range (uncacheable) 0 or 1 1 uncacheable memory range 32 model 8/[f:8] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information memory-range restrictions the following rules regarding the address alignment and size of each range must be adhered to when programming the physical base address and physical address mask fields of the uwccr register: n the minimum size of each range is 128 kbytes. n the physical base address must be aligned on a 128-kbyte boundary. n the physical base address must be range-size aligned . for example, if the size of the range is 1 mbyte, then the physical base address must be aligned on a 1-mbyte boundary. n all bits set to 1 in the physical address mask must be contiguous. likewise, all bits set to 0 in the physical address mask must be contiguous. for example: 111_1111_1100_0000b is a valid physical address mask. 111_1111_1101_0000b is invalid. table 16 lists the valid physical address masks and the resulting range sizes that can be programmed in the uwccr register. table 16. valid masks and range sizes for uwccr register masks size 111_1111_1111_1111b 128 kbytes 111_1111_1111_1110b 256 kbytes 111_1111_1111_1100b 512 kbytes 111_1111_1111_1000b 1 mbyte 111_1111_1111_0000b 2 mbytes 111_1111_1110_0000b 4 mbytes 111_1111_1100_0000b 8 mbytes 111_1111_1000_0000b 16 mbytes 111_1111_0000_0000b 32 mbytes 111_1110_0000_0000b 64 mbytes 111_1100_0000_0000b 128 mbytes 111_1000_0000_0000b 256 mbytes 111_0000_0000_0000b 512 mbytes 110_0000_0000_0000b 1 gbyte 100_0000_0000_0000b 2 gbytes 000_0000_0000_0000b 4 gbytes model 8/[f:8] registers 33 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information examples suppose that the range of memory from 16 mbytes to 32 mbytes is uncacheable, and the 8-mbyte range of memory on top of 1 gbyte is write-combinable. range 0 is defined as the uncacheable range, and range 1 is defined as the write- combining range. n extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 16 mbytes (0100_0000h) yields a physical base address 0 field of 000_0000_1000_0000b. because the uncacheable range size is 16 mbytes, the physical mask value 0 field is 111_1111_1000_0000b, according to table 16 on page 32. bit 1 of the uwccr register (wc0) is set to 0, and bit 0 of the uwccr register is set to 1 (uc0). n extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 1 gbyte (4000_0000h) yields a physical base address 1 field of 010_0000_0000_0000b. because the write-combining range size is 8 mbytes, the physical mask value 1 field is 111_1111_1100_0000b, according to table 16. bit 33 of the uwccr register (wc1) is set to 1 and bit 32 of the uwccr register is set to 0 (uc1). 34 model 8/[f:8] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information processor state observability register (psor) models 8/[f:8], 9, and standard-power versions of model d provide the processor state observability register (psor) as defined in figure 8. the psor register is msr c000_0087h. note: see page 46 for definitions of the psor bit fields for low- power model d processors. . figure 8. processor state observability register (psor ) (models 8/[f:8], 9, and standard-power d) nol2 bit this read-only bit indicates whether the processor contains an l2 cache. note: this bit is always set to 1 for model 8/[f:8]. note: this bit is always set to 0 for models 9 and d. step field this read-only field contains the stepping id. this is identical to the value returned by the cpuid standard function 1 in eax[3:0]. bf field this read-only field contains the value of the bf signals sampled by the processor during the falling transition of reset, which allows the bios to determine the frequency of the host bus. n the core frequency must first be known, which can be determined using the time stamp counter method (see time stamp counter (tsc) on page 16). n the core frequency is then divided by the processor-clock to bus-clock ratio as determined by the bf field of the psor register (see table 17 and table 18 on page 35). n the result is the frequency of the processor bus. 20 63 bf reserved symbol description bit nol2 no l2 functionality 8 step processor stepping 7-4 bf bus frequency divisor 2-0 3 4 step 7 8 9 n o l 2 model 8/[f:8] registers 35 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information table 17. processor-to-bus clock ratios (models 8/[f:8] and 9) table 18. processor-to-bus clock ratios (model standard-power d) state of bf[2:0] processor-clock to bus-clock ratio 100b 2.5x 101b 3.0x 110b 6.0x 1 notes: 1. the 2.0x ratio that is supported on models 7 and 8/[7:0] is not supported on models 8/[f:8] or 9. instead, if bf[2:0] equals 110b, a ratio of 6.0x is selected. 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x state of bf[2:0] processor-clock to bus-clock ratio 100b 2.0x 1 notes: 1. the 2.5x ratio that is supported on model 8/[f:8] and 9 is not supported on standard-power model d. instead, if bf[2:0] equals 100b, a ratio of 2.0x is selected. 101b 3.0x 110b 6.0x 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x 36 model 8/[f:8] registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information page flush/invalidate register (pfir) models 8/[f:8], 9, and d contain the page flush/invalidate register (pfir) (see figure 9) that allows cache invalidation and optional flushing of a specific 4-kbyte page from the linear address space. the total amount of l1 cache in the processor is 64 kbytes. using this register can result in a much lower cycle count for flushing particular pages versus flushing the entire cache. when the pfir is written to (using the wrmsr instruction), the invalidation and, optionally, the flushing begins. the pfir register is msr c000_0088h. note: the invalidate and flush operations affect both the l1 and l2 caches on models 9 and d. figure 9. page flush/invalidate register (pfir) (models 8/[f:8], 9, and d) linpage field this 20-bit field must be written with bits 31:12 of the linear address of the 4-kbyte page that is to be invalidated and optionally flushed from the l1 cache. pf bit if an attempt to invalidate or flush a page results in a page fault, the processor sets the pf bit to 1, and the invalidate or flush operation is not performed (even though invalidate operations do not normally generate page faults). in this case, an actual page fault exception is not generated. if the pf bit equals 0 after an invalidate or flush operation, then the operation executed successfully. the pf bit must be read after every write to the pfir register to determine if the invalidate or flush operation executed successfully. linpage 10 63 f / i reserved symbol description bit linpage 20-bit linear page address 31-12 pf page fault occurred 8 f/i flush/invalidate command 0 11 31 12 32 p f 987 model 8/[f:8] registers 37 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information f/i bit this bit is used to control the type of action that occurs to the specified linear page. if a 0 is written to this bit, the operation is a flush, in which case all cache lines in the modified state within the specified page are written back to memory, after which the entire page is invalidated. if a 1 is written to this bit, the operation is an invalidation, in which case the entire page is invalidated without the occurrence of any writebacks. 38 model 9 registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information model 9 registers the amd-k6-iii processor (model 9) provides the eleven model- specific registers listed in table 19. the contents of ecx selects the msr to be addressed by the rdmsr and wrmsr instruction. the amd-k6-iii processor contains a split level-1 (l1) 64-kbyte writeback cache organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes, and lines are read from memory using an efficient pipelined burst read cycle. in addition, the processor also contains a 256-kbyte, 4-way set associative, unified level-2 (l2) cache. further performance gains are achieved by the implementation of a write allocation scheme. table 19. model-specific registers supported by model 9 register name mnemonic ecx value description comments machine-check address register mcar 00h page 16 identical on all models machine-check type register mctr 01h page 16 identical on all models test register 12 tr12 0eh page 16 identical on all models time stamp counter tsc 10h page 16 identical on all models extended feature enable register efer c000_0080h page 39 adds l2 disable bit (l2d) to model 8/[f:8] implementation write handling control register whcr c000_0082h page 27 identical to model 8/[f:8] syscall/sysret target address regis- ter star c000_0081h page 22 identical to model 8/[7:0] uc/wc cacheability control register uwccr c000_0085h page 30 identical to model 8/[f:8] processor state observability register psor c000_0087h page 34 identical to model 8/[f:8] page flush/invalidate register pfir c000_0088h page 36 identical to model 8/[f:8]. the invalidate and flush operations affect both the l1 and l2 caches on the amd-k6- iii processor. level-2 cache array access register l2aar c000_0089h page 40 new for model 9 model 9 registers 39 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information extended feature enable register (efer) figure 10 shows the format of the efer register for models 9 and d, and table 20 defines the function of each bit of the efer register. the efer register is msr c000_0080h. note: bits 3:0 of the efer register in models 9 and d are identical to the implementation of these bits in model 8/[f:8]. for models 9 and d, the l2 disable bit (l2d), efer[4], is added. the complete new register description is included in this section. figure 10. extended feature enable register (efer) (models 9 and d) note: setting l2d to 1 does not guarantee cache coherency. to ensure coherency, the processors caches must be disabled (by setting the cd bit of the cr0 register to 1), then flushed prior to setting l2d to 1. table 20. extended feature enable register (efer) definition (models 9 and d) bit description r/w function 63C5 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 4 l2 disable (l2d) r/w if l2d is set to 1, the l2 cache is completely disabled. this bit is provided for debug and testing purposes. for normal operation and maximum performance, this bit must be set to 0 (this is the default setting following reset). 3-2 ewbe control (ewbec) r/w this 2-bit field controls the behavior of the processor with respect to the ordering of write cycles and the ewbe# signal. efer[3] and efer[2] are global ewbe# disable (gewbed) and speculative ewbe# disable (sewbed), respectively. 1 data prefetch enable (dpe) r/w dpe must be set to 1 to enable data prefetching (this is the default setting follow- ing reset). if enabled, cache misses initiated by a memory read within a 32-byte cache line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. 0 system call extension (sce) r/w sce must be set to 1 to enable usage of the syscall and sysret instructions. 10 63 s c e reserved 2 3 4 d p e ewbec l 2 d symbol description bit l2d l2 disable 4 ewbec ewbe control 3-2 dpe data prefetch enable 1 sce system call extension 0 5 40 model 9 registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information level-2 cache array access register (l2aar) models 9 and d provide the l2aar register that allows for direct access to the l2 cache and l2 tag arrays. the l2 cache in the amd-k6-iii processor is organized as shown in figure 11: n four 64-kbyte ways n each way contains 1024 sets n each set contains four 64-byte sectors (one sector in each way) n each sector contains two 32-byte cache lines n each cache line contains four 8-byte octets n each octet contains an upper and lower dword (4 bytes) each line within a sector contains its own mesi state bits, and associated with each sector is a tag and least recently used (lru) information. figure 11. l2 cache organization (amd-k6? -iii processor) the l2aar register is msr c000_0089h. the operation that is performed on the l2 cache is a function of the instruction executedrdmsr or wrmsrand the contents of the edx register. the edx register specifies the location of the access, and whether the access is to the l2 cache data or tags (see figure 13 on page 41). figure 12 on page 41 shows the l2 cache sector and line organization. if bit 5 (see figure 13) of the address of a cache line equals 1, then this cache line is stored in line 1 of a sector. similarly, if bit 5 of the address of a cache line equals 0, then this cache line is stored in line 0 of a sector. 1024 sets set 0 64 bytes way 2 line1/mesi line0/mesi tag/lru 64 bytes way 1 line1/mesi line0/mesi tag/lru 64 bytes way 0 line1/mesi line0/mesi tag/lru 64 bytes way 3 line1/mesi line0/mesi tag/lru set 1023 model 9 registers 41 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information figure 12. l2 cache sector and line organization bit 20 of edx (t/d) determines whether the access is to the l2 cache data or tag. table 21 on page 42 describes the operation that is performed based on the instruction and the t/d bit. figure 13. l2 tag or data location (amd-k6? -iii processor)edx upper dword lower dword octet 0 line 1 octet 1 octet 2 octet 3 upper dword lower dword line 0 sector reserved 0 set 21 31 20 19 17 16 5 15 18 way 4321 6 symbol description bit set selects the desired cache set 15-6 line selects line1 (1) or line0 (0) 5 octet selects one of four octets 4-3 dword selects upper (1) or lower (0) dword 2 l i n e octet d w o r d t / d symbol description bit t/d selects tag (1) or data (0) access 20 way selects desired cache way 17-16 42 model 9 registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information when the l2aar is read or written, edx is left unchanged. this facilitates multiple accesses when testing the entire cache/tag array. if the l2 cache data is read (as opposed to reading the tag information), the result (dword) is placed in eax in the format as illustrated in figure 14. similarly, if the l2 cache data is written, the write data is taken from eax. figure 14. l2 dataeax if the l2 tag is read (as opposed to reading the cache data), the result is placed in eax in the format as illustrated in figure 15 on page 43. similarly, if the l2 tag is written, the write data is taken from eax. when accessing the l2 tag, the line, octet, and dword fields of the edx register are ignored. table 21. tag versus data selector instruction t/d (edx[20]) operation rdmsr 0 read dword from l2 data array into eax. dword location is specified by edx. rdmsr 1 read tag, line state and lru information from l2 tag array into eax. location of tag is specified by edx. wrmsr 0 write dword to the l2 data array using data in eax. dword location is specified by edx. wrmsr 1 write tag, line state and lru information into l2 tag array from eax. location of tag is specified by edx. 0 31 data model 9 registers 43 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information figure 15. l2 tag information (amd-k6? -iii processor)eax lru (least recently used) field for the 4-way set associative l2 cache, each way has a 2-bit lru field for each sector. values for the lru field are 00b, 01b, 10b, and 11b, where 00b indicates that the sector is most recently used, and 11b indicates that the sector is least recently used (see figure 16). eax[7:6] indicate lru information for way 0, eax[5:4] for way 1, eax[3:2] for way 2, and eax[1:0] for way 3. figure 16. lru byte writing to l2 tag of amd-k6? -iii processor when writing to the l2 tag of the amd-k6-iii processor, special consideration must be given to the least significant bit of the tag field of the eax register eax[15]. the length of the l2 tag required to support the 256-kbyte l2 cache on the amd-k6-iii processor is 16 bits, which corresponds to bits 31:16 of the eax register. however, the amd-k6-iii processor provides a total of 17 bits for storing the l2 tagthat is, 16 bits for the tag (eax[31:16]), plus an additional bit for internal purposes (eax[15]). during normal operation, the amd-k6-iii processor ensures that this additional bit (bit 15) always corresponds to the set in which the tag resides. note that bits c m d reserved 0 tag 15 31 14 12 10 9 7 8 11 lru line0st line1st symbol description bit tag tag data read or written 31-15 line1st line 1 state (m=11, e=10, s=01, i=00) 11-10 line0st line 0 state (m=11, e=10, s=01, i=00) 9-8 lru two bits of lru for each way 7-0 7654 32 1 0 way 2 lru values 00b most recently used 01b used more recently than 10b, but less recently than 00b 10b used more recently than 11b, but less recently than 01b 11b least recently used way 3 way 0 way 1 44 model 9 registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information 15:6 of the address determine the set, in which case bit 15 equal to 0 addresses sets 0 through 511, and bit 15 equal to 1 addresses sets 512 through 1023. in order to set the full 17-bit l2 tag properly when using the l2aar register, eax[15] must likewise correspond to the set in which the tag is being writtenthat is, eax[15] must be equal to edx[15] (refer to figure 13 on page 41 and figure 15 on page 43). it is important to note that this special consideration is only required if the amd-k6-iii processor will subsequently be expected to properly execute instructions or access data from the l2 cache following the setup of the l2 cache by means of the l2aar register. if the intent of using the l2aar register is solely to test or debug the l2 cache without the subsequent intent of executing instructions or accessing data from the l2 cache, then this consideration is not required. model d registers 45 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information model d registers the amd-k6-2e+ and amd-k6-iiie+ processors (model d) provide the twelve model-specific registers listed in table 22. the contents of ecx selects the msr to be addressed by the rdmsr and wrmsr instruction. the amd-k6-2e+ and amd-k6-iiie+ processors contain a split level-1 (l1) 64-kbyte writeback cache organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes, and lines are read from memory using an efficient pipelined burst read cycle. in addition, these processors also contain a 128- kbyte (amd-k6-2e+ processor) or a 256-kbyte (amd-k6-iiie+ processor), 4-way set associative, unified level-2 (l2) cache. further performance gains are achieved by the implementation of a write allocation scheme. table 22. model-specific registers supported by model d register name mnemonic ecx value description comments machine-check address register mcar 00h page 16 identical on all models machine-check type register mctr 01h page 16 identical on all models test register 12 tr12 0eh page 16 identical on all models time stamp counter tsc 10h page 16 identical on all models extended feature enable register efer c000_0080h page 39 adds l2 disable bit (l2d) to model 8/[f:8] implementation write handling control register whcr c000_0082h page 27 identical to model 8/[f:8] syscall/sysret target address register star c000_0081h page 22 identical to model 8/[7:0] uc/wc cacheability control register uwccr c000_0085h page 30 identical to model 8/[f:8] processor state observability register psor c000_0087h page 34 1 , page 46 2 notes: 1. standard-power versions only. 2. low-power versions only. standard-power implementation is identical to model 8/[f:8]. low- power implementation adds new fields and renames bf to ebf. page flush/invalidate register pfir c000_0088h page 36 identical to model 8/[f:8] level-2 cache array access register l2aar c000_0089h page 48 identical to model 9, but note dif- fering l2 cache sizes on model d. enhanced power management register 2 epmr c000_0086h page 54 new for model d. supported on low-power versions only. 46 model d registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information processor state observability register (psor) (low-power versions) the low-power versions of the amd-k6-2e+ and amd-k6-iiie+ processors provide the processor state observability register (psor) as defined in figure 17. note: standard-power versions of model d support the psor as defined on page 34. the psor register is msr c000_0087h. . figure 17. processor state observability register (psor ) (model d low-power versions) pbf[2:0] field this read-only field contains the bf divisor values externally applied to the processor bf[2:0] pins. these input bf values are sampled by the processor during the falling transition of reset. note: this bf divisor value may be different than the bf divisor value supplied to the processors internal pll. vid field this read-only field contains the voltage id bits driven to the processor vid[4:0] pins at reset. these bits are initialized to 01010b and driven on the vid[4:0] pins at reset. note: low-power amd-k6-2e+ and amd-k6-iiie+ processors support amd powernow! technology, which enables dynamic alteration of the processors core voltage. see enhanced power management register (epmr) (low- power versions) on page 54 for information on programming the vid[4:0] pins. 2 0 63 ebf[2:0] reserved symbol description bits nol2 no l2 functionality 8 step processor stepping 7-4 ebf effective bus frequency divisor 2-0 3 4 step 7 8 9 n o l 2 vid pbf[2:0] 16 20 23 21 15 24 symbol description bits pbf pin bus frequency divisor 23-21 vid voltage id 20-16 model d registers 47 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information nol2 bit this read-only bit indicates whether the processor contains an l2 cache. note: this bit is always set to 0 for model d. step field this read-only field contains the stepping id. this is identical to the value returned by cpuid standard function 1 in eax[3:0]. ebf[2:0] field this read-only field contains the effective value of the bf divisor supplied to the processors internal pll, which allows the bios to determine the frequency of the host bus. n the core frequency must first be determined using the time stamp counter method (see time stamp counter (tsc) on page 16). n the core frequency is then divided by the processor-to-bus clock ratio as determined by the ebf field of the psor register (see table 23). n the result is the frequency of the processor bus. table 23. processor-to-bus clock ratios (low-power model d) state of ebf[2:0] processor-to-bus clock ratio 100b 2.0x 1 notes: 1. the 2.5x ratio that was supported on models 8 and 9 is not supported on low-power model d. instead, a ratio of 2.0x is selected when ebf[2:0] equals 100b. 101b 3.0x 110b 6.0x 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x 48 model d registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information level-2 cache array access register (l2aar) model d also provides the l2aar register that allows for direct access to the l2 cache and l2 tag arrays. note: the l2aar register is identical to the model 9 implementation. some information in this section is duplicated to account for the different l2 cache sizes in the amd-k6-2e+ and amd-k6-iiie+ processors. the l2 cache in the amd-k6-2e+ and amd-k6-iiie+ processors is organized as shown in figure 18: n four 32-kbyte ways (amd-k6-2e+ processor) or four 64- kbyte ways (amd-k6-iiie+ processor) n each way contains 512 (amd-k6-2e+ processor) or 1024 (amd-k6-iiie+ processor) sets n each set contains four 64-byte sectors (one sector in each way) n each sector contains two 32-byte cache lines n each cache line contains four 8-byte octets n each octet contains an upper and lower dword (4 bytes) each line within a sector contains its own mesi state bits, and associated with each sector is a tag and lru (least recently used) information. figure 18. l2 cache organization 512 or 1024 sets set 0 64 bytes way 2 line1/mesi line0/mesi tag/lru 64 bytes way 1 line1/mesi line0/mesi tag/lru 64 bytes way 0 line1/mesi line0/mesi tag/lru 64 bytes way 3 line1/mesi line0/mesi tag/lru set 1023 model d registers 49 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information the l2aar register is msr c000_0089h. the operation that is performed on the l2 cache is a function of the instruction executedrdmsr or wrmsrand the contents of the edx register. the edx register specifies the location of the access, and whether the access is to the l2 cache data or tags (refer to figure 20 on page 50 for the amd-k6-2e+ processor and figure 21 on page 50 for the amd-k6-iiie+ processor). figure 19 shows the l2 cache sector and line organization. if bit 5 (refer to figure 20 for the amd-k6-2e+ processor and figure 21 for the amd-k6-iiie+ processor) of the address of a cache line equals 1, then this cache line is stored in line 1 of a sector. similarly, if bit 5 of the address of a cache line equals 0, then this cache line is stored in line 0 of a sector. figure 19. l2 cache sector and line organization (same as figure 12) bit 15 of edx, which is the most significant bit of the set field, is not used for the amd-k6-2e+ because there are half as many sets implemented on the amd-k6-2e+ (512 sets) as the amd-k6-iiie+ processor (1024 sets). bit 20 of edx (t/d) determines whether the access is to the l2 cache data or tag. table 24 on page 51 describes the operation that is performed based on the instruction and the t/d bit. upper dword lower dword octet 0 line 1 octet 1 octet 2 octet 3 upper dword lower dword line 0 sector 50 model d registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information figure 20. l2 tag or data location (amd-k6?-2e+ processor)edx figure 21. l2 tag or data location (amd-k6?- iii e+ processor)edx reserved 0 set 21 31 20 19 17 16 5 15 18 way 4321 6 symbol description bit set selects the desired cache set 14-6 line selects line1 (1) or line0 (0) 5 octet selects one of four octets 4-3 dword selects upper (1) or lower (0) dword 2 l i n e octet d w o r d t / d symbol description bit t/d selects tag (1) or data (0) access 20 way selects desired cache way 17-16 14 reserved 0 set 21 31 20 19 17 16 5 15 18 way 4321 6 symbol description bit set selects the desired cache set 15-6 line selects line1 (1) or line0 (0) 5 octet selects one of four octets 4-3 dword selects upper (1) or lower (0) dword 2 l i n e octet d w o r d t / d symbol description bit t/d selects tag (1) or data (0) access 20 way selects desired cache way 17-16 model d registers 51 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information when the l2aar is read or written, edx is left unchanged. this facilitates multiple accesses when testing the entire cache/tag array. if the l2 cache data is read (as opposed to reading the tag information), the result (dword) is placed in eax in the format as illustrated in figure 22. similarly, if the l2 cache data is written, the write data is taken from eax. figure 22. l2 dataeax (same as figure 14) if the l2 tag is read (as opposed to reading the cache data), the result is placed in eax in the format as illustrated in figure 23 on page 52 (amd-k6-2e+ processor) and figure 24 (amd-k6-iiie+ processor). similarly, if the l2 tag is written, the write data is taken from eax. when accessing the l2 tag, the line, octet, and dword fields of the edx register are ignored. table 24. tag versus data selector (same as table 21) instruction t/d (edx[20]) operation rdmsr 0 read dword from l2 data array into eax. dword location is specified by edx. rdmsr 1 read tag, line state and lru information from l2 tag array into eax. location of tag is specified by edx. wrmsr 0 write dword to the l2 data array using data in eax. dword location is specified by edx. wrmsr 1 write tag, line state and lru information into l2 tag array from eax. location of tag is specified by edx. 0 31 data 52 model d registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information figure 23. l2 tag information (amd-k6?-2e+ processor)eax figure 24. l2 tag information (amd-k6?- iii e+ processor)eax lru (least recently used) field for the 4-way set associative l2 cache, each way has a 2-bit lru field for each sector. values for the lru field are 00b, 01b, 10b, and 11b, where 00b indicates that the sector is most recently used, and 11b indicates that the sector is least recently used (see figure 25 on page 53). eax[7:6] indicate the lru information for way 0, eax[5:4] for way 1, eax[3:2] for way 2, and eax[1:0] for way 3. c m d reserved 0 tag 31 14 12 10 9 7 8 11 lru line0st line1st symbol description bit tag tag data read or written 31-14 line1st line 1 state (m=11, e=10, s=01, i=00) 11-10 line0st line 0 state (m=11, e=10, s=01, i=00) 9-8 lru two bits of lru for each way 7-0 13 c m d reserved 0 tag 15 31 14 12 10 9 7 8 11 lru line0st line1st symbol description bit tag tag data read or written 31-15 line1st line 1 state (m=11, e=10, s=01, i=00) 11-10 line0st line 0 state (m=11, e=10, s=01, i=00) 9-8 lru two bits of lru for each way 7-0 model d registers 53 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information figure 25. lru byte (same as figure 16) writing to l2 tag of amd-k6- iii e+ processor when writing to the l2 tag of the amd-k6-iiie+ processor, special consideration must be given to the least significant bit of the tag field of the eax register eax[15]. the length of the l2 tag required to support the 256-kbyte l2 cache on the amd-k6-iii and amd-k6-iiie+ is 16 bits, which corresponds to bits 31:16 of the eax register. however, the amd-k6-iiie+ processor provides a total of 17 bits for storing the l2 tagthat is, 16 bits for the tag (eax[31:16]), plus an additional bit for internal purposes (eax[15]). during normal operation, the amd-k6-iii and amd-k6-iiie+ ensure that this additional bit (bit 15) always corresponds to the set in which the tag resides. note that bits 15:6 of the address determine the set, in which case bit 15 equal to 0 addresses sets 0 through 511, and bit 15 equal to 1 addresses sets 512 through 1023. in order to set the full 17-bit l2 tag properly when using the l2aar register, eax[15] must likewise correspond to the set in which the tag is being writtenthat is, eax[15] must be equal to edx[15] (refer to figure 21 on page 50 and figure 24 on page 52). it is important to note that this special consideration is only required if the amd-k6-iiie+ processor will subsequently be expected to properly execute instructions or access data from the l2 cache following the setup of the l2 cache by means of the l2aar register. if the intent of using the l2aar register is solely to test or debug the l2 cache without the subsequent intent of executing instructions or accessing data from the l2 cache, then this consideration is not required. note: this special consideration when writing to the l2 tag is not applicable to the amd-k6-2e+ processor. 7654 32 1 0 way 2 lru values 00b most recently used 01b used more recently than 10b, but less recently than 00b 10b used more recently than 11b, but less recently than 01b 11b least recently used way 3 way 0 way 1 54 model d registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information enhanced power management register (epmr) (low-power versions) to support amd powernow! technology, the low-power versions of the amd-k6-2e+ and amd-k6-iiie+ processors model d are designed with enhanced power management (epm) features: dynamic bus divisor control, and dynamic voltage id control. the epmr register (see figure 26) defines the base address for a 16-byte block of i/o address space. enabling the epmr allows software to access the epm 16-byte i/o block, which contains bits for enabling, controlling, and monitoring the epm features. table 25 defines the functions of each bit in the epmr register. the epmr register is msr c000_0086h. figure 26. enhanced power management register (epmr) (low-power model d) table 25. enhanced power management register (epmr) definition (low-power model d) bit description r/w function 1 notes: 1. all bits default to 0 when reset is asserted. 63C16 reserved r all reserved bits are always read as 0. 15-4 i/o base address (iobase) r/w iobase defines a base address for a 16-byte block of i/o address space accessible for enabling, controlling, and monitor- ing the epm features. 3-2 reserved r all reserved bits are always read as 0. 1 generate special bus cycle (gsbc) r/w this bit controls whether a special bus cycle is generated upon dword accesses within the epm 16-byte block. if set to 1, an epm special bus cycle is generated, where be[7:0]# = bfh and a[4:3] = 00b. 0 enable amd powernow! technology management (en) r/w this bit controls access to the mapped i/o address space for the epm features. clearing this bit does not affect the state of bits defined in the epm 16-byte i/o block. c m d reserved 0 16 63 15 4 31 2 e n g s b c iobase symbol description bit iobase i/o base address 15-4 gsbc generate special bus cycle 1 en enable amd powernow! technology management 0 model d registers 55 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information epm 16-byte i/o block (low-power versions only) the epm 16-byte i/o block contains one 4-byte fieldbus divisor and voltage id control (bvc)for enabling, controlling, and monitoring the epm features (see figure 27). all accesses to the epm 16-byte i/o block must be aligned dword accesses. except for the epm special bus cycle, valid accesses to the epm 16-byte block do not generate i/o bus cycles, while non-aligned and non-dword accesses are passed to the i/o bus. figure 27. epm 16-byte i/o block (low-power model d) table 26 defines the function of the byte-field within the epm 16-byte i/o block mapped by the epmr. bvc field figure 28 on page 56 shows the format and table 27 defines the function of each bit of the bvc field located within the 16-byte i/o block. note: the epm stop grant state is a low-power, clock-control state entered by writing a non-zero value to the sgtc field for altering the core voltage and frequency settings. system- initiated inquire (snoop) cycles are not supported and must be prevented during epm stop grant clock control state. reserved 0 12 15 11 87 bvc symbol description bytes bvc bus divisor and voltage id control 11-8 table 26. epm 16-byte i/o block definition (low-power model d) byte description r/w function 1 notes: 1. all bits default to 0 when reset is asserted. 15-12 reserved r all reserved bits are always read as 0. 11-8 bus divisor and voltage id control (bvc) r/w the bit fields within the bvc bytes allow software to change the processor bus divisor and core voltage. 7-0 reserved r all reserved bits are always read as 0. 56 model d registers embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information figure 28. bus divisor and voltage id control (bvc) field (low-power model d) table 27. bus divisor and voltage id control (bvc) definition (low-power model d) bit description r/w function 1 notes: 1. all bits default to 0 when reset is asserted, except the vido bits which default to 01010b. 31-12 stop grant time-out counter (sgtc) w writing a non-zero value to this field causes the processor to enter the epm stop grant state internally. this 20-bit value is multiplied by 4096 to determines the duration of the epm stop grant state, measured in processor bus clocks. 11 bus divisor and vid change mode (bvcm) r/w this bit controls the mode in which the bus-divisor and the voltage con- trol bits are allowed to change. if bvcm=0, the bus divisor and voltage id changes take effect only upon entering the epm stop grant state as a result of the sgtc field being programmed. bvcm=1 is reserved. 10 voltage id control (vidc) r/w this bit controls the mode of voltage id control. if vidc=0, the proces- sor vid[4:0] pins are unchanged upon entering the epm stop grant state. if vidc=1, the processor vid[4:0] pins are programmed to the vido value upon entering the epm stop grant state. bios should ini- tialize this bit to 1 during the post routine. 9-8 bus divisor control (bdc) r/w this 2-bit field controls the mode of bus divisor control. if bdc[1:0]=00b, the bf[2:0] pins are sampled at the falling edge of reset. if bdc[1:0]=1xb, the ibf[2:0] field is sampled upon entering the epm stop grant state. bdc[1:0]=01b is reserved. bios should initialize these bits to 10b during the post routine. 7-5 internal bf divisor (ibf) r/w if bdc[1:0]=1xb, the processor ebf[2:0] field of the psor is pro- grammed to the ibf[2:0] value upon entering the epm stop grant state. 4-0 voltage id output (vido) r/w this 5-bit value is driven out on the processor vid[4:0] pins upon enter- ing the epm stop grant state if the vidc bit=1. these bits are initialized to 01010b and driven on the processor vid[4:0] pins at reset. reserved 0 12 31 9 8 75 symbol description bits sgtc stop grant time-out counter 31-12 bvcm bus divisor and vid change mode 11 vidc voltage id control 10 bdc bus divisor control 9-8 ibf[2:0] internal bf divisor 7-5 vido voltage id output 4-0 v i d c ibf[2:0] 11 10 b v c m bdc vido 4 sgtc embedded amd processor recognition 57 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information embedded amd processor recognition the cpuid instruction provides a simple way for hardware and software to identify the type of processor and its feature set. after detecting the processor and its capabilities, software can be accurately tuned to the system for optimal performance and benefit to users. n for example, game software can test the performance level available from a particular processor by detecting the type or speed of the processor. if the features warrant executing additional capabilities or advanced algorithms, these can be enabled with software. n another example involves testing for the presence of 3dnow! or mmx instructions on the processor. if the software finds these features present when it checks the feature bits, it can utilize these more powerful extensions for dramatically better performance on new multimedia software. see http://www.amd.com/products/cpg/bin for example software and source code to detect processor information. cpuid instruction overview software operating at any privilege level can execute the cpuid instruction to identify the processor and its feature set. in addition, the cpuid instruction implements multiple functions, each providing different information about the processor, including the vendor, model number, revision (stepping), features, cache organization, and processor name. the multiple-function approach allows the cpuid instruction to return a complete picture about the type of processor and its capabilitiesmore detailed information than could be returned by a single function. the cpuid instruction provides the flexibility of making only one call to obtain the specific data requested. the functions are divided into two types: standard functions and extended functions. 58 embedded amd processor recognition embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information n standard functions provide a simple method for software to access information common to all x86 processors. n extended functions provide information on extensions specific to a vendors processor (for example, amds processors). the flexibility of the cpuid instruction allows for the addition of new cpuid functions in future generations of processors. appendix a on page 71 contains a detailed description of the cpuid instruction. testing for the cpuid instruction beginning with the amd-k6e processor model 7, all amd processors support the cpuid instruction. however, it is still recommended that software verify that the cpuid instruction is supported. to use the cpuid instruction, software must first determine if the processor supports the cpuid instruction. cpuid support is determined in one of the following ways: n execute the cpuid instruction and check whether an illegal instruction exception occurs. if an exception occurs, the processor does not have cpuid support. n check if the id bit (bit 21) of the eflags register is writable. if the bit is writable (that is, it can be modified), the cpuid instruction is supported. the operating system (os) environment determines which approach is more appropriate. these techniques are described in the following sections. illegal instruction exception method this technique requires a way for a user program to detect and handle illegal instruction exceptions. where such capabilities are present, this method represents a reliable way of detecting support for the cpuid instruction. the cpuid sample code described on page 67 uses this approach. eflags id-bit method this technique retrieves the contents of eflags using the pushfd instruction, toggles the id bit, and uses the popfd instruction to write the modified value of the id bit into the eflags register. it then retrieves the contents of eflags using a second pushfd instruction and checks whether the value of the id bit differs from the original value. embedded amd processor recognition 59 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information if the value has changed, the cpuid instruction is available for identifying the processor and its features. the following code sample demonstrates the way a program uses the pushfd and popfd instructions to test the id bit. pushfd ; save eflags to stack pop eax ; store eflags in eax mov ebx, eax ; save in ebx for testing later xor eax, 00200000h ; switch bit 21 push eax ; copy changed value to stack popfd ; save changed eax to eflags pushfd ; push eflags to top of stack pop eax ; store eflags in eax cmp eax, ebx ; see if bit 21 has changed jz no_cpuid ; if no change, no cpuid a potential problem with this approach is that an interrupt or a trap (such as a debug trap) can occur between the popfd and the following pushfd, and that the interrupt or trap handler code destroys the value of the id bit. where possible, the above code should be preceded by a cli instruction and followed by an sti instruction, which ensures that no interrupts occur between the popfd and the pushfd. however, traps can still occur, even if the code is preceded by a cli instruction and followed by an sti instruction. using cpuid functions when software uses the cpuid instruction to identify a processor, it is important that it uses the instruction appropriately. the instruction has been defined to make it easy to identify the type and features of x86 processors manufactured by many different vendors. the standard functions (eax=0 and eax=1) are the same for all processors. having standard functions simplifies softwares task of testing for and implementing features common to x86 processors. software can test for these features and, as new x86 processors are released, benefit from these capabilities immediately. extended functions are specific to a vendors processor. these functions provide additional information about amd processors that software can use to identify enhanced features and functions. to test for extended functions, software checks 60 embedded amd processor recognition embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information for a value of at least 8000_0001h in the eax register returned by function 8000_0000h. within amds family of processors, different members can execute a different number of functions. table 28 summarizes the cpuid functions currently implemented on amd processors. 76 i dentifying the processors vendor software must execute the standard function eax=0. the cpuid instruction returns a 12-character string that identifies the processors vendor. the instruction also returns the largest standard function input value defined for the cpuid instruction on the processor. for amd processors, function 0 returns a vendor string of authenticamd. this string informs the software to follow table 28. cpuid functions 1 in amd-k6? processors 2 notes: 1. appendix a on page 71 contains detailed descriptions of the functions. 2. future versions of these processors may implement additional functions. standard function extended function description amd-k6?e processor (model 7) amd-k6?-2 and amd-k6?-2e processors (model 8) amd-k6? -iii processor (model 9) amd-k6?-2e+ and amd-k6?- iii e+ processors (model d) 0 vendor string and largest standard function value xx x x 1 processor signature and standard feature bits xx x x 8000_0000h largest extended function value x x x x 8000_0001h extended processor signature and extended feature bits xx x x 8000_0002h processor name x x x x 8000_0003h processor name x x x x 8000_0004h processor name x x x x 8000_0005h l1 tlb 3 cache information 3. tlb = translation lookaside buffer xx x x 8000_0006h l2 tlb 3 cache information x x 8000_0007h amd powernow! technology x 4 4. low-power versions only embedded amd processor recognition 61 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information amds definition for subsequent cpuid functions and the registers returned for those functions. once the software identifies the processors vendor, it knows the definition for all the functions supplied by the cpuid instruction. by using these functions, the software obtains the processor information needed to properly tune its functionality to the capabilities of the processor. testing for extended functions software must test for extended functions with function 8000_0000h. the eax register returns the largest extended function input value defined for the cpuid instruction on the processor. if this value is at least 8000_0001h, extended functions are supported. with one exception, the amd extended feature flags include all the information provided in the standard feature flags as well as indicators for the additional amd processor-specific feature enhancements. the duplication of standard feature bits within the extended feature bits can minimize the number of function calls required by software. the exception is bit 11, which indicates that the sysenter and sysexit instructions are supported in the standard features and that the syscall and sysret instructions are supported in the extended features. determining the processor signature standard function 1 (eax=1) of the cpuid instruction returns the standard processor signature and feature bits. the standard processor signature is returned in the eax register and provides information regarding the specific revision (stepping) and model of the processor and the instruction family level supported by the processor. the revision level can be used to determine if the processor supports specific features. however, it is not recommended that the revision level be used in this manner unless this information is not available through the standard or extended feature bits. 62 embedded amd processor recognition embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information all amd-k6 processor models belong to instruction family 5 (as returned in eax by function 1). all amd athlon? processor models belong to instruction family 6 (as returned in eax by function 1). figure 29 shows the contents of the eax register obtained by function 1. table 29 summarizes the specific processor signature values returned for amd processors. figure 29. contents of eax register returned by function 1 instruction family 11C8 model 7C4 stepping 3C0 12 11 7 3 0 31 reserved 4 8 table 29. processor signatures for amd-k6? processors processor instruction family model stepping id 1 amd-k6e processor (model 7) 0101b (5h) 0111b (7h) xxxx amd-k6-2 processor (model 8) amd-k6-2e processor (model 8) 0101b (5h) 1 000b (8h) xxxx amd-k6- iii processor (model 9) 0101b (5h) 1001b (9h) xxxx amd-k6-2e+ processor (model d) amd-k6- iii e+ processor (model d) 0101b (5h) 1101b (dh) xxxx notes: 1. contact your amd representative for the latest stepping information. refer to table 1 on page 2 for the range of allowable step ping ids associated with each model number. embedded amd processor recognition 63 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information identifying supported features the feature bits are returned in the edx register for two cpuid functionsstandard function 1 and extended function 8000_0001h. each bit corresponds to a specific feature and indicates if that feature is present on the processor. table 30 summarizes the standard and extended feature bits. table 30. standard and extended feature bits bit 1 feature description standard 2 extended 2 0 floating-point unit a floating-point unit is available. 1 1 1 virtual mode extensions virtual mode extensions are available. 1 1 2 debugging extensions i/o breakpoint debug extensions are supported. 1 1 3 pse (page size extensions) 4-mbyte pages are supported. 1 1 4 time stamp counter (with rdtsc and cr4 disable bit) a time stamp counter is available in the processor, and the rdtsc instruction is supported. 11 5 k86? family of processors model-specific registers (with rdmsr and wrmsr) the k86 model-specific registers are available in the processor, and the rdmsr and wrmsr instructions are supported. 11 6 pae (page address extensions) page address extensions are supported using an 8-byte directory entry. 11 7 mce (machine check exception) the machine check exception is supported. 1 1 8 cmpxchg8b instruction the cmpxchg8b instruction is supported. 1 1 9 apic a local apic unit is available. 1 1 10 reserved on all amd processors 00 11 sysenter/sysexit instructions the sysenter and sysexit instructions are supported. 10 syscall and sysret instructions the syscall and sysret instructions and associated extensions are supported. 01 12 mtrr (memory type range registers) memory type range registers are available. 1 1 13 global paging extension global paging extensions are available. 1 1 14 mca (machine check architecture) machine check architecture is supported 1 1 15 conditional move instructions the conditional move instructions cmov, fcmov, and fcomi are supported. 11 16 pat (page attribute table) the page attribute tables are supported. 1 1 17 pse-36 (page size extension) page size extensions for 36-bit addresses are supported using a 4-byte directory entry. 11 18C21 reserved on all amd processors 00 22 amd multimedia instruction extensions amd additions to the original mmx? instruction set are supported. 3 01 64 embedded amd processor recognition embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information before using any of the enhanced features added to the latest generation of processors, software should test each feature bit returned by functions 1 and 8000_0001h to identify the capabilities available on the processor. for example, software must test feature bit 23 to determine if the processor executes the mmx technology instructions. attempting to execute an unavailable feature can cause errors and exceptions. bit 31, as returned by extended function 8000_0001h, designates the presence of 3dnow! technology. other processor vendors have adopted this technology, so bit 31 is now considered an open standard. appendix a on page 71, and appendix b on page 81 contain details on bit values. determining instruction set support it is preferable to use cpuid feature flags as much as possible, rather than deriving capabilities from vendor specifiers combined with cpuid model numbers. the amd-k6-2e+ and amd-k6-iiie+ processors add a new set of powerful extensions to the x86 instruction set3dnow! extensions. see the amd extensions to the 3dnow!? and mmx? instruction sets manual , order# 22466 for more information about these new instructions. 23 mmx? instructions the mmx instruction set is supported. 1 1 24 fxsave/fxrstor fast floating-point save and restore is supported. 1 1 25 streaming simd extensions (sse) streaming single instruction multiple data (simd) extensions (sse) are supported 00 26 reserved on all amd processors 00 30 amd 3dnow!? instruction extensions digital signal processing (dsp) extensions to the 3dnow! instruction set are supported. 3 01 31 amd 3dnow! instructions 3dnow! instructions are supported. 0 1 notes: 1. appendix a on page 71 contains details on bit values. 2. bit definitions: 0 = no support, 1 = support 3. for more information on these instructions, see the amd extensions to the 3dnow!? and mmx? instructions sets manual, order# 22466. table 30. standard and extended feature bits (continued) bit 1 feature description standard 2 extended 2 embedded amd processor recognition 65 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information detection algorithm for determining instruction set support to simplify the detection of the new instructions and the original 3dnow! and mmx instructions, use the following algorithm. a code sample using the cpuid instruction to identify the processor and its features is available from amds website at http://www.amd.com/products/cpg/bin. there are other ways to implement detection besides the way shown in the sample. cpuid test 1. establish that the processor has support for cpuid. see testing for the cpuid instruction on page 58. standard function test 2. execute cpuid function 0, which returns the processor vendor string and the highest standard function supported. save the vendor string for a later comparison. (see step 9.) 3. if step 2 indicates that the highest standard function is at least 1, execute cpuid function 1, which returns the standard feature flags in the edx register. mmx? test 4. if bit 23 of the standard feature flags is set to 1, mmx technology is supported. mmx instruction support is the basic minimum processor feature required to support other instruction extensions. optional sse test 5. optionally, if bit 25 of the standard feature flags is set, the processor has streaming single instruction multiple data (simd) extensions (sse) capabilities. further qualification of sse is done by checking for os support. sse support might be present in the processor, but not usable due to a lack of os support for the additional architected registers. extended functions test 6. execute cpuid extended function 8000_0000h. this function returns the highest extended function supported in eax. if eax=0, there is no support for extended functions. 7. if the highest extended function supported is at least 8000_0001h, execute cpuid function 8000_0001h. this function returns the extended feature flags in edx. 3dnow!? test 8. if bit 31 of the extended feature flags is set to 1, the 3dnow! instructions are supported. vendor check 9. if the previously saved vendor string (see step 2) contains authenticamd, continue on to the next step. 66 embedded amd processor recognition embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information 3dnow! extensions test 10. if bit 30 of the extended feature flags is set to 1, the additions to the 3dnow! instruction set are supported. amd multimedia instruction extensions test 11. if bit 22 of the extended feature flags is set to 1, the new multimedia enhancement instructions that augment the mmx instruction set are supported. amd processor signature (extended function) extended function 8000_0001h returns the embedded amd processor signature. the signature is returned in the eax register and provides generation, model, and stepping information for amd processors. figure 30 shows the contents returned in the eax register. figure 30. contents of eax register returned by extended function 8000_0001h displaying the processors name extended functions 8000_0002h, 8000_0003h, and 8000_0004h return an ascii string containing the name of the processor (also called the boot string or name string). these functions eliminate the need for software to search for the processor name in a lookup table, a process requiring a large block of memory and frequent updates. instead, software can simply call these three functions to obtain the name string (48 ascii characters in little-endian format) and display it on the screen. although the name string can be up to 48 characters in length, shorter names have the remaining byte locations filled with the ascii null character (00h). to simplify the display routines and avoid using screen space, software only needs to display characters until a null character is detected. 12 11 7 3 0 31 reserved 4 8 generation/family 11C8 model 7C4 stepping 3C0 embedded amd processor recognition 67 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information note: extended functions 8000_0002h, 8000_0003h, and 8000_0004h return an incorrect name string for the amd-k6-2e+ and amd-k6-iiie+ processors (model d). see functions 8000_0002h, 8000_0003h, and 8000_0004h processor name string on page 77 for more information. displaying cache information extended functions 8000_0005h and 8000_0006h provide cache information for the processor. some diagnostic software displays information about the system and the processors configuration. it is common for this type of software to provide cache size and organization information. functions 8000_0005h and 8000_0006h provide a simple way for software to obtain information about the on-chip caches and translation lookaside buffer (tlb) structures. the size and organization information is returned in the registers as described in appendix a on page 71. software can simply display these values, eliminating the need for large pieces of code to test the memory structures. determining amd powernow!? technology information extended function 8000_0007h provides information regarding the processors support for amd powernow! and its enhanced power management (epm) features. based on the status of the epm flags, software can determine if the processor supports programmable bus frequency control and programmable voltage id control. a 1 for each bit indicates that the feature is supported; however, the feature must be enabled by software. see function 8000_0007h amd powernow!? technology information on page 79 for more detailed bit descriptions. sample code a code sample using the cpuid instruction to identify the processor and its features is available from amds website at http://www.amd.com/products/cpg/bin. 68 new amd-k6? processor instructions embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information new amd-k6? processor instructions all models/steppings of the amd-k6 processor family implement the following new instruction set: n mmx? instructions57 new instructions for multimedia software. see the amd-k6? mmx? enhanced processor multimedia technology manual , order# 20726 for more information. all models/steppings of the amd-k6-2, amd-k6-2e, amd-k6-2e+, amd-k6-iii, and the amd-k6-iiie+ processors implement the following additional instructions: n 3dnow!? instructions21 new instructions for multimedia software. see the 3dnow!? technology manual , order# 21928 for more information. n syscall and sysret see the syscall and sysret instruction specification application note , order# 21086 for more information. (note that model 7 processors do not support these instructions.) the amd-k6-2e+ model d/[7:4] and the amd-k6-iiie+ model d/[3:0] processors implement the following additional instructions: n 3dnow!? instruction extensions5 new instructions for multimedia software. see the amd extensions to the 3dnow!? and mmx? instruction sets manual , order# 22466 for more information. additional considerations 69 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information additional considerations software timing dependencies relative to memory controller setup processors in the k86 family differ from other processors with regards to instruction latencies and the order or priority of processor bus cycles. timing-dependent software that relies on the specific latencies of other processors should be re-tested for proper operation with the k86 processor. in addition, re-testing should be performed on components with variable timing (such as memory modules, oscillators, and timers). particular attention should be paid to memory-setup subroutines that determine the type of dram in the system. some chipsets may not tolerate a dram mode change (such as, edo to sdram) on the same clock as a dram refresh cycle. for example some chipsets do not tolerate having its memory refresh enabled prior to changing memory mode types. refresh should only be enabled after the memory type has been determined. note: the bios for the k86 family of processors should enable the write allocate mechanisms only after performing any memory sizing or typing algorithms. pipelining support all production models and steppings of the amd-k6 processor support the waelim form of write allocate, which is the only form of write allocate that should be enabled. amd does not recommend enabling the obsolete form of write allocate (wcde) because system performance can be degraded by doing so. early implementations of the amd-k6 processor did not support the whcr register and therefore did not support the waelim form of write allocate. wcde was the only form of write allocate supported, which required the chipset to assert ken# for cacheable memory write cycles. because ken# is sampled by the processor on the clock edge on which the first brdy# or na# is sampled asserted, some chipsets that supported the wcde form of write allocate did not assert na# during write cycles in order to prevent the processor from 70 additional considerations embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information sampling ken# before it was valid (in this case, brdy# was used by the processor to sample ken#). if na# is not asserted during memory write cycles, then the processor does not fully take advantage of the potential performance gains that bus pipelining can achieve. for proper functionality, always program the wcde bit to 0 for models 7 and 8/[7:0]. models 8/[f:8], 9, and d do not support the wcde bit. read-only memory the processors caches must be flushed prior to defining any area of memory as cacheable and read-only. (the bios is typically shadowed into main memory and defined as cacheable and read-only.) if the caches are not flushed, then a line that resides in the processors cache that falls within a read- only area of memory can be written to, which would place the cache line in the modified state. if this modified line is subsequently replaced and written back to memory, then the system may hang (or other unpredictable effects may occur) because the writeback is directed to an area of memory defined as read-only by the chipset. appendix a 71 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information appendix a cpuid mnemonic opcode description cpuid 0f a2h identify the processor and its feature set privilege: none registers affected: eax, ebx, ecx, edx flags affected: none exceptions generated: none the cpuid instruction is an application-level instruction that software executes to identify the processor and its feature set. this instruction offers multiple functions, each providing a different set of information about the processor. the cpuid instruction can be executed from any privilege level. software can use the information returned by this instruction to tune its functionality for the specific processor and its features. beginning with the amd-k6e processor model 7, all amd processors support the cpuid instruction. however, it is still recommended that software verify that the cpuid instruction is supported. see testing for the cpuid instruction on page 58 for more information. the cpuid instruction supports multiple functions. the information associated with each function is obtained by executing the cpuid instruction with the function number in the eax register. functions are divided into two types: standard functions and extended functions. standard functions are found in the low function space, 0000_0000hC7fff_ffffh. in general, all x86 processors have the same standard function definitions. extended functions are defined specifically for processors supplied by the vendor listed in the vendor identification string. extended functions are found in the high function space, 8000_0000hC8fff_ffffh. because not all vendors have defined extended functions, software must test for their presence on the processor. 72 appendix a embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information standard functions function 0 largest standard function input value and vendor identification string input: eax = 0 output: eax = largest function input value recognized by the cpuid instruction ebx, edx, ecx = vendor identification string this is a standard function found in all processors implementing the cpuid instruction. it returns two values. the first value is returned in the eax register and indicates the largest standard function value recognized by the processor. the second value is the vendor identification string. this 12-character ascii string is returned in the ebx, edx, and ecx registers in little-endian format. amd processors return a vendor identification string of authenticamd as follows: software uses the vendor identification string as follows: n to identify the processor as an amd processor n to apply amds definition of the cpuid instruction for all additional function calls function 1 processor signature and standard feature flags input: eax = 1 output: eax = processor signature ebx = reserved ecx = reserved edx = standard feature flags function 1 returns two valuesthe processor signature and the standard feature flags. the processor signature is returned in the eax register and identifies the specific processor by providing information on its typeinstruction family, model, and revision (stepping). the information is formatted as follows: n eax[3C0] stepping id n eax[7C4] model n eax[11C8] instruction family n eax[31C12] reserved ebx edx ecx htua i tne dmac 68 74 75 41 69 74 6e 65 44 4d 41 63 appendix a 73 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information the standard feature flags are returned in the edx register and indicate the presence of specific features. in most cases, a 1 indicates the feature is present, and a 0 indicates the feature is not present. table 31 on page 74 contains a list of the currently defined standard feature flags for the amd-k6 family of processors. reserved bits will be used for new features as they are added. 74 appendix a embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information table 31. standard feature flag descriptions bit feature 1 notes: 1. bit definitions: 0 = no support, 1 = support. amd-k6e processor (model 7) amd-k6-2 & amd-k6-2e processors (model 8) amd-k6- iii processor (model 9) amd-k6-2e+ and amd-k6- iii e+ processors (model d) 0 floating-point unit 1 1 1 1 1 virtual mode extensions 1 1 1 1 2 debugging extensions 1 1 1 1 3 page size extensions (4-mbyte pages) 1 1 1 1 4 time stamp counter (with rdtsc and cr4 disable bit) 11 1 1 5 k86 family of processors model-specific registers (with rdmsr and wrmsr) 11 1 1 6 pae (page address extensions) 0 0 0 0 7 machine check exception 1 1 1 1 8 cmpxchg8b instruction 1 1 1 1 9 apic 0 0 0 0 10 reserved on all amd processors 00 0 0 11 sysenter/sysexit 0 0 0 0 12 memory type range registers 0 0 0 0 13 global paging extension 1 1 11 14 machine check architecture 0 0 0 0 15 conditional move instruction 0 0 0 0 16 pat (page attribute table) 0 0 0 0 17 pse-36 (page size extensions) 0 0 0 0 18C21 reserved on all amd processors 00 0 0 22 amd multimedia instruction extensions 0 0 0 0 23 mmx instructions 1 1 1 1 24 fxsave/fxrstor 0 0 0 0 25 streaming simd extensions (sse) 0 0 0 0 26C29 reserved on all amd processors 00 0 0 30 amd 3dnow! instruction extensions 0 0 0 1 31 amd 3dnow! instructions 1 1 1 1 appendix a 75 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information extended functions function 8000_0000h largest extended function input value input: eax = 8000_0000h output: eax = largest function input value recognized by the cpuid instruction ebx = reserved ecx = reserved edx = reserved function 8000_0000h returns a value in the eax register that indicates the largest extended function value recognized by the processor. function 8000_0001h amd processor signature and extended feature flags input: eax = 8000_0001h output: eax = amd processor signature ebx = reserved ecx = reserved edx = extended feature flags function 8000_0001h returns two valuesthe amd processor signature and the extended feature flags. the amd processor signature is returned in the eax register and identifies the specific processor by providing information regarding its typegeneration/family, model, and revision (stepping). the information is formatted as follows: n eax[3C0] stepping id n eax[7C4] model n eax[11C8] generation/family n eax[31C12] reserved the extended feature flags are returned in the edx register and indicate the presence of specific features found in amd processors. in most cases, a 1 indicates the feature is present, and a 0 indicates the feature is not present. table 32 on page 76 contains a list of the currently defined extended feature flags for the amd-k6 family of processors. reserved bits will be used for new features as they are added. 76 appendix a embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information table 32. extended feature flag descriptions bit feature 1 notes: 1. bit definitions: 0 = no support, 1 = support amd-k6e processor (model 7) amd-k6-2 and amd-k6-2e processors (model 8) amd-k6- iii processor (model 9) amd-k6-2e+ and amd-k6- iii e+ processors (model d) 0 floating-point unit 1 1 1 1 1 virtual mode extensions 1 1 1 1 2 debugging extensions 1 1 1 1 3 page size extensions (4-mbyte pages) 1 1 1 1 4 time stamp counter (with rdtsc and cr4 disable bit) 111 1 5 k86 family of processors model-specific registers (with rdmsr and wrmsr) 111 1 6 pae (page address extensions) 0 0 0 0 7 machine check exception 1 1 1 1 8 cmpxchg8b instruction 1 1 1 1 9 apic 0 0 0 0 10 reserved on all amd processors 000 0 11 syscall and sysret instructions 1 1 1 1 12 memory type range registers 0 0 0 0 13 global paging extension 1 1 1 1 14 machine check architecture 0 0 0 0 15 conditional move instruction 0 0 0 0 16 pat (page attribute table) 0 0 0 0 17 pse-36 (page size extensions) 0 0 0 0 18C21 reserved on all amd processors 000 0 22 amd multimedia instruction extensions 0 0 0 0 23 mmx instructions 1 1 1 1 24 fxsave/fxrstor 0 0 0 0 25 streaming simd extensions (sse) 0 0 0 0 26C29 reserved on all amd processors 000 0 30 amd 3dnow! instruction extensions 0 0 0 1 31 3dnow! instructions 1 1 1 1 appendix a 77 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information functions 8000_0002h, 8000_0003h, and 8000_0004h processor name string input: eax = 8000_0002h, 8000_0003h, or 8000_0004h output: eax = processor name string ebx = processor name string ecx = processor name string edx = processor name string functions 8000_0002h, 8000_0003h, and 8000_0004h each return part of the processor name string in the eax, ebx, ecx, and edx registers. these three functions use the four registers to return an ascii string of up to 48 characters in little endian format. for example, function 8000_0002h returns the first 16 characters of the processor name. the first character resides in the least significant byte of eax, and the last character (of this group of 16) resides in the most significant byte of edx. the null character (ascii 00h) is used to indicate the end of the processor name string. this feature is useful for processor names that require fewer than 48 characters. note: extended functions 8000_0002h, 8000_0003h, and 8000_0004h return an incorrect name string for the amd-k6-2e+ and amd-k6-iiie+ processors (model d). the returned name string should be amd-k6?-2+ for the amd-k6-2e+ processor and amd-k6?-iii+ for the amd-k6-iiie+ processor. however, the actual value returned for either processor is amd-k6?-iii. the amd cpuid utility v2.07 should be used to display the name string specified for amd-k6e, model d processors. this utility can be obtained from http: //www.amd.com/products/cpg/bin/amdcpuid.exe. feature bits returned by the standard and extended function calls of the cpuid instruction should still be used to determine the features and capabilities supported by the processor in use. 78 appendix a embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information f unction 8000_0005h l1 cache information input: eax = 8000_0005h output: eax = reserved ebx = tlb information ecx = l1 data cache information edx = l1 instruction cache information function 8000_0005h returns information about the processors on-chip l1 caches and associated tlbs. tables 33, 34, and 35 provide the format for the information returned by the 8000_0005h function. table 33. ebx format returned by function 8000_0005h data tlb instruction tlb associativity 1 notes: 1. see associativity for l1 caches and l1 tlbs on page 80 for more information. # entries associativity 1 # entries ebx bits 31C24 bits 23C16 bits 15C8 bits 7C0 table 34. ecx format returned by function 8000_0005h l1 data cache size (kbytes) associativity 1 notes: 1. see associativity for l1 caches and l1 tlbs on page 80 for more information lines per tag line size (bytes) ecx bits 31C24 bits 23C16 bits 15C8 bits 7C0 table 35. edx format returned by function 8000_0005h l1 instruction cache size (kbytes) associativity 1 notes: 1. see associativity for l1 caches and l1 tlbs on page 80 for more information. lines per tag line size (bytes) edx bits 31C24 bits 23C16 bits 15C8 bits 7C0 appendix a 79 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information function 8000_0006h l2 cache information this function is only available on amd-k6 processors models 9 and d. input: eax = 8000_0006h output: eax = reserved ebx = reserved ecx = l2 unified cache information edx = reserved function 8000_0006h returns information about the processors l2 cache. table 36 provides the format for the information returned by the 8000_0006h function. function 8000_0007h amd powernow!? technology information the amd powernow! technology function for enhanced power management is available on low-power versions of the amd-k6-2e+ and amd-k6-iiie+ processors, model d. input: eax = 8000_0007h output: eax = reserved ebx = reserved ecx = reserved edx = epm flags function 8000_0007h returns information about the processors amd powernow! technology support. table 37 provides the format for the information returned by the 8000_0007h function. table 36. ecx format returned by function 8000_0006h l2 cache size (kbytes) associativity 1 notes: 1. see associativity for l2 cache on page 80 for more information lines per tag line size (bytes) ecx bits 31C16 bits 15C12 bits 11C8 bits 7C0 table 37. edx format returned by function 8000_0007h amd powernow!? technology reserved voltage id control bus divisor control reserved edx 1 notes: 1. a 1 indicates the feature is present, however the feature must still be enabled by software. bits 31C3 bit 2 bit 1 bit 0 80 appendix a embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information cache associativity field definitions this section describes the values returned in the associativity fields. associativity for l1 caches and l1 tlbs the associativity fields for the l1 data cache, l1 instruction cache, l1 data tlb, and l1 instruction tlb are all 8 bits wide. except for 00h (reserved) and ffh (full), the number returned in the associativity field represents the actual number of ways, with a range of 01h through feh. for example, a returned value of 02h indicates 2-way associativity and a returned value of 04h indicates 4-way associativity. associativity for l2 cache the associativity field for the l2 cache is 4 bits wide. table 38 shows the value returned in the associativity field. table 38. associativity values for l2 cache bits 15C12 associativity 0000b l2 off 0001b direct-mapped 0010b 2-way 0011b reserved 0100b 4-way 0101b reserved 0110b 8-way 0111b reserved 1000b 16-way 1001b reserved 1010b reserved 1011b reserved 1100b reserved 1101b reserved 1110b reserved 1111b full appendix b 81 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information appendix b values returned by the cpuid instruction table 39 contains all the values returned for amd-k6 processors by the cpuid instruction. table 39. cpuid values returned by amd-k6? processors function register amd-k6e processor (model 7) amd-k6-2 & amd-k6-2e processors (model 8) amd-k6- iii processor (model 9) amd-k6-2e+ & amd-k6- iii e+ processors (model d) function: 0 eax ebx ecx edx 0000_0001h 6874_7541h 444d_4163h 6974_6e65h 0000_0001h 6874_7541h 444d_4163h 6974_6e65h 0000_0001h 6874_7541h 444d_4163h 6974_6e65h 0000_0001h 6874_7541h 444d_4163h 6974_6e65h function: 1 eax ebx ecx edx 0000_057xh reserved reserved 0080_01bfh 0000_058xh reserved reserved 0080_21bfh 0000_059xh reserved reserved 0080_21bfh 0000_05dxh reserved reserved 0080_21bfh function: 8000_0000h eax ebx ecx edx 8000_0005h reserved reserved reserved 8000_0005h reserved reserved reserved 8000_0006h reserved reserved reserved 8000_0007h 1 reserved reserved reserved function: 8000_0001h eax ebx ecx edx 0000_067xh reserved reserved 0080_05bfh 0000_068xh reserved reserved 8080_29bfh 0000_069xh reserved reserved 8080_29bfh 0000_06dxh reserved reserved c080_29bfh function: 8000_0002h eax ebx ecx edx 2d44_4d41h 6d74_364bh 202f_7720h 746c_756dh 2d44_4d41h 7428_364bh 3320_296dh 2 7270_2044h 2 2d44_4d41h 7428_364bh 3320_296dh 3 5020_2b44h 3 2d44_4d41h 7428_364bh 492d_296dh 6020_4949h 82 appendix b embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information function: 8000_0003h eax ebx ecx edx 6465_6d69h 6520_6169h 6e65_7478h 6e6f_6973h 7365_636f 2 h 0072_6f73 2 h 0000_0000h 0000_0000h 6563_6f72h 3 726f_7373h 3 0000_0000h 0000_0000h 6563_6f72h 726f_7373h 0000_0000h 0000_0000h function: 8000_0004h eax ebx ecx edx 0000_0073h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h function: 8000_0005h eax ebx ecx edx reserved 0280_0140h 2002_0220h 2002_0220h reserved 0280_0140h 2002_0220h 2002_0220h reserved 0280_0140h 2002_0220h 2002_0220h reserved 0280_0140h 2002_0220h 2002_0220h function: 8000_0006h eax ebx ecx edx undefined undefined undefined undefined undefined undefined undefined undefined reserved reserved 0100_4220h reserved reserved reserved 0xx0_4220h 4 reserved function: 8000_0007h eax ebx ecx edx undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined reserved reserved reserved 0000_0007h 1 notes: 1. low-power versions only. reserved on standard-power version. 2. extended functions 8000_0002h, 8000_0003h, and 8000_0004h each return part of the processor name string. some amd-k6-2e pro- cessors may have the following name string: function 8000_0002h, ecx = 322d_296dh and edx = 6f72_5020h, and function 8000_0003h, eax = 7373_6563h and ebx = 0000_726fh. 3. extended functions 8000_0002h, 8000_0003h, and 8000_0004h each return part of the processor name string. some amd-k6- iiie+ processors may have the following name string: function 8000_0002h, ecx = 492d_296dh and edx = 5020_4949h, and function 8000_0003h, eax = 6563_6f72h and ebx = 726f_7373h. 4. extended function 8000_0006h returns the processor l2 cache information. for the amd-k6-2e+ processor model d, ecx = 0080_4220h. for the amd-k6-iiie+ processor model d, ecx = 0100_4220h. table 39. cpuid values returned by amd-k6? processors (continued) function register amd-k6e processor (model 7) amd-k6-2 & amd-k6-2e processors (model 8) amd-k6- iii processor (model 9) amd-k6-2e+ & amd-k6- iii e+ processors (model d) 83 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information index a address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 amd powernow!? technology determining information . . . . . . . . . . . . . . . . . . . . . . . . . . 67 enabling epm features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 enhanced power management register (epmr) . . . . . . . 54 epm 16-byte i/o block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 epm stop grant clock control state . . . . . . . . . . . . . . . . . . 55 amd processor signature . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 amd-k6? processor family features (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 model-specific register (msr) differences (table) . . 14C15 amd-k6?-2 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 model-specific registers supported (table). . . . . . . . . 17, 23 amd-k6?-2e embedded processor . . . . . . . . . . . . . . . . . . . . 4 model-specific registers supported (table). . . . . . . . . . . . 23 amd-k6?-2e+ embedded processor . . . . . . . . . . . . . . . . . . . 4 model-specific registers supported (table). . . . . . . . . . . . 45 amd-k6?e embedded processor . . . . . . . . . . . . . . . . . . . . . 3 model-specific registers supported (table). . . . . . . . . . . . 17 amd-k6?-iii processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 model-specific registers supported (table). . . . . . . . . . . . 38 amd-k6?-iiie+ embedded processor. . . . . . . . . . . . . . . . . . 5 model-specific registers supported (table). . . . . . . . . . . . 45 associativity field definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 l1 caches and l1 tlbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 l2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 l2 cache values (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 authenticamd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60, 65, 72 b bdc field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 bf field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 bf signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 bios considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 bios boot strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 bus divisor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 cache invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 cpu speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 cpuid instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 displaying processor name . . . . . . . . . . . . . . . . . . . . . . . . . 66 efer recommended setting . . . . . . . . . . . . . . . . . . . . . . . 26 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . 6 shadowed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 smm issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 voltage id control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 write allocate limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 write allocate mechanisms. . . . . . . . . . . . . . . . . . . . . . . . . 69 bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 brdy# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bus divisor and vid change mode bit. . . . . . . . . . . . . . . . . 56 bus divisor and voltage id control bit . . . . . . . . . . . . . . . . 55 bus divisor control field . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 bus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 bvc field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 bvcm bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 c cache associativity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 associativity values for l2 cache (table) . . . . . . . . . . . . . 80 displaying information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 l2 tag writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43, 53 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 cache inhibit bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 cd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 ci bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 cli instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 cmov instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 cmpxchg8b instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 cpuid instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 6, 65, 71 eflags id-bit test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 flow chart (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 functions in embedded amd processors (table) . . . . . . . 60 identification algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . 11 illegal instruction exception test . . . . . . . . . . . . . . . . . . . . 58 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 values returned (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 cr0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 cr4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 e eas register time stamp counter value . . . . . . . . . . . . . . . . . . . . . . . . . . 16 eax register bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 extended function 8000_0001h (figure) . . . . . . . . . . . . . . 66 function 1 (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 l2 tag information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43, 52 ebf field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ebx register function 8000_0005h (table) . . . . . . . . . . . . . . . . . . . . . . . .78 ecx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 function 8000_0005h (table) . . . . . . . . . . . . . . . . . . . . . . . .78 function 8000_0006h (table) . . . . . . . . . . . . . . . . . . . . . . . .79 msr selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 edx register cache access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 extended feature flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 function 8000_0005h (table) . . . . . . . . . . . . . . . . . . . . . . . .78 function 8000_0007h (table) . . . . . . . . . . . . . . . . . . . . . . . .79 ignored fields during l2 tag access . . . . . . . . . . . . . . . . . . 42 l2 tag or data location . . . . . . . . . . . . . . . . . . . . . . . . . 41, 50 standard feature flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 time stamp counter value . . . . . . . . . . . . . . . . . . . . . . . . . . 16 effective bus frequency divisor field . . . . . . . . . . . . . . . . . 47 eflags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 eip address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 en bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 enable amd powernow! technology management bit . . . . 54 enhanced power management. . . . . . . . . . . . . . . . . . . . . . . .79 determining information . . . . . . . . . . . . . . . . . . . . . . . . . . 67 enabling epm features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 enhanced power management register (epmr) . . . . . . . . 54 epm 16-byte i/o block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 epm stop grant clock control state . . . . . . . . . . . . . . . . . . 55 ewbe# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24C26 extended feature enable register (efer) ewbec settings (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 model 8 ? [f:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 models 7 and 8 ? [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 models 9 and d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 extended features flag descriptions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 standard and extended feature bits (table) . . . . . . . . . . . 63 extended functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 84 embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information f f/i bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 fcmov instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 fcomi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 floating-point state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flush# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flush/invalidate command bit . . . . . . . . . . . . . . . . . . . . . . . 37 g generate special bus cycle bit . . . . . . . . . . . . . . . . . . . . . . . 54 generation/family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 gsbc bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 i i/o base address field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 i/o trap dword configuration at offset ffa4h (table). . . . . . . . . . . . . . . . 13 differences in amd-k6? processors . . . . . . . . . . . . . . . . 13 ibf field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 id bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 init signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8C9 inquire cycles not supported during epm stop grant state. . . . . . . . . . . 55 instructions 3dnow! extensions test . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3dnow! test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 cli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 cpuid test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 determining supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 extended functions test . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62, 72 illegal exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 latencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 mmx extensions test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 mmx test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 new . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 popfd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 pushfd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 rdmsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 rdtsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 sse test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 standard function test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 sti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 syscall. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 sysenter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sysexit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sysret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15, 22 trapped i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 vendor check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 wbinvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 wrmsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 internal bf divisor field . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 iobase field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 k ken# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 l l1 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 l2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 associativity values (table) . . . . . . . . . . . . . . . . . . . . . . . . 80 data in eax (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42, 51 organization (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . 40, 48 sector and line organization (figure) . . . . . . . . . . . . . 41, 49 tag information in eax . . . . . . . . . . . . . . . . . . . . . . . . 43, 52 tag or data location in edx . . . . . . . . . . . . . . . . . . . . . 41, 50 tag writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43, 53 level-2 cache array access register (l2aar) model 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 model d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 linear page address field . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 linpage field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 lru byte (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43, 53 m machine check exception (mce) bit . . . . . . . . . . . . . . . . . . 16 machine-check address register (mcar). . . . . . . . . . . . . . 16 machine-check type register (mctr). . . . . . . . . . . . . . . . . 16 memory dram mode changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 range restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 refresh enabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 setup subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30C31 uncacheable (uc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 valid masks and range sizes (table) . . . . . . . . . . . . . . . . . 32 write-combining (wc). . . . . . . . . . . . . . . . . . . . . . . . . . 30C31 memory type range registers (mtrrs) . . . . . . . . . . . . . . . 30 model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72, 75 model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 model 8 ? [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 model 8 ? [f:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 model 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 model d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . 6, 14 amd-k6? family msr differences (table) . . . . . . . . 14C15 amd-k6?-2 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 amd-k6?-2e processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 amd-k6?-2e+ processor . . . . . . . . . . . . . . . . . . . . . . . . . . 45 amd-k6?e processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 amd-k6?-iii processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 amd-k6?-iiie+ processor . . . . . . . . . . . . . . . . . . . . . . . . . 45 enhanced power management register (epmr) . . . . . . . 54 extended feature enable register (efer) . . . . . .18, 24, 39 level-2 cache array access register (l2aar) . . . . . . . 40, 48 machine-check address register (mcar) . . . . . . . . . . . . .16 machine-check type register (mctr) . . . . . . . . . . . . . . . . 16 model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 model 8 ? [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 model 8 ? [f:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 model 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 model d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 page flush/invalidate register (pfir) . . . . . . . . . . . . . . . . 36 processor state observability register (psor) . . . 34, 40, 46 standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 syscall/sysret target address register (star) . . . . 22 test register 12 (tr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . 16 uc/wc cacheability control register (uwccr) . . . . . . . 30 write handling control register (whcr) . . . . . . . . . .19, 27 msr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 mtrr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mtrr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 n na# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 name string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 nol2 bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 nw bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 o operating frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 out-of-order write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 85 23913A/0november 2000 embedded amd-k6? processors bios design guide preliminary information p page flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 page flush/invalidate register (pfir) models 8 ? [f:8], 9, and d . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 pbf field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 performance ewbec field settings (table) . . . . . . . . . . . . . . . . . . . . . . 26 l2 cache disable setting . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 merging multiple write cycles . . . . . . . . . . . . . . . . . . . . . . 30 tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11, 57 write allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 write ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25C26 pf bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 physical address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 pin bus frequency divisor field . . . . . . . . . . . . . . . . . . . . . . 46 pipelining support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 write allocation methods . . . . . . . . . . . . . . . . . . . . . . . . . . 69 popfd instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 post routine vidc bit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 processor bios boot strings . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 11, 66 bus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 determining signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 displaying name . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 11, 66 extended functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 identifying supported features . . . . . . . . . . . . . . . . . . . . . 63 identifying vendor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 name string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 recognition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 signature (extended function) . . . . . . . . . . . . . . . . . . . 66, 75 signature (standard function) . . . . . . . . . . . . . . . . . . . . . . 72 signatures for embedded amd processors (table) . . . . . 62 speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 standard functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 state after init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 state after reset (table) . . . . . . . . . . . . . . . . . . . . . . . . 8C9 steppings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 processor state observability register (psor) model d low-power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 models 8 ? [f:8], 9, and standard-power d . . . . . . . . . . . . . 34 processor-to-bus clock ratios model d low-power (table) . . . . . . . . . . . . . . . . . . . . . . . . . 47 model d standard-power (table) . . . . . . . . . . . . . . . . . . . . 35 models 8 ? [f:8]) and 9 (table) . . . . . . . . . . . . . . . . . . . . . . . 35 pushfd instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 r rdmsr instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14, 16 l2 tag or data selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 rdtsc instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 read-only memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 registers enhanced power management (epmr) . . . . . . . . . . . . . . 54 extended feature enable (efer) . . . . . . . . . . . . . 18, 24, 39 level-2 cache array access (l2aar) . . . . . . . . . . . . . . 40, 48 machine-check address (mcar) . . . . . . . . . . . . . . . . . . . . 16 machine-check type (mctr) . . . . . . . . . . . . . . . . . . . . . . . 16 page flush/invalidate (pfir) . . . . . . . . . . . . . . . . . . . . . . . 36 processor state observability (psor) . . . . . . . . . . 34, 40, 46 states after reset and init. . . . . . . . . . . . . . . . . . . . . . . . 8 syscall/sysret target address (star) . . . . . . . . . . . 22 test 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . 16 uc/wc cacheability control (uwccr) . . . . . . . . . . . . . . 30 write handling control (whcr) . . . . . . . . . . . . . . . . . 19, 27 reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 34 reset state model 8/[f:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 models 7 and 8 ? [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 models 9 and d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 s sgtc field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 smi# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 13 snoop cycles not supported during epm stop grant state . . . . . . . . . . . 55 software memory controller setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timing dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 special bus cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 standard features flag descriptions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 standard and extended feature bits (table) . . . . . . . . . . .63 standard functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 state-save map differences . . . . . . . . . . . . . . . . . . . . . . . . . . 13 step field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 stepping id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72, 75 sti instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 stop grant time-out counter field . . . . . . . . . . . . . . . . . . . . 56 streaming simd extensions (sse) . . . . . . . . . . . . . . . . . . . . 65 syscall instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 22 syscall/sysret target address register (star) models 8 ? [f:8], 9, and d. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 sysenter instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sysexit instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sysret instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18, 22 system management mode (smm) . . . . . . . . . . . . . . . . . . . . 13 i/o trap dword differences . . . . . . . . . . . . . . . . . . . . . . . . . 13 issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 state-save map differences . . . . . . . . . . . . . . . . . . . . . . . . . 13 t test register 12 (tr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 u uc/wc cacheability control register (uwccr) model 8 ? [f:8], 9, and d . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 valid masks and range sizes (table) . . . . . . . . . . . . . . . . . . 32 uncacheable (uc) memory . . . . . . . . . . . . . . . . . . . . . . . . . . 30 v vendor identification string . . . . . . . . . . . . . . . . . . . . . . . . . 72 vid field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 vid[4:0] outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 vidc bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 vido field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 voltage id control bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 voltage id output field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 w wae15m bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 waelim field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 69 wbinvd instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 wc/uc memory type for uwccr register (table) . . . . . . 31 wcde bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 write allocation methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 waelim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 wcde . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 86 embedded amd-k6? processors bios design guide 23913A/0november 2000 preliminary information write cycles out-of-order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 write handling control register (whcr) models 7 and 8 ? [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 models 8 ? [f:8], 9, and d . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24C25 write-combining (wc) memory . . . . . . . . . . . . . . . . . . . 30C31 wrmsr instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14, 16 l2 tag or data selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 page flush/invalidate register (pfir) . . . . . . . . . . . . . . . . 36 |
Price & Availability of 23913A
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