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W181
Peak-Reducing EMI Solution
Features
* Cypress PREMISTM family offering * Generates an EMI optimized clocking signal at the output * Selectable input to output frequency * Single 1.25% or 3.75% down or center spread output * Integrated loop filter components * Operates with a 3.3V or 5V supply * Low-power CMOS design * Available in 8-pin small outline integrated circuit (SOIC) or 14-pin thin shrink small outline package (TSSOP select options only)
Simplified Block Diagram
3.3 or 5.0V
Pin Configurations
SOIC W181-01/51 CLKIN or X1 NC or X2 GND SS% 1 2 3 4 8 7 6 5 FS2 FS1 VDD CLKOUT
X1 XTAL Input X2
40 MHz Max.
W181
Spread Spectrum Output (EMI suppressed)
CLKIN or X1 NC or X2 GND 3.3 or 5.0V SS%
1 2 3 4
8 7 6 5
SSON# FS1 VDD CLKOUT
TSSOP FS2 CLKIN or X1 Oscillator or Reference Input 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC NC FS1 NC VDD NC CLKOUT
W181-02/03 W181-52/53 W181-01
W181
Spread Spectrum Output (EMI suppressed)
NC or X2 GND NC SS% NC
Cypress Semiconductor Corporation Document #: 38-07152 Rev. *D
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised July 06, 2004
W181
Pin Definitions
Pin Name CLKOUT CLKIN or X1 Pin No. (SOIC) 5 1 Pin No. (TSSOP)(-01) 8 2 Pin Type O I Pin Description Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock (SSON# asserted). Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection: If using an external reference, this pin must be left unconnected. Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Frequency Selection Bit(s) 1 and 2: These pins select the frequency range of operation. Refer to Table 2. These pins have internal pull-up resistors. Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. This pin has an internal pull-up resistor. Power Connection: Connected to 3.3V or 5V power supply. Ground Connection: Connect all ground pins to the common system ground plane. No Connection
NC or X2 SSON#
2 8(02/03/52/53)
3 --
I I
FS1:2
7, 8 (01/51)
12, 1
I
SS%
4
6
I
VDD GND NC
6 3
10 4 5, 7, 9, 11, 13, 14
P G NC
Key Specifications
Supply Voltages: .........................................VDD = 3.3V 5% .................................................................or VDD = 5V 10% Frequency Range: ............................ 28 MHz Fin 75 MHz Crystal Reference Range.................. 28 MHz Fin 40 MHz Cycle to Cycle Jitter: ....................................... 300 ps (max.) Selectable Spread Percentage: ................... 1.25% or 3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time: .................................. 5 ns (max.) Table 1. Modulation Width Selection SS% 0 1 W181-01, 02, 03 Output W181-51, 52, 53 Output -1.25% (Down Spread) -3.75% (Down Spread) 0.625 (Center Spread) 1.875% (Center Spread)
Overview
The W181 products are one series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple implementation.
Functional Description
The W181 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. (Note: For the W181 the output frequency is equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Page 2 of 9
Table 2. Frequency Range Selection W181 Option# FS2 0 0 1 1 FS1 0 1 0 1 -01, 51 (MHz) 28 FIN 38 38 FIN 48 46 FIN 60 58 FIN 75 -02, 52 (MHz) 28 FIN 38 38 FIN 48 N/A N/A -03, 53 (MHz) N/A N/A 46 FIN 60 58 FIN 75
Document #: 38-07152 Rev. *D
W181
Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied.
VDD Clock Input Reference Input Freq. Divider Q Phase Detector Charge Pump
Using frequency select bits (FS1:2 pins), the frequency range can be set. Spreading percentage is set to be 1.25% or 3.75% (see Table 1). A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common.
Modulating Waveform
VCO
Post Dividers
CLKOUT (EMI suppressed)
Feedback Divider P
PLL
GND
Figure 1. Functional Block Diagram
Spread Spectrum Frequency Timing Generation
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2. As shown in Figure 2, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in Figure 3. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. Figure 3 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices.
Document #: 38-07152 Rev. *D
Page 3 of 9
W181
EMI Reduction
SSFTG
Typical Clock
Amplitude (dB)
Amplitude (dB)
Spread Spectrum Enabled
NonSpread Spectrum
Frequency Span (MHz) Center spread
Frequency Span (MHz) Down Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
10%
20%
30%
40%
50%
60%
70%
80%
100%
90%
MIN.
Figure 3. Typical Modulation Profile
Document #: 38-07152 Rev. *D
100%
Page 4 of 9
W181
.
Absolute Maximum Conditions[2]
Parameter VDD, VIN TSTG TA TB PD Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W
DC Electrical Characteristics: 0C < TA < 70C, VDD = 3.3V 5%
Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI CI RP ZOUT Description Supply Current Power-Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Capacitance Input Pull-Up Resistor[3] Clock Output Impedance Note 3 Note 3 @ 0.4V, VDD = 3.3V @ 2.4V, VDD = 3.3V All pins except CLKIN CLKIN pin only First locked clock cycle after Power Good Test Condition Min. - - - 2.4 - 2.4 - - - - - - - - Typ. 18 - - - - - - - 15 15 v 6 500 25 Max. 32 5 0.8 - 0.4 - -100 10 - - 7 10 - - Unit mA ms V V V V A A mA mA pF pF k
DC Electrical Characteristics: 0C < TA < 70C, VDD = 5V 10%
Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI CI RP Description Supply Current Power-Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Capacitance Input Pull-Up Resistor Note 3 Note 3 @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V All pins except CLKIN CLKIN pin only 6 500 24 24 7 10 2.4 -100 10 0.7VDD 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 30 Max. 50 5 0.15VDD Unit mA ms V V V V A A mA mA pF pF k
Notes: 1. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability 2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. 3. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
Document #: 38-07152 Rev. *D
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W181
AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V 5% or 5V10%
Parameter fIN fOUT tR tF tOD tID tJCYC Description Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Harmonic Reduction fout = 40 MHz, third harmonic measured, reference board, 15-pF load 8 Test Condition Input Clock Spread Off VDD, 15-pF load 0.8V-2.4V VDD, 15-pF load 2.4V-0.8V 15-pF load 40 40 250 Min. 28 28 2 2 Typ. Max. 75 75 5 5 60 60 300 Unit MHz MHz ns ns % % ps dB
CLKOUT Frequency Offset (Shift)[4,5]: TA = 0C to +70C, VDD = 3.3V 5% or 5V10% (For only W181-02, -02 and -03 products)
Parameter FOFFSET-1 FOFFSET-2 FOFFSET-3 FOFFSET-4 Description Frequency Offset (Shift) Frequency Offset (Shift) Frequency Offset (Shift) Frequency Offset (Shift) Frequency Range (MHz) FS2=0, FS1=0, 28FIN38 FS2=0, FS1=1, 38FIN48 FS2=1, FS1=0, 46FIN60 FS2=1, FS1=1, 58FIN75 Min. -0.8 -1.1 -0.2 -0.8 Typ. -1.0 -1.4 -0.5 -1.0 Max. -1.2 -1.7 -0.8 -1.2 Unit % % % %
Application Information
Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-F decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the
increased trace inductance will negate its decoupling capability. The 10-F decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Recommended Board Layout Figure 5 shows a recommended 2-layer board layout.
Reference Input NC GND
1 W181 2 3 4
8 7 6 5
R1 Clock Output C1 0.1 F
3.3 or 5V System Supply
FB
C2 10-F Tantalum
Figure 4. Recommended Circuit Configuration
Notes: 4. The frequency offset (shift) is given with respect to ideal peak value which is the same as input reference frequency in the case of down spread only for W180-01,-02 and -03 products. 5. There is no offset (shift) for center spread for W180-51,-52 and -53 products.
Document #: 38-07152 Rev. *D
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W181
C1 = C2 = High frequency supply decoupling capacitor (0.1-F recommended). Common supply low frequency decoupling capacitor (10-F tantalum recommended). Match value to line impedance Ferrite Bead Via To GND Plane
R1 = FB Reference Input NC =
=
G C1 G G
Clock Output R1
G
Power Supply Input (3.3 or 5V) FB
C2
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code W181-01G W181-01GT W181-02G W181-02GT W181-03G W181-03GT W181-51G W181-51GT W181-52G W181-52GT W181-53G W181-53GT W181-01X W181-01XT Lead-free Devices CYW181-01SX CYW181-01SXT CYW181-02SX CYW181-02SXT CYW181-03SX CYW181-03SXT CYW181-51SX CYW181-51SXT CYW181-52SX CYW181-52SXT CYW181-53SX CYW181-53SXT 8 pin Plastic SOIC (150-mil) 8-pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil) 8-pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil) 8 pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil)) 8-pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil) 8-pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil) 8 pin Plastic SOIC (150-mil) - Tape and Reel Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Page 7 of 9 Package Type 8-pin Plastic SOIC (150-mil) 8-pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil) 8-pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil 8-pin Plastic SOIC (150-mil) - Tape and Reel 8-pin Plastic SOIC (150-mil) 8-pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil) 8-pin Plastic SOIC (150-mil) - Tape and Reel 8 pin Plastic SOIC (150-mil 8-pin Plastic SOIC (150-mil) - Tape and Reel 14-pin Plastic TSSOP 14-pin Plastic TSSOP - Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
Document #: 38-07152 Rev. *D
W181
Package Drawing and Dimension
14-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z14
PIN 1 ID
1
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
DIMENSIONS IN MM(INCHES)
14
0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 0-8
51-85117-*A
8 Lead (150 Mil) SOIC - S08 (150-Mil) SOIC S8 8-lead
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
PREMIS is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07152 Rev. *D Page 8 of 9
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W181
Document History Page
Document Title: W181 Peak Reducing EMI Solution Document Number: 38-07152 REV. ** *A *B Orig. of ECN No. Issue Date Change 110262 122687 127906 12/15/01 12/27/02 07/07/03 SZV RBI IJA Description of Change Change from Spec number: 38-00790 to 38-07152 Added power up requirements to maximum ratings information. Changed Modulation Width Selection values in Table 1 Added CLKOUT Frequency Offset Table Created Cypress approved drawings to replace old ones Updated Ordering Information to clarify and match ordering codes to Dev Master Added Lead-free for all the SOIC packages in the ordering information Corrected the Lead Free Coding in the Ordering Information table
*C *D
131492 241879
01/22/04 See ECN
RGL RGL
Document #: 38-07152 Rev. *D
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