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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-10174-3E
MEMORY
CMOS 1M x 4 BIT FAST PAGE MODE DYNAMIC RAM
MB81V4400C-60/-70
CMOS 1,048,576 x 4 BIT Fast Page Mode Dynamic RAM s DESCRIPTION
The Fujitsu MB81V4400C is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory cells accessible in 4-bit increments. The MB81V4400C features a "fast page" mode of operation whereby highspeed random access of up to 1,024 x 4-bits of data within the same row can be selected. The MB81V4400C DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. Since the standby current of the MB81V4400C is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. The MB81V4400C is fabricated using silicon gate CMOS and Fujitsu's advanced four-layer polysilicon process. This process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for the MB81V4400C are not critical and all inputs are LVTTL compatible.
s PRODUCT LINE & FEATURES
Parameter RAS Access Time CAS Access Time Address Access Time Random Cycle Time Fast Page Mode Cycle Time Low power Dissipation * * * * * Operating current Standby current MB81V4400C-60 MB81V4400C-70 60 ns max. 70 ns max. 15 ns min. 20 ns min. 30 ns max. 35 ns max. 110 ns max. 125 ns max. 40 ns min. 45 ns min. 220 mW max. 195 mW max. 7.2 mW max. (LVTTL level)/3.6 mW max. (CMOS level) * * * * Early write or OE controlled write capability RAS-only, CAS-before-RAS, or Hidden Refresh Fast page Mode, Read-Modify-Write Capability On chip substrate bias generator for high Performance
1,048,576 words x 4 bit organization Silicon gate, CMOS, 3D-Stacked Capacitor Cell All input and output are LVTTL compatible 1024 refresh cycles every 16.4 ms Self refresh function
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
1
MB81V4400C-60/MB81V4400C-70
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage at any pin relative to VSS Voltage of VCC supply relative to VSS Power Dissipation Short Circuit Output Current Storage Temperature Symbol VIN, VOUT VCC PD IOUT TSTG Value -0.5 to +4.6 -0.5 to +4.6 1.0 -55 to +50 -55 to +125 Unit V V W mA C
WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
s PACKAGE
Marking side
Marking side
Plastic TSOP Package (FPT-26P-M01) (Normal Bend)
Plastic TSOP Package (FPT-26P-M02) (Reverse Bend)
Package and Ordering Information - 26-pin plastic (300 mil) TSOP-II with normal bend leads, order as MB81V4400C-xxPFTN - 26-pin plastic (300 mil) TSOP-II with reverse bend leads, order as MB81V4400C-xxPFTR
2
MB81V4400C-60/MB81V4400C-70
Fig. 1 - MB81V4400C DYNAMIC RAM - BLOCK DIAGRAM
RAS CAS
Clock Gen #1 Write Clock Gen Mode Control
WE
Clock Gen #2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
Refresh Address Counter Substrate Bias Gen Address Buffer & PreDecoder Row Decoder * * * Column Decoder Sense Ampl & I/O Gate * * *
Data In Buffer
DQ1 to DQ4
4,194,304 Bit Storage Cell
Data Out Buffer
OE VCC VSS
s CAPACITANCE
(TA = 25C, f = 1 MHz)
Parameter Input Capacitance, A0 toA9 Input Capacitance, RAS, CAS, WE, OE Input/Output Capacitance, DQ1 to DQ4
Symbol CIN1 CIN2 CDQ
Typ. -- -- --
Max. 5 7 7
Unit pF pF pF 3
MB81V4400C-60/MB81V4400C-70
s PIN ASSIGNMENTS AND DESCRIPTIONS
26-Pin TSOP: (TOP VIEW) DQ1 DQ2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 VSS DQ4 DQ3 CAS OE 26-Pin TSOP: (TOP VIEW) VSS DQ4 DQ3 CAS OE 26 25 24 23 22 1 2 3 4 5 DQ1 DQ2 WE RAS A9
A0 A1 A2 A3 VCC
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
A8 A7 A6 A5 A4
18 17 16 15 14
9 10 11 12 13
A0 A1 A2 A3 VCC
Designator DQ1 to DQ4 WE RAS A0 to A9 VCC OE CAS VSS
Function Data Input/Output. Write Enable. Row address strobe. Address inputs. +3.3 volt power supply Output enable. Column address strobe. Circuit ground.
4
MB81V4400C-60/MB81V4400C-70
s RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs* Notes 1 1 1 Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 -0.3 Typ. 3.3 0 -- -- Max. 3.6 0 VCC + 0.3 0.8 Unit V V V 0C to +70C Ambient Operating Temp
* : Undershoots of up to -2.0 volts with a pulse width not exceeding 20 ns are acceptable.
s FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty input bits are required to decode any four of 4,194,304 cell addresses in the memory matrix. Since only ten address bits are available, the column and row inputs are separately strobed by CAS and RAS as shown in Figure 5. First, ten row address bits are input on pins A0-through-A9 and latched with the row address strobe (RAS) then, ten column address bits are input and latched with the column address strobe (CAS). Both row and column addresses must be stable on or before the falling edge of CAS and RAS, respectively. The flow-through latch type is used for the address latch; thus, address information appearing after tRAH (min.)+ tT is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways-an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data (DQ1-DQ4) is strobed by CAS and the setup/hold times are referenced to the falling edge of CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the falling edge of WE.
DATA OUTPUT
The three-state buffers are LVTTL compatible with a fanout of one TTL loads. Polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: tRAC : from the falling edge of RAS when tRCD (max.) is satisfied. tCAC : from the falling edge of CAS when tRCD is greater than tRCD (max.). tAA : from column address input when tRAD is greater than tRAD (max.). tOEA : from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA. The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the output buffers remain in a high-impedance state during the entire cycle.
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each fast page of memory, any of 1,024 x 4-bits can be accessed and, when multiple MB81V4400Cs are used, CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read, write, and/or ready-modify-write cycles are permitted. 5
MB81V4400C-60/MB81V4400C-70
s DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter Output high voltage Output low voltage Notes 1 1 Symbol VOH VOL Conditions IOH = -2 mA IOL = 2 mA 0 V VIN 3.6 V 3.0 V VCC 3.6 V VSS = 0 V; All other pins not under test = 0 V 0 V VOUT 3.6 V Data out disabled RAS & CAS cycling; tRC = min. RAS = CAS = VIH ICC2 CMOS level MB81V4400C-60 ICC3 2 MB81V4400C-70 MB81V4400C-60 2 ICC4 MB81V4400C-70 MB81V4400C-60 ICC5 2 MB81V4400C-70 MB81V4400C-60 ICC9 MB81V4400C-70 RAS = CAS VCC -0.2 V CAS = VIH, RAS cycling; tRC = min. -- -- 1.0 61 -- -- 54 41 -- -- 37 49 -- -- 44 1000 -- -- 1000 A mA mA mA
Notes 3
Values Min. 2.4 -- Typ. -- -- Max. -- V 0.4 Unit
Input leakage current (any input)
II(L)
-10
--
10 A
Output leakage current Operating current (Average Power supply current) Standby current (Power supply current) Refresh current#1 (Average power supply current) Fast Page Mode current Refresh current#2 (Average power supply current) Refresh current#3 (Average power supply current) MB81V4400C-60
IO(L)
-10
--
10 61
ICC1 2 MB81V4400C-70 LVTTL level
--
-- 54 2.0
mA
mA
RAS = VIL, CAS cycling; tPC = min. RAS cycling; CAS-before-RAS; tRC = min. RAS = CAS 0.2 V Self refresh;
6
MB81V4400C-60/MB81V4400C-70
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Parameter Time Between Refresh Random Read/Write Cycle Time Read-Modify-Write Cycle Time Access Time from RAS Access Time from CAS Column Address Access Time Output Hold Time Output Buffer Turn On Delay Time Output Buffer Turn off Delay Time Transition Time RAS Precharge Time RAS Pulse Width RAS Hold Time CAS to RAS Precharge Time RAS to CAS Delay Time CAS Pulse Width CAS Hold Time CAS Precharge Time (Normal) Row Address Set Up Time Row Address Hold Time Column Address Set Up Time Column Address Hold Time RAS to Column Address Delay Time Column Address to RAS Lead Time Column Address to CAS Lead Time Read Command Set Up Time Read Command Hold Time Referenced to RAS Read Command Hold Time Referenced to CAS Write Command Set Up Time Write Command Hold Time WE Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time 13 19 11, 12 10 6, 9 7, 9 8, 9 Notes Symbol tREF tRC tRWC tRAC tCAC tAA tOH tON tOFF tT tRP tRAS tRSH tCRP tRCD tCAS tCSH tCPN tASR tRAH tASC tCAH tRAD tRAL tCAL tRCS 14 14 15 tRRH tRCH tWCS tWCH tWP tRWL tCWL
Notes 3, 4, 5
MB81V4400C-70 Min. Max. -- 16.4 125 -- 170 -- -- -- -- 0 0 -- 2 45 70 20 0 20 20 70 10 0 10 0 12 15 35 35 0 0 0 0 10 10 18 18 70 20 35 -- -- 15 50 -- 100000 -- -- 50 10000 -- -- -- -- -- -- 35 -- -- -- -- -- -- -- -- -- -- Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MB81V4400C-60 Min. Max. -- 16.4 110 -- 150 -- -- -- -- 0 0 -- 2 40 60 15 0 20 15 60 10 0 10 0 12 15 30 30 0 0 0 0 10 10 15 15 60 15 30 -- -- 15 50 -- 100000 -- -- 45 10000 -- -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- --
7
MB81V4400C-60/MB81V4400C-70
s AC CHARACTERISTICS (Continued)
(At recommended operating conditions unless otherwise noted.)
No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Parameter Notes Symbol tDS tDH tRWD tCWD tAWD tRPC tCSR tCHR tWSR tWHR tOEA tOEZ tOEL 16 tOEH tOED 17 17 tDZC tDZO tPC tPRWC tCPA tCP tRASP tRHCP tCPWD
Notes 3, 4, 5
MB81V4400C-70 Min. Max. 0 -- 10 -- 90 -- 40 -- 55 -- 5 0 10 0 10 -- -- 10 0 15 0 0 45 85 -- 10 -- 40 60 -- -- -- -- -- 20 15 -- -- -- -- -- -- -- 40 -- 200000 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DIN Set Up Time DIN Hold Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS Precharge Time to CAS Active Time (Refresh cycles) CAS Set Up Time for CAS-before-RAS Refresh CAS Hold Time for CAS-before-RAS Refresh WE SetUp Time from RAS WE Hold Time from RAS Access Time from OE Output Buffer Turn Off Delay from OE OE to RAS Lead Time for Valid Data OE Hold Time Referebced to WE OE to Data in Delay Time DIN to CAS Delay Time DIN to OE Delay Time 20 20 9 10
MB81V4400C-60 Min. Max. 0 -- 10 -- 80 -- 35 -- 50 -- 5 0 10 0 10 -- -- 10 0 15 0 0 40 80 -- 10 -- 35 55 -- -- -- -- -- 15 15 -- -- -- -- -- -- -- 35 -- 200000 -- --
Fast Page Mode Read/Write Cycle Time Fast Page Mode Read-Modify-Write Cycle Time Access Time from CAS Precharge Fast Page Mode CAS Precharge Time Fast Page Mode RAS Pulse width Fast Page Mode RAS Hold Time from CAS Precharge Fast Page Mode CAS Precharge to WE Delay Time 9, 18
8
MB81V4400C-60/MB81V4400C-70
Notes: 1. Referenced to VSS. 2. ICC depends on the output load conditions and cycle rates; The specified values are obtained with the output open. ICC depends on the number of address change as RAS = VIL and CAS = VIH, VIL > -0.3 V. ICC1, ICC3 and ICC5 are specified at one time of address change during RAS= VIL and CAS = VIH. ICC4 is specified at one time of address change during one Page cycle. 3. An Initial pause (RAS = CAS = VIH) of 200 s is required after power-up followed by any eight RASonly cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 4. AC characteristics assume tT = 5 ns. 5. Input voltage levels are 0 V and 3.0 V, and input reference levels are VIH (min.) and VIL (max.) for measuring timing of input signals. Also, the transmission time (tT) is measured between VIH (min.) and VIL (max.). The output reference levels are VOH = 2.0 V and VOL = 0.8 V. 6. Assumes that tRCD tRCD (max.), tRAD tRAD (max.). If tRCD is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig. 2 and 3. 7. If tRCD tRCD (max.), tRAD tRAD (max.), and tASC tAA - tCAC - tT, access time is tCAC. 8. If tRAD tRAD (max.) and tASC 3 tAA - tCAC - tT, access time is tAA. 9. Measured with a load equivalent to one TTL loads and 100 pF. 10. tOFF and tOEZ is specified that output buffer change to high impedance state. 11. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only; if tRCD is greater than the specified tRCD (max.) limit, access time is controlled exclusively by tCAC or tAA. 12. tRCD (min.) = tRAH (min.)+ 2tT + tASC (min.). 13. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only; if tRAD is greater than the specified tRAD (max.) limit, access time is controlled exclusively by tCAC or tAA. 14. Either tRRH or tRCH must be satisfied for a read cycle. 15. tWCS is specified as a reference point only. If tWCS tWCS (min.) the data output pin will remain High-Z state through entire cycle. 16. Assumes that tWCS < tWCS (min.). 17. Either tDZC or tDZO must be satisfied. 18. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H"). Therefore, if tCP is long, tCPA is longer than tCPA (max.). 19. Assumes that CAS-before-RAS refresh. 20. Assumes that Test mode function.
9
MB81V4400C-60/MB81V4400C-70
Fig. 2 - tRAC vs. tRCD
tRAC (ns) tRAC (ns)
Fig. 3 - tRAC vs. tRAD
tCPA (ns) 80
Fig. 4 - tCPA vs. tCP
140 120 100 80 60 40
100 70 90 60 80 70 60 50 70ns Version 60ns Version 50 40 30 70ns Version 60ns Version
70ns version 60ns version
20
40
60
80
100 120
10
20
30
40
50
60
10
20
30
40
50
60
tRCD (ns)
tRAD (ns)
tCP (ns)
s FUNCTIONAL TRUTH TABLE
Clock Input Operation Mode Standby Read Cycle Write Cycle (Early Write) Read-ModifyWrite Cycle RAS-only Refresh Cycle CAS-before-RAS Refresh Cycle Hidden Refresh Cycle Test mode Set Cycle (CBR) Test mode Set Cycle (Hidden) RAS CAS H L L L L L H L L H L H L L L H L L L L WE X H L H L X H H L L OE X L X L H X X L X X Address Row -- Valid Valid Valid Valid -- -- -- -- Column -- Valid Valid Valid -- -- -- -- -- Input Data Input -- -- Valid Valid -- -- -- -- -- Output High-Z Valid High-Z Valid High-Z High-Z Valid High-Z Valid Refresh -- Yes* Yes* Yes* Yes Yes Yes Yes Yes tCSR tCSR (min.) Previous data is kept. tCSR tCSR (min.) tWSR tWSR (min.) tCSR tCSR (min.) tWSR tWSR (min.) tRCS tRCS (min.) tWCS tWCS (min.) tCWD tCWD (min.) Note
X; "H" or "L" *; It is impossible in Fast Page Mode.
10
MB81V4400C-60/MB81V4400C-70
Fig. 5 - READ CYCLE
tRC tRAS RAS VIH VIL tCRP
tRCD
tCSH tRSH tCAS tRAD tRAL tCAL tCAH
COLUMN ADD
tRP
CAS
VIH VIL tASR VIH VIL
ROW ADD
tRAH
tASC
tOEL
A0 to A9
tRCS VIH VIL tRAC VOH DQ (Output) VOL
HIGH-Z VALID DATA
tRRH tRCH tAA tCAC tOH tOFF
WE
tDZC
tON tOEA tOEZ
DQ (Input)
VIH VIL tDZO
HIGH-Z
tOED
OE
VIH VIL
"H" or "L"
DESCRIPTION To implement a read operation, a valid address is latched in by the RAS and CAS address strobes and with WE set to a High level and OE set to a low level, the output is valid once the memory access time has elapsed. The access time is determined by RAS(tRAC), CAS(tCAC), OE (tOEA) or column addresses (tAA) under the following conditions: If tRCD > tRCD (max.), access time = tCAC. If tRAD > tRAD (max.), access time = tAA. If OE is brought Low after tRAC, tCAC, or tAA (which ever occurs later), access time = tOEA. However, if either CAS or OE goes High, the output returns to a high-impedance state after tOH is satisfied.
11
MB81V4400C-60/MB81V4400C-70
Fig. 6 - EARLY WRITE CYCLE (OE="H" or "L")
tRC tRAS RAS VIH VIL tCSH tCRP tRCD CAS VIH VIL tASR tRAD tRAH tASC A0 to A9 VIH VIL
ROW ADD COLUMN ADD
tRSH tCAS
tRP
tRAL tCAL tCAH
tWCS WE VIH VIL
tWCH
tDS DQ VIH (Input) VIL
tDH
VALID DATA IN
DQ VOH (Output) VOL
HIGH-Z
"H" or "L"
DESCRIPTION A write cycle is similar to a read cycle except WE is set to a Low state and OE is a "H" or "L" signal. A write cycle can be implemented in either of three ways-early write, OE write (delayed write), or read-modify-write. During all write cycles, timing parameters tRWL, tCWL and tRAL must be satisfied. In the early write cycle shown above tWCS satisfied, data on the DQ pin is latched with the falling edge of CAS and written into memory.
12
MB81V4400C-60/MB81V4400C-70
Fig. 7 - OE (DELAYED WRITE CYCLE)
tRC tRAS RAS VIH VIL tCRP tRCD CAS VIH VIL tRAH tASR VIH VIL tASC
ROW ADD COL ADD
tCSH
tRP tCAS tRSH
tRAD tCAH tRAL tCAL
A0 to A9
tWCH WE VIH VIL tWP tDZC tDS DQ (Input)
VIH VIL HIGH-Z
tCWL tRWL
tDH
VALID DATA IN
tOED tCAC tAA tRAC
HIGH-Z
VOH DQ (Output) VOL
HIGH-Z
tDZO VIH VIL
tOEA tOEZ
tOEH
OE
"H" or "L" Invalid Data
DESCRIPTION In the OE (delayed write) cycle, tWCS is not satisfied ; thus, the data on the DQ pins is latched with the falling edge of WE and written into memory. The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED+ tT + tDS).
13
MB81V4400C-60/MB81V4400C-70
Fig. 8 - READ-MODIFY-WRITE CYCLE
tRWC tRAS RAS VIH VIL tCSH tCRP VIH VIL tRAH tASR A0 to A9 VIH VIL
ROW ADD COL ADD
tRP tCAS tRSH
tRCD
CAS
tRAD tASC tCAH
tRAL
tRWD tRCS WE VIH VIL tDZC DQ (Input) VIH VIL tCWD tAWD tDS tWP tDH
HIGH-Z
tCWL tRWL
tAA tRAC DQ VOH (Output) VOL
HIGH-Z
tOED tCAC
VALID DATA IN
VALID
HIGH-Z
tOEA tDZO OE VIH VIL
tON tOEZ
tOEH
"H" or "L"
DESCRIPTION The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the readmodify-write cycle, OE must be changed from Low to High after the memory access time.
14
MB81V4400C-60/MB81V4400C-70
Fig. 9 - FAST PAGE MODE READ CYCLE
tRASP RAS VIH VIL tRAD tCRP CAS VIH VIL tASR tRAH VIH A0 to A9 VIL
ROW ADD
tRCD
tRHCP tRP
tPC tCSH tCAS
tRSH tCP tCAS tCAS tCAH tASC tRAL
COL ADD
tASC tASC
COL ADD
tCAH
tCAH
tRRH
COL ADD
tRCS VIH VIL tDZC DQ (Input) VIH VIL tRAC DQ (Output) VOL VOH tDZO tON
tRCH
tRCS tRCH tCAL tOEL tCPA tDZC tDZC tRCS
tRCH
WE
HIGH-Z
HIGH-Z
HIGH-Z
tOH tCAC tOFF
tDZO tCAC tON tAA
tOH tOFF
tDZO
HIGH-Z
tAA tOEA OE VIH VIL tOED tOEZ
tOEA
tOEZ
tOED "H" or "L" Valid Data
DESCRIPTION The fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The access time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring.
15
MB81V4400C-60/MB81V4400C-70
Fig. 10 - FAST PAGE MODE WRITE CYCLE (OE="H" or "L")
tRASP RAS VIH VIL tCSH tCRP tRCD CAS VIH VIL tRAH tASR VIH A0 to A9 VIL
ROW ADD
tRHCP tRSH tPC tCAS tCP tCAS tCAS tRP
tRAD tCAH tASC
COL ADD
tCAH tASC tCAL
COL ADD
tASC
COL ADD
tCAH tRAL
tWCS tCWL WE VIH VIL
tWP
tWCH
tWCS tCWL
tWCH tWCS tCWL
tWCH
tWP tWP tRWL tDH
VALID DATA
tDS DQ (Input) VIH VIL
VALID DATA
tDH
tDS
tDS
tDH
VALID DATA
VOH DQ (Output) VOL
HIGH-Z
"H" or "L"
DESCRIPTION The fast page mode write cycle is executed in the same manner as the fast page mode read cycle except the states of WE and OE are reversed. Data appearing on the DQ pins is latched on the falling edge of CAS and written into memory. During the fast page mode write cycle, including the delayed (OE) write and read-modify-write cycles, tCWL must be satisfied.
16
MB81V4400C-60/MB81V4400C-70
Fig. 11 - FAST PAGE MODE OE WRITE CYCLE
tRAD VIH RAS VIL tCRP VIH CAS VIL tRAH tASR VIH A0 to A9 VIL
ROW ADD.
tRASP tPC tCP tCAS tASC tCAH tASC
COL ADD COL ADD COL ADD
tRP tRSH tCAS
tRCD tCSH tCAS
tASC
tCAH tCAH
tRAL
tCWL VIH WE VIL tDZC tDS tDH DQ (Input) VIH VIL
VALID
tRCS tWP tWP tDS
tCWL
tRWL tCWL tWP
tDH
VALID
tDH tDS
VALID
tAA tCAC tOED tOEH tAA
tOED
tAA tCAC tOEH tCAC
tOED
VOH DQ (Output) VOL
tRAC
HIGH-Z
tDZO tOEA tOEZ tOEA tOEZ
tOEA tOEZ
tOEH
VIH OE VIL
"H" or "L" Invalid Data
DESCRIPTION The fast page mode OE (delayed) write cycle is executed in the same manner as the fast page mode write cycle except for the states of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the fast page mode delayed write cycle, OE must be changed from Low to High before WE goes Low (tOED + tT + tDS).
17
MB81V4400C-60/MB81V4400C-70
Fig. 12 - FAST PAGE MODE READ-MODIFY-WRITE CYCLE
tRAD VIH RAS VIL tCRP VIH CAS VIL tRAH tASR A0 to A9 VIH VIL
ROW ADD
tRASP tPRWC tRCD tCSH tCAS tCAH
COL ADD
tRSH tCP tCAS tASC tASC tCAH
COL ADD
tRP
tCAS
tASC
COL ADD
tCAH
tRAL
tRCS VIH WE VIL tDZC DQ (Input) VIH VIL tAA VOH DQ (Output) VOL
HIGH-Z
tCWL tCWD tAWD tDS
VALID
tCPWD tRCS tWP tDS tDH
VALID
tCWL tWP
tRCS
tRWL tCWL tWP tDS
tCWD
tDH
VALID
tDH
tOED tCAC
tAA
tOED tCAC
tON tDZO tOEZ tOEH
tON tOEZ
VIH OE VIL tOEA tCPA tOEA
"H" or "L" Valid Data
DESCRIPTION During fast page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input date appears at the DQ pins during a normal cycle.
18
MB81V4400C-60/MB81V4400C-70
Fig. 13 - RAS-ONLY REFRESH (WE = OE = "H" or "L")
tRC tRAS VIH RAS VIL tASR VIH A0 to A9 VIL tCRP CAS VIH VIL tOH DQ VOH (Output) VOL
HIGH-Z
tRP tRAH
ROW ADDRESS
tRPC
tOFF
"H" or "L"
DESCRIPTION Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1024 row addresses every 16.4-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched on the falling edge of RAS. During RAS-only refresh, DQ pin is kept in a high-impedance state.
Fig. 14 - CAS-BEFORE-RAS REFRESH (A0 to A9 = OE = "H" or "L")
tRC RAS VIH VIL tCPN CAS VIH VIL tWSR WE VIH VIL tOFF tOH DQ VOH (Output) VOL
DESCRIPTION HIGH-Z
tRAS tCSR
tRP
tCHR
tRPC
tWHR
"H" or "L"
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low for the specified setup time (tCSR) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-before-RAS refresh operation. WE must be held High for the specified set up time (tWSR) before RAS goes low in order not to enter "test mode".
19
MB81V4400C-60/MB81V4400C-70
Fig. 15 - HIDDEN REFRESH CYCLE
tRC RAS VIH VIL tRCD tRAD CAS VIH VIL tASR VIH A0 to A9 VIL [Normal Mode] WE VIH VIL tDZC DQ (Input) VIH VIL tON VOH DQ (Output) VOL VIH VIL tRCS tRRH tAA tRAC tDZC DQ (Input) VIH VIL tON VOH DQ (Output) VOL
VIH VIL HIGH-Z HIGH-Z
tRC tRP tRAS tRP tCHR tCRP
tRAS tOEL
tRSH tRAH tASC tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS tAA tRAC tCAC
tRRH
tWSR
tWHR
HIGH-Z
tOFF tOH
VALID DATA OUT
tDZO OE
tOEA
tOEZ tOED
[Test Mode] WE VIH VIL
tWSR
tWHR
tCAC
HIGH-Z
tOFF tOH
VALID DATA OUT
tDZO
tOEA
tOEZ tOED
OE
"H" or "L"
DESCRIPTION A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of CAS and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row address that is required by DRAMs that do not have CAS-before-RAS refresh capability. WE must be held High for the specified set up time (tWSR) before RAS goes Low in order not to enter "test mode" .
20
MB81V4400C-60/MB81V4400C-70
Fig. 16 - TEST MODE SET CYCLE (A0 to A9, OE = "H" or "L")
tRC VIH VIL tRAS tRP
RAS
tCPN VIH VIL
tCSR
tRPC tCHR
CAS
tWSR WE VIH VIL tOFF tOH DOUT VOH VOL
tWHR
HIGH-Z
"H" or "L"
DESCRIPTION Test Mode ; The purpose of this test mode is to reduce device test time to half of that required to test the device conventionally. The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle. In the test mode, read and write operations are executed in units of eights bits which are selected by the address combination of CA0. In the write mode, data is written into eight cells simultaneously. But the data must be input from all DQ pins. In the read mode, the data of eight cells at the selected addresses are read out from DQ and checked in the following manner When the eight bits are all "L" or all "H", a "H" level is output.. When the eight bits show a combination of "L" and "H", a "L" level is output.. The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle. In test mode operation, the following parameters are delayed approximately 5ns from the specified value in the data sheet.. tRC, tRWC, tRAC, tAA, tRAS, tCSH, tRAL, tRWD, tAWD, tPC, tPRWC, tCPA, tRHCP, tCPWD
21
MB81V4400C-60/MB81V4400C-70
Fig. 17 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
RAS VIH VIL VIH VIL tCSR tCHR tCP
tFRSH tFCAS tFCAH tRAL
tRP
CAS
A0 to A9 VIH VIL tWSR WE VIH VIL
tASC tWHR tRCS tDZC
COLUMN ADDRESS
tFCWD
tCWL tRWL tWP tDH
VALID DATA IN
tDS
HIGH-Z
DQ (Input)
VIH VIL
tOED tFCAC
HIGH-Z
VOH DQ (Output) VOL OE VIH VIL
tDZO
tON tOEA tOEZ
HIGH-Z
tOEH
"H" or "L" Valid Data
DDESCRIPTION A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle. CAS makes a transition from High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows: Row Address: Bits A0 through A9 are defined by the on-chip refresh counter. Column Address: Bits A0 through A9 are defined by latching levels on A0-A9 at the second falling edge of CAS. The CAS-before-RAS Counter Test procedure is as follows ; 1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles. 2) Use the same column address throughout the test. 3) Write "0" to all 1024 row addresses at the same column address by using normal write cycles. 4) Read "0" written in procedure 3) and check; simultaneously write "1" to the same addresses by using CAS-before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 1024 times with addresses generated by the internal refresh address counter. 5) Read and check data written in procedure 4) by using normal read cycle for all 1024 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5). (At recommended operating conditions unless otherwise noted.) No. 90 91 92 93 94 Parameter Access Time from CAS Column Address Hold Time CAS to WE Delay Time CAS Pulse width RAS Hold Time Symbol tFCAC tFCAH tFCWD tFCAS tFRSH MB81V4400C-60 Min. -- 30 55 35 35 Max. 35 -- -- -- -- MB81V4400C-70 Min. -- 30 60 40 40 Max. 40 -- -- -- -- Unit ns ns ns ns ns
Note. Assumes that CAS-before-RAS refresh counter test cycle only.
22
MB81V4400C-60/MB81V4400C-70
Fig. 18 - SELF REFRESH CYCLE (A0-A9 = OE = "H" or "L")
tRPS
RAS
VIH VIL tCPN tCSR
tRASS
tRPC tCHS
CAS
VIH VIL tWSR tWHR
WE
VIH VIL tOFF tOH
DOUT
VOH VOL
HIGH-Z
"H" or "L"
(At recommended operating conditions unless otherwise noted.) No. 100 101 102 Parameter RAS Pulse Width RAS Precharge Time CAS Hold Time Symbol tRASS tRPS tCHS MB81V4400C-60 Min. 100 110 -50 Max. -- -- -- MB81V4400C-70 Min. 100 125 -50 Max. -- -- -- Unit s ns ns
Note. Assumes self refresh cycle only
DESCRIPTION The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter. If CAS goes to "L" before RAS goes to "L" (CBR) and the condition of CAS "L" and RAS "L" is kept for term of tRASS (more than 100 s), the device can be entered the self refresh cycle. And after that, refresh operation is automatically executed per fixed interval using internal refresh address counter during "RAS=L" and "CAS=L". And exit from self refresh cycle is performed by toggling of RAS and CAS to "H" with specifying tCHS min. Restruction for Self refresh operation ; For self refresh operation, the notice below must be considered. 1) In the case that distribute CBR refresh are operated in read/write cycles Self refresh cycles can be executed without special rule if 1024 cycles of distribute CBR refresh are executed within tREF max.. 2) In the case that burst CBR refresh or RAS-only refresh are operated in read/write cycles 1024 times of burst CBR refresh or 1024 times of burst RAS-only refresh must be executed before and after Self refresh cycles.
Read/Write operation RAS VIH VIL tNS<1ms 1024 times of burst refresh
Self Refresh operation tRASS
Read/Write operation
tSN<1ms 1024 times of burst refresh
23
MB81V4400C-60/MB81V4400C-70
s PACKAGE DIMENSIONS
(Suffix : -PFTN)
26 pin, Plastic TSOP(II) (FPT-26P-M01)
Details of "A" part
26 22 18 14
0.15(.006)
0.25(.010) INDEX "A" 0.15(.006)MAX 0.50(.020)MAX LEAD No.
1 5 9 13
* 17.140.10
(.675.004) 0.400.10 (.016.004) 0.21(.008)
M
1.10 -0.05 +.004 .043 -.002
+0.10
9.220.20 (.363.008) 7.620.10 (.300.004)
0.150.05 (.006.002)
1.27(.050)TYP
0.10(.004) 15.24(.600)REF
0(0)MIN (STAND OFF)
0.500.10 (.020.004)
8.220.20 (.324.008)
Dimensions in mm(inches).
C
1994 FUJITSU LIMITED F26001S-3C-3
24
MB81V4400C-60/MB81V4400C-70
s PACKAGE DIMENSIONS (Continued)
(Suffix : -PFTR)
26 pin, Plastic TSOP(II) (FPT-26P-M02)
Details of "A" part
26 22 18 14
0.15(.006)
0.25(.010) INDEX "A" 0.15(.006)MAX 0.50(.020)MAX LEAD No.
1 5 9 13
15.24(.600)REF 1.27(.050)TYP 0.10(.004) 0(0)MIN (STAND OFF) 0.500.10 (.020.004) 8.220.20 (.324.008) 0.150.05 (.006.002)
0.400.10 (.016.004)
0.21(.008)
M
1.10 -0.05 +.004 .043 -.002
+0.10
* 17.140.10
(.675.004)
7.620.10 (.300.004) 9.220.20 (.363.008)
Dimensions in mm(inches).
C
1994 FUJITSU LIMITED F26002S-3C-3
25
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
24

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