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IS61LV10248
1M x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
* High-speed access times: 8, 10 ns * High-performance, low-power CMOS process * Multiple center power and ground pins for greater noise immunity * Easy memory expansion with CE and OE options * CE power-down * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 3.3V power supply * Packages available: - 48-ball miniBGA (9mm x 11mm) - 36-ball miniBGA (9mm x 11mm) - 44-pin TSOP (Type II) * Lead-free available
ISSI
APRIL 2006
(R)
DESCRIPTION The ISSI IS61LV10248 is a very high-speed, low power,
1M-word by 8-bit CMOS static RAM. The IS61LV10248 is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. The IS61LV10248 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV10248 is available in 48 ball mini BGA, 36-ball mini BGA, and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A19
DECODER
1M X 8 MEMORY ARRAY
VDD GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE OE WE CONTROL CIRCUIT
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
1
IS61LV10248
ISSI
48-pin Mini BGA (M ) (9mm x 11mm)
1 2 3 4 5 6
(R)
PIN CONFIGURATION
36 mini BGA (B) (9mm x 11mm)
1
2
3
4
5
6
A B C D E F G H
A0 I/O4 I/O5 GND VDD I/O6 I/O7 A9
A1 A2
NC WE A19
A3 A4 A5
A6 A7
A8 I/O0 I/O1 VDD GND
A B C D E F G H
NC NC NC GND VDD NC NC A18
OE NC NC NC NC NC NC A8
A0 A3 A5 A17 NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
NC I/O0 I/O2 VDD GND I/O6 I/O7 A19
A18 OE A10 CE A11
A17 A16 A12 A15 A13
I/O2 I/O3 A14
PIN DESCRIPTIONS
A0-A19 CE OE WE I/O0-I/O7 VDD GND NC Address Inputs Chip Enable Input Output Enable Input Write Enable Input Data Input / Output Power Ground No Connection
44-pin TSOP (Type II )
NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 GND VDD I/O5 I/O4 A14 A13 A12 A11 A10 A19 NC NC
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
IS61LV10248
ISSI
CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ICC ICC ICC
(R)
TRUTH TABLE
Mode WE X H H L Not Selected (Power-down) Output Disabled Read Write
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value -0.5 to VDD + 0.5 -0.3 to 4.0 -65 to +150 1.0 Unit V V C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V +10%, -5% 3.3V +10%, -5%
CAPACITANCE(1,2)
Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
3
IS61LV10248
ISSI
Test Conditions VDD = Min., IOH = -4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 -- 2.2 -0.3 GND VIN VDD GND VOUT VDD, Outputs Disabled Com. Ind. Com. Ind. -1 -5 -1 -5 Max. -- 0.4 VDD + 0.3 0.8 1 5 1 5 V V V V A A
(R)
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage
(1)
Unit
Note: 1. VIL = -3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 Symbol Parameter ICC ISB1 VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., VIN = VIH or VIL CE VIH, f = 0 VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. Min. -- -- -- -- -- -- Max. 110 120 30 35 20 25 -10 Min. Max. -- -- -- -- -- -- 100 110 30 35 20 25 Unit mA mA
ISB2
mA
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
IS61LV10248
ISSI
Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
(R)
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load
AC TEST LOADS
319
ZO = 50 OUTPUT 30 pF Including jig and scope 50 1.5V
3.3V
OUTPUT 5 pF Including jig and scope
Figure 2
353
Figure 1
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
5
IS61LV10248
ISSI
-8 Min. 8 -- 3 -- -- -- 0 -- 3 0 -- Max. -- 8 -- 8 3.5 3 -- 3 -- -- 8 -10 Min. Max. 10 -- 3 -- -- -- 0 0 3 0 -- -- 10 -- 10 4 4 -- 4 -- -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns
(R)
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output Power Up Time Power Down Time
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tPU tPD
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage.
6
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
IS61LV10248
ISSI
(R)
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t RC
ADDRESS
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t RC
ADDRESS
t AA
OE
t OHA
t DOE
CE
t HZOE
t LZOE t ACE t LZCE t HZCE
DATA VALID
CE_RD2.eps
DOUT
HIGH-Z
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
7
IS61LV10248
ISSI
-8 -10 Max. -- -- -- -- -- -- -- -- -- 3.5 -- Min. 10 8 8 0 0 8 10 6 0 -- 2 Max. -- -- -- -- -- -- -- -- -- 5 -- Unit ns ns ns ns ns ns ns ns ns ns ns Min. 8 6.5 6.5 0 0 6.5 8 5 0 -- 2
(R)
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
(2)
tWC tSCE tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE(2) tLZWE
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
8
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
IS61LV10248
ISSI
t WC
(R)
AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
ADDRESS
VALID ADDRESS
t SA
CE
t SCE t AW t PWE1 t PWE2 t HZWE
t HA
WE
t LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
9
IS61LV10248
ISSI
(R)
AC WAVEFORMS WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
WE
t PWE1 t SA t HZWE
DATA UNDEFINED
HIGH-Z
t LZWE
DOUT
t SD
DIN
t HD
DATAIN VALID
CE_WR2.eps
Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH.
10
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
IS61LV10248
ISSI
(R)
AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS OE CE
VALID ADDRESS
LOW
t HA
LOW
t AW
WE
t PWE2 t SA t HZWE
HIGH-Z
t LZWE
DOUT
DATA UNDEFINED
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
11
IS61LV10248
ISSI
(R)
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 8 Order Part No. IS61LV10248-8M IS61LV10248-8T IS61LV10248-8B IS61LV10248-10T Package 48 mini BGA (9mm x 11mm) TSOP (Type II) 36 mini BGA (9mm x 11mm) TSOP (Type II)
10
Industrial Range: -40C to +85C
Speed (ns) 8 Order Part No. IS61LV10248-8MI IS61LV10248-8TI IS61LV10248-8BI IS61LV10248-10MI IS61LV10248-10TI IS61LV10248-10TLI IS61LV10248-10BI IS61LV10248-10BLI Package 48 mini BGA (9mm x 11mm) TSOP (Type II) 36 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm) TSOP (Type II) TSOP (Type II), Lead-free 36 mini BGA (9mm x 11m) 36 mini BGA (9mm x 11m), Lead-free
10
12
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
IS61LV10248
ISSI
Top View 1 2 3 4 56 6 Bottom View
b (36x)
(R)
Mini Ball Grid Array Package Code: B (36-pin)
5
4
3
2
1
A B C D D E F G H D1
e
A B C D E F G H
e E E1
A2 SEATING PLANE A1
A
Notes: 1. Controlling dimensions are in millimeters.
mBGA - 9mm x 11mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.24 0.60
INCHES Min. Typ. Max.
Min. Typ. Max.
36 -- -- -- 1.20 0.30 --
-- 0.009 0.024
-- -- --
0.047 0.012 --
10.90 11.00 11.10 5.25 BSC 8.90 9.00 9.10 3.75 BSC 0.75 BSC 0.30 0.35 0.40
0.429 0.433 0.437 0.207 BSC 0.350 0.354 0.358 0.148 BSC 0.030 BSC 0.012 0.014 0.016
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 04/13/06
13
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: M (48-pin)
ISSI
Bottom View
b (48x)
(R)
Top View 1 2 3 4 56 6
5
4
3
2
1
A B C D D E F G H D1
e
A B C D E F G H
e E E1
A2 SEATING PLANE A1
A
Notes: 1. Controlling dimensions are in millimeters.
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 01/15/03
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: M (48-pin)
ISSI
(R)
mBGA - 6mm x 8mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.25 0.60
INCHES Min. Typ. Max.
Min. Typ. Max.
48 -- -- -- 5.60BSC 5.90 6.00 6.10 4.00BSC 0.80BSC 0.40 0.45 0.50 1.20 0.40 --
.-- 0.010 0.024
-- 0.047 -- 0.016 -- --
7.90 8.00 8.10
0.311 0.314 0.319 0.220BSC 0.232 0.236 0.240 0.157BSC 0.031BSC 0.016 0.018 0.020
mBGA - 7.2mm x 8.7mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0 .24 0.60
mBGA - 9mm x 11mm
INCHES Min. Typ. Max. Sym.
N0. Leads
MILLIMETERS Min. Typ. Max.
48 -- 0.24 0.60 -- -- -- 5.25BSC 8.90 9.00 9.10 3.75BSC 0.75BSC 0.30 0.35 0.40 1.20 0.30 -- --
INCHES Min. Typ. Max.
Min. Typ. Max.
48 -- -- -- 5.25BSC 7.10 7.20 7.30 3.75BSC 0.75BSC 0.30 0.35 0.40 1.20 0.30 --
-- 0.009 0.024
-- -- --
0.047 0.012 --
A A1 A2 D D1 E E1 e b
-- -- --
0.047 0.012 --
0.009 0.024
8.60 8.70 8.80
0.339 0.343 0.346 0.207BSC 0.280 0.283 0.287 0.148BSC 0.030BSC 0.012 0.014 0.016
10.90 11.00 11.10
0.429 0.433 0.437 0.207BSC 0.350 0.354 0.358 0.148BSC 0.030BSC 0.012 0.014 0.016
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 01/15/03
PACKAGING INFORMATION
Plastic TSOP Package Code: T (Type II)
ISSI
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
(R)
N
N/2+1
E1
E
1 D
N/2
SEATING PLANE
ZD
A
.
e b L A1 C
Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD
Millimeters Min Max
Inches Min Max
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0 5 0 5
Millimeters Min Max 50 -- 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0 5
Inches Min Max
(N) 32 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0 5 0 5
-- 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0 5
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 06/18/03

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