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| K3N6C3000E-DC 32M-Bit (4Mx8) CMOS MASK ROM FEATURES * 4,194,304x8 bit organization * Fast access time 100ns(Max.) : CL=50pF 120ns(Max.) : CL=100pF * Supply voltage : single +5V * Current consumption Operating : 50mA(Max.) Standby : 50A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package -. K3N6C3000E-DC : 42-DIP-600 CMOS MASK ROM GENERAL DESCRIPTION The K3N6C3000E-DC is a fully static mask programmable ROM organized 4,194,304x8 bit. It is fabricated using silicongate CMOS process technology. This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor and data memory, character generator. The K3N6C3000E-DC is packaged in a 42-DIP. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION A21 . . . . . . . . A0 X BUFFERS AND DECODER MEMORY CELL MATRIX (4,194,304x8) A19 A18 A8 A7 A6 A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 A20 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 Y BUFFERS AND DECODER SENSE AMP. BUFFERS A4 A3 A2 A1 CE DIP 33 A17 32 A21 31 VSS 30 A0 29 Q7 28 N.C 27 Q6 26 N.C 25 Q5 24 N.C 23 Q4 22 VCC ... VSS OE CE OE CONTROL LOGIC Q0 Q7 Q0 N.C Q1 N.C Q2 N.C Pin Name A0 - A21 Q0 - Q7 CE OE VCC VSS Pin Function Address Inputs Data Outputs Chip Enable Output Enable Power (+5V) Ground Q3 N.C K3N6C3000E-DC K3N6C3000E-DC ABSOLUTE MAXIMUM RATINGS Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG Rating CMOS MASK ROM Unit V C C -0.3 to +7.0 -10 to +85 -55 to +150 NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70C) Item Supply Voltage Supply Voltage Symbol VCC VSS Min 4.5 0 Typ 5.0 0 Max 5.5 0 Unit V V DC CHARACTERISTICS Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions Cycle=5MHz, all outputs open CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition) CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC Min 2.2 -0.3 2.4 Max 50 1 50 10 10 VCC+0.3 0.8 0.4 Unit mA mA A A A V V V V NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. MODE SELECTION CE H L L OE X H L Mode Standby Operating Operating Data High-Z High-Z Dout Power Standby Active Active CAPACITANCE(TA=25C, f=1.0MHz) Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF NOTE : Capacitance is periodically sampled and not 100% tested. K3N6C3000E-DC CMOS MASK ROM AC CHARACTERISTICS(TA=0C to +70C,VCC=5V10%, unless otherwise noted.) TEST CONDITIONS Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value 0.6V to 2.4V 10ns 0.8V and 2.0V 1 TTL Gate and CL=50pF or 100pF READ CYCLE Item Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA tOE tDF tOH 0 K3N6C3000E-DC10 (CL=50pF) Min 100 100 100 50 20 0 Max K3N6C3000E-DC12 (CL=100pF) Min 120 120 120 60 20 0 Max K3N6C3000E-DC15 (CL=100pF) Min 150 150 150 70 30 Max ns ns ns ns ns ns Unit TIMING DIAGRAM READ ADD ADD1 tRC tACE ADD2 tDF(Note) CE tOE OE tOH DOUT VALID DATA VALID DATA tAA NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level. |
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