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CS5106 Multi-Feature, Synchronous plus Auxiliary PWM Controller
The CS5106 is a fixed frequency, current mode controller with one single NFET driver and one dual FET, synchronous driver. The synchronous driver allows for increased efficiency of the main isolated power stage and the single driver allows the designer to develop auxiliary supplies for controller power as well as secondary side house keeping. In addition, because the synchronous drivers have programmable FET non-overlap, the CS5106 is an ideal controller for soft-switched converter topologies. The CS5106 is specifically designed for isolated topologies where speed, flexibility, reduced size and reduced component count are requirements. The controller contains the following features: Undervoltage Shutdown, Overvoltage Shutdown, Programmable Frequency, Programmable Synchronous Non-Overlap Time, Master/Slave Clocking with Frequency Range Detection, Enable, Output Undervoltage Protection with Timer, 20 mA 5.0 V Output, 80 ns PWM propagation delay, and Controlled Hiccup Mode. The CS5106 has junction temperature and supply ranges of -40C to 125C and 9.0 V to 16 V respectively and is available in the 24 lead SSOP package.
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24 1 SSOP-24 SW SUFFIX CASE 940D
PIN CONNECTIONS AND MARKING DIAGRAM
UVSD OVSD V5REF OAM OAOUT OUVDELAY ILIM1 RAMP1 VFB1 VSS VCC GATE1 1 24 ENABLE PROGRAM SYNCIN SYNCOUT FADJ DLYSET ILIM2 RAMP2 VFB2 GATE2B GATE2 VDD
* * * * * * * * * * * *
Features Programmable Fixed Frequency Programmable FET Non-Overlap Enable Lead 12 V Fixed Auxiliary Supply Control Under and Overvoltage Shutdown Output Undervoltage Protection with Timer Master/Slave Clock Sync Capability Sync Frequency Range Detection 80 ns PWM Propagation Delay 20 mA 5.0 V Reference Output Small 24 Lead SSOP Package Controlled Hiccup Mode
CS5106 AWLYYWW
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS5106LSW24 CS5106LSWR24 Package SSOP-24 Shipping 59 Units/Rail
SSOP-24 2000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
February, 2001 - Rev. 8
Publication Order Number: CS5106/D
Figure 1. Application Diagram, 48 V to 3.3 V Forward Converter with Synchronous Rectifiers
VIN SYNCIN ENABLE R27 R1 VAUXP R2 UVSD OVSD V5REF V5REF
R3
CS5106
ENABLE PROGRAM SYNCIN OAM SYNCOUT OAOUT FADJ OUVDELAY DLYSET ILIM2 ILIM1 RAMP2 RAMP1 VFB2 VFB1 VSS GATE2B GATE2 VCC VDD GATE1
SYNCOUT D5 C6 R24 D8 R25 R15 R7 R20 R16 C14 R18 R17 C13 R14 C8 CNY17-4 TL431 R19
R4 C1 C2
C3
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CS5106
VAUXP
VIN T1 VIN
2
C4
D1
R13 T4 R9
VAUXS Q7 R21
C5
D2
R8 Q2 Q1 R5
D3 C9 C10 R10 VIN R11 T3 D4 R12 D7 R26 Q6
T2 R23 C11
L1 Q5 Q4 C12
VMAIN
VAUXS
C7
R6
D6
Q3 R22
CS5106
ABSOLUTE MAXIMUM RATINGS*
Rating Operating Junction Temperature, TJ Operating Temperature Range, TA Storage Temperature Range, TS ESD Susceptibility (Human Body Model) Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1.) Value 150 -40 to 85 -65 to +150 2.0 230 peak Unit C C C kV C
ABSOLUTE MAXIMUM RATINGS
Pin Name Undervoltage Shutdown Input Overvoltage Shutdown Input 5.0 V Reference Output Error Amp Minus Input Error Amp Output Output Overcurrent Timer Capacitor Auxiliary Primary Side Current Limit Input Auxiliary Primary Side Current Ramp Input Auxiliary Voltage Feedback Input Bootstrapped Power Input Main Power Input Auxiliary FET Driver Output Ground Synchronous FET Driver Output Synchronous FET Driver Output B Synchronous Voltage Feedback Input Synchronous Primary Side Current Ramp Input Synchronous Primary Side Current Limit Input Gate Non-Overlap Programming Input Frequency Programming Input Clock Master Output Clock Slave Input Enable Programming Input Enable Input Pin Symbol UVSD OVSD V5REF OAM OAOUT OUVDELAY ILIM1 RAMP1 VFB1 VSS VCC GATE1 GND GATE2 GATE2B VFB2 RAMP2 ILIM2 DLYSET FADJ SYNCOUT SYNCIN PROGRAM ENABLE VMAX 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 20 V 20 V 20 V 0V 20 V 20 V 6.0 V 6.0 V 6.0 V 2.5 V 2.5 V 6.0 V 6.0 V 16 V 16 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V 0V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE 1.0 mA 1.0 mA 150 mA 250 A 300 A 15 A 10 A 10 A 5.0 A 2.0 A See Note 2. 0.5 A Peak, 100 mA DC 0.5 A Peak 0.5 A Peak, 100 mA DC 0.5 A Peak, 100 mA DC 10 A 10 A 10 A 125 A 125 A 50 mA N/A 30 A 300 A ISINK N/A N/A 25 mA 1.2 mA 100 mA N/A N/A N/A 100 A 0.5 A Peak, 300 mA DC 0.5 A Peak, 300 mA DC 0.5 A Peak, 100 mA DC N/A, 300 mA DC 0.5 A Peak, 100 mA DC 0.5 A Peak, 100 mA DC 100 A N/A N/A N/A N/A 100 mA 1.0 mA N/A N/A
2. Current out of VCC is not limited. Care should be taken to prevent shorting VCC to Ground.
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CS5106
ELECTRICAL CHARACTERISTICS (TJ = -40C to 125C, VSS = 9.0 to 16 V, V5REF ILOAD = 2.0 mA, SYNCOUT Free Running, unless otherwise specified. For All Specs: UVSD = 6.0 V, OVSD = 0 V, ENABLE = 0 V, ILIM(1,2) = 0, VFB(1,2) = 3.0 V, RFADJ = RDLYSET = 27.4 k.)
Characteristic VSS Supply Current VSS Supply Current Measure current into VSS when V5REF ILOAD = 0 mA. 9.0 V VSS 13 V. Measure current into VSS when V5REF ILOAD = 0 mA. 13 V < VSS 16 V. Measure current into VSS when V5REF ILOAD = 0 mA. 16 V < VSS 20 V. - - - 16 16 16 23 25 30 mA mA mA Test Conditions Min Typ Max Unit
Low VCC Supply Current Low VCC Supply Current VSS to VCC Diode Diode ON Voltage Reference 5.0 V Internal Voltage Reference VREFOK Threshold Low VCC Lockout VCC Turn-on Threshold Voltage VCC Turn-off Threshold Voltage Hysteresis Clock Operating Frequency1 SYNCIN Input Impedance SYNCOUT Output Low Voltage SYNCOUT Output High Voltage SYNCIN Detect Frequency Max. Low SYNC Rej. Frequency Min. High SYNC Rej. Frequency SYNCIN Input Threshold Voltage Main PWM Clock Pulse Width Aux PWM Clock Pulse Width Measure frequency from SYNCOUT. Measure input impedance. RLOAD = 2.0 k to V5REF RLOAD = 2.0 k to GND Verify SYNCOUT = SYNCIN, RLOAD = 2.0 k to GND Verify SYNCOUT = FCLK when RLOAD = 2.0 k to GND Verify SYNCOUT = FCLK when RLOAD = 2.0 k to GND Functional Testing Verify FCLK from 1.0 V to 2.8 V (GBD) - CLPH1 One Shot Pulse Width (GBD) - CLPH2 One Shot Pulse Width 485 7.0 - 3.5 425 - 690 0.9 80 80 512 15 1.0 4.2 - - - 1.85 100 100 540 - 1.5 - 555 340 - 2.9 120 120 kHz k V V kHz kHz kHz V ns ns VCC increasing until ICC > 3.5 mA V5REF ILOAD = 0 mA VCC decreasing until ICC < 3.5 mA V5REF ILOAD = 0 mA Turn-on - Turn-off 7.0 6.3 0.40 7.25 6.7 0.55 7.5 7.1 0.70 V V V Measure VREF voltage when IREF = 0 and IREF = 20 mA Adjust VREF from 4.8 V-4.0 V until PWM1,2 goes low. 4.85 4.3 5.0 4.55 5.15 4.7 V V Measure VSS - VCC 0.2 0.75 1.0 V Float VSS. Set VCC = 7.0 V & measure VCC current while V5REF ILOAD = 0 mA. - 1.5 3.5 mA
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CS5106
ELECTRICAL CHARACTERISTICS (continued) (TJ = -40C to 125C, VSS = 9.0 to 16 V, V5REF ILOAD = 2.0 mA, SYNCOUT Free Running, unless otherwise specified. For All Specs: UVSD = 6.0 V, OVSD = 0 V, ENABLE = 0 V, ILIM(1,2) = 0, VFB(1,2) = 3.0 V, RFADJ = RDLYSET = 27.4 k.)
Characteristic Bias Supply Error Amplifier Output Low Voltage Output High Voltage Output High Source Current Output Low Sink Current VSS Set Point Large Signal Gain Unity Gain Bandwidth Common Mode Input Range VSS Voltage VSS Reset Voltage Toggle ENABLE between GND & VCC, then adjust VSS from 2.0 V-0.8 V until OAOUT goes high. 1.0 1.4 1.8 V VSS > 12.6 V. Measure OAOUT voltage when sinking 1.0 mA. VSS < 11.4 V. Measure OAOUT voltage when sourcing 150 A. VSS < 11.4 V. Measure OAOUT source current when OAOUT = 0.5 V VSS > 12.6 V. Measure OAOUT sink current when OAOUT = 2.5 V. Adjust VSS until OAOUT goes low. (GBD) (GBD) (GBD) - 4.55 150 3.0 11.6 15 - 1.0 43 4.75 225 20 12.25 - 1.0 - 85 - 300 50 12.8 - - 2.0 mV V A mA V V/mV MHz V Test Conditions Min Typ Max Unit
Undervoltage Lockout UVSD Turn-On Threshold Voltage UVSD Turn-Off Threshold Voltage Hysteresis UVSD Input Bias Current Overvoltage Lockout OVSD Threshold Voltage OVSD Input Bias Current ENABLE & PROGRAM ENABLE Lead Output Current PROGRAM Lead Output Current PROGRAM Threshold Voltage ENABLE Threshold Voltage Measure current out of ENABLE when ENABLE = 0 V Measure current out of PROGRAM when PROGRAM = 0 V ENABLE = GND. Adjust PROGRAM from 1.0 V-1.8 V until GATE1,2 goes high. PROGRAM = GND. Adjust ENABLE from 1.0 V-1.8 V until GATE1,2 goes high. 100 20 1.2 1.2 266 60 1.4 1.4 500 100 1.6 1.6 A A V V Adjust OVSD from 4.7 V-5.3 V until GATE1,2 goes low. Set OVSD = 0 V. Measure Current out of OVSD lead. 4.85 - 5.0 0.2 5.15 0.5 V A Adjust UVSD from 4.7 V-5.3 V until GATE1,2 goes high. Adjust UVSD from 5.1 V-4.3 V until GATE1,2 goes low. Turn-on - Turn-off Set UVSD = 0 V. Measure Current out of UVSD lead. 4.8 4.45 0.2 - 5.0 4.7 0.27 0.2 5.1 4.95 0.4 0.5 V V V A
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CS5106
ELECTRICAL CHARACTERISTICS (continued) (TJ = -40C to 125C, VSS = 9.0 to 16 V, V5REF ILOAD = 2.0 mA, SYNCOUT Free Running, unless otherwise specified. For All Specs: UVSD = 6.0 V, OVSD = 0 V, ENABLE = 0 V, ILIM(1,2) = 0, VFB(1,2) = 3.0 V, RFADJ = RDLYSET = 27.4 k.)
Characteristic Output Undervoltage Delay OUVDELAY Charging Current OUVDELAY Latch-off Voltage Set OUVDELAY = 1.0 V, VFB1 = 4.4 V Measure OUVDELAY ICHARGE. Toggle ENABLE between GND & VCC, then adjust OUVDELAY from 4.7 V-5.3 V until GATE1,2, goes low. OUVDELAY = VOCLO + 50 mV. Measure current into OUVDELAY. VSS = 1.0 V. Toggle ENABLE between GND & VCC, adjust VFB1 from 3.8 V-4.6 V until GATE1,2 goes low. VSS = 1.0 V. Toggle ENABLE between GND & VCC, adjust VFB2 from 3.8 V-4.6 V until GATE1,2 goes low. 7.5 4.8 10 5.0 12.5 5.2 A V Test Conditions Min Typ Max Unit
OUVDELAY Set Current VFB1 Charge Threshold
- 4.05
0.5 4.22
1.0 4.4
mA V
VFB2 Charge Threshold
3.9
4.15
4.35
V
Current Limit Circuits ILIM1 Current Limit Threshold Voltage ILIM1 Short Circuit Threshold Voltage ILIM1 Input Bias Current ILIM2 Current Limit Threshold Voltage ILIM2 Short Circuit Threshold Voltage ILIM2 Input Bias Current Voltage Feedback Control RAMP1 Offset Voltage RAMP1 Input Bias Current RAMP2 Offset Voltage RAMP2 Input Bias Current VFB1 Input Impedance VFB2 Input Impedance VFB1 = 0 V. Adjust RAMP1 from 0 V-0.3 V until GATE1 goes low. Measure VRAMP1. Set RAMP1 = 0 V. Measure Current out of RAMP1 lead. VFB2 = 0 V. Adjust RAMP2 from 0 V-3.0 V until GATE2 goes low. Measure VRAMP2. Set RAMP2 = 0 V. Measure Current out of RAMP2 lead. Measure input impedance. Measure input impedance. 0.08 - 0.08 - 60 60 0.13 0.5 0.13 0.5 120 120 0.2 5.0 0.2 5.0 220 220 V A V A k k Adjust ILIM1 from 1.0 V-1.3 V until GATE1 goes low. Adjust ILIM1 from 1.30 V-1.50 V until GATE1 skips 2-cycles with reference to SYNCOUT. Set ILIM1 = 0 V. Measure current out of ILIM1 lead. Adjust ILIM2 from 1.0 V-1.3 V until GATE2 goes low. Adjust ILIM2 from 1.30 V-1.50 V until GATE2 skips 2-cycles with reference to SYNCOUT. Set ILIM2 = 0 V. Measure current out of ILIM2 lead. 1.16 1.35 - 1.16 1.35 - 1.24 1.44 0.5 1.24 1.44 0.5 1.3 1.51 5.0 1.3 1.51 5.0 V V A V V A
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CS5106
ELECTRICAL CHARACTERISTICS (continued) (TJ = -40C to 125C, VSS = 9.0 to 16 V, V5REF ILOAD = 2.0 mA, SYNCOUT Free Running, unless otherwise specified. For All Specs: UVSD = 6.0 V, OVSD = 0 V, ENABLE = 0 V, ILIM(1,2) = 0, VFB(1,2) = 3.0 V, RFADJ = RDLYSET = 27.4 k.)
Characteristic Gate1, 2, 2B, Output Voltages GATE1 Low State GATE2 Low State GATE2B Low State GATE2B High State GATE2 High State GATE1 High State Propagation Delays ILIM1 Delay to Output GATE1 ILIM2 Delay to Output GATE2 RAMP1 Delay to Output GATE1 RAMP2 Delay to Output GATE2 GATE2, 2B Non-Overlap Delay GATE2 Turn-on Delay from GATE2B GATE2B Turn-on Delay from GATE2 GATE1, 2, 2B Rise & Fall Times GATE1 Rise Time GATE1 Fall Time GATE2 Rise Time GATE2 Fall Time GATE2B Rise Time GATE2B Fall Time Measure delay from GATE2B going low @ 1.7 V to GATE2 going high @ 1.7 V. Measure delay from GATE2 going low @ 1.7 V to GATE2B going high @ 1.7 V. VSS = 12 V, VCC = VSS-VDON Measure GATE1 Rise Time from 90% to 10%. CLOAD = 150 pF. Measure GATE1 Fall Time from 10% to 90%. CLOAD = 150 pF. Measure GATE2 Rise Time from 90% to 10%. CLOAD = 50 pF. Measure GATE2 Fall Time from 10% to 90%. CLOAD = 50 pF. Measure GATE2B Rise Time from 90% to 10%. CLOAD = 50 pF. Measure GATE2B Rise Time from 10% to 90%. CLOAD = 50 pF. - - - - - - 50 30 50 15 50 15 80 60 80 30 80 30 ns ns ns ns ns ns 20 20 45 45 70 70 ns ns Measure delay from ILIM1 going high to GATE1 going low. Measure delay from ILIM2 going high to GATE2 going low. Measure delay from RAMP1 going high to GATE1 going low. Measure delay from RAMP2 going high to GATE2 going low. - - - - 80 80 80 80 120 100 115 100 ns ns ns ns Test Conditions VSS = 12 V. VCC = VSS - VDON PROGRAM = 0 V. Measure GATE1 voltage when sinking 1.0 mA. PROGRAM = 0 V. Measure GATE2 voltage when sinking 1.0 mA. PROGRAM = 0 V. Measure GATE2B voltage when sinking 1.0 mA. Measure VCC - GATE2B voltage when sourcing 1.0 mA. Measure VCC - GATE2 voltage when sourcing 1.0 mA. Measure VCC - GATE1 voltage when sourcing 1.0 mA. - - - - - - 0.15 0.18 0.18 1.65 1.65 1.65 0.8 0.8 0.8 2.0 2.0 2.0 V V V V V V Min Typ Max Unit
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CS5106
PACKAGE PIN DESCRIPTION
PACKAGE PIN # SSOP-24 1 PIN SYMBOL UVSD FUNCTION Undervoltage shutdown lead. Typically this lead is connected through a resistor divider to the main high voltage (VIN) line. If the voltage on this lead is less than 5.0 V then a fault is initiated such that GATE1, GATE2 and GATE2B go low. Overvoltage shutdown lead. Typically this lead is connected through a resistor divider to the main high voltage (VIN) line. If the voltage on this lead exceeds 5.0 V then a fault is initiated such that GATE1, GATE2 and GATE2B go low. 5.0 V reference output lead. Capable of 20 mA nominal output. If this lead falls to 4.5 V, a fault is initiated such that GATE1, GATE2 and GATE2B go low. Auxiliary error amplifier minus input. This lead is compared to 1.2 V nominal on the auxiliary error amp plus lead and represents the VSS voltage divided by ten. Auxiliary error amplifier output lead. Source current 300 A max. Output undervoltage timing capacitor lead. If the controlled output voltages of either the main or the auxiliary supply are such that either VFB1 or VFB2 is greater that 4.1 V nominal, then capacitor from OUVDELAY to ground will begin charging. If the over voltage duration is such that the OUVDELAY voltage exceeds 5.0 V, then a fault will be initiated such that GATE1, GATE2 and GATE2B will go low. Pulse by pulse over current protection lead for the auxiliary PWM. A voltage exceeding 1.2 V nominal on ILIM1 will cause GATE1 to go low. A voltage exceeding 1.4 V nominal on ILIM1 will cause GATE1 to go low for at least two clock cycles. Current Ramp Input Lead for the Auxiliary PWM. A voltage which is linear with respect to current in the primary side of the auxiliary transformer is usually represented on this lead. A voltage exceeding VFB1 - 0.13 on RAMP1 will cause GATE1 to go low. Voltage Feedback Lead for the Auxiliary PWM. A voltage which represents the auxiliary power supply output voltage is fed to this lead. A voltage less than RAMP1+0.13 on VFB1 will cause GATE1 to go low. VSS power/feedback input lead. See VCC for description of power operation. In addition, this lead is fed to a divide by ten resistor divider and compared to 1.2 V nominal at the positive side of the error amplifier. VCC power input lead. This input runs off a Zener referenced supply until VSS > VCC. Then an internal diode which runs between VSS and VCC turns on and all main power is derived from VSS. Auxiliary PWM gate drive lead. This output normally drives the FET which drives the auxiliary transformer. Ground lead. Synchronous PWM gate drive lead. This output normally drives the FET which drives the main transformer. Synchronous PWM gate drive lead. This output normally drives the FET for the gate drive transformer used for synchronous rectification. Voltage feedback lead for the synchronous PWM. A voltage which represents the main power supply output voltage is fed to this lead. A voltage less than RAMP2+0.13 on VFB2 will cause GATE2 to go low and GATE2B to go high. Current ramp input lead for the synchronous PWM. A voltage which is linear with respect to current in the primary side of the main transformer is usually represented on this lead. A voltage exceeding VFB2 - 0.13 on RAMP2 will cause GATE2 to go low and GATE2B to go high. Pulse by pulse over current protection lead for the synchronous PWM. A voltage exceeding 1.2V nominal on ILIM2 will cause GATE2 to go low and GATE2B to go high. A voltage exceeding 1.4 V nominal on ILIM2 will cause GATE2 to go low and GATE2B to go high for at least two clock cycles. GATE2, GATE2B non-overlap time adjustment lead. A 27 k resistor from DLYSET to ground sets the non-overlap time to 45 ns nominal.
2
OVSD
3 4 5 6
V5REF OAM OAOUT OUVDELAY
7
ILIM1
8
RAMP1
9
VFB1
10
VSS
11
VCC
12 13 14 15 16
GATE1 GND GATE2 GATE2B VFB2
17
RAMP2
18
ILIM2
19
DLYSET
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CS5106
PACKAGE PIN # SSOP-24 20 21 22 PIN SYMBOL FADJ SYNCOUT SYNCIN FUNCTION Frequency adjustment lead. A 27 k resistor from FADJ to ground sets the clock frequency to 512 kHz nominal. Clock output lead. This is a 50% duty cycle, 1.0 V to 5.0 V pulse whose rising edge is in phase with GATE1. This signal can be used to synchronize other power supplies. Clock synchronization lead. The internal clock frequency can be adjusted +10%, -15% by the onset of positive edges of an external clock occurring on the SYNCIN lead. If the external clock frequency is outside the internal clock frequency by +25%, -35% the external clock is ignored and the internal clock free runs. ENABLE programming input. See ENABLE for programming states. PROGRAM has at least 20 A min. of available source current. PWM enable input. If PROGRAM is HIGH then a LOW on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If PROGRAM is LOW then a HIGH on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If ENABLE is left floating, it will pull up to a HIGH level. ENABLE has at least 100 A (min) of available source current.
23 24
PROGRAM ENABLE
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OUVDELAY VCC 1.2 V
+ - +
OAOUT
-
A1 V C2
-
OAM V VREFOK G18 C3 + ENABLE Comparator VSS Restart Comparator Under Voltage Comparator Over Voltage Comparator Sync Detection G7 Freq too High G8
+ -
G3
VSS 45 k 5.0 k C4
- +
RSFF Q R F1 S Set Dominant RUN1 1.4 V V TPeriod
- +
D1 G4 P1 G5
-
Output Undervoltage Timer
Fault Latch RSFF R Q F2 S C5 Reset Dominant A2 VSS
CLK1 SYNCIN
- +
C7 100 k V 1.4 V RUN1 VREFOK Comparator
- +
G6 RUN2 OSC
CLK2 SYNCOUT IFSET IDSET
C8 +
VCC
ENABLE ENABLE VREF
+
Start Stop VREF = 5.0 V 4.5
+
-
C9 1.5 V
+
Freq too Low
V V VREFOK V A2
7.4/6.8 V
V5REF 0.13 V V 2R R RUN1 C10+
+ + - - - +
+
CS5106
RAMP1 Aux. PWM Comparator C11 G11 C12
+ -
0.13 V V
RSFF Q R F4 S Reset Dominant G10 C13
+ -
Aux. Current Limit Comparator CLOCK
Skip 2B Skip Two5 Clock Pulses BIT
V
Main Current Limit Comparator CLOCK
Skip Two Clock Pulses Skip 2B
G14
G15 G17 SET
RUN2
DELAY -
GND SET DAC
+
C15 C16- Aux. 2nd Current Threshold Comparator 1.4 V V
- +
+
C17 Main 2nd Current Threshold Comparator
ILIM1
-
RSFF Q R F3 S Q Reset Dominant
C14
+
Figure 2. Block Diagram
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Main PWM Comparator 2R R G9
VFB1
RUN2
GATE1
Driver
G13
DELAY
G12
Driver
G16
1.7 V V
+
-
+
Aux. Error Amp G1 C1 1.4 V
-
Driver
+
5.0 V
PROGRAM
V ENABLE UVSD
V
OVSD TFF Q T1 SYNCOUT DYLSET FADJ RAMP2 VFB2
SYNCIN
10
GATE2
GATE2B
ILIM2
CS5106
THEORY OF APPLICATION THEORY OF OPERATION
Powering the IC
7.5 V VREF VREF(OK), RUN1 VCC
The IC has one supply, VCC, and one Ground lead. If VSS is used for a bootstrapped supply the diode between VSS and VCC is forward biased, and the IC will derive its power from VSS. The internal logic monitors the supply voltage, VCC. During abnormal operating conditions, all GATE drivers are held in a low state. The CS5106 requires 1.5 mA nominal of startup current.
Startup
CLK1 GATE1 VFB1 RAMP1 VSS > VCC VSS RUN2 CLK2 GATE2 GATE2B VFB2 RAMP2
Assume the part is enabled and there are no over voltage or under voltage faults present. Also, assume that all auxiliary and main regulated output voltages start at 0 V. An 8.0 V, Zener referenced supply is typically applied to VCC. When VCC exceeds 7.5 V, the 5.0 V reference is enabled and the OSC begins switching. If the V5REF lead is not excessively loaded such that V5REF < 4.5 V nominal, `VREFOK' goes `high' and `RUN1' will go `high', releasing GATE1 from its low state. After GATE1 is released, it begins switching according to conditions set by the auxiliary control loop and the auxiliary supply, VSS begins to rise. When VSS > VCC + V(D1), P1 turns on and `RUN2' goes `high', releasing GATE2 and GATE2B from their low state. GATE2 and GATE2B begin switching according to conditions set by the main control loop and the main regulated output begins to rise. See startup waveforms in Figure 3.
Soft Start
Figure 3. Startup Waveforms Voltage and Current Ramp PWM Comparator Inputs (VFB1,2 and RAMP1,2 leads)
C10 and C11 are the PWM comparators for the auxiliary and main supplies. The feedback voltage (VFB) is divided by three and compared with a linear, voltage representation of the current in the primary side of the transformer (RAMP). When the output of the feedback comparator goes `high', a reset signal is sent to the PWM flip-flop and the GATE driver is driven `low'. A 130 mV offset on the RAMP leads allows the drivers to go to 0% duty cycle in the presence of light loads.
Feedback Voltage for GATE1 Driver (VFB1)
Soft Start for the auxiliary power supply is accomplished by placing a capacitor between OAOUT and Ground. The error amplifier has 200 A of nominal of source current and is ideal for setting up a Soft Start condition for the auxiliary regulator. Care should be taken to make sure that the Soft Start timing requirements are not in conflict with any transient load requirements for the auxiliary supply as large capacitors on OAOUT will slow down the loop response. Also, the Soft Start capacitor must be chosen such that during start or restart, both outputs will come into regulation before the OUVDELAY timer trips. Soft Start for the main supply is accomplished by charging Soft Start capacitor C6 through D5 and R7 at start up. After the main supply has come into regulation C6 continues to charge and is disconnected from the feedback loop by D8.
Typically the output of the auxiliary error amplifier (A1) is tied to VFB1. The VSS output is programmed to 12 V by a 10:1 resistive divider on the negative input of the error amplifier and a fixed 1.2 V reference on the positive input of the error amplifier.
Pulse by Pulse Over Current Protection and Hiccup Mode (ILIM1,2 leads)
C12 and C13 are the pulse by pulse current limit comparators for the auxiliary and main supplies. When the current in the primary side of the transformer increases such that the voltage across the current sense resistor exceeds 1.2 V nominal, the output of the current limit comparator goes
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CS5106
`high' and a reset signal is sent to the PWM flip-flop and the GATE driver is driven `low'. C16 and C17 are the second threshold, pulse by pulse current limit comparators for the auxiliary and main supplies. If the current in the primary side of the transformer increases so quickly that the current sense voltage is not limited by C12 or C13 and the voltage across the current sense resistor exceeds 1.4 V, the second threshold comparator will trip a delay circuit and force the GATE driver stage to go low and stay low for the next two clock cycles.
Undervoltage and Overvoltage Thresholds
Once this fault is triggered, the IC will restart the power supplies only if the OUVDELAY fault is reset and ENABLE or UVSD is toggled while VSS < 1.4 V. To reset the OUVDELAY fault, both the VFB inputs must be less than 4.1 V. In the application circuit shown, VFB1 is brought low by OAOUT when RUN1 stops the oscillators. VFB2 is brought low when VAUXP bleeds down and the VFB2 opto-isolator is no longer powered.
1000
100 TIME (ms)
C5 and C8 are the undervoltage and overvoltage detection comparators. Typically, these inputs are tied across the middle resistor in a three resistor divider with the top resistor to VIN and bottom resistor to Ground. The under voltage comparator has 200 mV of built in hysteresis with respect to a direct input on the UVSD lead. The under voltage comparator has its positive input referenced to 5.0 V while the over voltage comparator has its negative input referenced to 5.0 V. The output of both comparators are ORed at (G4) with the over current and enable inputs. The output of G4 feeds the input to the fault latch (F2).
PROGRAM and ENABLE Leads
10
1.0
0.1
0.01
0.1
1.0
10
100
1000
CAPACITANCE (nF)
The PROGRAM lead controls the polarity of the ENABLE lead. If the PROGRAM lead is `high' or floating, the GATE outputs will go low if the ENABLE input is tied `high' or floating. If the PROGRAM lead is tied low, the GATE outputs will go low if the ENABLE input is tied `low'. If the part is then enabled after switching the outputs low, the part will restart according to the procedure outlined in the "Startup" section.
FAULT Logic
Figure 4. OUVDELAY Time vs. OUVDELAY Capacitance FADJ and DLYSET Leads
If a VREF, UVSD or OVSD fault occurs at any time, G4 resets the fault latch (F2). RUN1 goes low and all gate drivers cease switching and return to their `low' state. When RUN1 goes low, the output of the auxiliary op-amp (A1) discharges the Soft Start capacitor and holds it low while RUN1 is low. If the fault condition is removed before the OUVDELAY timer is tripped, the IC will restart the power supplies when VSS < 1.4 V. If the OUVDELAY timer trips, the power supply must be restarted as explained in the following section.
Output Undervoltage Delay Timer for the Main and Auxiliary Regulated Outputs
Amplifier A2 and transistor N3 create a current source follower whose output is FADJ. An external resistor from FADJ to ground completes the loop. The voltage across the resistor is set by a buffered, trimmed, precision reference. In this fashion, an accurate current is created which is used to charge and discharge an internal capacitor thereby creating an oscillator with a tight frequency tolerance. For FADJ resistor value selection, see Figure 5. Transistor N2 is in parallel with N3 and is used to created an independent current across the resistor from DLYSET to ground. This current is used to program the GATE non-overlap delay blocks in the main PWM drivers. For DLYSET resistor value selection, see Figure 6.
1100 1000 900 Frequency (kHz) 800 700 600 500 400 300 200 100 0 0
C7 and C4 are the output under voltage monitor comparators for the auxiliary and main supplies. If a regulated output drops such that its associated VFB voltage exceeds 4.1 V, the output undervoltage monitor comparator goes `high' and the OUVDELAY capacitor begins charging from 0 V. A timing relation is set up by a 10 A nominal current source, the OUVDELAY capacitor and a 5.0 V fault threshold at the input of C2 (see Figure 4). If any regulated output drops and stays low for the entire charge time of the OUVDELAY capacitor, a fault is triggered and all GATE drivers will go into a low state.
10
20
30 40 50 Resistance (k)
60
70
80
Figure 5. SYNCOUT Frequency vs. FADJ Resistors
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CS5106
80 70 60 50 Time (ns) 40 30 20 10 0 0 5 10 15 20 25 30 35 Resistance (k) 40 45 50
are in synchronized operation, the synchronized supplies will stop and restart free running. If the SYNCIN signal drifts out of frequency specification while the power supplies are in synchronized operation, the synchronized supplies will begin to free run without restarting.
Slope Compensation
Figure 6. GATE Non-Overlap Time vs. DLYSET Resistance Oscillator
The oscillator generates two clock signals which are 180 degrees out of phase with respect to time. One clock signal feeds the main driver and the other feeds the auxiliary driver. Because the drivers are never turned on at the same time, ground noise and supply noise is minimized. The clock signals are actually 100 ns pulse spikes. These spikes create a narrow driver turn-on window. This narrow window prevents the driver from spurious turn on in the middle of a clock cycle. The oscillator can be synchronized by an external clock (slave) or drive the clocks of other controllers (master). See Figure 7 for the relationship between SYNC, CLK, and GATE waveforms.
SYNCIN CLK1 GATE1 CLK2 SYNCOUT
DC-DC converters with current mode control require slope compensation to avoid instability at duty cycles greater than 50%. A slope is added to the current sense waveform (or subtracted from the voltage waveform) that is equal to a percentage (75% typical) of the down slope of the inductor current. In the application diagram shown, the bootstrap (flyback) transformer inductance can be chosen so that the duty cycle never exceeds 50% and therefore does not require slope compensation. The buck indicator in the forward converter would typically be chosen to work in continuous conduction mode with a maximum duty cycle of 50-60% and would require slope compensation. Slope compensation is accomplished as follows: R9 and C9 form a ramp waveform rising each time GATE 2 turns on. C9 is discharged through D3 to the same level each cycle regardless of duty cycle. R10 and R11 are chosen to control the amount of slope compensation. C10 provides filtering for noise and turn-on spikes. To calculate the required slope compensation, calculate the buck indicator down current and the corresponding voltage slope at the current sense resistor - R12. The buck inductor down slope is:
Inductor_Slope + VOUT ) VQ5 A ms L1(mH)
The equivalent down slope at the current sense resistor for this application circuit is:
Slope @ R12 + Inductor_Slope NST2 NPT2 NPT3 NST3 V R12 ms
GATE2 GATE2B
After choosing R9 and C9 to generate a ramp with a time constant of about 5 times the oscillator period, R10 and R11 can be chosen for the voltage at RAMP2 to be 1.75 of the voltage across R12.
Synchronous Rectification
Figure 7. SYNC, GATE and CLOCK Waveforms SYNCIN and SYNCOUT Leads
Multiple supplies can be synchronized to one supply by using the SYNC leads. The SYNCIN and SYNCOUT pulses are always 180 degrees out of phase. The SYNCIN input is always in phase with the clock signal for the main driver and the SYNCOUT output is always in phase with the clock signal for the auxiliary driver. If the IC is being used as a slave, the incoming frequency must be within +10%, -20% of the programmed frequency set by its own FADJ resistor. If the frequency on the SYNCIN lead is outside the internal frequency by +25%, -35%, the SYNCIN input will be ignored. If the SYNC signal stops while the power supplies
Synchronous rectification was chosen to reduce losses in the forward converter. Improvements in efficiency will be most significant in low voltage, medium and high current converters where improvement in conduction loss offsets any added losses for gate drive. In the application circuit Q4 is turned on and off by the forward transformer. Q5 is turned on and off through pulse transformer T4 and the gate driver formed by Q6 and Q7. Because Q4 and Q5 are driven through different types of components, differences in propagation delay must be considered. The DLYSET resistor should be chosen to avoid shoot-through or excessive off time.
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CS5106
Gate Drive Capability Design Considerations
All GATE drive outputs have nominal peak currents of 0.5A. See Figures 8 and 9 for typical rise and fall times.
70 60 Rise Time 50 Time (ns) 40 30 20 10 0 50 200 500 1000 1500 Load Capacitance (pF) 2000 Fall Time
The circuit board should utilize high frequency layout techniques to avoid pulse width jitter and false triggering of high impedance inputs. Ground plane(s) should be employed. Signal grounds and power grounds should be run separately. Portions of the circuit with high slew rates or current pulses should be segregated from sensitive areas. Shields and decoupling capacitors should be used as required. Special care should be taken to prevent coupling between the SYNC leads and the surrounding leads. Depending on the circuit board layout and component values, decoupling capacitors or reduction in resistor values might be required to reduce noise pick-up on the FADJ and DLYSET resistors. Decoupling capacitors or active pull-up/down might be required to prevent false triggering of the ENABLE and PROGRAM leads.
Figure 8. Typical GATE2, 2B Switching Times
70 60 50 Rise Time Time (ns) 40 30 20 10 0 50 200 500 1000 1500 Load Capacitance (pF) 2000 Fall Time
Figure 9. Typical GATE1 Switching Times
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CS5106
PACKAGE DIMENSIONS
SSOP-24 SW SUFFIX CASE 940D-03 ISSUE D
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 8.07 8.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.44 0.60 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.317 0.328 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.017 0.024 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
K
24 PL REF
0.12 (0.005)
M
TU
S
V
S
L/2 L
PIN 1 IDENT
24
13
J B -U-
1
12
A -V- 0.20 (0.008)
M
N M
TU
S
N F DETAIL E -W-
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SSOP-24 23 117 Unit C/W C/W
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CCCC EEEE CCCC EEEE CCCC
K1 SECTION N-N
K
J1
0.25 (0.010)
CS5106
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CS5106/D

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