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YTD423
IHDLC2
ISDN BRI controller with B-ch HDLC controllers
1 INTRODUCTION
YTD423 is a high-performance communication LSI for the ISDN BRI user-network interface function (digital four-wire time-division full-duplex operation), supporting D-channel layer 1, layer 2 and HDLC controller for Bchannels, all in one 100-pin SQFP chip. YTD423 supports layer 1 (physical layer) control function conforming to ITU-T Recommendation I.430 and fully supports layer 2 (LAP-D protocol) function conforming to ITU-T Recommendations Q.920 and Q.921. ETSI (European Telecommunications Standards Institute) and several North American standard operating modes are also supported. In addition, YTD423 includes layer 3 processor interface function and 2-channel HDLC controller for B-channels, which operate in DMA transfer mode or I/O transfer mode. This gives a great advantage to mounting and functional designing of both \active" (with CPU on board) terminal equipment and \passive" (no CPU on board) PC cards. In order to support the U interface, YTD423 has a TTL interface (no built-in analog driver/receiver) suitable for connecting to an NT1 chip or a DSU module. S/T reference point can also be supported by connecting it to YTD421 (analog driver/receiver LSI).
1.1 Features
1. Layer 1 function Supports layer 1 control function conforming to ITU-T Recommendation I.430 [1992 edition] and TTC Standard JT-I430 [1993 edition] (default) { TTL interface { 192 kbps transmission rate { Interface structure : 2B + D (B = 64 kbps, D = 16 kbps) { Frame assembling and disassembling function { Collision control (built-in random number (Ri) reset), priority control (built-in retransmission control), and state transition control { Programmable T3 and T4 timers
YTD423D CATALOG CATALOG No.:4TD423D2 1999.2
Internal clock mode: Inputs/outputs the B-channel data with 64 k, 56 k or 32 kHz internal clock { External clock mode (PCM Highway mode): Inputs/outputs the B channel data with a 128 kHz to 2048 kHz external clock B channel selection function { Internal clock mode: Selects/switches B channel I/O pins { External clock mode (PCM Highway mode): Selects/switches B channel time slots Multiframing capability Abundant Test functions (for testing and maintenance) { Three kinds of loop-back modes (Loop-back 1 to 3) { INFO signals output for testing { Test pulse output for pulse shape evaluation INFO1 transmission and INFO4 reception monitor pins SLEEP monitor pin I.430 transmission frame phase adjustment function 2. Layer 2 function Conforms to ITU-T Recommendation Q.920 and Q.921 [1992 edition] and TTC Standard JT-Q920 and JT-Q921 [1993 edition] (default) { HDLC frame control (Flag control, FCS generation/checking, automatic zero insertion/deletion, abort pattern transmission/detection, etc.) { LAP-D status control (sequence control, ow control, SAPI control) { Built-in timer for time-out check Supports ETSI ETS 300 125 [September 1991], National ISDN-1/2, AT&T 5ESS 5E9 and Nortel DMS100 S208-6 operating modes Multi-link capability (circuit switching, packet switching) Automatic assigned TEI/non-automatic assigned TEI (VC/PVC) Leased line mode (disable layer 2 function) 3. Layer 3 interface function Connects to 8-bit or 16-bit microprocessor (8086 family, Z80 family, 6800 family and 68000 family) Operates in one of two data transfer modes { DMA transfer mode (with the built-in 24-bit address DMA controller) { I/O transfer mode (with the built-in FIFO) Primitive logical interface
{
Supports ETSI ETS 300 012 [April 1992] and ANSI T1.605 operating modes Leased line capability (JT-I430-a) B channel I/O clock selection function
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4. HDLC controller for B-channels HDLC frame control (Flag control, optional marks or ags in idle state, optional FCS generation/checking, automatic zero insertion/deletion, abort pattern transmission/detection, optional address eld generation/checking etc.) Full-duplex communication 2 2 channels Data rates Network synchronization clock mode : 56 k or 64 kbps Network independent clock mode : Up to 128 kbps Optional 16-bit/32-bit CRC Programmable data transfer modes { DMA transfer mode (with the built-in DMA controller) 3 optional 8-bit/16-bit access 3 24-bit address 3 4 channels { I/O transfer mode (with the built-in FIFO) 3 Tx FIFO : 32 bytes 2 2 3 Rx FIFO : 64 bytes 2 2 3 Variable interrupt levels 3 Byte/Word access selection Optional transparent mode (disable HDLC controller function) 5. Low-power operation (the host processor clock control function, LSI internal clock freezing function) 6. CMOS technology 7. 100-pin SQFP 8. Single +5V volt supply
1.2 Applications

Terminal Adapter (TA) Router ISDN PC Card PBX ISDN Telephone
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2 BLOCK DIAGRAM
2.1 User Network Interface Block Diagram
YTD423 is the most-suited LSI for terminal equipment such as terminal adapters and ISDN telephones and for PHS base stations. YTD423 contains layer 1 and layer 2 functions as well as the HDLC controller and DMA controller for the B channel. Because of this, terminal equipment can be optimally congured by adding few circuits such as the layer 3 control processor and analog driver/receiver. The block diagram of the user network interface with YTD423 is shown in Figure 1.
S T U
ISDN Network
TE1 (ISDN terminal)
NT2 (PBX etc.)
NT1 (DSU)
R
TE2
S
(Non-ISDN terminal) TA(Terminal Adapter)
S/T
TE1 TE2
R
YTD423 U YTD421 (Driver / Receiver) YTD428 (DSU)
S/T
TE1
TA with built-in DSU
User's premises
Figure 1: User Network Interface Block Diagram
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2.2 YTD423 Peripheral LSI Interface Block Diagram
B1 , B2 HRD LRD HTD LTD
YTD421
or
YTD423
A0 ~ A23 D0 ~ D15 CS CS
Memory
A0 ~ A23 D0 ~ D7 R/W CS
Peripheral LSI
A0 ~ A23 D0 ~ D15
YTD428
Figure 2: Peripheral LSI Interface Block Diagram
CLK
Decoder
System address bus (A0 ~ A23)
System data bus (D0 ~ D15)
Control signal bus
A0 ~ A23
D0 ~ D15
MPU
(8086 , 68000 etc.)
System interrupt controller
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6
M,S,FA bit SYNC HW/B1, B2 bit CH-A HDLC frame disassembly DPLL Internal block Multiframe control Frame synchronization HRD LRD Frame disassembly CH-A HDLC frame assembly CH-A HDLC frame disassembly CH-A HDLC frame assembly Bch interface B D HDLC frame disassembly Priority, collision control Buffer B D HDLC frame assembly Buffer Internal bus FA bit Layer 2 control block Layer 3 interface block Clock generator Buffer Buffer Buffer Buffer Internal controller Microprocessor bus MPU interface Bch DMAC
2.3 YTD423 Internal Block Diagram
Figure 3: Internal Block Diagram
B channel control block
Register
Buffer
D, E Layer 1 control block HTD LTD Frame assembly S Q
Dch DMAC
3 Pin Assignments
CL56K DRD CLKR CLKX DXD CLKSEL CL128K/CL8K EXTCLK/CL64K TBHW/RB2 RBHW/RB1 VSS VDD TSYNC/TB2 RSYNC/TB1 AEN A23 A22 A21 A20 A19 A18 A17 A16 VSS A15 CL32K CL4K VSS RM HTD LTD HRD LRD PDOWN INF4 INF1 TEST1 RESET VDD VSS X2 X1 CKOSEL CLKOUT PDSEL PDET PSDET WAKEUP TEST2 CS 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
R/W /WR MWR VSS AS/RD MRD INT BGACK BG/HLDAK BR/HLDRQ DTACK/READY 80/68 16/8 VDD SYSCLK VSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
YTD423-S 100pin SQFP
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 VSS VDD A4 A3 A2 A1 A0/LBE UBE D15 D14 D13 D12 VSS D11 D10
Figure 4: YTD423-S (100-pin SQFP) Pin Assignments
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4 ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Ratings
Supply Voltage Input Voltage Operating Temperature Storage Temperature (Based on VSS = 0.0 V)
4.2
Parameter
Symbol
VDD VIN Top Tstg
Min.
00:3 00:3 020 050
+7.0 VDD +0.3 +70 +125
Max.
Units
V V C C
Recommended Operating Conditions
Supply Voltage Operating Temperature
5 V 6 5 % (Based on VSS = 0.0V) 020 - 70 C
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4.3
DC Characteristics
(VDD = 5 V 6 5%, Top = 020 - 70 C) High-Level Input Voltage (CMOS) Low-Level Input Voltage (CMOS) High-Level Input Voltage (TTL) Low-Level Input Voltage (TTL) High-Level Output Voltage (CMOS) Low-Level Output Voltage (CMOS) High-Level Output Voltage (TTL) Low-Level Output Voltage (TTL) Low-Level Output Voltage (Open-D) Leakage Current O-State Leakage Current Power Supply Current
Note 1: Parameter Symbol
VIH VIL VIH VIL VOH VOL VOH VOL VOL IL ILZ IDD
jIOH j < 10A jIOL j < 10A
Condition (Note (Note (Note (Note
1) 1) 2) 2)
0.8VDD 2.2 VDD 00:4 2.7
Min.
Typ.
Max.
Units
0.2VDD 0.8 VSS +0.4 0.4 0.4 10 10
(Note 3) (Note 3) (Note 4) (Note 5) (Note 6) (Note 7)
010 010
17 0.2
mA mA
A A
V V V V V V V V V
With respect to X1,RESET, TEST1, TEST2, WAKEUP, PDET, CLKSEL, PSDET pins. Note 2: With respect to other pins. Note 3: CLKOUT pin Test condition: IOH = -1.0 mA, IOL = 2.0 mA other output pins Test condition: IOH = -0.4 mA, IOL = 1.2 mA Note 4: HTD, LTD, INT pin Test condition : IOL = 1.2 mA INF1 pin Test condition : IOL = 3 mA RBHW pin Test condition : IOL = 0.8 mA, RL = 500
Note 5: With respect to cases in which D0-D15, A0-A23, and UBE pins are in the input state and MWR and MRD pins are in Hi-Z state. Note 6: RUN state (SYSCLK = 8 MHz) Note 7: SLEEP state
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5 PACKAGE OUTLINE
(Note)
The LSIs for surface mount need special consideration on storage and soldering conditions. For detailed information, please contact your nearest Yamaha agent.
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IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. Yamaha assumes no liability for incidental , consequential, or special damages or injury that may result from misapplication or improper use or operation of the Products. 4. Yamaha makes no warranty or representation that the Products are subject to intellectual property license from Yamaha or any third party, and Yamaha makes no warranty excludes any liability to the Customer or any third party arising from or related to the Products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. Examples of use described herein are merely to indicate the characteristics and performance of Yamaha products. Yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. Yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, fitness for a particular use and title.
The specifications of this product are subject to improvement changes without prior notice.
AGENCY
Address inquiries to: Semiconductor Sales & Marketing Department Head Office 203, Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192 Electronic Equipment Business section Tel. 81-539-62-4918 Fax. 81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. 81-3-5488-5431 Fax. 81-3-5488-5088 Namba Tsujimoto Nissei Bldg, 4F 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. 81-6-6633-3690 Fax. 81-6-6633-3691 YAMAHA Systems Technology. 100 Century Center Court, San Jose, CA95112 Tel. 1-408-467-2300 Fax. 1-408-437-8791
Tokyo Office Osaka Office
U.S.A. Office
All rights reserved (c) 1999

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