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IT8711F
Low Pin Count Input / Output (LPC I/O) Preliminary Programming Guide V0.1
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Notice: The information provided in this publication is believed to be accurate. Integrated circuits sold by ITE are covered by the warranty and patent indemnification provisions stipulated in the terms ITE Terms and Conditions of Sale, as revised from time to time. ITE makes no warranty, expressed, statutory, implied, or by description, regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement, except as specifically provided in the ITE Terms and Conditions of Sale. Furthermore, ITE makes no warranty of merchantability or fitness for any purpose. ITE reserves the right to halt production or modify specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the specification and other information included in this publication is current before placing product orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environment or reliability requirements (e.g., military equipment or medical life-support equipment) are specifically not recommended without additional processing by ITE for such applications. All trademarks are the sole property of their respective owners.
To find out more about ITE, visit our World Wide Web site at: http://www.ite.com.tw http://www.iteusa.com Copyright (c) ITE, Inc. 2001 THE TERMS AND CONDITIONS IN THE BACK OF THIS DOCUMENTATION GOVERN ALL SALES BY ITE. ITE WILL NOT BE BOUND BY ANY TERMS INCONSISTENT WITH THESE UNLESS ITE AGREES OTHERWISE IN WRITING. ACCEPTANCE OF BUYER' ORDER SHALL BE BASED ON THESE TERMS. S
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Contents
Contents
1. Overview ............................................................................................................................................................... 1 2. Block Diagram ...................................................................................................................................................... 3 3. Pin Configuration.................................................................................................................................................. 5 4. Programming Sequence and Flow Charts ......................................................................................................... 7 4.1 Configuring Sequence Description .......................................................................................................... 7 4.2 FDC (LDN=00h) ........................................................................................................................................ 8 4.3 Serial Port 1 (LDN=01h)........................................................................................................................... 9 4.4 Serial Port 2 (LDN=02h).........................................................................................................................10 4.4.1 Serial Port 2 Configuration Registers (LDN=02h) .................................................................10 4.4.1.1 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h)....................... 10 4.4.1.2 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h)........................ 10 4.4.1.3 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h) .................................10 4.4.1.4 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h)...............11 4.4.1.5 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h)...............11 4.4.1.6 Serial Port 2 Special Configuration Register 3 (Index=F2h, Default=00h)...............11 4.4.1.7 Serial Port 2 Special Configuration Register 4 (Index=F3h, Default=7Fh) .............. 12 4.5 Parallel Port (LDN=03h) .........................................................................................................................14 4.5.1 SPP and EPP Modes .............................................................................................................. 14 4.6 SWC (LDN=04h).....................................................................................................................................17 4.7 Keyboard (LDN=05h).............................................................................................................................. 17 4.8 Game Port (LDN=08h) ........................................................................................................................... 20 4.8.1 Game Port (Base+0h) ............................................................................................................. 22 4.9 CIR (LDN=09h) ....................................................................................................................................... 22 4.10 MIDI (LDN=0Ah) .....................................................................................................................................25
Figures
Figure 4-1. Enter the MB PnP Mode Flow Chart ..................................................................................................... 7 Figure 4-2. FDC Control Flow Chart......................................................................................................................... 8 Figure 4-3. Serial Port Control Flow Chart............................................................................................................... 9 Figure 4-4. Smart Card Operating Sequence Example ........................................................................................ 12 Figure 4-5. Flow Chart for IT8711F Smart Card Reader ......................................................................................13 Figure 4-6. Select Parallel Port Modes Flow Chart ............................................................................................... 16 Figure 4-7. KBC Command Byte Register Test Flow Chart ................................................................................. 19 Figure 4-8. Game Port Register.............................................................................................................................. 20 Figure 4-9. Game Port I/O Flow Chart ................................................................................................................... 21 Figure 4-10. CIR RX Flow Chart............................................................................................................................. 23 Figure 4-11. CIR TX Flow Chart ............................................................................................................................. 24 Figure 4-12. MIDI I/O Flow Chart............................................................................................................................ 26
Tables
Table 4-1. FDC Configuration Registers.................................................................................................................. 8 Table 4-2. Serial Port 1 Configuration Registers ..................................................................................................... 9
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IT8711F Programming Guide
Table 4-3. Serial Port 2 Configuration Registers................................................................................................... 10 Table 4-4. Parallel Port Configuration Registers ................................................................................................... 14 Table 4-5. Address Map and Bit Map for SPP and EPP Modes .......................................................................... 14 Table 4-6. Bit Map of the ECP Registers ...............................................................................................................15 Table 4-7. ECP Register Definitions....................................................................................................................... 15 Table 4-8. ECP Mode Descriptions ........................................................................................................................ 15 Table 4-9. SWC Configuration Registers ...............................................................................................................17 Table 4-10. Keyboard Configuration Registers...................................................................................................... 17 Table 4-11. Data Register READ/WRITE Controls ............................................................................................... 18 Table 4-12. Status Register .................................................................................................................................... 18 Table 4-13. Game Port Configuration Registers ................................................................................................... 20 Table 4-14. Consumer IR Configuration Registers ............................................................................................... 22 Table 4-15. MIDI Port Configuration Registers...................................................................................................... 25
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Overview
1. Overview
The IT8711F is a LPC Interface based highly integrated Super I/O. The IT8711F provides the most commonly used legacy Super I/O functionality The device' LPC interfa ce complies with Intel "LPC Interface s Specification Rev. 1.01". The IT8711F meets the "Microsoft (R) PC98/PC99/PC2001 System Design Guide" requirements and is ACPI compliant. Features include one high-performance 2.88MB floppy disk controller, with digital data separator, supporting one 360K/720K/1.2M/1.44M/2.88M floppy disk drive. One multi-mode high-performance parallel port features the bi-directional Standard Parallel Port (SPP), the Enhanced Parallel Port (EPP V.1.7 and EPP V.1.9 are supported), and the IEEE 1284 compliant Extended Capabilities Port (ECP). Two 16C550 standard compatible enhanced UARTs perform asynchronous communication, and support SIR. The Smart Card Interface is internally connected to UART2. The Keyboard Controller, Consumer IR, MIDI and Game Port are also supported. These 9 logical devices can be individually enabled or disabled via software configuration registers. The IT8711F utilizes power-efficient circuitry to reduce power consumption. Once a logical device is disabled, the inputs are gated inhibit, the outputs are TRI-STATE and the input clock is disabled. The IT8711F requires a single 24/48 MHz clock input and operates with a +3.3V power supply. The IT8711F is available in 100-pin QFP (Quad Flat Package).
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IT8711F Programming Guide V0.1 Dec. 27, 2001
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IT8711F Programming Guide V0.1
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Block Diagram
2. Block Diagram
LPC Bus
24/48 MHz Clock
Clock Gen.
LPC Interface
Floppy Disk Controller
PCI PME#
Consumer IR Interface Serial Port 1 Interface Parallel Port Interface Serial Port 2 or SCR or SIR
Consumer IR
Floppy Drive Interface Keyboard/ Mouse Interface Game Interface I/O Ports
16C550 UART1 IEEE1284 Parallel Port 16C550 UART2 or SCR
Central Interface Bus
Keyboard Controller Game General Purpose I/O MIDI
MIDI
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Pin Configuration
3. Pin Configuration
JVR/GP61 JACX/GP50 JACY/GP51 JBCX/GP52 JBCY/GP53 JAB1/GP54 JAB2/GP55 JBB1/GP56 JBB2/GP57 VCC DSR1# SOUT1/JP3 SIN1 RTS1#/JP2 DTR1#/JP1 DCD1# RI1# CTS1# PD7 PD6 DCD2#/GP62 SIN2/GP63 GND RI2#/GP10 CTS2#/GP11 DTR2#/GP12 RTS2#/GP13 DSR2#/GP14 SOUT2/GP15 GA20/GP16 KRST#/GP17 KCLK/GP20 KDAT/GP21 MCLK/GP22 MDAT/GP23 PWBTIN#/GP24 PWBTOUT#/GP25 SLPSX#/GP26 PWRCTL#/GP27 VID0/GP30 VID1/GP31 VID2/GP32 VID3/GP33 VID4/GP34 GP35* GP36* VCCH GND VBAT KBLK#/CIRTX/GP40* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
IT8711F 100-QFP
PD5 PD4 GND PD3 PD2 PD1 PD0 STB# AFD# ERR# INIT# SLIN# BUSY ACK# SLCT PE WPT# INDEX# TRK0# DSKCHG# RDATA# DIR# WGATE# HDSEL# STEP# WDATA# VCC GND CLKIN DRVA#
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CIRRX/GP41* IRTX/GP42* IRRX/GP43* PME# SCPSNT#/GP44 SCRST/GP45 SCPWR/GP46 SCCLK/GP47 SCIO/GP60 LDRQ# LFRAME# LRESET# SERIRQ LAD0 LAD1 LAD2 LAD3 PCICLK DENSEL# MTRA#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Programming Sequence and Flow Charts
4. Programming Sequence and Flow Charts
4.1 Configuring Sequence Description
Hardware Reset
Any other I/O transition cycle
Wait for key string
N
I/O write to 2Eh (or 4Eh)
Is the data "87h" ?
Y
Wait for next data
Any other I/O transition cycle
I/O write to 2Eh (or 4Eh) N
"87h"?
Y
MB PnP Mode
Figure 4-1. Enter the MB PnP Mode Flow Chart (1) Enter the MB PnP Mode To enter the MB PnP Mode, 2 specific I/O write operations (87h) must be performed during the " Wait for key" state. The addresses of the configuration Index/Data register pair are determined by the power-on strapping of pin 89 (JP3). 2Eh/2Fh is selected when the power-on strapping value of this pin is high (internal pull-up resistor); 4Eh/4Fh is selected when the power-on strapping value of this pin is low (external pull-down resistor). (2) Modifying the Data of the Registers All configuration registers can be accessed after the MB PnP Mode is accessed. Before accessing a selected register, the content of Index 07h must be changed to the LDN to which the register belongs, except some Global registers. (3) Exiting the MB PnP Mode Set bit 1 of the configure control register (Index=02h) to "1" to exit the MB PnP Mode.
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IT8711F Programming Guide V0.1
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IT8711F Programming Guide
FDC (LDN=00h) Table 4-1. FDC Configuration Registers LDN 00h 00h 00h 00h 00h 00h 00h Index 30h 60h 61h 70h 74h F0h F1h R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 03h F0h 06h 02h 00h 00h FDC Activate FDC Base Address MSB Register FDC Base Address LSB Register FDC Interrupt Level Select FDC DMA Channel Select FDC Special Configuration Register 1 FDC Special Configuration Register 2 Configuration Register or Action
4.2
Go in Configuration out 2e 87 out 2e 87
Set LDN=00h out 2e 07 out 2f 00 Get FDC base address out 2e 60 in 2 f out 2e 61 in 2 f
Set FDC Command
Read, Write...
Figure 4-2. FDC Control Flow Chart www.ite.com.tw www.iteusa.com 8 IT8711F Programming Guide V0.1
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Programming Sequence and Flow Charts
4.3
Serial Port 1 (LDN=01h) Table 4-2. Serial Port 1 Configuration Registers
LDN 01h 01h 01h 01h 01h
Index 30h 60h 61h 70h F0h
R/W R/W R/W R/W R/W R/W
Default 00h 03h F8h 04h 00h
Configuration Register or Action Serial Port 1 Activate Serial Port 1 Base Address MSB Register Serial Port 1 Base Address LSB Register Serial Port 1 Interrupt Level Select Serial Port 1 Special Configuration Register
Go in Configuration out 2e 87 out 2e 87
Set LDN=01h out 2e 07 out 2f 01 Get Serial port 1 base address out 2e 60 in 2 f out 2e 61 in 2 f
Set Read or Write Command
Read, Write...
Figure 4-3. Serial Port Control Flow Chart
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IT8711F Programming Guide
Serial Port 2 (LDN=02h) Table 4-3. Serial Port 2 Configuration Registers LDN 02h 02h 02h 02h 02h 02h 02h 02h Index 30h 60h 61h 70h F0h F1h F2h F3h R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 02h F8h 03h 00h 50h 00h 7Fh Configuration Register or Action Serial Port 2 Activate Serial Port 2 Base Address MSB Register Serial Port 2 Base Address LSB Register Serial Port 2 Interrupt Level Select Serial Port 2 Special Configuration Register 1 Serial Port 2 Special Configuration Register 2 Serial Port 2 Special Configuration Register 3 Serial Port 2 Special Configuration Register 4
4.4
4.4.1
Serial Port 2 Configuration Registers (LDN=02h)
4.4.1.1 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h) Bit Description 7-4 Read only with "0h" for Base Addresses [15:12]. 3-0 Read/write, mapped as Base Addresses [11:8]. 4.4.1.2 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h) Bit Description 7-3 Read/write, mapped as Base Addresses [7:3]. 2-0 Read only as "000b." 4.4.1.3 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h) Bit Description 7-4 Reserved with default "0h." 3-0 Select the interrupt level Note1 for Serial Port 2. Note 1: Interrupt level mapping Fh-Dh: not valid Ch: IRQ12 . . 3h: IRQ3 2h: not valid 1h: IRQ1 0h: no interrupt selected
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Programming Sequence and Flow Charts
4.4.1.4 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h) Bit Description 7-1 Reserved 0 S2_IRQ_SHR (Serial Port 2 Interrupt Request Sharing) 0: Normal (default). 1: Enable S2 IRQ sharing. 4.4.1.5 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h)
Bit Description 7 IR_R2T_DLY (IR RX to TX Delay Mode) 0: Transmission delays (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode. (default) 1: No transmission delays (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode. 6 IR_T2R_DLY (IR TX to RX Delay Mode) 0: Transmission delays (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode. 1: No transmission delays (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode (default). 5 Reserved with default "0b" 4 HF_DLX (Half Duplex Enable) 0: Full Duplex 1: Half Duplex (default) 3 Reserved with default "0b" 2-0 S2_MOD (Serial Port 2 Mode) 000: Standard (default) 001: IrDA SIR 010: ASKIR 100: Smart Card Reader (SCR) else: Reserved 4.4.1.6 Serial Port 2 Special Configuration Register 3 (Index=F2h, Default=00h) Bit Description 7 COM_PNP_EN 0: Disable COM Port device Plug-and-Play operation (default). 1: Enable COM Port device Plug-and-Play operation. 6-5 Reserved 4 PNP_ID This bit is only available when bit 7=1. 0: PNP_ID Access mode (default). 1: Normal Plug-and-Play operation mode. 3 Reserved 2 SCPWR_POR (SCPWR Polarity) 0: Active low (default). 1: Active high. 1-0 SCCLK_SEL1-0 (SCCLK Frequency Selection) 00: Stop (default) 01: 3.5 MHz 10: 7.1 MHz 11: Special Frequency (96 MHz/SCDIV) www.ite.com.tw www.iteusa.com 11 IT8711F Programming Guide V0.1
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IT8711F Programming Guide
4.4.1.7 Serial Port 2 Special Configuration Register 4 (Index=F3h, Default=7Fh) Bit 7 Reserved 6-0 SCDIV6-0 (SCCLK Special Divisor). H/W Reset IDLE
N
Description
Waiting for ICC Insertion
Interrupt by UART sense PRESENT#
Insert
Y
Power Up, Clock Reset Card
N1
Power up FET to 5V, then allow CLOCK out and Reset control, I/O in receive mode Active level may differ ICC responses to Answer-To-Reset within 400 - 40000 clock cycles of SCCLK, if N1, then RESET active high, if N2, then deactive
ATR
Y
Driver translates the ATR
Decoding ATR
Protocol Error
More Protocols
Y Y
If no protocol is available, then treat as all default setting; If more protocols are available, the Driver can select a suitable transfer protocol
IFD sends Protocol-Type-Selection request, and intends to change Xfer protocol
PTS Request
N N2
PTS Confirm
Change Protocol
If the ICC accepts, then returns a confirm code Both IFD and ICC changed to new compromised protocol
Transfer
N
Begin to Xfer Data
Finish
Y
For normal deactivation, the Driver controls the IFD to enter Deactive sequence Stop Clock Then power down FET
Clock Stop Power Down Emergency Remove
Remove
If users remove the ICC at any time
Figure 4-4. Smart Card Operating Sequence Example www.ite.com.tw www.iteusa.com 12 IT8711F Programming Guide V0.1
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Programming Sequence and Flow Charts
Go in I/O configuration OUT 2Eh, 87h, 87h Save original value Set LDN=01h or 02h to select UART1 or UART2 Configuration Register UART Function select: F1[2:0]=100b; Smart Card Reader F2[1:0]=01b; SCR_CLKSEL = 3.5 MHz F2[1:0]=01b; SCR_CLKSEL = 3.5 MHz Set Baud rate = 9600 1. LCR[7] = 1b 2. DLL[7:0] = 0Ch 3. DLM[7:0] = 00h 4. LCR[7] = 0b No parity; 8 data bits in width; 1 stop bit; LCR[3:0] = 0011b Enable FIFO: write FCR[0] = 1b FCR[7:6] = 00b IF FIFO is enabled, read IIR[7:6] = 11b Out2 enable; Reset SCR and generate clock; 1. MCR [3] = 1b 2. MCR[1:0] = 00b 3. MCR[1:0] = 01b 4. MCR[1:0] = 11b Wait for smart card ATR and smart card command
BIOS Level
Kernel mode driver
Figure 4-5. Flow Chart for IT8711F Smart Card Reader
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IT8711F Programming Guide
Parallel Port (LDN=03h) Table 4-4. Parallel Port Configuration Registers LDN 03h 03h 03h 03h 03h 03h 03h 03h 03h 03h Index 30h 60h 61h 62h 63h 64h 65h 70h 74h F0h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 03h 78h 07h 78h 00h 80h 07h 03h 03h
Note2
4.5
Configuration Register or Action Parallel Port Activate Parallel Port Primary Base Address MSB Register Parallel Port Primary Base Address LSB Register Parallel Port Secondary Base Address MSB Register Parallel Port Secondary Base Address LSB Register POST Data Port Base Address MSB Register POST Data Port Base Address LSB Register Parallel Port Interrupt Level Select Parallel Port DMA Channel Select
Note1
Parallel Port Special Configuration Register
Note 1: When the ECP mode is not enabled, this register is read only as "04h", and cannot be written. Note 2: When the bit 2 of the Primary Base Address LSB Register of Parallel Port is set to 1, the EPP mode cannot be enabled. Bit 0 of this register is always 0. 4.5.1 SPP and EPP Modes Table 4-5. Address Map and Bit Map for SPP and EPP Modes Register Data Port Status Port Control Port EPP Address Port Address Base 1+1h R/W RO D0 PD0
TMOUT
D1 PD1 1 AFD PD1 PD1 PD1 PD1 PD1
D2 PD2 1 INIT PD2 PD2 PD2 PD2 PD2
D3 PD3
D4 PD4
D5 PD5 PE PD5 PD5 PD5 PD5 PD5
D6 PD6 1 PD6 PD6 PD6 PD6 PD6
D7 PD7 1 PD7 PD7 PD7 PD7 PD7
Mode SPP/EPP SPP/EPP EPP EPP EPP EPP EPP
Base 1+0h R/W Base 1+2h R/W Base 1+3h R/W
ERR# SLCT PD3 PD3 PD3 PD3 PD3 PD4 PD4 PD4 PD4 PD4
ACK# BUSY# SPP/EPP
STB PD0 PD0 PD0 PD0 PD0
SLIN IRQE PDDIR
EPP Data Port0 Base 1+4h R/W EPP Data Port1 Base 1+5h R/W EPP Data Port2 Base 1+6h R/W EPP Data Port3 Base 1+7h R/W
Note 1: The Base address 1 depends on the Logical Device configuration registers of Parallel Port (0X60, 0X61).
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Programming Sequence and Flow Charts
Table 4-6. Bit Map of the ECP Registers
Register data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr
D7 PD7 Addr/RLE nBusy 1
D6 PD6 nAck 1
D5 PD5 PError PDDIR
D4 PD4 Select IRQE
D3 PD3 nFault SelectIn Address or RLE field
D2 PD2 1 nInit
D1 PD1 1 AutoFd
D0 PD0 1 Strobe
Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 0 0 intrValue mode 0 0 1 0 nErrIntrEn 0 0 dmaEn 0 0 ServiceIntr 0 0 full 0 0 empty
Table 4-7. ECP Register Definitions Name Data EcpAFifo Dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr Address Base 1 +000H Base 1 +000H Base 1 +001H Base 1 +002H Base 2 +000H Base 2 +000H Base 2 +000H Base 2 +000H Base 2 +001H Base 2 +002H R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W ECP Mode 000-001 011 All All 010 011 110 111 111 All Function Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
Table 4-8. ECP Mode Descriptions Mode 000 001 010 011 110 111 Standard Parallel Port Mode PS/2 Parallel Port Mode Parallel Port FIFO Mode ECP Parallel Port Mode Test Mode Configuration Mode Description
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IT8711F Programming Guide
Go in Configuration out 2e 87 out 2e 87
Set LDN = 03h out 2e 07 out 2f 03 Get Parallel Port base address out 2e 60 in 2 f out 2e 61 in 2 f
Set SPP Mode out 2e f 0 out 2f 00
Select SPP, EPP or ECP Mode?
Select ECP Mode out 2e f 0 out 2f 02 Set DMA 3 out 2e 74 out 2f 03
Set EPP Mode out 2e f 0 out 2f 01
Read, Write...
Figure 4-6. Select Parallel Port Modes Flow Chart
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Programming Sequence and Flow Charts
4.6
SWC (LDN=04h) Table 4-9. SWC Configuration Registers
LDN 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h
Index E0h E1h E2h E3h E4h E5h E6h E7h F0h F1h F2h F3h F4h F5h F6h
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Power-Well Default VSB VSB VSB VSB VSB VSB VSB VSB VPP VPP VPP VPP VPP VPP
Note
Configuration Register or Action SWC Status Register 1 SWC Status Register 2 SWC_STS1 to PME during VCC ON Enable Register SWC_STS2 to PME during VCC ON Enable Register SWC_STS1 to PME during VCC OFF Enable Register SWC_STS1 to SMI during VCC ON Enable Register SWC_STS2 to SMI during VCC ON Enable Register SWC_STS1 to SMI during VCC OFF Enable Register Power ON Event Enable Register Power ON Status Register Power ON Control Register Reserved SWC Miscellaneous Control Register SWC Special Code Index Register SWC Special Code Data Register
--00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h -
VSB
Note Note Note Note Note
Note: VPP is supported by VSB when VSB is present, and is supported by VBAT when VSB is not present. 4.7 Keyboard (LDN=05h) Table 4-10. Keyboard Configuration Registers LDN 05h 05h 05h 05h 05h 05h 05h 05h Index 30h 60h 61h 62h 63h 70h 71h F0h R/W R/W R/W R/W R/W R/W R/W ROR/W R/W Default 00h 60h 00h 64h 01h 02h 00h Configuration Register or Action KBC Data Base Address MSB Register KBC Data Base Address LSB Register KBC Command Base Address MSB Register KBC Command Base Address LSB Register Keyboard Interrupt Level Select Keyboard Interrupt Type
Note
00h or 01h Keyboard Activate
KBC Special Configuration Register
Note: The register is read only unless the write enable bit (Index=F0h) is asserted.
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IT8711F Programming Guide
Table 4-11. Data Register READ/WRITE Controls Host Address 60h 60h 64h 64h
Note
R/W* RO WO RO WO
Function READ DATA WRITE DATA, (Clear F1) READ Status WRITE Command, (set F1)
Table 4-12. Status Register 7 ST7 6 ST6 5 ST5 4 ST4 3 F1 2 F0 1 IBF 0 OBF
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Programming Sequence and Flow Charts
Save 8259 IMR Save LED status
Get master IMR (21h) Disable keyboard interrupt Send Write keyboard command (60h)
No Set first test pattern 256 bytes
Read Keyboard command (20h) Out data to Buffer No
Check DATA 256 bytes?
Fail
Yes
KBC is ok!
KBC fails!
Figure 4-7. KBC Command Byte Register Test Flow Chart
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IT8711F Programming Guide
Game Port (LDN=08h) Table 4-13. Game Port Configuration Registers LDN 08h 08h 08h Index 30h 60h 61h R/W R/W R/W R/W Default 00h 02h 01h Configuration Register or Action Game Port Activate Game Port Base Address MSB Register Game Port Base Address LSB Register
4.8
GAME PORT REGISTERS
R/W Bit 7 B - #2 Button
Bit 6
B - #1 Button Digital Input
Bit 5
A - #2 Button
Bit 4
B - #1 Button
Bit 3
B - Y Coordinate
Bit 2
B - X Coordinate Resistive Input
Bit 1
A - Y Coordinate
Bit 0
A - X Coordinate
Figure 4-8. Game Port Register www.ite.com.tw www.iteusa.com 20 IT8711F Programming Guide V0.1
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Programming Sequence and Flow Charts
Go in Configuration out 2e 87 out 2e 87
Set LDN = 08h out 2e 07 out 2f 08 Get Game Port base address out 2e 60 in 2 f out 2e 61 in 2 f
Send Game Port Message
Input, Output
Figure 4-9. Game Port I/O Flow Chart The Game port integrates four timers for two joysticks. The IT8711F allows the Game Port base address to be located within the host I/O address space 100h to 0FFFh. Currently, most game software assume that the Game (or Joystick) I/O port is located at 201h. A write to the Game port base address will trigger four timers. A read from the same address returns four bits that correspond to the output from the four timers, and other four status bits corresponding to the joystick buttons will also be returned. A button value of 0 indicates that the button is pressed. When the Game port base address is written, the X/Y timer bits go high. Once the Game port base address is written, each timer output remains high for a duration of time determined by the current joystick position.
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IT8711F Programming Guide V0.1
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IT8711F Programming Guide
Game Port (Base+0h) Signal JBB2 JBB1 JBCY JBCX JAB2 JAB1 JACY JACX Description Joystick B, Button 2 (pin 56 of Joystick connector) Joystick B, Button 1 (pin 55 of Joystick connector) Joystick B, Coordinate Y (pin 54 of Joystick connector) Joystick B, Coordinate X (pin 53 of Joystick connector) Joystick A, Button 2 (pin 52 of Joystick connector) Joystick A, Button 1 (pin 51 of Joystick connector) Joystick A, Coordinate Y (pin 50 of Joystick connector) Joystick A, Coordinate X (pin 49 of Joystick connector)
4.8.1 Bit 7 6 5 4 3 2 1 0 4.9
CIR (LDN=09h) Table 4-14. Consumer IR Configuration Registers
LDN 09h 09h 09h 09h 09h
Index 30h 60h 61h 70h F0h
R/W R/W R/W R/W R/W R/W
Default 00h 03h 10h 0Bh 00h
Configuration Register or Action Consumer IR Activate Consumer IR Base Address MSB Register Consumer IR Base Address LSB Register Consumer IR Interrupt Level Select Consumer IR Special Configuration Register
a. Set CIR Registers: TX: baud rate, frequency, pulse width, pulse mode, deferral mode, RLE mode and FIFO threshold. RX: Baud rate frequency range, sync mode and FIFO threshold. b. Begin to Transmit/Receive Data: TX: Before transmitting any data, the TX FIFO must be cleared first. The device then starts to transmit one frame data into the FIFO. During data transmit, the TX FIFO byte count must be monitored closely to ensure the byte count is remained below the maximum FIFO value, for FIFO to receive further data. It is recommended to clear the FIFO data before the next frame data transmission can be started.
RX: Before transmitting any data, the RX FIFO must be cleared first. RXEN and RXEND are then enabled, and RXACT is asserted low by writing 1 to clear this bit, as illustrated in the diagram on the next page.
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IT8711F Programming Guide V0.1
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Programming Sequence and Flow Charts
Go in I/O configuration Save original value
Set LDN=09h Enable CIR, select interrupt level,clock select. Hook system interrupt.
Set RX baud rate. Set RX demodulation parameter: carrier range,sync mode. Set RX FIFO threshold.
Make sure RX FIFO is cleared. Set RCR register: RXEN and RXEND to 1.
Set RXACT to 1 to assert low. Wait data until timeout.
Interrupt mode
PIO mode or Interrupt mode?
PIO mode
Identify if Receiver data stored interrupt level is on ISR.
Poll the RSR byte count register to monitor the received data.
Read data to main memory and decode.
No
Receive data over?
Yes
Go in I/O Configuration. Disable CIR. Restore parameter.
Figure 4-10. CIR RX Flow Chart
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IT8711F Programming Guide V0.1
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IT8711F Programming Guide
Go in I/O configuration Save original value
Set LDN=09h Enable CIR, select interrupt level, clock select. Hook system interrupt.
Set TX baud rate Set TX modulation parameter: carrier frequency, pulse mode, pulse width, deferral mode. Set TX FIFO mode.
Make sure TX FIFO byte count is 0. And TXUDR bit is 1. If FIFO is not cleared again, then send data into FIFO.
Interrupt mode
PIO mode or Interrupt mode?
PIO mode
Identify if Transmitter low data level interrupt is on ISR.
Poll theTSR register if byte count left is enough.
Send next data frame to FIFO
Data all sent out?
Yes
Go in I/O Configuration. Disable CIR. Restore parameter.
Figure 4-11. CIR TX Flow Chart
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IT8711F Programming Guide V0.1
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Programming Sequence and Flow Charts
4.10
MIDI (LDN=0Ah) Table 4-15. MIDI Port Configuration Registers
LDN 0Ah 0Ah 0Ah 0Ah 0Ah
Index 30h 60h 61h 70h F0h
R/W R/W R/W R/W R/W R/W
Default 00h 03h 00h 0Ah 00h MIDI Port Activate
Configuration Register or Action MIDI Port Base Address MSB Register MIDI Port Base Address LSB Register MIDI Port Interrupt Level Select MIDI Port Special Configuration Register
The IT8711F supports the MIDI capability by incorporating hardware to emulate the MPU-401 in the UART mode. It is software compatible with MPU-401 interface, but only supports the UART mode (non-intelligent mode). The UART is used to convert parallel data to the serial data required by MIDI. The serial data format is RS-232 like: 1 start bit, 8 data bits, and 1 stop bit. The serial data rate is fixed at 31.25 Kbaud. The MPU-401 logical device occupies two consecutive I/O spaces. The device also uses an interrupt. Both the base address and the interrupt level are programmable. MIDI Base+0 is the MIDI Data port, and MIDI Base+ 1 is the Command/Status port. MIDI Data Port: The MIDI Data Port is used to transmit and receive MIDI data. When in UART mode, all transmit data is transferred through a 16-byte FIFO and receive data through another 16-byte FIFO. UART Mode: 1. All reads of the Data port, MIDI Base+0, return the next byte in the receive buffer FIFO. The serial data received from the MIDI_IN pin is stored in the receive buffer FIFO. The bit 7 RXS of the Status register is updated to reflect the new receive buffer FIFO status. The receive data available interrupt will be issued only if the FIFO has reached its programmed trigger level. The interrupts will be cleared as soon as the FIFO drops below its trigger level. The trigger level is programmable by changing bits 2-1 of the MIDI port Special Configuration Register, LDN8_F0h. All writes to the Data port, MIDI Base+0, are placed in the transmit buffer FIFO. Whenever the transmit buffer FIFO is not empty, the data bytes are read from the buffer in turn and sent out from the MIDI_OUT pin. The bit 6 TXS of the Status Register is updated to reflect the new transmit buffer FIFO status. All writes to the Command port, MIDI Base+1, are monitored and acknowledged below:
2.
3.
FFh: Set the interface into the initialization condition. The interface returns to the intelligent mode Others: No operation
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IT8711F Programming Guide V0.1
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IT8711F Programming Guide
Go in Configuration out 2e 87 out 2e 87
Set LDN=0Ah out 2e 07 out 2f 0A Enable MIDI out 2e 30 out 2f 01 Get MIDI base address out 2e 60 in 2 f out 2e 61 in 2 f
Set into UART mode out Command/Status Port, 3 f h
Send R/W Command out Data Port, Data or in Data Port, Data
Input, Output
Figure 4-12. MIDI I/O Flow Chart
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IT8711F Programming Guide V0.1
INTEGRATED TECHNOLOGY EXPRESS, INC. TERMS AND CONDITIONS OF SALE (Rev: May `98) www..com
These Terms and Conditions of Sale apply to all items designed, sold and/or made by Integrated Technology Express, Inc. ("ITE Taiwan") and/or Integrated Technology Express, Inc. ("ITE California"), and Buyer agrees they apply to all such items.
OTHERWISE). THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY REMEDY. (e) No action against Seller, whether for breach, indemnification, contribution or otherwise, shall be commenced more than one year after the cause of action has accrued, or more than one year after either the Buyer, user or other person knew or with reasonable diligence should have known of the matter or of any claim of dissatisfaction or defect involved; and no such claim may be brought unless Seller has first been given commercially reasonable notice, a full written explanation of all pertinent details, and a good faith opportunity to resolve the matter. (f) BUYER EXPRESSLY AGREES TO THE LIMITATIONS OF THIS PARAGRAPH 5 AND TO THEIR REASONABLENESS.
0.
PARTIES
ITE Taiwan is a company headquartered in the Republic of China, Taiwan, and incorporated under Taiwan law, and ITE California is a separate company incorporated under California law and headquartered in California. These two companies are independent, and, except as to the entity which invoices for goods delivered to it, Buyer holds no rights against and has no commitments from ITE California and/or ITE Taiwan. Subject to the foregoing, "Seller" refers to the entity which invoices Buyer for product, provided however that both ITE Taiwan and ITE California shall each be entitled to claim protection under paragraphs 4(b)-4(f), 5, 8, 9, 10, 11, 12 and 13 below.
1.
ACCEPTANCE OF TERMS
BUYER ACCEPTS THESE TERMS (i) BY WRITTEN ACCEPTANCE (BY PURCHASE ORDER OR OTHERWISE), OR (ii) BY FAILURE TO RETURN GOODS DESCRIBED ON THE FACE OF THE PACKING LIST WITHIN FIVE DAYS OF THEIR DELIVERY.
6.
SUBSTITUTIONS AND MODIFICATIONS
2.
DELIVERY
(a) Delivery will be made Free Carrier (Incoterms), Seller's warehouse, Science-Based Industrial Park, Taiwan (if Seller is ITE Taiwan or ITE California) or Santa Clara, California (if Seller is ITE California). (b) Title to the goods and the entire risk will pass to Buyer upon delivery to carrier. (c) Shipments are subject to availability. Seller shall make every reasonable effort to meet the date(s) quoted or acknowledged; and if Seller makes such effort, Seller will not be liable for any delays.
Seller may at any time make substitutions for product ordered which do not materially and adversely affect overall performance with the then current specifications in the typical and intended use. Seller reserves the right to halt deliveries and shipments and alter specifications and prices without notice. Buyer shall verify that the literature and information is current before purchasing.
7.
CANCELLATION
3.
(a) The contract may not be canceled by Buyer except with written consent by Seller and Buyer's payment of reasonable cancellation charges (including but not be limited to expenses already incurred for labor and material, overhead, commitments made by Seller, and a reasonable profit). (b) In no event will Buyer have rights in partially completed goods.
TERMS OF PAYMENT
(a) Terms are as stated on Seller's quotation, or if none are stated, net thirty (30) days. Accounts past due will incur a monthly charge at the rate of one percent (1%) per month (or, if less, the maximum allowed by applicable law) to cover servicing costs. (b) Seller reserves the right to change credit terms at any time in its sole discretion.
8.
INDEMNIFICATION
4.
LIMITED WARRANTY
(a) Seller warrants that the goods sold will be free from defects in material and workmanship and comply with Seller's applicable published specifications for a period of ninety (90) days from the date of Seller's delivery. (b) Goods or parts which have been subject to abuse (including without limitation repeated or extended exposure to conditions at or near the limits of applicable absolute ratings) misuse, accident, alteration, neglect, or unauthorized repair or improper application are not covered by any warranty. No warranty is made with respect to custom products or goods produced to Buyer's specifications (unless specifically stated in a writing signed by Seller). (c) No warranty is made with respect to goods used in devices intended for use in applications where failure to perform when properly used can reasonably be expected to result in significant injury (including, without limitation, navigation, aviation or nuclear equipment, or for surgical implant or to support or sustain life) and Buyer agrees to indemnify, defend, and hold harmless Seller from all claims, damages and liabilities arising out of any such uses. (d) This Paragraph 4 is the only warranty by Seller with respect to goods and may not be modified or amended except in writing signed by an authorized officer of Seller. (e) Buyer acknowledges and agrees that it is not relying on any applications, diagrams or circuits contained in any literature, and Buyer will test all parts and applications under extended field and laboratory conditions. Notwithstanding any cross-reference or any statements of compatibility, functionality, interchangeability, and the like, the goods may differ from similar goods from other vendors in performance, function or operation, and in areas not contained in the written specifications, or as to ranges and conditions outside such specifications; and Buyer agrees that there are no warranties and that Seller is not responsible for such things. (f) EXCEPT AS PROVIDED ABOVE, SELLER MAKES NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY; AND SELLER EXPRESSLY EXCLUDES AND DISCLAIMS ANY WARRANTY OR CONDITION OF MERCHANTABILITY OR FITNESS FOR PARTICULAR PURPOSE OR APPLICATION.
Seller will, at its own expense, assist Buyer with technical support and information in connection with any claim that any parts as shipped by Seller under this purchase order infringe any valid and enforceable copyright, or trademark, provided however, that Buyer (i) gives immediate written notice to Seller, (ii) permits Seller to participate and to defend if Seller requests to do so, and (iii) gives Seller all needed information, assistance and authority. However, Seller will not be responsible for infringements resulting from anything not entirely manufactured by Seller, or from any combination with products, equipment, or materials not furnished by Seller. Seller will have no liability with respect to intellectual property matters arising out of products made to Buyer's specifications, code, or designs. Except as expressly stated in this Paragraph 8 or in another writing signed by an authorized officer, Seller makes no representations and/or warranties with respect to intellectual and/or industrial property and/or with respect to claims of infringement. Except as to claims Seller agrees in writing to defend, BUYER WILL INDEMNIFY, DEFEND AND HOLD HARMLESS SELLER FROM ALL CLAIMS, COSTS, LOSSES, AND DAMAGES (INCLUDING ATTORNEYS FEES) AGAINST AND/OR ARISING OUT OF GOODS SOLD AND/OR SHIPPED HEREUNDER.
9.
10.
NO CONFIDENTIAL INFORMATION
Seller shall have no obligation to hold any information in confidence except as provided in a separate non-disclosure agreement signed by both parties.
ENTIRE AGREEMENT
(a) These terms and conditions are the entire agreement and the only representations and understandings between Seller and Buyer, and no addition, deletion or modification shall be binding on Seller unless expressly agreed to in a writing signed by an officer of Seller. (b) Buyer is not relying upon any warranty or representation except for those specifically stated here.
11.
APPLICABLE LAW
5.
LIMITATION OF LIABILITY
(a) Seller will not be liable for any loss, damage or penalty resulting from causes beyond its reasonable control, including but not limited to delay by others, force majeure, acts of God, or labor conditions. In any such event, the date(s) for Seller's performance will be deemed extended for a period equal to any delay resulting. (b) THE LIABILITY OF SELLER ARISING OUT OF THE CONTRACT OR ANY GOODS SOLD WILL BE LIMITED TO REFUND OF THE PURCHASE PRICE OR REPLACEMENT OF PURCHASED GOODS (RETURNED TO SELLER FREIGHT PRE-PAID) OR, WITH SELLER'S PRIOR WRITTEN CONSENT, REPAIR. (c) Buyer will not return any goods without first obtaining a customer return order number. (d) AS A SEPARATE LIMITATION, IN NO EVENT WILL SELLER BE LIABLE FOR COSTS OF SUBSTITUTE GOODS; FOR ANY SPECIAL, CONSEQUENTIAL, INCIDENTAL OR INDIRECT DAMAGES; OR LOSS OF USE, OPPORTUNITY, MARKET POTENTIAL, AND/OR PROFIT ON ANY THEORY (CONTRACT, TORT, FROM THIRD PARTY CLAIMS OR
The contract and all performance and disputes arising out of or relating to goods involved will be governed where Seller is ITE Taiwan by the laws of Taiwan, Republic of China or, where Seller is ITE California, by the laws of California and the United States of America, in either event without reference to the U.N. Convention on Contracts for the International Sale of Goods or to conflict of laws principles. Buyer agrees at its sole expense to comply with all applicable laws in connection with the purchase, use or sale of the goods provided hereunder and to indemnify Seller from any failure by Buyer to so comply. Without limiting the foregoing, Buyer certifies that no technical data or direct products thereof will be made available or re-exported, directly or indirectly, to any country to which such export or access is prohibited or restricted under U.S. law or regulations, unless prior authorization is obtained from the appropriate officials and agencies of the government as required under U.S. laws and regulations.
12.
JURISDICTION AND VENUE
Where Seller is ITE Taiwan, the courts located in Hsinchu, Taiwan, Republic of China, will have the sole and exclusive jurisdiction and venue over any dispute arising out of or relating to the contract or any sale of goods hereunder. Where Seller is ITE California, the courts located in Santa Clara County, California, USA, will have the sole and exclusive jurisdiction and venue over any dispute arising out of or relating to the contract or any sale of goods hereunder. Buyer hereby consents to the jurisdiction of such courts.
13.
ATTORNEYS' FEES
Reasonable attorneys' fees and costs will be awarded to the prevailing party in the event of litigation involving and/or relating to the enforcement or interpretation of the contract and/or any goods sold under it.
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HEADQUARTERS: 3F, No. 13, Innovation Rd.1, Science-Based Industrial Park, Hsin-Chu, Taiwan 300, R.O.C. Tel: 886-3-5798658 Fax: 886-3-5794803
ASIA SALES OFFICE: 7F, No. 435, Nei Hu District, Jui Kuang Road, Taipei 114, Taiwan, R.O.C. Tel: 886-2-26579896 Fax: 886-2-26578561, 26578576 Contact Person: P.Y. Chang E-mail: py.chang@ite.com.tw
ITE (U.S.A. West) Inc.: 1235 Midas Way, Sunnyvale, CA 94086, U.S.A. Tel: (408) 5308860 Fax: (408) 5308861 Contact Person: David Lin E-mail: david.lin@iteusa.com
ITE (U.S.A. Eastern) Inc.: 896 Summit St., #105, Round Rock, TX 78664, U.S.A. Tel: (512) 3887880 Fax: (512) 3883108 Contact Person: Don Gardenhire E-mail: don.gardenhire@iteusa.com

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