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CMOS
MT88E43B
Extended Voltage Calling Number Preliminary Information Identification Circuit 2
Features
* Compatible with: * British Telecom (BT) SIN227 & SIN242 * U.K.'s Cable Communications Association (CCA) specification TW/P&E/312 * Bellcore GR-30-CORE (formerly known as TR-NWT-000030) & SR-TSV-002476 Bellcore `CPE Alerting Signal' (CAS) and BT `Idle State Tone Alert Signal' detection Ring and line reversal detection 1200 baud Bell 202 and CCITT v.23 Frequency Shift Keying (FSK) demodulation 3 or 5V 10% supply voltage High input sensitivity (-40dBV Tone and FSK Detection) Selectable 3-wire FSK data interface (microcontroller or MT88E43B initiated) Low power CMOS with powerdown mode Input gain adjustable amplifier Carrier detect status output Uses 3.58 MHz crystal
DS5157 ISSUE 1 April 1999
Ordering Information MT88E43BE 24 Pin Plastic DIP (0.6 inch package only) MT88E43BS 24 Pin SOIC -40 C to +85 C
* * * * * * * * * *
Description
The MT88E43B Calling Number Identification Circuit 2 is a low power CMOS integrated circuit intended for receiving physical layer signals transmitted according to BT (British Telecom) SIN227 & SIN242, the U.K.'s CCA (Cable Communications Association) TW/P&E/312 and Bellcore GR-30-CORE & SR-TSV-002476 specifications. The MT88E43B is suitable for applications using a fixed voltage power source between 3 and 5V 10%. The MT88E43B contains a FSK demodulator and a CAS/Tone Alert Signal detector. The 1200 baud FSK demodulator is compatible with both Bell 202 and CCITT v.23 formats. To facilitate FSK data extraction, a dual mode 3-wire serial data interface is provided. In one mode data transfer is initiated by the device. In the second mode, the microcontroller initiates the 8-bit data word extraction from the device. The MT88E43B also offers line reversal detection capability for BT's CLIP, ring burst detection for the U.K.'s CCA's CLIP, and ring detection for Bellcore's CID.
Applications
* BT Calling Line Identity Presentation (CLIP), CCA CLIP, and Bellcore Calling Identity Delivery (CID) systems Feature phones, including Analog Display Services Interface (ADSI) phones Phone set adjunct boxes FAX and answering machines Database query and Computer Telephony Integration (CTI) systems
* * * *
FSKen IN+ INGS
MODE DCLK DATA DR
+ -
Anti-alias Filter
FSK Bandpass Filter
FSK Demodulator
Data Timing Recovery
To internal cct.
VRef CAP PWDN
Bias Generator
Carrier Detector Interrupt Generator Alert Signal High Tone Filter
CD INT
To internal cct.
Alert Signal Low Tone Filter Oscillator
Tone Detection Algorithm
Guard Time
StD St/GT ESt VDD VSS
OSCin OSCout TRIGin
TRIGRC
TRIGout
Figure 1- Functional Block Diagram
53
MT88E43B
IN+ INGS VRef CAP TRIGin TRIGRC TRIGout MODE OSCin OSCout VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD St/GT ESt StD INT CD DR DATA DCLK FSKen PWDN IC
Preliminary Information
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4 5 6 7 Name IN+ INGS VRef CAP Description Non-inverting Input of the internal opamp. Inverting Input of the internal opamp. Gain Select (Output) of internal opamp. The opamp's gain should be set according to the nominal Vdd of the application using the information in Figure 10. Reference Voltage (Output). Nominally VDD/2. It is used to bias the input opamp. Capacitor. A 0.1F decoupling capacitor should be connected across this pin and VSS.
TRIGin Trigger Input. Schmitt trigger buffer input. Used for line reversal and ring detection. TRIGRC Trigger RC (Open Drain Output/Schmitt Input). Used to set the (RC) time interval from TRIGin going low to TRIGout going high. An external resistor connected to VDD and capacitor connected to VSS determine the duration of the (RC) time interval. TRIGout Trigger Out (CMOS Output). Schmitt trigger buffer output. Used to indicate detection of line reversal and/or ringing. MODE 3-wire interface: Mode Select (CMOS Input). When low, selects FSK data interface mode 0. When high, selects FSK data interface mode 1. See pin 16 (DCLK) description to understand how MODE affects the DCLK pin. Oscillator Input. A 3.579545MHz crystal should be connected between this pin and OSCout. It may also be driven directly from an external clock source.
8 9
10 11 12 13 14
OSCin
OSCout Oscillator Output. A 3.579545MHz crystal should be connected between this pin and OSCin. When OSCin is driven by an external clock, this pin should be left open. VSS IC Power Supply Ground. Internal Connection. Must be connected to VSS for normal operation.
PWDN Power Down (Schmitt Input). Active high. When high, the device consumes minimal power by disabling all functionality except TRIGin, TRIGRC and TRIGout. Must be pulled low for device operation. FSKen FSK Enable (CMOS Input). Must be high for FSK demodulation. This pin should be set low to prevent the FSK demodulator from reacting to extraneous signals (such as speech, alert signal and DTMF which are all in the same frequency band as FSK). 3-wire Interface: Data Clock (CMOS Input/Output). In mode 0 (MODE pin low), this pin is an output. In mode 1 (MODE pin high), this pin is an input. 3-wire Interface: Data (CMOS Output). In mode 0 the FSK data appears at the pin once demodulated. In mode 1 the FSK data is shifted out on the rising edge of the microcontroller supplied DCLK.
15
16 17
DCLK DATA
54
Preliminary Information
Pin Description
Pin # 18 Name DR Description
MT88E43B
3-wire Interface: Data Ready (CMOS Output). Active low. In mode 0 this output goes low after the last DCLK pulse of each data word. This identifies the 8-bit word boundary on the serial output stream. Typically, DR is used to latch 8-bit words from a serial-to-parallel converter into a microcontroller. In mode 1 this pin will signal the availability of data. Carrier Detect (CMOS Output). Active low. A logic low indicates the presence of in-band signal at the output of the FSK bandpass filter. Interrupt (Open Drain Output). Active low. It is active when TRIGout or DR is low, or StD is high. This output stays low until all three signals have become inactive. Dual Tone Alert Signal Delayed Steering Output (CMOS Output). When high, it indicates that a guard time qualified alert signal has been detected. Dual Tone Alert Signal Early Steering Output (CMOS Output). Alert signal detection output. Used in conjunction with St/GT and external circuitry to implement the detect and non-detect guard times. Dual Tone Alert Signal Steering Input/Guard Time (Analog Input/CMOS Output). A voltage greater than VTGt (see figure 4) at the St/GT pin causes the device to indicate that a dual tone has been detected by asserting StD high. A voltage less than VTGt frees the device to accept a new dual tone. Positive Power Supply. P&E/312, data is transmitted after a single burst of ringing rather than before the first ringing cycle (as specified in the BT standards). The Idle State Tone Alert Signal is not required as it is replaced by a single ring burst. The MT88E43B has the capability to detect the ring burst. It can also demodulate the Bell 202 or CCITT v.23 FSK following the ring burst. The U.K.'s CCA specifies that data can be transmitted in either format. Bellcore specification GR-30-CORE is the generic requirement for transmitting asynchronous voiceband data to Customer Premises Equipment (CPE). Another Bellcore specification SR-TSV-002476 describes the same requirements from the CPE's perspective. The data transmission technique specified in both documents is applicable in a variety of services like Calling Number Delivery (CND), Calling Name Delivery (CNAM) and Calling Identity Delivery on Call Waiting (CIDCW) - services promoted by Bellcore. In CND/CNAM service, information about a calling party is embedded in the silent interval between the first and second ring burst. The MT88E43B detects the first ring burst and can then be setup to receive and demodulate the incoming Bell 202 FSK data. The device will output the demodulated data onto a 3-wire serial interface.
19 20 21 22
CD INT StD ESt
23
St/GT
24
VDD
Functional Overview
The MT88E43B is compatible with the caller ID specifications of BT, the U.K.'s CCA and Bellcore. As shown in Figure 1, the MT88E43B provides an FSK demodulator and a CAS/BT Tone Alert Signal detector. A 3-wire FSK data interface provides two modes of operation - a mode whereby data transfer is initiated by the device and a mode whereby data transfer is initiated by an external microcontroller. The MT88E43B also provides line reversal detection and ring detection. BT specifications SIN227 and SIN242 describe the signalling mechanism between the network and the Terminal Equipment (TE) for the Caller Display Service (CDS). CDS provides Calling Line Identity Presentation (CLIP), which delivers to an on hook (idle state) TE the identity of an incoming caller before the first ring. An incoming CDS call is indicated by a polarity reversal on the A and B wires (see Figure 3), followed by an Idle State Tone Alert Signal. Caller ID information is then transmitted in CCITT v.23 format FSK. The MT88E43B can detect the line reversal, tone alert signal, and demodulate the incoming FSK signal. The U.K.'s CCA specification TW/P&E/312 proposes an alternate CDS TE interface. According to TW/
55
MT88E43B
In CIDCW service, information about an incoming caller is sent to the subscriber, while he/she is already engaged in another call. A CPE Alerting Signal (CAS) indicates the arrival of CIDCW information. The MT88E43B can detect the CAS and then be setup to demodulate the incoming FSK containing the CIDCW information.
Preliminary Information
components R5 and C3 (see Figure 3) at TRIGRC ensure a minimum TRIGout low interval. In a TE designed for CLIP, the TRIGout high to low transition may be used to interrupt or wake-up the microcontroller. The controller can thus be put into power-down mode to conserve power in a battery operated TE. Ring Burst Detection CCA does not support the dual tone alert signal (refer to Dual Tone Alert Signal Detection section). Instead, CCA requires that the TE be able to detect a single burst of ringing (duration 200-450ms) that precedes CLIP FSK data. The ring burst may vary from 30 to 75Vrms and is approximately 25Hz. Again in a TE designed for CCA CLIP, the TRIGout high to low transition may be used to interrupt or wake-up the microcontroller. The controller can thus be put into power-down mode to conserve power in a battery operated TE. Ring Detection In Bellcore's CND/CNAM scheme, the CID FSK data is transmitted between the first and second ringing cycles. The circuit in Figure 3 will generate a ring envelope signal (active low) at TRIGout for a ring voltage of at least 40Vrms. R5 and C3 filter the ring signal to provide an envelope output. The diode bridge shown in Figure 3 works for both single ended and balanced ringing. A fraction of the
Functional Description
Detection of CLIP/CID Call Arrival Indicators The circuit in Figure 3 illustrates the relationship between the TRIGin, TRIGRC and TRIGout signals. Typically, the three pin combination is used to detect an event indicated by an increase of the TRIGin voltage from VSS to above the Schmitt trigger high going threshold VT+ (see DC electrical characteristics). Figure 3 shows a circuit to detect any one of three CLIP/CID call arrival indicators: line reversal, ring burst and ringing. Line Reversal Detection Line reversal, or polarity reversal on the A and B wires indicates the arrival of an incoming CDS call, as specified in SIN227. When the event (line reversal) occurs, TRIGin rises past the high going Schmitt threshold VT+ and TRIGout, which is normally high, is pulled low. When the event is over, TRIGin falls back to below the low going Schmitt threshold VT- and TRIGout returns high. The
Tip/A
C1=100nF V1 R1=499K
VDD V3 MT88E43B
max VT+ = 0.68 VDD min VT+ = 0.48 VDD
R3=200K R4=301K
TRIGin
Ring/B
R2=499K
V4
R5=150K
C2=100nF V2
Notes: The application circuit must ensure that, VTRIGin>max VT+ where max VT+=3.74V @VDD=5.5V. Tolerance to noise between A/B and VSS is: max Vnoise = (min VT+)/0.30+0.7 = 5.6Vrms @4.5V VDD where min VT+ = 2.16V @VDD=4.5V. Suggested R5C3 component values: R5 from 10K to 500K C3 from 47nF to 0.68F An example is C3=220nF, R5=150K; TRIGout low from 21.6ms to 37.6ms after the TRIGin signal stops triggering the circuit.
TRIGRC C3=220nF
To determine values for C3 and R5: R5C3 = -t / ln(1-V TRIGRC/VDD)
TRIGout To Microcontroller
Figure 3 - Circuit to Detect Line Reversal, Ring Burst and Ringing
56
Preliminary Information
ring voltage is applied to the TRIGin input. When the voltage at TRIGin is above the Schmitt trigger high going threshold VT+, TRIGRC is pulled low as C3 discharges. TRIGout stays low as long as the C3 voltage stays below the minimum VT+. In a CPE designed for CND/CNAM, the TRIGout high to low transition may be used to interrupt or wake up the microcontroller. The controller can thus be put into power down mode to conserve power. If precise ring duration determination is critical, capacitor C3 in Figure 3 may be removed. The microcontroller will now be able to time the ring duration directly. The result will be that TRIGout will be low only as long as the ringing signal is present. Previously the RC time constant would cause only one interrupt. Dual Tone Alert Signal Detection The BT on hook (idle state) caller ID scheme uses a dual tone alert signal whose characteristics are shown in Table 1. Table 1 also shows the Bellcore specifications for a similar dual tone signal called CPE Alerting Signal (CAS) for use in off-hook data transmission. For the CIDCW service, the CAS must be detected in the presence of near end speech. The CAS detector must also be immune to imitation from near and far end speech. In the MT88E43B the dual tone signal is separated into a high and a low tone by two bandpass filters. A detection algorithm examines the two filter outputs to determine the presence of a dual tone alert signal. The ESt pin goes high when both tones are present. Note that ESt is only a preliminary indication. The indication must be sustained over the tone present guard time to be considered valid. Tone present and tone absent guard times can be implemented with external RC components. The tone present guard time rejects signals of insufficient duration. The tone absent guard time masks momentary detection dropout once the tone present guard time has been satisfied. StD is the guard time qualified detector output.
MT88E43B
Item Low tone frequency High tone frequency Received signal level Signal reject level Signal level differential (twist) Unwanted signals Duration Speech present BT 2130Hz 1.1% 2750Hz 1.1% Bellcore 2130Hz 0.5% 2750Hz 0.5%
-2 to -40dBV -14 to -32dBma per tone on-hook per tone off-hook (0.22 to -37.78dBm) -46dBV (-43.78dBm) up to 7dB -45dBm up to 6dB
<= -20dB (300-3400Hz) 88ms to 110msc No
<= -7dBm ASLb near end speech 75ms to 85ms Yes
Table 1 - Dual Tone Alert Signal Characteristics
a. The signal power is expressed in dBm referenced to 600 ohm at the CPE A/B (tip/ring) interface. b. ASL = active speech level expressed in dBm referenced to 600 ohm at the CPE tip/ring interface. The level is measured according to method B of Recommendation P.56 "Objective Measurement of Active Speech Level" published in the CCITT Blue Book, volume V "Telephone Transmission Quality" 1989. EPL (Equivalent Peak Level) = ASL+11.7dB c. SIN227 suggests that the recognition time should be not less than 20ms if both tones are detected.
Dual Tone Detection Guard Time When the dual tone signal is detected by the MT88E43B, ESt goes high. When the signal ceases to be detected, ESt goes low. The ESt pin indicates raw detection of the dual tone signal. Since the BT application requires a minimum signal duration and the Bellcore application requires protection from imitation by speech, ESt detection must be guard time qualified. The StD pin provides guard time qualified signal detection. When the MT88E43B is used in a caller identity system, StD indicates correct CAS/Tone Alert Signal detection. Figure 4 shows the relationship between the St/GT, ESt and StD pins. It also shows the operation of the guard time circuit. The total recognition time is tREC = tGP + tDP , where tGP is the tone present guard time and tDP is the tone
57
MT88E43B
present detect time (refer to timing between ESt, St/ GT and StD in Figures 17 and 20). The total tone absent time is tABS = tGA + tDA , where tGA is the tone absent guard time and tDA is the tone absent detect time (refer to timing between ESt, St/ GT and StD in Figures 17 and 20). Bellcore states that it is desirable to be able to turn off CAS detection for an off-hook capable CPE. The disable switch allows the subscriber who disconnects a service that relies on CAS detection (e.g., CIDCW) but retains the CPE, to turn off the detector and not be bothered by false detection. When SW1 in Figure 4 is in the B position the guard time circuit is disabled. The detector will still process CAS/Alerting tones but the MT88E43B will not signal their presence by ensuring that StD is low. BT specifies that the idle state tone alert signal recognition time should not be less than 20ms when both tones are used for detection. That is, both tones must be detected together for at least 20ms before the signal can be declared valid. This requirement can be met by setting the tGP (refer to Figure 5) to at least 20ms. BT also specifies that the TE is required to apply a DC wetting pulse and an AC load 15-25ms after the end of the alerting signal. If tABS=tDA+tGA is 15 to 25ms, the DC current wetting pulse and the AC load can both be applied at the falling edge of StD. The maximum tDA is 8ms so tGA should be 15-17ms. Therefore, tGP must be greater than tGA. Figure 5(a) shows a possible implementation. The values in Figures 9 and 11 (R2=R3=422K, C=0.1F) will meet the BT timing requirements.
MT88E43B Both tones detected From detector + VTGt Comparator
N P
Preliminary Information
MT88E43B
VDD St/GT
R1 C VD=diode forward voltage R2
ESt (a) tGP > tGA tGP = R1C ln [VDD/(VDD-VTGt)] tGA = R PC ln [(V DD-VD(RP/R2))/(V TGt-V D(RP/R2))] RP = R1R2/(R1+R2)
MT88E43B
VDD St/GT
R1 C VD=diode forward voltage R2
ESt (b) tGP < tGA tGP = RPC ln [(VDD-VD(RP/R2))/(VDD-VTGt-VD(RP/R2))] tGA = R1C ln (VDD/VTGt) RP = R1R2/(R1+R2)
Figure 5 - Guard Time Circuits with Unequal Times Input Configuration The MT88E43B provides an input arrangement comprised of an operational amplifier, and a bias source (VRef) which is used to bias the opamp inputs at VDD/2. The feedback resistor at the opamp output (GS) can be used to adjust the gain. In a single-ended configuration, the opamp is connected as shown in Figure 6. For a differential input configuration, Figure 7 shows the necessary connections.
IN+
VDD Q1 C St/GT RF R Q2 = VSS SW1 A B ESt StD VSS GS C RIN IN-
Voltage Gain (AV) = RF / RIN
VRef
Figure 6 - Single-Ended Input Configuration
Figure 4 - Guard Time Circuit Operation
58
Preliminary Information
MT88E43B
Item BT 1300Hz 1.5% 2100Hz 1.5% -8 to -40dBV (-5.78 to -37.78dBm) up to 6dB Bellcore 1200Hz 1% 2200Hz 1% -12 to -36dBma
C1
R1
IN+ IN-
Mark frequency (logic 1) Space frequency (logic 0) Received signal level Signal level differential (Twist) Unwanted signals Transmission rate Word format
C2
R4
R5 GS R3 R2
VRef
Differential Input Amplifier C1 = C2 R1 = R4 (For unity gain R5= R4) R3 = (R2R5) / (R2 + R5) Voltage Gain (AVdiff) = R5/R1 (see Figure 9,10,11) Input Impedance (ZINdiff) = 2 R12 + (1/C)2
up to 10dBb
<= -20dB (300-3400Hz) 1200 baud 1% 1 start bit (logic 0), 8 bit word (LSB first), 1 to 10 stop bits (logic 1)
<= -25dB (0-4kHz)c 1200 baud 1% 1 start bit (logic 0), 8 bit word (LSB first), 1 stop bit (logic 1)d
Figure 7 - Differential Input Configuration FSK Demodulation The MT88E43B first bandpass filters and then demodulates the FSK signal. The carrier detector provides an indication of the presence of signal at the bandpass filter output. The MT88E43B's dual mode 3-wire interface allows convenient extraction of the 8-bit data words in the demodulated FSK bit stream. Note that signals such as CAS/Tone Alert Signal, speech and DTMF tones lie in the same frequency band as FSK. They will, therefore, be demodulated and as a result, false data will be generated. To avoid demodulation of false data, an FSKen pin is provided so that the FSK demodulator may be disabled when FSK signal is not expected. There are two events that if either is true, should be used to disable FSKen. The events are the carrier detector output CD returning high or receiving all the data indicated by the message length word. Table 2 shows the BT and Bellcore FSK signal characteristics. The BT frequencies correspond to CCITT v.23 format. The Bellcore frequencies correspond to Bell 202. The U.K.'s CCA requires that the TE be able to receive both CCITT v.23 and Bell 202 formats. The MT88E43B is compatible with both formats without any adjustment.
Table 2 - FSK Characteristics
a. The signal power is expressed in dBm referenced to 600 ohm at the CPE Tip/Ring (A/B) interface. b. SR-3004, Issue 2, January 1995. c. The frequency range is specified in GR-30-CORE. d. Up to 20 marks may be inserted in specific places in a single or multiple data message.
3-wire FSK Data Interface The MT88E43B provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated FSK bit stream can be extracted without the need either for an external UART or for the TE/CPE's microcontroller to perform the UART function in software. The interface is specifically designed for the 1200 baud rate and is comprised of the DATA, DCLK (data clock) and DR (data ready) pins. Two modes (modes 0 and 1) are selectable via control of the device's MODE pin: in mode 0, data transfer is initiated by the MT88E43B; in mode 1, data transfer is initiated by the external microcontroller. Mode 0 This mode is selected when the MODE pin is low. In this mode, data transfer is initiated by the device. The MT88E43B receives the FSK signal, demodulates it, and outputs the data directly to the DATA pin (refer to Figure 14). For each received stop and start bit sequence, the MT88E43B outputs a
59
MT88E43B
fixed frequency clock string of 8 pulses at the DCLK pin. Each clock rising edge occurs in the centre of each DATA bit cell. DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift register or a micro-controller. The MT88E43B also outputs an end of word pulse (data ready) on the DR pin. The data ready signal indicates the reception of every 10-bit word (including start and stop bits) sent from the network to the TE/CPE. This DR signal can be used to interrupt a micro-controller. DR can also cause a serial to parallel converter to parallel load its data into a microcontroller. The mode 0 data pin can also be connected to a personal computer's serial communication port after converting from CMOS to RS-232 voltage levels. Mode 1 This mode is selected when the MODE pin is high. In this mode, the microcontroller supplies read pulses (DCLK) to shift the 8-bit data words out onto the MT88E43B DATA pin. The MT88E43B asserts DR to denote the word boundary and indicate to the microprocessor that a new word has become available (refer to Figure 16). Internal to the MT88E43B, the demodulated data bits are sampled and stored. After the 8th bit, the word is parallel loaded into an 8 bit shift register and DR goes low. The shift register's contents are shifted out to the DATA pin on the supplied DCLK's rising edge in the order they were received. If DCLK begins while DR is low, DR will return to high upon the first DCLK. This feature allows the associated interrupt (see section on "Interrupt") to be cleared by the first read pulse. Otherwise DR is low for half a nominal bit time (1/2400 sec). After the last bit has been read, additional DCLKs are ignored. Carrier Detector The carrier detector provides an indication of the presence of a signal in the FSK frequency band. It detects the presence of a signal of sufficient amplitude at the output of the FSK bandpass filter. The signal is qualified by a digital algorithm before the CD output is set low to indicate carrier detection. An 8ms hysteresis is provided to allow for momentary signal drop out once CD has been activated. CD is released when there is no activity at the FSK bandpass filter output for 8 ms.
Preliminary Information
When CD is inactive (high), the raw output of the demodulator is ignored by the data timing recovery circuit (refer to Figure 1). In mode 0, the DATA pin is forced high. No DCLK or DR signal is generated. In mode 1, the internal shift register is not updated. No DR is generated. If the mode 1 DCLK is clocked, DATA is undefined. Note that signals such as CAS/Tone Alert Signal, speech and DTMF tones also lie in the FSK frequency band and the carrier detector may be activated by these signals. The signals will be demodulated and presented as data. To avoid false data detection, the FSKen pin should be used to disable the FSK demodulator when no FSK signal is expected. Ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector. Interrupt To facilitate interfacing with microcontrollers running interrupt driven firmware, an open drain interrupt output INT is provided. INT is asserted when TRIGout is low, StD is high, or DR is low. When INT is asserted, these signals should be read (into an input port of the microcontroller) to determine the cause of the interrupt (TRIGout, StD or DR) so that the appropriate response can be made. When system power is first applied, TRIGout will be low because capacitor C3 at TRIGRC (see Figure 3) has no initial charge. This will result in an interrupt upon power up. Also when system power is first applied and the PWDN pin is low, an interrupt will occur due to StD. Since there is no charge across the capacitor at the St/GT pin in Figure 4, StD will be high triggering an interrupt. The interrupts will not clear until both capacitors are charged. The microcontroller should ignore interrupt from these sources on initial power up until there is sufficient time to charge the capacitors. It is possible to clear StD and its interrupt by asserting PWDN immediately after system power up. When PWDN is high, StD is low. PWDN will also force both ESt and the comparator output low, Q2 will turn on so that the capacitor at the St/GT pin charges up quickly (refer to Figure 4). Power Down For applications requiring reduced power consumption, the MT88E43B can be powered up only when it is required, that is, upon detection of one of three CLIP/CID call arrival indicators: line reversal, ring burst and ringing.
60
Preliminary Information
The MT88E43B is powered down by setting the PWDN pin to logic high. In power down mode, the oscillator, input opamp and all internal circuitry are disabled except for TRIGin, TRIGRC and TRIGout pins. These three pins are not affected by power down, such that, the MT88E43B can still react to call arrival indicators. The MT88E43B can be powered up by setting the PWDN pin to logic low. Crystal Oscillator The MT88E43B requires a 3.579545MHz crystal oscillator as the master timing source.
MT88E43B
MT88E43B OSC1 OSC2
MT88E43B OSC1 OSC2
MT88E43B OSC1 OSC2
3.579545 MHz
to the next MT88E43B
Figure 8 - Common Crystal Connection The crystal specification is as follows (e.g. CTS MP036S) :
Frequency: Frequency tolerance: Resonance mode: Load capacitance: Maximum series resistance: Maximum drive level (mW):
3.579545 MHz 0.1%(-40oC+85oC) Parallel 18 pF 150 ohms 2 mW
Any number of MT88E43B devices can be connected as shown in Figure 8 such that only one crystal is required. The connection between OSC2 and OSC1 can be DC coupled as shown, or the OSC1 input on all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected. To meet BT and Bellcore requirements for proper tone detection the crystal must have a frequency tolerance of 0.1%. VRef and CAP Inputs VRef is the output of a low impedance voltage source equal to VDD/2 and is used to bias the input opamp. A 0.1F capacitor is required between CAP and VSS to eliminate noise on VRef.
61
MT88E43B
Vdd
TIP / A
Preliminary Information
Vdd R4 MT88E43B 1N4003 IN+ Vdd 60K4 1N4003 22nF 5% R1 1N4003 53K6 R4 Vdd 464K INGS VRef CAP Vdd
1N914
1N4003 22nF 5% R1
TISP4180, TISP5180, TPA150A12 or TPB150B12
VDD St/GT ESt StD INT CD DR DATA DCLK FSKen PWDN IC R3
C
Vdd
100K
20%
1N914
RING / B
R2
499K, 5% 100nF 1N914 5%
1N914
TRIGin TRIGRC TRIGout MODE
150K 5%
499K, 5% 100nF 5%
200K 5% 301K 5% 220nF 100nF
OSCin OSCout VSS
1N914
NOTE: Resistors must have 1% tolerance and capacitors have 20% tolerance unless otherwise specified. : Crystal is 3.579545MHz, 0.1% frequency tolerance. : For BT application C=0.1F 5%, R3=422k 1%, R2=422k 1% : For applications where CAS speech immunity is required (e.g. CIDCW) C=0.1F 5%, R3=825k 1%, R2=226k 1% : R1 = 430K, R4 = 34K for VDD = 5V 10% (See Figure 10) : R1 = 620K, R4 = 63K4 for VDD = 3V 10% (See Figure 10)
= To microcontroller = From microcontroller (FSK Interface Mode 0 selected)
Figure 9 - Application Circuit
Application Circuits
The circuits shown in Figures 9 and 11 are application circuits for the MT88E43B. As supply voltage (VDD) is decreased, the threshold of the device's tone and FSK detectors will be reduced. Therefore, to meet the BT or Bellcore tone reject level requirements the gain of the input opamp should be reduced according to the graph in Figure 10. For example when VDD=5V (+/- 10%), R1 should equal 430k and R4 should equal 34k; and if VDD=3V (+/- 10%) R1 should equal 620k and R4 should equal 63.4k. Resistors R1 and R4 are shown in Figures 9 and 11. The circuit shown in Figure 9 illustrates the use of the MT88E43B in a proprietary system that doesn't need to meet FCC, DOC, and UL approvals. It should be noted that if glitches on the Tip/Ring interface are of sufficient amplitude, the circuit will falsely detect these signals as ringing or line reversal. The circuit shown in Figure 11 will provide common mode rejection of signals received by the ringing circuit. This circuit should pass safety related tests specified by FCC Part 68, DOC CS-03, UL 1459, and CSA C22.2.
62
These safety tests will simulate high voltage faults that may occur on the line. The circuit provides isolation from these high voltage faults via R1 and the 12.1k resistors as well as the 22nF & 330nF capacitors. IRC manufactures a resistor (part number GS3) that should be used for R1. This resistor is a 3W, 5%, 1kV power resistor. The 12k1 resistor is manufactured by IRC (part number FA8425F). This resistor is a 1.5W, 5%, fuseable type resistor. The 22nF and 330nF capacitors have a 400V rating. See the application note "MSAN-164: Applications of the MT8843 Calling Number Identification Circuit 2" for information on designing the MT88E43B into CID and CIDCW systems.
100nF
Preliminary Information
MT88E43B
1
0.95
0.9
0.85
Gain Ratio
0.8
0.75
0.7
0.678
0.65
0.6 2
2.5
3
3.5 4 4.5 Nominal Vdd (Volts)
5
5.5
6
Figure 10: Gain Ratio as a function of Nominal Vdd Note: In the application circuits shown in Figures 9 and 11, the Gain Ratio of MT88E43B opamp is
464k GainRatio = -----------------R1 + R4
63
MT88E43B
Vdd 1N4003 R1 1N4003 IN+
RING / B
Preliminary Information
Vdd R4 MT88E43B VDD St/GT ESt StD INT CD DR DATA DCLK FSKen PWDN IC R2 R3
1N914
TIP / A
53K6
1N4003 R1 1N4003
60K4
22nF 5%
Vdd R4
C
Vdd
100K
464K
INGS VRef CAP TRIGin
20%
Vdd 150K 5% 100nF 10% 220nF 100nF
1N5231B
TRIGRC TRIGout MODE OSCin OSCout VSS
330nF 12K1 Vdd Motorola 10% 5% 4N25 464K 5%
200K 5% 10nF
NOTE: Resistors must have 1% tolerance, capacitors have 20% tolerance unless specified otherwise. : Bridge rectifier diodes are 1N914. : For BT application C=0.1F 5%, R3=422k 1%, R2=422k 1% : For applications where CAS speech immunity is required (e.g. CIDCW) C=0.1F 5%, R3=825k 1%, R2=226k 1% : R1 = 430K, R4 = 34K for VDD = 5V 10% (See Figure 10) : R1 = 620K, R4 = 63K4 for VDD = 3V 10% (See Figure 10)
= To microcontroller = From microcontroller (FSK Interface Mode 0 selected)
Figure 11 - Application Circuit with Improved Common Mode Noise Immunity and Isolation in Line Interface Approvals FCC Part 68, DOC CS-03, UL 1459, and CAN/ CSA-22.2 No. 225-M90 are all system (i.e. connectors, power supply, cabinet, etc.) requirements. Since the MT88E43B is a component and not a system, the application circuit (Figure 11) has been designed to meet the CO Trunk interface requirements of FCC, DOC, UL, and CSA; thus enabling the complete system to be approved by these standards bodies. Products are designed in accordance with meeting the above requirements; however, full conformance to these standards is dependent upon the application in which the MT88E43B is being used, and therefore, approvals are the responsibility of the customer and Mitel will not have tested the product to meet the above standards.
64
100nF
22nF 5%
Preliminary Information
Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated.
Parameter 1 2 3 4 Supply voltage with respect to Vss Voltage on any pin other than supplies ** Current at any pin other than supplies Storage Temperature Symbol VDD VPIN IPIN TST Min -0.3 Vss-0.3 -65
MT88E43B
Max 6 VDD+0.3 10 150
Units V V mA
oC
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ** Under normal operating conditions voltage on any pin except supplies can be minimum VSS-1V to maximum VDD+1V for an input current limited to less than 200A. .
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 Power Supplies Clock Frequency Tolerance on Clock Frequency Operating Temperature
25oC
Sym VDD fOSC fc TOP
Min 2.7 -0.1 -40
Typ 3.579545 -
Max 5.5 +0.1 85
Units V MHz %
oC
Typical figures are at
and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics
Characteristics 1 Standby Supply Current Sym IDDQ Min Typ 0.5 Max 15 Units A Test Conditions AlI inputs are VDD/ VSS except for oscillator pins. No analog input. Outputs unloaded. PWDN=VDD All inputs are VDD/ VSS except for oscillator pins. No analog input. Outputs unloaded. PWDN=VSS FSKen=VDD
2
S U P P L Y
Operating Supply Current VDD = 5V 10% VDD = 3V 10%
IDD 3.0 2.1 8 4.5 mA mA
3 4
TRIGin TRIGRC PWDN
Power Consumption Schmitt Input High Threshold Schmitt Input Low Threshold Schmitt Hysteresis
DCLK MODE FSKen
PO VT+ VTVHYS VIH VIL
0.48*VDD 0.28*VDD 0.2 0.7*VDD VSS
-
44 0.68*VDD 0.48*VDD VDD 0.3*VDD
mW V V V V V
5 6
CMOS Input High Voltage CMOS Input Low Voltage
65
MT88E43B
DC Electrical Characteristics (continued)
Characteristics 7
TRIGout DCLK DATA DR, CD StD, ESt St/GT TRIGout DCLK DATA DR, CD StD, ESt St/GT TRIGRC INT IN+, INTRIGin PWDN DCLK MODE FSKen
Preliminary Information
Sym IOH
Min 0.8
Typ -
Max -
Units mA
Test Conditions VOH=0.9*VDD
Output High Sourcing Current
8
Output Low Sinking Current
IOL
2
-
-
mA
VOL=0.1*VDD
9
Input Current
Iin1 Iin2
-
-
1 10
A A
Vin=VDD to VSS Vin=VDD to VSS
10 11 12 13 14 15
TRIGRC INT St/GT VRef
Output High-Impedance Current
Ioz1 Ioz2 Ioz3
0.5VDD0.05 0.5VDD0.05
-
1 10 5 0.5VDD+ 0.05 2 0.5VDD+ 0.05
A A V k V
Vout =VDD to VSS
Output Voltage Output Resistance
VRef RRef VTGt
No Load
St/GT
Comparator Threshold Voltage
DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
66
Preliminary Information
AC Electrical Characteristics - Dual Tone Alert Signal Detection
Characteristic 1 2 3 Low tone frequency High tone frequency Frequency deviation accept Sym fL fH Min 1.1% Typ 2130 2750 Max Unit Hz Hz
MT88E43B
Notes*
range within which tones are accepted ranges outside of which tones are rejected dBVa dBmb dBV dBm dBV dBm dB dB 1, 2 3 3
4
Frequency deviation reject
3.5%
-
-
5 6 7 8 9
Accept signal level per tone Reject signal level per tone (Vdd = 5V 10% only) Reject signal level per tone (Vdd = 3 to 5V 10%) Positive and negative twistc accept Signal to Noise Ratio SNRTONE
-40 -37.78 7 20
-
-2 0.22 -46 -43.78 -47.22 -45 -
a. dBV = decibels above or below a reference voltage of 1Vrms. Signal level is per tone. b. dBm = decibels above or below a reference power of 1mW into 600 ohms. 0dBm = 0.7746Vrms. Signal level is per tone. c. Twist = 20 log (fH amplitude / fL amplitude). *Notes: 1. Both tones have the same amplitude. 2. Band limited random noise 300-3400Hz. Measurement valid only when tone is present. 3. Tip/Ring signal level. Input opamp configured to 0dB gain at VDD=5V+/-10%, -3.38dB gain at VDD=3V+/-10%. (see Figure 10) AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated. Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics 1 2 3 CMOS Threshold Voltage Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Low Sym VCT VHM VLM Level 0.5*VDD 0.7*VDD 0.3*VDD Units V V V Notes
67
MT88E43B
Electrical Characteristics - Gain Setting Amplifier
Characteristics 1 2 3 4 5 6 7 8 9 Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Ratio Common Mode Rejection DC Open Loop Voltage Gain Unity Gain Bandwidth Output Voltage Swing Capacitive Load (GS) Sym IIN Rin VOS PSRR CMRR AVOL fC VO CL RL VCM Min 10 40 40 30 0.3 0.5 100 1.0 Max 1 25 VDD-0.7 50 VDD-1.0
Preliminary Information
Units A M mV dB dB dB MHz V pF k V
Test Conditions VSS VIN VDD
1kHz ripple on VDD VCMmin VIN VCMmax
Load 100k
10 Resistive Load (GS) 11 Common Mode Range Voltage
Electrical characteristics are over recommended operating conditions, unless otherwise stated.
AC Electrical Characteristics - FSK Demodulation
Characteristics 1 Input Level Sym Min -40 -37.78 10.0 1188 1188 2178 Typ Max Units Notes* 1, 3 -8 dBVa -5.78 dBmb 398.1 mVrms 1212 1212 2222 baud Hz Hz Hz Hz dB 1, 2
2 Transmission Rate 3 Input Frequency Bell 202 Mark (1) Bell 202 Space (0) CCITT v.23 Mark (1) CCITT v.23 Space (0) 4 Signal to Noise Ratio SNRFSK
1200 1200 2200
1280.5 1300 1319.5 2068.5 2100 2131.5 20 -
a. dBV = decibels above or below a reference voltage of 1Vrms. b. dBm = decibels above or below a reference power of 1mW into 600 ohms. 0dBm = 0.7746Vrms. *Notes 1. Both mark and space have the same amplitude. 2. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is 300-3400Hz, the Bellcore band is 0-4kHz. 3. Tip/Ring signal level. Input opamp configured to 0dB gain at VDD=5V+/-10%, -3.38dB gain at VDD=3V+/-10%. (see Figure 10) AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated. Typical figures are nominal values and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - Dual Tone Alert Signal Timing
Characteristics 1 2 Alert Signal present detect time Alert Signal absent detect time Sym tDP tDA Min 0.5 0.1 Max 10 8 Units ms ms Notes* 1 1
*Notes 1. Refer to Figures 17 and 20
68
Preliminary Information
AC Electrical Characteristics - Carrier Detect and Power Down Timing
Characteristics 1 2 3 4 5
CD PWDN OSC1
MT88E43B
Sym tPU tPD tCP tCA
Min 8 8
Max 50 1 25 -
Units ms ms ms ms ms
Notes
Power-up time Power-down time Input FSK to CD low delay Input FSK to CD high delay Hysteresis
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics - 3-Wire Interface Timing (Mode 0)
Characteristics 1 2 3 4
DATA DR
Sym tRR tRF tRL tIDD tR tF tDCD tCDD fDCLK0 tCH tCL
Min 415 1188 6 6 1201.6 415 415
Typ 416 1200 1 416 416 1202.8 416 416
Max 200 200 417 1212 5 200 200 1204 417 417
Units ns ns s baud ms ns ns s s Hz s s
Notes* into 50pF Load into 50pF Load 2 1
Rise time Fall time Low time Rate Input FSK to DATA delay Rise time
DATA DCLK
5 6 7 8 9 10 11 12 13
DCLK
into 50pF Load into 50pF Load 1, 2, 3 1, 2, 3 2 2 2 2
Fall time DATA to DCLK delay DCLK to DATA delay Frequency High time Low time
DCLK DCLK to DR delay tCRD 415 416 417 s DR AC Electrical Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing. *Notes: 1. FSK input data at 1200 12 baud. 2. OSC1 at 3.579545 MHz 0.1%. 3. Function of signal condition.
AC Electrical Characteristics - 3-Wire Interface Timing (Mode 1)
Characteristics 1 2 3 4 5
DCLK DR DCLK
Sym fDCLK1 tR1 tDDS tDDH
Min 30 500 500
Max 1 70 20 -
Units MHz % ns ns ns
Notes
Frequency Duty cycle Rise time DCLK low set up to DR DCLK low hold time after DR
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
69
MT88E43B
tDCD tCDD
Preliminary Information
DATA tR DCLK tCL tR tCH tF tF
VHM VCT VLM VHM VCT VLM
Figure 12 - DATA and DCLK Mode 0 Output Timing
tRF
tRR
DR tRL
VHM VCT VLM
Figure 13 - DR Output Timing
TIP/RING (A/B) WIRES
start stop b7
tIDD
start stop b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7
start stop 1 0 b0 b1 b2
1
0
start DATA b7 stop b0 b1 b2 b3 b4 b5 b6 b7 stop 1/fDCLK0 DCLK
tCRD
start b0 b1 b2 b3 b4 b5 b6 b7 stop
start b0 b1 b2
DR tRL
Figure 14 - Serial Data Interface Timing (Mode 0)
70
Preliminary Information
MT88E43B
VHM
DCLK
VLM
tR1
Figure 15 - DCLK Mode 1 Input Timing
Demodulated internal bit stream DR
word N 7 stop start 0 1 2
word N+1 3 4 5 6 tRL 7 stop
tDDS tDDH DCLK
1/fDCLK1
DATA
6 word N-1
7
0
1
2
3
4
5
6
7
0
word N
DCLK clears DR DCLK does not clear DR, so DR is low for maximum time (1/2 bit width)
Figure 16 - Serial Data Interface Timing (Mode 1)
71
MT88E43B
Alerting Signal Line Reversal
Preliminary Information
Ch. seizure A/B Wires
Mark
Data Packet
Ring
A
B
C
D
E
F
G
Note 6
TRIGout
Note 1 Note 2
PWDN
tDP
ESt
tDA
50-150ms
tGP
St/GT
tGA VTGt tABS
151ms Note 3
tREC
StD
TE DC load
< 0.5mA (optional)
<120A 205ms Current wetting pulse (see SIN227) Zss (Refer to SIN227) Note 4
TE AC load
FSKen
Note 5
tCP
CD
tCA A 100ms B = 88-110ms C 45ms (up to 5sec) D = 80-262ms E = 45-75ms F 2.5sec (typ. 500ms) G > 200ms Note: All values obtained from SIN227 Issue 1
DR
DCLK
DATA
..101010..
Data
tPU
OSCout
tPD
Figure 17 - Input and Output Timing for BT Caller Display Service (CDS), e.g., CLIP
Notes: 1) The total recognition time is tREC = tGP + tDP , where tGP is the tone present guard time and tDP is the tone present detect time (refer to section "Dual Tone Detection Guard Time" on page 57 for details). VTGt is the comparator threshold (refer to Figure 4). 2) The total tone absent time is tABS = tGA + tDA , where t GA is the tone absent guard time and tDA is the tone absent detect time (refer to section "Dual Tone Detection Guard Time" on page 57 for details). VTGt is the comparator threshold (refer to Figure 4). 3) By choosing tGA=15ms, tABS will be 15-25ms so that the current wetting pulse and AC load can be applied right after the StD falling edge. 4) SIN227 specifies that the AC and DC loads should be removed between 50-150ms after the end of the FSK signal, indicated by CD returning to high. The MT88E43B may also be powered down at this time. 5) FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as speech, Tone Alert Signal and DTMF tones. 6) TRIGout is the ring envelope during ringing.
72
Preliminary Information
MT88E43B
Ring Burst Line Reversal
First Ring Cycle
Ch. seizure A/B Wires A TRIGout B C
Mark D
Data Packet E F
Note 3
Note 3 50-150ms
PWDN
250-400ms
TE DC load
TE AC load
Note 1
FSKen tCP CD
Note 2
tCA
DR
DCLK
DATA
tPU
..101010..
Data tPD
OSCout
A = 200-450ms B 500ms C = 80-262ms D = 45-262ms E 2.5s (typ. 500ms) F >200ms Note: Parameter F from "CCA Exceptions Document Issue 3"
Figure 18 - Input and Output Timing for CCA Caller Display Service (CDS), e.g., CLIP
Notes: 1) TW/P&E/312 specifies that the AC and DC loads should be removed between 50 to 150ms after the end of the FSK signal, indicated by CD returning to high. The MT88E43B may also be powered down at this time. 2) FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as speech, and DTMF tones. 3) TRIGout represents the ring envelope during ringing.
73
MT88E43B
Preliminary Information
TIP/RING
1st Ring A B
Ch. seizure C
Mark D
Data Packet E F
2nd Ring
TRIGout
Note 4
PWDN
Note 1 tPU
Note 3
Note 1
OSCout tPD FSKen Note 2 tCP tCA
CD
DR
DCLK .101010..
A = 2sec typical B = 250-500ms C = 250ms D = 150ms E = feature specific Max C+D+E = 2.9 to 3.7sec F 200ms
Data
DATA
Figure 19 - Input and Output Timing for Bellcore On-hook Data Transmission Associated with Ringing, e.g., CID
Notes: This on-hook case application is included because a CIDCW (off-hook) CPE must be also capable of receiving on-hook data transmission (with ringing) from the end office. TR-NWT-000575 specifies that CIDCW will be offered only to lines which subscribe to CID. 1) The CPE designer may choose to enable the MT88E43B only after the end of ringing to conserve power in a battery operated CPE. CD is not activated by ringing. 2) The CPE designer may choose to set FSKen always high while the CPE is on-hook. Setting FSKen low prevents the FSK demodulator from reacting to other in-band signals such as speech, CAS or DTMF tones. 3) The microcontroller in the CPE powers down the MT88E43B after CD has become inactive. 4) The microcontroller times out if CD is not activated.
74
Preliminary Information
MT88E43B
CPE goes off-hook
CPE mutes handset & disables keypad CPE sends Mark D
Note 5
CPE unmutes handset and enables keypad Data Packet F G
TIP/RING
Note 1
CAS A B
ACK C
E
PWDN
FSKen OSCout
Note 2
Note 3
Note 4
tPU
tDP ESt tGP St/GT tREC StD (Note 6) CD DR
Note 7 Note 8
tDA tGA VTGt tABS tCP tCA
DCLK DATA Data
A = 75-85ms B = 0-100ms C = 55-65ms D = 0-500ms E = 58-75ms F = feature specific G 50ms
Figure 20 - Input and Output Timing for Bellcore Off-hook Data Transmission, e.g., CIDCW
Notes: 1) In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and use battery power while on-hook. The CPE must be also CID (on-hook) capable because TR-NWT-000575 specifies that CIDCW will be offered only to lines which subscribe to CID. 2) Non-FSK signals such as CAS, speech and DTMF tones are in the same frequency band as FSK. They will be demodulated and give false data. The FSKen pin should be set low to disable the FSK demodulator when FSK is not expected. 3) FSKen may be set high as soon as the CPE has finished sending the acknowledgment signal ACK. TR-NWT-000575 specifies that ACK = DTMF D for non-ADSI CPE, A for ADSI CPE. 4) FSKen should be set low when CD has become inactive. 5) In an unsuccessful attempt where the end office does not send the FSK signal, the CPE should unmute the handset and enable the keypad after this interval. 6) SR-TSV-002476 states that it is desirable that the CPE have an on/off switch for the CAS detector. See SW1 in Figure 4. 7) The total recognition time is tREC = tGP + tDP , where tGP is the tone present guard time and tDP is the tone present detect time (refer to section "Dual Tone Detection Guard Time" on page 57 for details). VTGt is the comparator threshold (refer to Figure 4). 8) The total tone absent time is tABS = tGA + tDA, where t GA is the tone absent guard time and tDA is the tone absent detect time (refer to section "Dual Tone Detection Guard Time" on page 57 for details). VTGt is the comparator threshold (refer to Figure 4).
75
Package Outlines
Pin 1
E
A
C L H
e D 4 mils (lead coplanarity) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) A & B Maximum dimensions include allowable mold flash B L
A1
DIM
A A1 B C D E e H L
16-Pin Min
0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.398 (10.1) 0.291 (7.40)
18-Pin Min
0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.447 (11.35) 0.291 (7.40)
20-Pin Min
0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.496 (12.60) 0.291 (7.40)
24-Pin
Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.5985 (15.2) 0.291 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.614 (15.6) 0.299 (7.40) Min
28-Pin
Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.7125 (18.1) 0.299 (7.40)
Max
0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.413 (10.5) 0.299 (7.40)
Max
0.104 (2.65) 0.012 (0.30) 0.030 (0.51) 0.013 (0.318) 0.4625 (11.75) 0.299 (7.40)
Max
0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.512 (13.00) 0.299 (7.40)
0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.697 (17.7) 0.291 (7.40)
0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27)
0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27)
0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27)
0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27)
0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27)
Lead SOIC Package - S Suffix
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters. 2. Converted inch dimensions are not necessarily exact.
General-7
Package Outlines
3 2 1
E1
E
n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A C eA e b eB eC
Plastic Dual-In-Line Packages (PDIP) - E Suffix
8-Pin DIM Min A A2 b b2 C D D1 E E1 e eA L eB eC
0 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.355 (9.02) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11)
16-Pin Plastic Max Min Max
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.780 (19.81) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014(0.356) 0.800 (20.32)
18-Pin Plastic Min Max
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.880 (22.35) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.920 (23.37)
20-Pin Plastic Min Max
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.980 (24.89) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 1.060 (26.9)
Plastic
0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.400 (10.16)
0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52)
0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52)
0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52)
0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52)
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
General-8
Package Outlines
3 2 1
E1
E
n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters)
A C eA
e b
eB
Plastic Dual-In-Line Packages (PDIP) - E Suffix
22-Pin DIM Min A A2 b b2 C D D1 E E E1 E1 e eA eA eB L
0.115 (2.93) 0.160 (4.06) 15 0.100 BSC (2.54) 0.400 BSC (10.16) 0.330 (8.39) 0.380 (9.65) 0.125 (3.18) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 1.050 (26.67) 0.005 (0.13) 0.390 (9.91) 0.430 (10.92)
24-Pin Plastic Max Min Max
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.150 (29.3) 0.005 (0.13) 0.600 (15.24) 0.290 (7.37) 0.485 (12.32) 0.246 (6.25) 0.670 (17.02) .330 (8.38) 0.580 (14.73) 0.254 (6.45) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.290 (32.7)
28-Pin Plastic Min Max
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.380 (35.1) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.565 (39.7)
40-Pin Plastic Min Max
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.980 (50.3) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 2.095 (53.2)
Plastic
0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.120 (28.44)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
0.100 BSC (2.54) 0.600 BSC (15.24) 0.300 BSC (7.62) 0.430 (10.92) 0.115 (2.93) 0.200 (5.08) 15
0.100 BSC (2.54) 0.600 BSC (15.24)
0.100 BSC (2.54) 0.600 BSC (15.24)
0.115 (2.93)
0.200 (5.08) 15
0.115 (2.93)
0.200 (5.08) 15
Shaded areas for 300 Mil Body Width 24 PDIP only
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