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User's Manual
PD780318, 780328, 780338 Subseries
8-Bit Single-Chip Microcontrollers
PD780316 PD780318 PD780326 PD780328 PD780336 PD780338 PD78F0338
Document No. U14701EJ3V0UD00 (3rd edition) Date Published September 2002 N CP(K)
(c)
Printed in Japan
2000, 2002
[MEMO]
2
User's Manual U14701EJ3V0UD
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP, EEPROM, and IEBus are trademarks of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. Ethernet is a trademark of Xerox Corporation. OSF/Motif is a trademark of OpenSoftware Foundation, Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
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3
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed: PD78F0338GC-9EB, 78F0338GC-9EV The customer must judge the need for a license for the following products:
PD780316GC-xxx-9EB, 780316GC-xxx-9EV, 780318GC-xxx-9EB, 780318GC-xxx-9EV, PD780326GC-xxx-9EB, 780326GC-xxx-9EV, 780328GC-xxx-9EB, 780328GC-xxx-9EV, PD780336GC-xxx-9EB, 780336GC-xxx-9EV, 780338GC-xxx-9EB, 780338GC-xxx-9EV
* The information in this document is current as of July, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4
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User's Manual U14701EJ3V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
* Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
* Branch Sweden Taeby, Sweden Tel: 08-63 80 820 NEC Electronics (Europe) GmbH Fax: 08-63 80 388 Duesseldorf, Germany * United Kingdom Branch Tel: 0211-65 03 01 Milton Keynes, UK Fax: 0211-65 03 327 Tel: 01908-691-133 Fax: 01908-670-290 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
J02.4
User's Manual U14701EJ3V0UD
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Major Revisions in This Edition
Page p.57 Description Change of Recommended Connection of Unused Pins for the following pins in Table 2-1 Pin I/O Circuit Types * P60 to P63 * P80/S32 to P87/S39 (for flash memory version) * P90/S24 to P97/S31 (for flash memory version) Addition of description to (1) Internal high-speed RAM and (2) Internal expansion RAM in 3.1.2 Internal data memory space Change of Manipulatable Bit Unit for ports 8 and 9 in Table 3-4 Special Function Register List Modification of Figure 4-18 P80 to P87 and P90 to P97 Block Diagram (Flash Memory Version) Modification of Caution in 4.2.11 Port 12 Modification of clear conditions in 7.3 (1) 16-bit timer counter 4 (TM4) Modification of Figure 7-1 16-Bit Timer/Event Counter 4 Block Diagram Modification of Note in Table 17-4 Frame Frequency Modification of Figure 17-6 Static/Dynamic Display Switching Register 3 (SDSEL3) Format Switch in order between 17.4 LCD Controller/Driver Settings and 17.5 LCD Display RAM of previous edition Deletion of Table 17-7 LCD Drive Voltages of previous edition
p.66
p.75 p.112 p.113 p.165 p.165 p.284 p.286 pp.288 and 289
p.291 in previous edition pp.291 to 293 and 390
Standardization of abbreviations * Output voltage of VLC0 pin: VLCD0 * Output voltage of VLC1 pin: VLCD1 * Output voltage of VLC2 pin: VLCD2 Addition of description to 17.8.1 Static display example Modification of LCD panel connection example * Figure 17-13 Static LCD Panel Connection Example (SDSEL3n = 1: n = 0, 1) * Figure 17-16 3-Time-Division LCD Panel Connection Example (SDSEL3n = 0: n = 0 to 2) * Figure 17-19 4-Time-Division LCD Panel Connection Example (SDSEL3n = 0, n = 0 to 2) Change of emulation probe name SWEX-120SE SWEX-120SE-1 Modification of Figure D-1 Distance from In-Circuit Emulator to Conversion Socket Modification of Figure D-2 Connection Condition of Target System The mark shows major revised points.
p.295
p.296 p.299 p.302 pp.406, 410, and 411 p.410 p.411
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User's Manual U14701EJ3V0UD
INTRODUCTION
Readers
This manual has been prepared for user engineers who wish to understand the functions of the PD780318, 780328, and 780338 Subseries and design and develop application systems and programs for these devices.
PD780318 Subseries: PD780316, 780318 PD780328 Subseries: PD780326, 780328 PD780338 Subseries: PD780336, 780338, 78F0338
Purpose This manual is intended to give users an understanding of the functions described in the organization below. Organization The PD780318, 780328, and 780338 Subseries manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series).
PD780318, 780328, 780338
Subseries User's Manual (This Manual) * Pin functions * Internal block functions * Interrupt * Other on-chip peripheral functions * Electrical specifications
78K/0 Series User's Manual Instructions * CPU functions * Instruction set * Explanation of each instruction
How To Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. * To gain a general understanding of functions: Read this manual in the order of the contents. * How to interpret the register format: For the bit number enclosed in square, the bit name is defined as a reserved word in RA78K0, and in CC78K0, already defined in the header file named sfrbit.h. * To check the details of a register when you know the register name. Refer to APPENDIX E REGISTER INDEX. Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary Decimal *** xxxx or xxxxB *** xxxx
Hexadecimal *** xxxxH
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Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No. This document U12326E
PD780318, 780328, 780338 Subseries User's Manual
78K/0 Series Instructions User's Manual
Documents Related to Development Software Tools (User's Manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later SM78K Series System Simulator Ver. 2.10 or Later ID78K Series Integrated Debugger Ver. 2.30 or Later RX78K0 Real-time OS Operation (WindowsTM Based) External Part User Open Interface Specifications Operation (Windows Based) Fundamentals Installation Project Manager Ver. 3.12 or Later (Windows Based) Document No. U14445E U14446E U11789E U14297E U14298E U14611E U15006E U15185E U11537E U11536E U14610E
Documents Related to Development Hardware Tools (User's Manuals)
Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-780338-NS-EM1 Emulation Board Document No. U13731E U14889E To be prepared
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
8
User's Manual U14701EJ3V0UD
Documents Related to Flash Memory Writing
Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Products & Packages Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
User's Manual U14701EJ3V0UD
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CONTENTS
CHAPTER 1 OUTLINE ...................................................................................................................... 1.1 Features ................................................................................................................................ 1.2 Applications ......................................................................................................................... 1.3 Ordering Information ........................................................................................................... 1.4 Pin Configuration (Top View) ..............................................................................................
1.4.1 1.4.2 1.4.3 1.4.4
27 27 28 28 29
29 31 33 35
PD780316, 780318 ................................................................................................................. PD780326, 780328 ................................................................................................................. PD780336, 780338 ................................................................................................................. PD78F0338 .............................................................................................................................
1.5 1.6
78K/0 Series Lineup ............................................................................................................. Block Diagram ......................................................................................................................
1.6.1 1.6.2 1.6.3 1.6.4
37 39
39 40 41 42
PD780316, 780318 ................................................................................................................. PD780326, 780328 ................................................................................................................. PD780336, 780338 ................................................................................................................. PD78F0338 .............................................................................................................................
1.7 1.8
Outline of Functions ............................................................................................................ Mask Options .......................................................................................................................
43 45 46 46 50
50 50 51 51 52 52 52 52 53 53 54 54 54 54 54 54 54 54 55 55 55 55 55 55
CHAPTER 2 PIN FUNCTIONS ......................................................................................................... 2.1 Pin Function List .................................................................................................................. 2.2 Description of Pin Functions ..............................................................................................
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 P00 to P05 (Port 0) ................................................................................................................... P10 to P17 (Port 1) ................................................................................................................... P20 to P25 (Port 2) ................................................................................................................... P30 to P34 (Port 3) ................................................................................................................... P40 to P47 (Port 4) ................................................................................................................... P50 to P57 (Port 5) ................................................................................................................... P60 to P67 (Port 6) ................................................................................................................... P70 to P73 (Port 7) ................................................................................................................... P80 to P87 (Port 8) ...................................................................................................................
2.2.10 P90 to P97 (Port 9) ................................................................................................................... 2.2.11 P120 (Port 12) ........................................................................................................................... 2.2.12 ANI0 to ANI9 ............................................................................................................................. 2.2.13 AVREF0 ....................................................................................................................................... 2.2.14 AVREF1 ....................................................................................................................................... 2.2.15 AVSS0 ......................................................................................................................................... 2.2.16 S0 to S39 .................................................................................................................................. 2.2.17 COM0 to COM3 ........................................................................................................................ 2.2.18 SCOM0 ..................................................................................................................................... 2.2.19 VLC0 to VLC2 ................................................................................................................................ 2.2.20 VLCDC ......................................................................................................................................... 2.2.21 CAPH and CAPL ....................................................................................................................... 2.2.22 RESET ...................................................................................................................................... 2.2.23 X1 and X2 ................................................................................................................................. 2.2.24 XT1 and XT2 .............................................................................................................................
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2.2.25 VDD0 and VDD1 ............................................................................................................................ 2.2.26 VSS0 and VSS1 ............................................................................................................................ 2.2.27 VPP (flash memory versions only) ............................................................................................. 2.2.28 IC (mask ROM version only) .....................................................................................................
55 55 55 56
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins ...................................
57 61 61
65 66 66 67
CHAPTER 3 CPU ARCHITECTURE ................................................................................................ 3.1 Memory Spaces ....................................................................................................................
3.1.1 3.1.2 3.1.3 3.1.4 Internal program memory space ............................................................................................... Internal data memory space ..................................................................................................... Special function register (SFR) area ......................................................................................... Data memory addressing .......................................................................................................... Control registers ........................................................................................................................ General-purpose registers ........................................................................................................ Special function register (SFR) ................................................................................................. Relative addressing ................................................................................................................... Immediate addressing ............................................................................................................... Table indirect addressing .......................................................................................................... Register addressing .................................................................................................................. Implied addressing .................................................................................................................... Register addressing .................................................................................................................. Direct addressing ...................................................................................................................... Short direct addressing ............................................................................................................. Special function register (SFR) addressing ............................................................................... Register indirect addressing ...................................................................................................... Based addressing ..................................................................................................................... Based indexed addressing ........................................................................................................ Stack addressing .......................................................................................................................
3.2
Processor Registers ............................................................................................................
3.2.1 3.2.2 3.2.3
70
70 73 74
3.3
Instruction Address Addressing ........................................................................................
3.3.1 3.3.2 3.3.3 3.3.4
79
79 80 81 82
3.4
Operand Address Addressing ............................................................................................
3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9
83
83 84 85 86 88 89 90 91 91
CHAPTER 4 PORT FUNCTIONS ..................................................................................................... 4.1 Port Functions ...................................................................................................................... 4.2 Port Configuration ...............................................................................................................
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 Port 0 ......................................................................................................................................... Port 1 ......................................................................................................................................... Port 2 ......................................................................................................................................... Port 3 ......................................................................................................................................... Port 4 ......................................................................................................................................... Port 5 ......................................................................................................................................... Port 6 ......................................................................................................................................... Port 7 ......................................................................................................................................... Ports 8 and 9 (mask ROM version) ...........................................................................................
92 92 96
96 98 99 101 104 106 107 109 111 112 113
4.2.10 Ports 8 and 9 (flash memory version) ....................................................................................... 4.2.11 Port 12 .......................................................................................................................................
4.3 4.4
Port Function Control Registers ........................................................................................ 114 Port Function Operations .................................................................................................... 120
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4.4.1 4.4.2 4.4.3
Writing to I/O port ...................................................................................................................... Reading from I/O port ............................................................................................................... Operations on I/O port ..............................................................................................................
120 120 120
4.5
Selection of Mask Option .................................................................................................... 121 122 122 122 124 126
126 127 130 130 132 133 134 135
CHAPTER 5 CLOCK GENERATOR ................................................................................................ 5.1 Clock Generator Functions ................................................................................................. 5.2 Clock Generator Configuration .......................................................................................... 5.3 Clock Generator Control Register ...................................................................................... 5.4 System Clock Oscillator ......................................................................................................
5.4.1 5.4.2 5.4.3 5.4.4 Main system clock oscillator ...................................................................................................... Subsystem clock oscillator ........................................................................................................ Divider ....................................................................................................................................... When no subsystem clocks are used ........................................................................................ Main system clock operations ................................................................................................... Subsystem clock operations ..................................................................................................... Time required for switchover between system clock and CPU clock ........................................ System clock and CPU clock switching procedure ...................................................................
5.5
Clock Generator Operations ............................................................................................... 131
5.5.1 5.5.2
5.6
Changing System Clock and CPU Clock Settings ............................................................ 134
5.6.1 5.6.2
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 ......................................................................... 6.1 Outline of 16-Bit Timer/Event Counter 0 ............................................................................ 6.2 16-Bit Timer/Event Counter 0 Functions ........................................................................... 6.3 16-Bit Timer/Event Counter 0 Configuration ..................................................................... 6.4 Registers to Control 16-Bit Timer/Event Counter 0 .......................................................... 6.5 16-Bit Timer/Event Counter 0 Operations ..........................................................................
6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 Interval timer operations ............................................................................................................ PPG output operations .............................................................................................................. Pulse width measurement operations ....................................................................................... External event counter operation .............................................................................................. Square-wave output operation ..................................................................................................
136 136 136 137 140 146
146 148 149 156 157
6.6
16-Bit Timer/Event Counter 0 Cautions ............................................................................. 159 164 164 164 164 166 169
169 172 173
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 4 ......................................................................... 7.1 Outline of 16-Bit Timer/Event Counter 4 ............................................................................ 7.2 16-Bit Timer/Event Counter 4 Functions ........................................................................... 7.3 16-Bit Timer/Event Counter 4 Configuration ..................................................................... 7.4 Registers to Control 16-Bit Timer/Event Counter 4 .......................................................... 7.5 16-Bit Timer/Event Counter 4 Operations ..........................................................................
7.5.1 7.5.2 7.5.3 Interval timer operation ............................................................................................................. Square-wave output operation .................................................................................................. External event counter operation ..............................................................................................
7.6
16-Bit Timer/Event Counter 4 Cautions ............................................................................. 174
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51, 52 ........................................................ 175 8.1 Outline of 8-Bit Timer/Event Counters 50, 51, and 52 ...................................................... 175 8.2 8-Bit Timer/Event Counters 50, 51, and 52 Functions ...................................................... 175
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8.3 8.4 8.5
8-Bit Timer/Event Counters 50, 51, and 52 Configurations .............................................. 178 Registers to Control 8-Bit Timer/Event Counters 50, 51, and 52 ..................................... 179 8-Bit Timer/Event Counters 50, 51, and 52 Operations .................................................... 184
8.5.1 8.5.2 8.5.3 8.5.4 Interval timer operation ............................................................................................................. External event counter operation .............................................................................................. Square-wave output operation .................................................................................................. PWM output operation .............................................................................................................. 184 187 188 189
8.6
8-Bit Timer/Event Counters 50, 51, and 52 Cautions ........................................................ 192 193 193 193 195 195 197
197 197
CHAPTER 9 WATCH TIMER ........................................................................................................... 9.1 Outline of Watch Timer ........................................................................................................ 9.2 Watch Timer Functions ....................................................................................................... 9.3 Watch Timer Configuration ................................................................................................. 9.4 Register to Control Watch Timer ........................................................................................ 9.5 Watch Timer Operations .....................................................................................................
9.5.1 9.5.2 Watch timer operation ............................................................................................................... Interval timer operation .............................................................................................................
CHAPTER 10 WATCHDOG TIMER ................................................................................................. 10.1 Outline of Watchdog Timer ................................................................................................. 10.2 Watchdog Timer Functions ................................................................................................. 10.3 Watchdog Timer Configuration .......................................................................................... 10.4 Registers to Control Watchdog Timer ............................................................................... 10.5 Watchdog Timer Operations ...............................................................................................
10.5.1 Watchdog timer operation ......................................................................................................... 10.5.2 Interval timer operation .............................................................................................................
198 198 198 200 200 204
204 205
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLERS ........................................ 11.1 Outline of Clock Output/Buzzer Output Controllers ......................................................... 11.2 Clock Output/Buzzer Output Controller Functions .......................................................... 11.3 Clock Output/Buzzer Output Controller Configuration .................................................... 11.4 Registers to Control Clock Output/Buzzer Output Controllers ....................................... 11.5 Clock Output/Buzzer Output Controller Operations .........................................................
11.5.1 Operation as clock output ......................................................................................................... 11.5.2 Operation as buzzer output .......................................................................................................
206 206 206 207 207 210
210 210
CHAPTER 12 A/D CONVERTER ..................................................................................................... 12.1 A/D Converter Functions ..................................................................................................... 12.2 A/D Converter Configuration .............................................................................................. 12.3 Registers to Control A/D Converter ................................................................................... 12.4 A/D Converter Operation .....................................................................................................
12.4.1 Basic operations of A/D converter ............................................................................................. 12.4.2 Input voltage and conversion results ......................................................................................... 12.4.3 A/D converter operation mode ..................................................................................................
211 211 212 213 216
216 218 219
12.5 How to Read the A/D Converter Characteristics Table .................................................... 222 12.6 A/D Converter Cautions ...................................................................................................... 225 CHAPTER 13 D/A CONVERTER ..................................................................................................... 231
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13.1 13.2 13.3 13.4
D/A Converter Functions ..................................................................................................... D/A Converter Configuration .............................................................................................. Register to Control D/A Converter ..................................................................................... D/A Converter Operation .....................................................................................................
13.4.1 Basic operations of D/A converter ............................................................................................. 13.4.2 Operation during standby mode ................................................................................................ 13.4.3 Operation at reset .....................................................................................................................
231 231 233 234
234 234 234
13.5 D/A Converter Cautions ...................................................................................................... 234 CHAPTER 14 SERIAL INTERFACE UART0 .................................................................................. 14.1 Serial Interface UART0 Functions ...................................................................................... 14.2 Serial Interface UART0 Configuration ................................................................................ 14.3 Registers to Control Serial Interface UART0 ..................................................................... 14.4 Serial Interface UART0 Operations ....................................................................................
14.4.1 Operation stop mode ................................................................................................................. 14.4.2 Asynchronous serial interface (UART) mode ............................................................................
236 236 238 239 243
243 244
CHAPTER 15 SERIAL INTERFACE SIO3 ...................................................................................... 15.1 Serial Interface SIO3 Functions .......................................................................................... 15.2 Serial Interface SIO3 Configuration ................................................................................... 15.3 Register to Control Serial Interface SIO3 .......................................................................... 15.4 Serial Interface SIO3 Operations ........................................................................................
15.4.1 Operation stop mode ................................................................................................................. 15.4.2 3-wire serial I/O mode ...............................................................................................................
256 256 257 258 260
260 261
CHAPTER 16 SERIAL INTERFACE CSI1 ...................................................................................... 16.1 Serial Interface CSI1 Functions .......................................................................................... 16.2 Serial Interface CSI1 Configuration .................................................................................... 16.3 Registers to Control Serial Interface CSI1 ......................................................................... 16.4 Serial Interface CSI1 Operations ........................................................................................
16.4.1 Operation stop mode ................................................................................................................. 16.4.2 3-wire serial I/O mode ...............................................................................................................
264 264 264 266 268
268 268
CHAPTER 17 LCD CONTROLLER/DRIVER ................................................................................... 17.1 LCD Controller/Driver Functions ........................................................................................ 17.2 LCD Controller/Driver Configuration ................................................................................. 17.3 Registers to Control LCD Controller/Driver ...................................................................... 17.4 LCD Display RAM ................................................................................................................. 17.5 LCD Controller/Driver Settings ........................................................................................... 17.6 Common Signals and Segment Signals ............................................................................ 17.7 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 ........................................................... 17.8 Display Modes ......................................................................................................................
17.8.1 Static display example ............................................................................................................... 17.8.2 3-time-division display example ................................................................................................ 17.8.3 4-time-division display example ................................................................................................ 17.8.4 Simultaneous driving of static display and dynamic display ......................................................
278 278 279 281 288 289 290 293 295
295 298 301 304
CHAPTER 18 INTERRUPT FUNCTIONS ........................................................................................ 305
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18.1 18.2 18.3 18.4
Interrupt Function Types ..................................................................................................... Interrupt Sources and Configuration ................................................................................. Interrupt Function Control Registers ................................................................................. Interrupt Servicing Operations ...........................................................................................
18.4.1 Non-maskable interrupt request acknowledge operation .......................................................... 18.4.2 Maskable interrupt request acknowledge operation .................................................................. 18.4.3 Software interrupt request acknowledge operation ................................................................... 18.4.4 Nesting processing .................................................................................................................... 18.4.5 Interrupt request hold ................................................................................................................
305 305 309 315
315 318 320 321 324
CHAPTER 19 STANDBY FUNCTION .............................................................................................. 325 19.1 Standby Function and Configuration ................................................................................. 325
19.1.1 Standby function ....................................................................................................................... 19.1.2 Standby function control register ............................................................................................... 19.2.1 HALT mode ............................................................................................................................... 19.2.2 STOP mode .............................................................................................................................. 325 326 327 330
19.2 Standby Function Operations ............................................................................................. 327
CHAPTER 20 RESET FUNCTION ................................................................................................... 333 20.1 Reset Function ..................................................................................................................... 333 CHAPTER 21 ROM CORRECTION ................................................................................................... 21.1 ROM Correction Function ................................................................................................... 21.2 ROM Correction Configuration ........................................................................................... 21.3 ROM Correction Control Register ...................................................................................... 21.4 ROM Correction Application ............................................................................................... 21.5 ROM Correction Example .................................................................................................... 21.6 Program Execution Flow ..................................................................................................... 21.7 Cautions on ROM Correction .............................................................................................. CHAPTER 22 PD78F0338 ............................................................................................................... 22.1 Memory Size Switching Register ........................................................................................ 22.2 Internal Expansion RAM Size Switching Register ............................................................ 22.3 Flash Memory Characteristics ............................................................................................
22.3.1 Programming environment ........................................................................................................ 22.3.2 Communication mode ............................................................................................................... 22.3.3 On-board pin processing ...........................................................................................................
337 337 337 339 340 343 344 346 347 348 349 350
350 351 353
CHAPTER 23 INSTRUCTION SET .................................................................................................. 356 23.1 Conventions ......................................................................................................................... 357
23.1.1 Operand identifiers and specification methods ......................................................................... 23.1.2 Description of "operation" column ............................................................................................. 23.1.3 Description of "flag operation" column ....................................................................................... 357 358 358
23.2 Operation List ....................................................................................................................... 359 23.3 Instructions Listed by Addressing Type ........................................................................... 367 CHAPTER 24 ELECTRICAL SPECIFICATIONS ............................................................................. 371
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CHAPTER 25 PACKAGE DRAWINGS ............................................................................................ 396 CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS ....................................................... 398 APPENDIX A DIFFERENCES BETWEEN PD780308, 780318, 780328, AND 780338 SUBSERIES .......................................................................................... 399 APPENDIX B DEVELOPMENT TOOLS .......................................................................................... B.1 Language Processing Software ......................................................................................... B.2 Flash Memory Writing Tools ............................................................................................... B.3 Debugging Tools ..................................................................................................................
B.3.1 B.3.2 Hardware ................................................................................................................................... Software ....................................................................................................................................
401 403 405 406
406 407
APPENDIX C EMBEDDED SOFTWARE ......................................................................................... 409 APPENDIX D NOTES ON DESIGNING TARGET SYSTEM ......................................................... 410 APPENDIX E REGISTER INDEX ..................................................................................................... 412 E.1 Register Name Index ........................................................................................................... 412 E.2 Register Symbol Index ........................................................................................................ 415 APPENDIX F REVISION HISTORY ................................................................................................. 418
16
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LIST OF FIGURES (1/7)
Figure No. 2-1
Title Pin I/O Circuit List ................................................................................................................................
Page 59
3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12
Memory Map (PD780316, 780326, 780336) ..................................................................................... Memory Map (PD780318, 780328, 780338) ..................................................................................... Memory Map (PD78F0338) ............................................................................................................... Data Memory Addressing (PD780316, 780326, 780336) .................................................................. Data Memory Addressing (PD780318, 780328, 780338) .................................................................. Data Memory Addressing (PD78F0338) ............................................................................................ Program Counter Format ..................................................................................................................... Program Status Word Format .............................................................................................................. Stack Pointer Format ........................................................................................................................... Data to Be Saved to Stack Memory ..................................................................................................... Data to Be Restored from Stack Memory ............................................................................................ General-Purpose Register Configuration .............................................................................................
62 63 64 67 68 69 70 70 72 72 72 73
4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24
Port Types ............................................................................................................................................ P00 to P04 Block Diagram ................................................................................................................... P05 Block Diagram .............................................................................................................................. P10 to P17 Block Diagram ................................................................................................................... P20, P22, P23, P25 Block Diagram ..................................................................................................... P21, P24 Block Diagram ...................................................................................................................... P30 Block Diagram .............................................................................................................................. P31, P32 Block Diagram ...................................................................................................................... P33, P34 Block Diagram ...................................................................................................................... P40 to P47 Block Diagram ................................................................................................................... Falling Edge Detector Block Diagram .................................................................................................. P50 to P57 Block Diagram ................................................................................................................... P60 to P63 Block Diagram ................................................................................................................... P64 to P67 Block Diagram ................................................................................................................... P70, P72 Block Diagram ...................................................................................................................... P71, P73 Block Diagram ...................................................................................................................... P80 to P87 and P90 to P97 Block Diagram (Mask ROM Version) ....................................................... P80 to P87 and P90 to P97 Block Diagram (Flash Memory Version) .................................................. P120 Block Diagram ............................................................................................................................ Port Mode Registers (PM0, PM2 to PM9, PM12) Format .................................................................... Pull-Up Resistor Option Registers (PU0, PU2 to PU7, PU12) Format ................................................ Memory Expansion Mode Register (MEM) Format ............................................................................. Key Return Switching Register (KRSEL) Format ................................................................................. Pin Function Switching Registers 8 and 9 (PF8, PF9) Format ............................................................
93 97 98 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 115 117 118 118 119
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LIST OF FIGURES (2/7)
Figure No. 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8
Title Clock Generator Block Diagram ........................................................................................................... Subsystem Clock Feedback Resistor .................................................................................................. Processor Clock Control Register (PCC) Format ................................................................................ External Circuit of Main System Clock Oscillator ................................................................................. External Circuit of Subsystem Clock Oscillator .................................................................................... Examples of Incorrect Resonator Connection ..................................................................................... Main System Clock Stop Function ....................................................................................................... System Clock and CPU Clock Switching .............................................................................................
Page 123 124 125 126 127 128 132 135
6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11
16-Bit Timer/Event Counter 0 Block Diagram ...................................................................................... 16-Bit Timer Mode Control Register 0 (TMC0) Format ........................................................................ Capture/Compare Control Register 0 (CRC0) Format ......................................................................... 16-Bit Timer Output Control Register 0 (TOC0) Format ...................................................................... Prescaler Mode Register 0 (PRM0) Format ......................................................................................... Port Mode Register 3 (PM3) Format .................................................................................................... Control Register Settings for Interval Timer Operation ........................................................................ Interval Timer Configuration Diagram .................................................................................................. Timing of Interval Timer Operation ....................................................................................................... Control Register Settings for PPG Output Operation ........................................................................... Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register ...................................................................................................................
137 141 142 143 144 145 146 147 147 148
149 150
6-12 6-13
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ................................ Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) ......................................................................
150 151 152
6-14 6-15 6-16
Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ............ Capture Operation of CR01 with Rising Edge Specified ...................................................................... Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) .................................................................................................................
152
6-17
Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers ......................................................................................................................... 153
6-18
Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) .................................................................... 154 155 155 156 157 157 158 158 159
6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26
Control Register Settings for Pulse Width Measurement by Means of Restart ................................... Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) ... Control Register Settings in External Event Counter Mode ................................................................. External Event Counter Configuration Diagram ................................................................................... External Event Counter Operation Timings (with Rising Edge Specified) ............................................ Control Register Settings in Square-Wave Output Mode ..................................................................... Square-Wave Output Operation Timing ............................................................................................... 16-Bit Timer Counter 0 (TM0) Start Timing ..........................................................................................
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LIST OF FIGURES (3/7)
Figure No. 6-27 6-28 6-29
Title Timings After Change of Compare Register During Timer Count Operation ....................................... Capture Register Data Retention Timing ............................................................................................. Operation Timing of OVF0 Flag ...........................................................................................................
Page 159 160 161
7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8
16-Bit Timer/Event Counter 4 Block Diagram ...................................................................................... 16-Bit Timer Mode Control Register 4 (TMC4) Format ........................................................................ Port Mode Register 7 (PM7) Format .................................................................................................... Interval Timer Operation Timings ......................................................................................................... Square-Wave Output Operation Timing ............................................................................................... External Event Counter Operation Timing ........................................................................................... 16-Bit Timer Counter 4 (TM4) Start Timing .......................................................................................... Timings After Change of Compare Register During Timer Count Operation .......................................
165 167 168 170 172 173 174 174
8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15
8-Bit Timer/Event Counter 50 Block Diagram ...................................................................................... 8-Bit Timer/Event Counter 51 Block Diagram ...................................................................................... 8-Bit Timer/Event Counter 52 Block Diagram ...................................................................................... Timer Clock Select Register 50 (TCL50) Format ................................................................................. Timer Clock Select Register 51 (TCL51) Format ................................................................................. Timer Clock Select Register 52 (TCL52) Format ................................................................................. 8-Bit Timer Mode Control Register 5n (TMC5n) Format ...................................................................... Port Mode Registers 3, 7 (PM3, PM7) Format ..................................................................................... Interval Timer Operation Timings ......................................................................................................... External Event Counter Operation Timing (with Rising Edge Specified) ............................................. Square-Wave Output Operation Timing ............................................................................................... PWM Output Operation Timing ............................................................................................................ Timing of Operation by CR5n Transition .............................................................................................. 8-Bit Timer Counter Start Timing ......................................................................................................... Timing After Compare Register Change During Timer Count Operation .............................................
176 176 177 179 180 181 182 183 184 187 188 190 191 192 192
9-1 9-2 9-3
Watch Timer Block Diagram ................................................................................................................. Watch Timer Operation Mode Register 0 (WTNM0) Format ................................................................ Operation Timing of Watch Timer/Interval Timer ..................................................................................
193 196 197
10-1 10-2 10-3 10-4
Watchdog Timer Block Diagram ........................................................................................................... Watchdog Timer Clock Select Register (WDCS) Format ..................................................................... Watchdog Timer Mode Register (WDTM) Format ............................................................................... Oscillation Stabilization Time Select Register (OSTS) Format ............................................................
198 201 202 203
11-1 11-2
Clock Output/Buzzer Output Controller Block Diagram ....................................................................... Clock Output Select Register (CKS) Format ........................................................................................
206 208
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LIST OF FIGURES (4/7)
Figure No. 11-3 11-4
Title Port Mode Register 0 (PM0) Format .................................................................................................... Remote Control Output Application Example ......................................................................................
Page 209 210
12-1 12-2 12-3 12-4
A/D Converter Block Diagram .............................................................................................................. A/D Converter Mode Register 0 (ADM0) Format ................................................................................. Analog Input Channel Specification Register 0 (ADS0) Format .......................................................... External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Format ..........................................................
211 214 215
215 217 218 220 221 222 222 223 223 223 223 225 226 227 228 228 229 230 230
12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22
Basic Operation of A/D Converter ........................................................................................................ Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................. A/D Conversion by Software Start ....................................................................................................... Overall Error ......................................................................................................................................... Quantization Error ................................................................................................................................ Zero Scale Error ................................................................................................................................... Full Scale Error .................................................................................................................................... Integral Linearity Error ......................................................................................................................... Differential Linearity Error .................................................................................................................... Example of Method of Reducing Current Consumption in Standby Mode ........................................... Analog Input Pin Connection ............................................................................................................... A/D Conversion End Interrupt Request Generation Timing ................................................................. Timing of Reading Conversion Result (When Conversion Result Is Undefined) ................................. Timing of Reading Conversion Result (When Conversion Result Is Normal) ...................................... Example of Connecting Capacitor to VDD1 and AVREF0 Pins ................................................................. Internal Equivalent Circuit of ANI0 to ANI9 Pins .................................................................................. Example of Connection If Signal Source Impedance Is High ..............................................................
13-1 13-2 13-3
D/A Converter Block Diagram .............................................................................................................. D/A Converter Mode Register 0 (DAM0) Format ................................................................................. Buffer Amp Insertion Example .............................................................................................................
232 233 235
14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9
Serial Interface UART0 Block Diagram ................................................................................................ Baud Rate Generator Block Diagram .................................................................................................. Asynchronous Serial Interface Mode Register 0 (ASIM0) Format ....................................................... Asynchronous Serial Interface Status Register 0 (ASIS0) Format ...................................................... Baud Rate Generator Control Register 0 (BRGC0) Format ................................................................. Baud Rate Error Tolerance (When k = 0), Including Sampling Errors .................................................. Format of Transmit/Receive Data in Asynchronous Serial Interface .................................................... Timing of Asynchronous Serial Interface Transmit Completion Interrupt Request ............................... Timing of Asynchronous Serial Interface Receive Completion Interrupt Request ...............................
237 237 240 241 242 250 251 253 254
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LIST OF FIGURES (5/7)
Figure No. 14-10
Title Receive Error Timing ...........................................................................................................................
Page 255
15-1 15-2 15-3
Serial Interface SIO3 Block Diagram ................................................................................................... Serial Operation Mode Register 3 (CSIM3) Format ............................................................................. Timing of 3-Wire Serial I/O Mode ........................................................................................................
256 259 263
16-1 16-2 16-3 16-4 16-5 16-6 16-7
Serial Interface CSI1 Block Diagram .................................................................................................... Serial Operation Mode Register 1 (CSIM1) Format ............................................................................. Serial Clock Select Register 1 (CSIC1) Format ................................................................................... Timing in 3-Wire Serial I/O Mode ......................................................................................................... Timing of Clock/Data Phase ................................................................................................................ Output Operation of First Bit ................................................................................................................ Output Value of SO1 Pin (Last Bit) .......................................................................................................
265 266 267 272 274 275 276
17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8
LCD Controller/Driver Block Diagram .................................................................................................. LCD Display Mode Register 3 (LCDM3) Format .................................................................................. Blinking Function .................................................................................................................................. LCD Clock Control Register 3 (LCDC3) Format .................................................................................. Relationship Between Reference Clock Generating Frame Frequency, and Frame Frequency .......... Static/Dynamic Display Switching Register 3 (SDSEL3) Format ......................................................... Pin Function Switching Registers 8 and 9 (PF8 and PF9) Format ...................................................... Relationship Between LCD Display Data, Contents of Blinking Select Bits, and Segment/Common Output Signals (4-Time Division) ...................................................................
280 282 283 284 285 286 287
288 291 292 293 295 296 297 298 299 300 301 302 303
17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 17-17 17-18 17-19 17-20
Common Signal Waveform .................................................................................................................. Common Signal and Segment Signal Voltages and Phases ............................................................... Example of Circuit to Adjust LCD Driver Reference Voltage ................................................................ Static LCD Panel Display Pattern and Electrode Connections ............................................................ Static LCD Panel Connection Example (SDSEL3n = 1: n = 0, 1) ........................................................ Static LCD Drive Waveform Examples ................................................................................................. 3-Time-Division LCD Display Pattern and Electrode Connections ...................................................... 3-Time-Division LCD Panel Connection Example (SDSEL3n = 0: n = 0 to 2) ..................................... 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ................................................... 4-Time-Division LCD Display Pattern and Electrode Connections ...................................................... 4-Time-Division LCD Panel Connection Example (SDSEL3n = 0, n = 0 to 2) ..................................... 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...................................................
18-1 18-2 18-3 18-4
Basic Configuration of Interrupt Function ............................................................................................ Interrupt Request Flag Registers (IF0L, IF0H, IF1L) Format ............................................................... Interrupt Mask Flag Registers (MK0L, MK0H, MK1L) Format ............................................................. Priority Specification Flag Registers (PR0L, PR0H, PR1L) Format .....................................................
307 310 311 312
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LIST OF FIGURES (6/7)
Figure No. 18-5
Title External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Format ..........................................................
Page
313 314 316 316 317 319 320 320 322 324
18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14
Program Status Word Format .............................................................................................................. Non-Maskable Interrupt Request Generation to Acknowledge Flowchart ........................................... Non-Maskable Interrupt Request Acknowledge Timing ....................................................................... Non-Maskable Interrupt Request Acknowledge Operation .................................................................. Interrupt Request Acknowledge Processing Algorithm ........................................................................ Interrupt Request Acknowledge Timing (Minimum Time) .................................................................... Interrupt Request Acknowledge Timing (Maximum Time) ................................................................... Nesting Examples ................................................................................................................................ Interrupt Request Hold .........................................................................................................................
19-1 19-2 19-3 19-4 19-5
Oscillation Stabilization Time Select Register (OSTS) Format ............................................................ HALT Mode Release by Interrupt Request Generation ........................................................................ HALT Mode Release by RESET Input ................................................................................................. STOP Mode Release by Interrupt Request Generation ....................................................................... STOP Mode Release by RESET Input ................................................................................................
326 328 329 331 332
20-1 20-2 20-3 20-4
Reset Function Block Diagram ............................................................................................................ Timing of Reset by RESET Input ......................................................................................................... Timing of Reset Due to Watchdog Timer Overflow .............................................................................. Timing of Reset in STOP Mode by RESET Input .................................................................................
333 334 334 334
21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9
ROM Correction Block Diagram ........................................................................................................... Correction Address Registers 0 and 1 Format ..................................................................................... Correction Control Register (CORCN) Format .................................................................................... Storing Example to EEPROM (When One Place Is Corrected) ........................................................... Initialization Routine ............................................................................................................................. ROM Correction Operation .................................................................................................................. ROM Correction Example .................................................................................................................... Program Transition Diagram (When One Place Is Corrected) ............................................................. Program Transition Diagram (When Two Places Are Corrected) .........................................................
337 338 339 340 341 342 343 344 345
22-1 22-2 22-3 22-4 22-5 22-6 22-7
Memory Size Switching Register (IMS) Format ................................................................................... Internal Expansion RAM Size Switching Register (IXS) Format .......................................................... Environment for Writing Program to Flash Memory ............................................................................. 3-Wire Serial I/O (SIO3) ....................................................................................................................... 3-Wire Serial I/O (CSI1) ....................................................................................................................... UART (UART0) .................................................................................................................................... VPP Pin Connection Example ...............................................................................................................
348 349 350 351 351 352 353
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Figure No. 22-8 22-9 22-10
Title Signal Conflict (Input Pin of Serial Interface) ....................................................................................... Abnormal Operation of Other Device ................................................................................................... Signal Conflict (RESET Pin) ................................................................................................................
Page 354 354 355
B-1
Development Tool Configuration ..........................................................................................................
402
D-1 D-2
Distance from In-Circuit Emulator to Conversion Socket ..................................................................... Connection Condition of Target System ...............................................................................................
410 411
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LIST OF TABLES (1/3)
Table No. 1-1
Title Mask Options of Mask ROM Versions .................................................................................................
Page 45
2-1
Pin I/O Circuit Types .............................................................................................................................
57
3-1 3-2 3-3 3-4
Internal Memory Capacity .................................................................................................................... Vector Table ......................................................................................................................................... Area That Can Be Used as LCD Display Data ..................................................................................... Special Function Register List .............................................................................................................
65 65 66 75
4-1 4-2 4-3 4-4 4-5 4-6
Port Types ............................................................................................................................................ Port Functions ...................................................................................................................................... Port Configuration ................................................................................................................................ Pull-Up Resistor of Port 6 .................................................................................................................... Ports 8 and 9 of Mask ROM Version .................................................................................................... Comparison Between Mask ROM Version and Flash Memory Version ...............................................
92 94 96 107 111 121
5-1 5-2 5-3
Clock Generator Configuration ............................................................................................................ Relationship of CPU Clock and Min. Instruction Execution Time ......................................................... Maximum Time Required for CPU Clock Switchover ...........................................................................
122 126 134
6-1 6-2 6-3
16-Bit Timer/Event Counter 0 Configuration ........................................................................................ TI00/P31 Pin Valid Edge and CR00, CR01 Capture Trigger ................................................................ TI01/P32 Pin Valid Edge and CR00 Capture Trigger ...........................................................................
137 138 138
7-1
16-Bit Timer/Event Counter 4 Configuration ........................................................................................
164
8-1
8-Bit Timer/Event Counters 50, 51, and 52 Configuration ...................................................................
178
9-1 9-2 9-3
Watch Timer Interrupt Request Time ................................................................................................... Interval Timer Interval Time ................................................................................................................. Watch Timer Configuration ..................................................................................................................
194 194 195
10-1 10-2 10-3 10-4 10-5
Watchdog Timer Runaway Detection Time .......................................................................................... Interval Time ........................................................................................................................................ Watchdog Timer Configuration ............................................................................................................ Watchdog Timer Runaway Detection Time .......................................................................................... Interval Timer Interval Time .................................................................................................................
199 199 200 204 205
11-1
Clock Output/Buzzer Output Controllers Configuration .......................................................................
207
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Table No. 12-1 12-2
Title A/D Converter Configuration ................................................................................................................ Resistances and Capacitances of Equivalent Circuit (Reference Values) ...........................................
Page 212 230
13-1
D/A Converter Configuration ................................................................................................................
231
14-1 14-2 14-3 14-4
Serial Interface (UART0) Configuration ............................................................................................... Relationship Between 5-Bit Counter's Source Clock and "n" Value ..................................................... Relationship Between Main System Clock and Baud Rate ................................................................. Causes of Receive Errors ....................................................................................................................
238 248 249 255
15-1
Serial Interface SIO3 Configuration .....................................................................................................
257
16-1 16-2 16-3
Serial Interface CSI1 Configuration ..................................................................................................... SCK1 Pin Status .................................................................................................................................. SO1 Pin Status ....................................................................................................................................
264 277 277
17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10
Segment Signals and Common Signals .............................................................................................. Maximum Number of Pixels Displayed ................................................................................................ LCD Controller/Driver Configuration .................................................................................................... Frame Frequency ................................................................................................................................. COM Signals ........................................................................................................................................ Output Voltages of VLC0 to VLC2 Pins .................................................................................................... Recommended Constants of External Circuit ...................................................................................... Selection and Non-Selection Voltages (SCOM0) ................................................................................. Selection and Non-Selection Voltages (COM0 to COM2) .................................................................... Selection and Non-Selection Voltages (COM0 to COM3) ....................................................................
278 279 279 284 290 293 294 295 298 301
18-1 18-2 18-3 18-4
Interrupt Source List ............................................................................................................................ Flags Corresponding to Interrupt Request Sources ............................................................................ Times from Generation of Maskable Interrupt Until Servicing ............................................................. Interrupt Request Enabled for Nesting During Interrupt Servicing .......................................................
306 309 318 321
19-1 19-2 19-3 19-4
HALT Mode Operating Statuses .......................................................................................................... Operation After HALT Mode Release ................................................................................................... STOP Mode Operating Statuses ......................................................................................................... Operation After STOP Mode Release ..................................................................................................
327 329 330 332
20-1
Hardware Statuses After Reset ...........................................................................................................
335
21-1
ROM Correction Configuration .............................................................................................................
337
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LIST OF TABLES (3/3)
Table No. 22-1 22-2 22-3 22-4
Title Differences Between PD78F0338 and Mask ROM Versions ............................................................. Memory Size Switching Register Settings ........................................................................................... Communication Mode List ................................................................................................................... Pin Connection List ..............................................................................................................................
Page 347 348 351 352
23-1
Operand Identifiers and Specification Methods ...................................................................................
357
26-1
Surface Mounting Type Soldering Conditions ...................................................................................... Major Differences Between PD780308, 780318, 780328, and 780338 Subseries ............................
398
A-1
399
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CHAPTER 1
OUTLINE
1.1 Features
*
Internal memory
Type Part Number Program Memory (ROM/Flash Memory) 48 KB 60 KB 60 KBNote Data Memory High-Speed RAM 1,024 bytes Expansion RAM 1,536 bytes 40 x 8 bits LCD Display RAM
PD780316, 780326, 780336 PD780318, 780328, 780338 PD78F0338
Note The capacity of internal flash memory can be changed by means of the memory size switching register (IMS).
* *
Minimum instruction execution time changeable from high speed (0.2 s: @10 MHz operation with main system clock) to ultra-low speed (122 s: @32.768 kHz operation with subsystem clock) Instruction set suited to system control * Bit manipulation possible in all address spaces * Multiply and divide instructions
*
I/O port * PD780316, 780318, 78F0338: 70 (Medium voltage N-ch open-drain: 4) * PD780326, 780328: * PD780336, 780338: 62 (Medium voltage N-ch open-drain: 4) 54 (Medium voltage N-ch open-drain: 4) 10 channels 1 channel
* * *
10-bit resolution A/D converter: 8-bit resolution D/A converter: LCD controller/driver * Segment signal output * PD780316, 780318: * PD780326, 780328: * Common signal output * Dynamic display: 4 max. * Static display: 1
24 max. 32 max.
* PD780336, 780338, 78F0338: 40 max.
* LCD reference voltage generator: booster type (x3 only) * Fine tuning of LCD reference voltage possible with external resistor * Blinking display possible (blinking interval can be selected: 0.5 s or 1 s) * Static display and dynamic display (1/3 bias only) can be used simultaneously (Static display up to 12)
*
Serial interface * UART/3-wire serial I/O mode: 1 channelNote * 3-wire serial I/O mode: 1 channel
*
Timer * 16-bit timer/event counter: 2 channels * 8-bit timer/event counter: * Watch timer: * Watchdog timer: 3 channels 1 channel 1 channel
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CHAPTER 1
OUTLINE
* * * *
ROM correction Vectored interrupt sources: 25 Two types of on-chip clock oscillators (main system clock and subsystem clock) Power supply voltage: VDD = 1.8 to 5.5 V Note Select either of the functions of these alternate-function pins.
1.2 Applications
Cordless telephones (handset), compact cameras, etc.
1.3 Ordering Information
Part Number Package 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Flash memory Flash memory
PD780316GC-xxx-9EB PD780316GC-xxx-9EV PD780318GC-xxx-9EB PD780318GC-xxx-9EV PD780326GC-xxx-9EB PD780326GC-xxx-9EV PD780328GC-xxx-9EB PD780328GC-xxx-9EV PD780336GC-xxx-9EB PD780336GC-xxx-9EV PD780338GC-xxx-9EB PD780338GC-xxx-9EV PD78F0338GC-9EB PD78F0338GC-9EV
Remark xxx indicates ROM code suffix.
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CHAPTER 1
OUTLINE
1.4 Pin Configuration (Top View)
1.4.1 PD780316, 780318 * 120-pin plastic TQFP (fine pitch) (14 x 14)
PD780316GC-xxx-9EB, 780316GC-xxx-9EV, 780318GC-xxx-9EB, 780318GC-xxx-9EV
120 119 118 117116 115 114 113 112111 110 109 108 107 106 105 104103 102 101100 99 98 97 96 95 94 93 92 91 P30/TO0 P31/TI00 P32/TI01 P33/TO50/TI50 P34/TO51/TI51 P20/RXD0/SI3 P21/TXD0/SO3 P22/SCK3 P23/SI1 P24/SO1 P25/SCK1 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3/ADTRG P04/INTP4 P05/INTP5/BUZ/PCL IC XT2 XT1 VSS1 VDD1 X2 X1 RESET AVREF0 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P87 P86 P85 P84 P83 P82 P81 P80 P97 P96 P95 P94 P93 P92 P91 P90 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1. 2. Connect the AVSS0 pin to VSS0. Remark When these devices are used in applications that require the reduction of noise generated from an onchip microcontroller, the implementation of noise measures is recommended, such as supplying VDD0 and VDD1 independently, connecting VSS0 and VSS1 independently to ground lines, and so on.
P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 ANI8 ANI9 AVSS0 P120/AO0 AVREF1 CAPH CAPL VLCDC VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 SCOM0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
P73/TI52 P72/TO52 P71/TI4 P70/TO4 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P67 P66 P65 P64 P63 P62 P61 P60 VDD0 VSS0
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ADTRG: ANI0 to ANI9: AO0: AVREF0, AVREF1: AVSS0: BUZ: CAPH, CAPL: IC: INTP0 to INTP5: P00 to P05: P10 to P17: P20 to P25: P30 to P34: P40 to P47: P50 to P57: P60 to P67: P70 to P73: P80 to P87: P90 to P97: P120:
AD trigger input Analog input Analog output Analog reference voltage Analog ground Buzzer output Capacitor for LCD Internally connected External interrupt input Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 12
PCL: RESET: RXD0: S0 to S23: SCK1, SCK3: SCOM0: SI1, SI3: SO1, SO3: TI00, TI01, TI04,
Programmable clock Reset Receive data Segment output Serial clock Common output for static display Serial input Serial output
COM0 to COM3: Common output for dynamic display
TI50, TI51, TI52: Timer input TO0, TO4, TO50, TO51, TO52: TXD0: VDD0, VDD1: VLC0 to VLC2: VLCDC: VSS0, VSS1: X1, X2: XT1, XT2: Timer output Transmit data Power supply LCD power supply Reference voltage control for LCD driver Ground Crystal (main system clock) Crystal (subsystem clock)
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1.4.2 PD780326, 780328 * 120-pin plastic TQFP (fine pitch) (14 x 14)
PD780326GC-xxx-9EB, 780326GC-xxx-9EV, 780328GC-xxx-9EB, 780328GC-xxx-9EV
120 119 118 117116 115 114 113 112111 110 109 108 107 106 105 104103 102 101100 99 98 97 96 95 94 93 92 91 P30/TO0 P31/TI00 P32/TI01 P33/TO50/TI50 P34/TO51/TI51 P20/RXD0/SI3 P21/TXD0/SO3 P22/SCK3 P23/SI1 P24/SO1 P25/SCK1 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3/ADTRG P04/INTP4 P05/INTP5/BUZ/PCL IC XT2 XT1 VSS1 VDD1 X2 X1 RESET AVREF0 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P87 P86 P85 P84 P83 P82 P81 P80 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1. 2. Connect the AVSS0 pin to VSS0. Remark When these devices are used in applications that require the reduction of noise generated from an onchip microcontroller, the implementation of noise measures is recommended, such as supplying VDD0 and VDD1 independently, connecting VSS0 and VSS1 independently to ground lines, and so on.
P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 ANI8 ANI9 AVSS0 P120/AO0 AVREF1 CAPH CAPL VLCDC VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 SCOM0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
P73/TI52 P72/TO52 P71/TI4 P70/TO4 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P67 P66 P65 P64 P63 P62 P61 P60 VDD0 VSS0
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ADTRG: ANI0 to ANI9: AO0: AVREF0, AVREF1: AVSS0: BUZ: CAPH, CAPL: IC: INTP0 to INTP5: P00 to P05: P10 to P17: P20 to P25: P30 to P34: P40 to P47: P50 to P57: P60 to P67: P70 to P73: P80 to P87: P120:
AD trigger input Analog input Analog output Analog reference voltage Analog ground Buzzer output Capacitor for LCD Internally connected External interrupt input Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 12
PCL: RESET: RXD0: S0 to S31: SCK1, SCK3: SCOM0: SI1, SI3: SO1, SO3: TI00, TI01, TI04,
Programmable clock Reset Receive data Segment output Serial clock Common output for static display Serial input Serial output
COM0 to COM3: Common output for dynamic display
TI50, TI51, TI52: Timer input TO0, TO4, TO50, TO51, TO52: TXD0: VDD0, VDD1: VLC0 to VLC2: VLCDC: VSS0, VSS1: X1, X2: XT1, XT2: Timer output Transmit data Power supply LCD power supply Reference voltage control for LCD driver Ground Crystal (main system clock) Crystal (subsystem clock)
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1.4.3 PD780336, 780338 * 120-pin plastic TQFP (fine pitch) (14 x 14)
PD780336GC-xxx-9EB, 780336GC-xxx-9EV, 780338GC-xxx-9EB, 780338GC-xxx-9EV
120 119 118 117116 115 114 113 112111 110 109 108 107 106 105 104103 102 101100 99 98 97 96 95 94 93 92 91 P30/TO0 P31/TI00 P32/TI01 P33/TO50/TI50 P34/TO51/TI51 P20/RXD0/SI3 P21/TXD0/SO3 P22/SCK3 P23/SI1 P24/SO1 P25/SCK1 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3/ADTRG P04/INTP4 P05/INTP5/BUZ/PCL IC XT2 XT1 VSS1 VDD1 X2 X1 RESET AVREF0 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1. 2. Connect the AVSS0 pin to VSS0. Remark When these devices are used in applications that require the reduction of noise generated from an onchip microcontroller, the implementation of noise measures is recommended, such as supplying VDD0 and VDD1 independently, connecting VSS0 and VSS1 independently to ground lines, and so on.
P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 ANI8 ANI9 AVSS0 P120/AO0 AVREF1 CAPH CAPL VLCDC VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 SCOM0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
P73/TI52 P72/TO52 P71/TI4 P70/TO4 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P67 P66 P65 P64 P63 P62 P61 P60 VDD0 VSS0
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ADTRG: ANI0 to ANI9: AO0: AVREF0, AVREF1: AVSS0: BUZ: CAPH, CAPL: IC: INTP0 to INTP5: P00 to P05: P10 to P17: P20 to P25: P30 to P34: P40 to P47: P50 to P57: P60 to P67: P70 to P73: P120: PCL:
AD trigger input Analog input Analog output Analog reference voltage Analog ground Buzzer output Capacitor for LCD Internally connected External interrupt input Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Programmable clock
RESET: RXD0: S0 to S39: SCK1, SCK3: SCOM0: SI1, SI3: SO1, SO3: TI00, TI01, TI04,
Reset Receive data Segment output Serial clock Common output for static display Serial input Serial output
COM0 to COM3: Common output for dynamic display
TI50, TI51, TI52: Timer input TO0, TO4, TO50, TO51, TO52: TXD0: VDD0, VDD1: VLC0 to VLC2: VLCDC: VSS0, VSS1: X1, X2: XT1, XT2: Timer output Transmit data Power supply LCD power supply Reference voltage control for LCD driver Ground Crystal (main system clock) Crystal (subsystem clock)
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1.4.4 PD78F0338 * 120-pin plastic TQFP (fine pitch) (14 x 14)
PD78F0338GC-9EB, 78F0338GC-9EV
120 119 118 117116 115 114 113 112111 110 109 108 107 106 105 104103 102 101100 99 98 97 96 95 94 93 92 91 P30/TO0 P31/TI00 P32/TI01 P33/TO50/TI50 P34/TO51/TI51 P20/RXD0/SI3 P21/TXD0/SO3 P22/SCK3 P23/SI1 P24/SO1 P25/SCK1 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3/ADTRG P04/INTP4 P05/INTP5/BUZ/PCL VPP XT2 XT1 VSS1 VDD1 X2 X1 RESET AVREF0 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P87/S39 P86/S38 P85/S37 P84/S36 P83/S35 P82/S34 P81/S33 P80/S32 P97/S31 P96/S30 P95/S29 P94/S28 P93/S27 P92/S26 P91/S25 P90/S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1. 2. Connect the AVSS0 pin to VSS0. Remark When these devices are used in applications that require the reduction of noise generated from an onchip microcontroller, the implementation of noise measures is recommended, such as supplying VDD0 and VDD1 independently, connecting VSS0 and VSS1 independently to ground lines, and so on.
P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 ANI8 ANI9 AVSS0 P120/AO0 AVREF1 CAPH CAPL VLCDC VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 SCOM0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
P73/TI52 P72/TO52 P71/TI4 P70/TO4 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P67 P66 P65 P64 P63 P62 P61 P60 VDD0 VSS0
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ADTRG: ANI0 to ANI9: AO0: AVREF0, AVREF1: AVSS0: BUZ: CAPH, CAPL: INTP0 to INTP5: P00 to P05: P10 to P17: P20 to P25: P30 to P34: P40 to P47: P50 to P57: P60 to P67: P70 to P73: P80 to P87: P90 to P97: P120: PCL:
AD trigger input Analog input Analog output Analog reference voltage Analog ground Buzzer output Capacitor for LCD External interrupt input Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 12 Programmable clock
RESET: RXD0: S0 to S39: SCK1, SCK3: SCOM0: SI1, SI3: SO1, SO3: TI00, TI01, TI04,
Reset Receive data Segment output Serial clock Common output for static display Serial input Serial output
COM0 to COM3: Common output for dynamic display
TI50, TI51, TI52: Timer input TO0, TO4, TO50, TO51, TO52: TXD0: VDD0, VDD1: VLC0 to VLC2: VLCDC: VPP: VSS0, VSS1: X1, X2: XT1, XT2: Timer output Transmit data Power supply LCD power supply Reference voltage control for LCD driver Programming power supply Ground Crystal (main system clock) Crystal (subsystem clock)
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1.5 78K/0 Series Lineup
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name.
Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD78014H PD78018F PD78083
Inverter control
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
PD78054 with timer and enhanced external interface
ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited function
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O EMI-noise reduced version of the PD78018F PD78018FY
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
VFD drive
On-chip inverter control circuit and UART. EMI-noise reduced.
100-pin 78K/0 Series 80-pin 80-pin 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. PD780308Y PD78064Y PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin
PD780948 PD78098B PD780702Y PD780703Y PD780833Y
PD780816
Meter control
On-chip CAN controller
PD78054 with IEBusTM controller
On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function
100-pin 80-pin 80-pin
PD780958 PD780852 PD780828B
For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same.
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The major functional differences between the subseries are shown below.
Function Subseries Name Control ROM Timer 8-Bit 10-Bit 8-Bit Capacity A/D A/D D/A (Bytes) 8-Bit 16-Bit Watch WDT 1 ch 1 ch 1 ch 8 ch - Serial Interface I/O VDD External MIN. Expansion Value 1.8 V
PD78075B 32 K to 40 K 4 ch PD78078 PD78070A
48 K to 60 K -
2 ch 3 ch (UART: 1 ch)
88
61 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68 69
2.7 V 1.8 V 2.7 V 2.0 V
PD780058 24 K to 60 K 2 ch PD78058F 48 K to 60 K PD78054
16 K to 60 K - 2 ch 1 ch 8 ch - - 8 ch
PD780065 40 K to 48 K PD780078 48 K to 60 K
PD780034A 8 K to 32 K PD780024A
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
PD78014H PD78018F 8 K to 60 K PD78083
Inverter control VFD drive 8 K to 16 K - - - 1 ch - 8 ch -
2 ch
53
1 ch (UART: 1 ch) 3 ch (UART: 2 ch)
33 47 4.0 V
- -
PD780988 16 K to 60 K 3 ch Note PD780208 32 K to 60 K 2 ch PD780232 16 K to 24 K 3 ch PD78044H 32 K to 48 K 2 ch PD78044F 16 K to 40 K
1 ch - 1 ch
1 ch - 1 ch
1 ch
8 ch 4 ch 8 ch
-
-
2 ch
74 40
2.7 V 4.5 V 2.7 V
1 ch 2 ch
68
LCD drive
PD780338 48 K to 60 K 3 ch PD780328 PD780318 PD780308 48 K to 60 K 2 ch PD78064B 32 K PD78064
16 K to 32 K 2 ch
2 ch
1 ch
1 ch
-
10 ch 1 ch 2 ch (UART: 1 ch)
54 62 70
1.8 V
-
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch)
57
2.0 V
Bus interface
PD780948 60 K PD78098B 40 K to 60 K
2 ch 1 ch 2 ch 2 ch
1 ch
1 ch
8 ch
-
- 2 ch
3 ch (UART: 1 ch)
79 69
4.0 V 2.7 V 4.0 V 2.2 V
-
supported PD780816 32 K to 60 K Meter control Dashboard control
12 ch - 1 ch - -
- -
2 ch (UART: 1 ch) 2 ch (UART: 1 ch)
46 69
PD780958 48 K to 60 K 4 ch PD780852 32 K to 40 K 3 ch
PD780828B 32 K to 60 K
-
1 ch
1 ch
1 ch
5 ch
-
-
3 ch (UART: 1 ch)
56 59
4.0 V
-
Note 16-bit timer: 2 channels 10-bit timer: 1 channel
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1.6 Block Diagram
1.6.1 PD780316, 780318
TO0/P30 TI00/P31 TI01/P32 TO4/P70 TI4/P71 TI50/TO50/P33
16-bit timer/ event counter 0 16-bit timer/ event counter 4 8-bit timer/ event counter 50 8-bit timer/ event counter 51 8-bit timer/ event counter 52 Watch timer Watchdog timer
Port 0 Port 1 Port 2 Port 3 Port 4 78K/0 CPU core ROM Port 5 Port 6 Port 7 Internal high-speed RAM 1,024 bytes Internal expansion RAM 1,536 bytes Port 8 Port 9 Port 12
6 8 6 5 8 8 8 4 8 8 1 4
P00 to P05 P10 to P17 P20 to P25 P30 to P34 P40 to P47 P50 to P57 P60 to P67 P70 to P73 P80 to P87 P90 to P97 P120 COM0 to COM3
TI51/TO51/P34 TO52/P72 TI52/P73
SI1/P23 SO1/P24 SCK1/P25 SI3/RXD0/P20 SO3/TXD0/P21 SCK3/P22 RXD0/P20 TXD0/P21 INTP0/P00 to INTP2/P02, INTP3/ADTRG/P03, INTP4/P04, INTP5/BUZ/PCL/P05 PCL/BUZ/INTP5/P05 ANI0/P10 to ANI7/P17, ANI8, ANI9 AVSS0 AVREF0 ADTRG/INTP3/P03 AO0/P120 AVSS0 AVREF1 10 6
Serial interface CSI1 Serial interface SIO3 UART0
LCD controller/ converter
Interrupt control Clock/buzzer output control System control
SCOM0 24 S0 to S23 VLC0 to VLC2 VLCDC CAPH, CAPL RESET X1 X2 XT1 XT2
A/D converter 0
VDD0, VDD1 VSS0, VSS1 D/A converter 0
IC
Remark The internal ROM capacity varies depending on the product.
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1.6.2 PD780326, 780328
TO0/P30 TI00/P31 TI01/P32 TO4/P70 TI4/P71 TI50/TO50/P33
16-bit timer/ event counter 0 16-bit timer/ event counter 4 8-bit timer/ event counter 50 8-bit timer/ event counter 51 8-bit timer/ event counter 52 Watch timer Watchdog timer
Port 0 Port 1 Port 2 Port 3 Port 4 78K/0 CPU core ROM Port 5 Port 6 Port 7 Internal high-speed RAM 1,024 bytes Internal expansion RAM 1,536 bytes Port 8 Port 12
6 8 6 5 8 8 8 4 8 1 4
P00 to P05 P10 to P17 P20 to P25 P30 to P34 P40 to P47 P50 to P57 P60 to P67 P70 to P73 P80 to P87 P120 COM0 to COM3
TI51/TO51/P34 TO52/P72 TI52/P73
SI1/P23 SO1/P24 SCK1/P25 SI3/RXD0/P20 SO3/TXD0/P21 SCK3/P22 RXD0/P20 TXD0/P21 INTP0/P00 to INTP2/P02, INTP3/ADTRG/P03, INTP4/P04, INTP5/BUZ/PCL/P05 PCL/BUZ/INTP5/P05 ANI0/P10 to ANI7/P17, ANI8, ANI9 AVSS0 AVREF0 ADTRG/INTP3/P03 AO0/P120 AVSS0 AVREF1 10 6
Serial interface CSI1 Serial interface SIO3 UART0
LCD controller/ converter
SCOM0 32 S0 to S31 VLC0 to VLC2 VLCDC CAPH, CAPL RESET X1 X2 XT1 XT2
Interrupt control Clock/buzzer output control
System control
A/D converter 0
VDD0, VDD1 VSS0, VSS1 D/A converter 0
IC
Remark The internal ROM capacity varies depending on the product.
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1.6.3 PD780336, 780338
TO0/P30 TI00/P31 TI01/P32 TO4/P70 TI4/P71 TI50/TO50/P33
16-bit timer/ event counter 0 16-bit timer/ event counter 4 8-bit timer/ event counter 50 8-bit timer/ event counter 51 8-bit timer/ event counter 52 Watch timer Watchdog timer
Port 0 Port 1 Port 2 Port 3 Port 4 78K/0 CPU core ROM Port 5 Port 6 Port 7 Internal high-speed RAM 1,024 bytes Internal expansion RAM 1,536 bytes Port 12
6 8 6 5 8 8 8 4 1 4
P00 to P05 P10 to P17 P20 to P25 P30 to P34 P40 to P47 P50 to P57 P60 to P67 P70 to P73 P120 COM0 to COM3
TI51/TO51/P34 TO52/P72 TI52/P73
SI1/P23 SO1/P24 SCK1/P25 SI3/RXD0/P20 SO3/TXD0/P21 SCK3/P22 RXD0/P20 TXD0/P21 INTP0/P00 to INTP2/P02, INTP3/ADTRG/P03, INTP4/P04, INTP5/BUZ/PCL/P05 PCL/BUZ/INTP5/P05 ANI0/P10 to ANI7/P17, ANI8, ANI9 AVSS0 AVREF0 ADTRG/INTP3/P03 AO0/P120 AVSS0 AVREF1 10 6
Serial interface CSI1 Serial interface SIO3 UART0
LCD controller/ converter
SCOM0 40 S0 to S39 VLC0 to VLC2 VLCDC CAPH, CAPL RESET X1 X2 XT1 XT2
Interrupt control Clock/buzzer output control
System control
A/D converter 0
VDD0, VDD1 VSS0, VSS1 D/A converter 0
IC
Remark The internal ROM capacity varies depending on the product.
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1.6.4 PD78F0338
TO0/P30 TI00/P31 TI01/P32 TO4/P70 TI4/P71 TI50/TO50/P33
16-bit timer/ event counter 0 16-bit timer/ event counter 4 8-bit timer/ event counter 50 8-bit timer/ event counter 51 8-bit timer/ event counter 52 Watch timer Watchdog timer
Port 0 Port 1 Port 2 Port 3 Port 4 78K/0 CPU core Flash memory 60 KB Port 5 Port 6 Port 7 Internal high-speed RAM 1,024 bytes Internal expansion RAM 1,536 bytes Port 8 Port 9 Port 12
6 8 6 5 8 8 8 4 8 8 1 4
P00 to P05 P10 to P17 P20 to P25 P30 to P34 P40 to P47 P50 to P57 P60 to P67 P70 to P73 P80 to P87 P90 to P97 P120 COM0 to COM3 SCOM0
S0 to S23, S24/P90 to S31/P97, S32/P80 to S39/P87
TI51/TO51/P34 TO52/P72 TI52/P73
SI1/P23 SO1/P24 SCK1/P25 SI3/RXD0/P20 SO3/TXD0/P21 SCK3/P22 RXD0/P20 TXD0/P21 INTP0/P00 to INTP2/P02, INTP3/ADTRG/P03, INTP4/P04, INTP5/BUZ/PCL/P05 PCL/BUZ/INTP5/P05 ANI0/P10 to ANI7/P17, ANI8, ANI9 AVSS0 AVREF0 ADTRG/INTP3/P03 AO0/P120 AVSS0 AVREF1 10 6
Serial interface CSI1 Serial interface SIO3 UART0
LCD controller/ converter
40
Interrupt control Clock/buzzer output control
VLC0 to VLC2 VLCDC CAPH, CAPL RESET X1 X2 XT1 XT2
System control
A/D converter 0
VDD0, VDD1 VSS0, VSS1 D/A converter 0
VPP
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1.7 Outline of Functions
(1/2)
Part Number Item Internal memory ROM 48 KB (mask ROM) 60 KB (mask ROM) 48 KB (mask ROM) 60 KB (mask ROM) 48 KB (mask ROM) 60 KB (mask ROM) 60 KBNote (flash memory)
PD780316 PD780318 PD780326 PD780328 PD780336 PD780338 PD78F0338
High-speed RAM Expansion RAM LCD display RAM Memory space General-purpose registers Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction set
1,024 bytes 1,536 bytes 40 x 8 bits 64 KB 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Function to change minimum instruction execution time provided 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (@VDD = 5 V, fX = 10 MHz) 122 s (@fXT = 32.768 kHz) * * * * 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulate (set, reset, test, and Boolean operation) BCD adjust, etc. 62 54 70
I/O ports CMOS input CMOS output
70 8 16
8
None
16 (alternate with segment pin)
CMOS I/O N-ch open-drain I/O (15 V) A/D converter
42 4 * 10-bit resolution x 10 channels * Low-voltage operation: AVREF0 = 1.8 to 5.5 V 8-bit resolution x 1 channel * * * * LCD reference voltage generator: booster type (x3 only) Fine tuning of LCD reference voltage possible with external resistor Blinking display possible (blinking interval can be selected: 0.5 s or 1 s) Static display and dynamic display (1/3 bias only) can be used simultaneously (Static display up to 12 segments) 32 max. 40 max. 40 max. (when alternate with port pins: 16)
D/A converter LCD controller/driver
Segment signal output
24 max.
Common signal output
4 max. (dynamic display), 1 (static display)
Note The capacity of the internal flash memory can be changed by means of the memory size switching register (IMS).
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(2/2)
Part Number Item Serial interface * 3-wire serial I/O mode/UART mode selectableNote: 1 channel * 3-wire serial I/O mode: 1 channel * * * * 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: 2 3 1 1 channels channels channel channel
PD780316 PD780318 PD780326 PD780328 PD780336 PD780338 PD78F0338
Timer
Timer outputs Clock output
5 (8-bit PWM output possible: 3) * 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (@10 MHz operation with main system clock) * 32.768 kHz (@32.768 kHz operation with subsystem clock) * 1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (@10 MHz operation with main system clock) Maskable Non-maskable Software Internal: 15, external: 7 Internal: 1 1 Provided VDD = 1.8 to 5.5 V TA = -40 to +85C 120-pin plastic TQFP (fine pitch) (14 x 14)
Buzzer output Vectored interrupt sources ROM correction Power supply voltage Operating ambient temperature Package
Note Select either of the functions of these alternate-function pins. The following table outlines the timers/event counters (for details, refer to CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0, CHAPTER 7 16-BIT TIMER/EVENT COUNTER 4, CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51, 52, CHAPTER 9 WATCH TIMER, and CHAPTER 10 WATCHDOG TIMER):
16-Bit Timer/ 16-Bit Timer/ 8-Bit Timer/ Event Counter 0 Event Counter 4 Event Counters 50, 51, 52 Operation mode Function Interval timer External event counter Timer output PPG output PWM output Pulse width measurement Square wave output Interrupt request -- -- -- -- -- -- 1 channel 1 channel 3 channels Watch Timer Watchdog Timer
1 channelNote 1 1 channelNote 2 -- -- -- -- -- -- -- -- -- -- -- --
Notes 1. The watch timer can be used both as a watch timer and an interval timer at the same time. 2. The watchdog timer can be used either as a watchdog timer or interval timer. Select one of the functions.
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1.8 Mask Options
The mask ROM versions (PD780316, 780318, 780326, 780328, 780336, and 780338) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device production. Using the mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. The mask options provided in the PD780318, 780328, and 780338 Subseries are shown in Table 1-1. Table 1-1. Mask Options of Mask ROM Versions
Pin Names P60 to P63 Mask Option Pull-up resistor connection can be specified in 1-bit units.
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2.1 Pin Function List
(1) Port pins (1/2)
Pin Name I/O Function After Reset Alternate Function INTP0 INTP1 INTP2 INTP3/ADTRG INTP4 INTP5/BUZ/PCL Input Port 1 8-bit input only port. Port 2 6-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. Input ANI0 to ANI7
P00 P01 P02 P03 P04 P05 P10 to P17
I/O
Port 0 6-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
P20 P21 P22 P23 P24 P25 P30 P31 P32 P33 P34 P40 to P47
I/O
Input
RXD0/SI3 TXD0/SO3 SCK3 SI1 SO1 SCK1
I/O
Port 3 5-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
TO0 TI00 TI01 TO50/TI50 TO51/TI51
I/O
Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. Interrupt request flag (KRIF) is set to 1 by falling edge detection. Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. Port 6 8-bit I/O port Input/output mode can be specified in 1bit units. LEDs can be driven directly. Medium-voltage N-ch open-drain I/ O port On-chip pull-up resistor can be specified by mask option (mask ROM version only). An on-chip pull-up resistor can be used by setting software.
Input
--
P50 to P57
I/O
Input
--
P60 to P63
I/O
Input
--
P64 to P67
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(1) Port pins (2/2)
Pin Name I/O Function After Reset Alternate Function TO4 TI4 TO52 TI52 Output Port 8 8-bit output only port Port 9 8-bit output only port Port 12 1-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. Output S32 to S39Note S24 to S31Note
P70 P71 P72 P73 P80 to P87Note P90 to P97Note
I/O
Port 7 4-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
Output
Output
P120
I/O
Input
AO0
Note
Ports 8 and 9 vary depending on the product.
Port 8 Port 9 P90 to P97 (without alternate pin) None None P80/S32 to P87/S39 P90/S24 to P97/S31
PD780316, 780318 PD780326, 780328 PD780336, 780338 PD78F0338
P80 to P87 (without alternate pin)
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(2) Non-port pins (1/2)
Pin Name I/O Function After Reset Alternate Function P00 P01 P02 P03/ADTRG P04 P05/BUZ/PCL Input Serial interface serial data input Input P23 P20/RXD0 Output Serial interface serial data output Input P24 P21/TXD0 I/O Serial interface serial clock input/output Input P25 P22 Input Output Input Asynchronous serial interface serial data input Asynchronous serial interface serial data output External count clock input to 16-bit timer/event counter 0 Capture trigger input to capture registers (CR00, CR01) of 16-bit timer/event counter 0 TI01 Capture trigger input to capture register (CR00) of 16-bit timer/event counter 0 External count clock input to 16-bit timer/event counter 4 Output 16-bit timer/event counter 0 output 16-bit timer/event counter 4 output Input External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 External count clock input to 8-bit timer/event counter 52 Output 8-bit timer/event counter 50 output 8-bit timer/event counter 51 output 8-bit timer/event counter 52 output Output Output Input Clock output (for main system clock, subsystem clock trimming) Buzzer output Analog input of A/D converter Input Input Input Input Input Input P32 Input Input Input P20/SI3 P21/SO3 P31
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI1 SI3 SO1 SO3 SCK1 SCK3 RxD0 TxD0 TI00
Input
External interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges)
Input
TI4 TO0 TO4 TI50 TI51 TI52 TO50 TO51 TO52 PCL BUZ ANI0 to ANI7 ANI8, ANI9 ADTRG AVREF0 AO0 AVREF1 AVSS0 Input Input Output Input --
P71 P30 P70 P33/TO50 P34/TO51 P73 P33/TI50 P34/TI51 P72 P05/INTP5/BUZ P05/INTP5/PCL P10 to P17 --
Trigger signal input of A/D converter Reference voltage input of A/D converter Analog output of D/A converter Reference voltage input of D/A converter Ground potential for A/D converter and D/A converter. Supply the same potential as that of VSS0 or VSS1.
Input -- Input -- --
P03/INTP3 -- P120 -- --
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(2) Non-port pins (2/2)
Pin Name S0 to S11Note S12 to S23Note S24 to S31Note S32 to S39Note COM0 to COM3 SCOM0 Output LCD controller/driver common signal output (for dynamic display) LCD controller/driver common signal output (for static display) LCD driving voltage * VLC0: Three times VLC2 output voltage * VLC1: Two times VLC2 output voltage * VLC2: Reference voltage LCD controller/driver reference voltage adjustment Booster capacitor connection for LCD drive voltage System reset input Crystal connection for main system clock oscillation Output I/O Function After Reset Alternate Function --
Output
LCD controller/driver segment signal output (Static and dynamic display can be selected) LCD controller/driver segment signal output (for dynamic display)
Output
-- P90 to P97Note P80 to P87Note --
Output
Output
--
VLC0 to VLC2
--
--
--
VLCDC CAPH, CAPL RESET X1 X2 XT1 XT2 VDD0 VDD1 VSS0 VSS1 IC VPP
-- -- Input Input -- Input -- -- -- -- -- -- --
-- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
Crystal connection for subsystem clock oscillation
-- --
Positive power supply for ports Positive power supply other than ports Ground potential for ports Ground potential other than ports Internally connected. Connect directly to VSS0 or VSS1. High-voltage application for program write/verify. Connect directly to VSS0 or VSS1 in normal operation mode.
-- -- -- -- -- --
Note
Segment signal output pins vary depending on the product. * PD780316, 780318: S0 to S23 (without alternate pin) * PD780326, 780328: S0 to S31 (without alternate pin) * PD780336, 780338: S0 to S39 (without alternate pin) * PD78F0338: S0 to S39 (S24 to S31 and P90 to P97, and S32 to S39 and P80 to P87 are alternate-function pins. These functions can be switched with port functions in 8-bit units.)
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2.2 Description of Pin Functions
2.2.1 P00 to P05 (Port 0) These are 6-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt request input, A/ D converter external trigger input, clock output, and buzzer output function. The following operation modes can be specified in 1-bit units. (1) Port mode These ports function as 6-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 0 (PM0). On-chip pull-up resistors can be used by setting pull-up resistor option register 0 (PU0). (2) Control mode In this mode, these ports function as an external interrupt request input, A/D converter external trigger input, clock output, and buzzer output. (a) INTP0 to INTP5 INTP0 to INTP5 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). (b) ADTRG A/D converter external trigger input pin. Caution When P03 is used as an A/D converter external trigger input, specify the valid edge by bits 1, 2 (EGA00, EGA01) of A/D converter mode register (ADM0) and set interrupt request mask flag (PMK3) to 1. (c) PCL Clock output pin. (d) BUZ Buzzer output pin. 2.2.2 P10 to P17 (Port 1) These are 8-bit input only ports. Besides serving as input ports, they function as an A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input only ports. (2) Control mode These ports function as A/D converter analog input pins (ANI0 to ANI7).
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2.2.3 P20 to P25 (Port 2) These are 6-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O. The following operation modes can be specified in 1-bit units. (1) Port mode These ports function as 6-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 2 (PM2). On-chip pull-up resistors can be used by setting pull-up resistor option register 2 (PU2). (2) Control mode These ports function as serial interface data I/O and clock I/O functions. (a) SI1, SI3, SO1, and SO3 Serial interface serial data I/O pins. (b) SCK1 and SCK3 Serial interface serial clock I/O pins. (c) RXD0 and TXD0 Asynchronous serial interface serial data I/O pins. 2.2.4 P30 to P34 (Port 3) These are 5-bit I/O ports. Besides serving as I/O ports, they function as timer I/O. (1) Port mode These ports function as 5-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 3 (PM3). On-chip pull-up resistors can be used by setting pull-up resistor option register 3 (PU3). P31 and P32 are also capture trigger signal input pins to the capture registers (CR00 and CR01) of the 16-bit timer/event counter 0 with a valid edge input. (2) Control mode These ports function as timer I/O. (a) TI00 External count clock input pin to 16-bit timer/event counter 0 and capture trigger signal input pin to capture registers (CR00 and CR01) of the 16-bit timer/event counter 0. (b) TI01 Capture trigger signal input pin to capture register (CR00) of the 16-bit timer/event counter 0. (c) TI50 and TI51 External count clock input pins to 8-bit timer/event counters 50 and 51. (d) TO0, TO50, and TO51 Timer output pins.
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2.2.5 P40 to P47 (Port 4) These are 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 4 (PM4). On-chip pull-up resistors can be used by setting pull-up resistor option register 4 (PU4). Interrupt request flag (KRIF) can be set to 1 by detecting the falling edge. The number of ports to detect the falling edge can be selected at either four (P40 to P43) or eight (P40 to P47) by setting bit 0 (KRSEL0) of the key return switching register (KRSEL). Cautions 1. Be sure to set memory expansion mode register (MEM) to 01H when using falling edge detection interrupt (INTKR). 2. If the number of key returns is set to four, the key return function cannot be evaluated with in-circuit emulator. 2.2.6 P50 to P57 (Port 5) These are 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 5 (PM5). On-chip pull-up resistors can be used by setting pull-up resistor option register 5 (PU5). 2.2.7 P60 to P67 (Port 6) These are 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 6 (PM6). Port 6 can drive LEDs directly. P60 to P63 are medium-voltage N-ch open-drain. On-chip pull-up resistors can be used by a mask option with the mask ROM versions. P64 to P67 can use on-chip pull-up resistors by setting pull-up resistor option register 6 (PU6). 2.2.8 P70 to P73 (Port 7) These are 4-bit I/O ports. Besides serving as I/O ports, they function as timer I/O. (1) Port mode These ports function as 4-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 7 (PM7). On-chip pull-up resistors can be used by setting pull-up resistor option register 7 (PU7). (2) Control mode These ports function as timer I/O. (a) TI4 External count clock input pin to 16-bit timer/event counter 4. (b) TI52 External count clock input pin to 8-bit timer/event counter 52. (c) TO4 and TO52 Timer output pins.
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2.2.9 P80 to P87 (Port 8)Notes 1, 2 These are 8-bit output-only ports. Besides serving as output ports, they function as segment signal output (for dynamic display) of the LCD controller/driver. Either the output port or segment signal output function can be selected by setting the pin function switching register 8 (PF8)Note 3. (1) Port mode These ports function as 8-bit output-only ports. (2) Control mode These ports function as segment signal output pins (S32 to S39) (for dynamic display) of the LCD controller/driver. Notes 1. These ports are not provided in the PD780336 and 780338. 2. Port 8 and segment signal output pins vary depending on the product.
Pin Function
PD780316, 780318 PD780326, 780328 PD780336, 780338 PD78F0338
P80 to P87
S32 to S39 P80/S32 to P87/S39
3. Pin function switching register 8 (PF8) is provided for the PD78F0338 only. 2.2.10 P90 to P97 (Port 9)Notes 1, 2 These are 8-bit output-only ports. Besides serving as output ports, they function as segment signal output (for dynamic display) of the LCD controller/driver. Either the output port or segment signal output function can be selected by setting the pin function switching register 9 (PF9)Note 3. (1) Port mode These ports function as 8-bit output-only ports. (2) Control mode These ports function as segment signal output pins (S24 to S31) (for dynamic display) of the LCD controller/driver. Notes 1. These ports are not provided in the PD780326, 780328, 780336, and 780338. 2. Port 9 and segment signal output pins vary depending on the product.
Pin Function
PD780316, 780318 PD780326, 780328 PD780336, 780338 PD78F0338
P90 to P97 S24 to S31
P90/S24 to P97/S31
3. Pin function switching register 9 (PF9) is provided for the PD78F0338 only.
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2.2.11 P120 (Port 12) This is a 1-bit I/O port. Besides serving as an I/O port, this port functions as an analog output of the D/A converter. (1) Port mode This is a 1-bit I/O port. It can be specified as an input or output port in 1-bit units with port mode register 12 (PM12). An on-chip pull-up resistor can be used by setting pull-up resistor option register 12 (PU12). (2) Control mode This port functions as an analog output pin of the D/A converter (AO0). Caution Set this port to input mode using the port mode register 12 and disconnect pull-up resistor before using the D/A converter. 2.2.12 ANI0 to ANI9 These are A/D converter analog input pins. ANI0 to ANI7 are also used with P10 to P17. 2.2.13 AVREF0 This is an A/D converter reference voltage input pin. Supply power when using an A/D converter because this pin also functions as an analog power supply. When A/D converter is not used, connect this pin to VSS0 or VSS1 pin. 2.2.14 AVREF1 This is a D/A converter reference voltage input pin. When D/A converter is not used, connect this pin to VDD0 or VDD1 pin. 2.2.15 AVSS0 This is a ground potential pin of A/D converter and D/A converter. Always use the same potential as that of the VSS0 or VSS1 pin even when an A/D converter and D/A converter are not used. 2.2.16 S0 to S39Note These are segment signal output pins of the LCD controller/driver. S0 to S11: Static or dynamic display can be switched
S12 to S39: For dynamic display Note Segment signal output pins vary depending on the product. * PD780316, 780318: S0 to S23 (without alternate pin) * PD780326, 780328: S0 to S31 (without alternate pin) * PD780336, 780338: S0 to S39 (without alternate pin) * PD78F0338: S0 to S39 (S24 to S31 and P90 to P97, and S32 to S39 and P80 to P87 are alternate-function pins. These functions can be switched with port functions in 8-bit units.) 2.2.17 COM0 to COM3 These are common signal output pins (for dynamic display) of the LCD controller/driver. 2.2.18 SCOM0 This is a common signal output pin (for static display) of the LCD controller/driver.
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2.2.19 VLC0 to VLC2 These are LCD driving voltage pins. Individually connect to capacitors (recommended value: 0.47 F) externally between VLC0 and GND, VLC1 and GND, VLC2 and GND to supply LCD driving voltage corresponding to each bias to the inside of VLC0 to VLC2 pins. * VLC0: Three times of VLC2 output voltage * VLC1: Two times of VLC2 output voltage * VLC2: Reference voltage 2.2.20 VLCDC This is an LCD controller/driver reference voltage adjustment pin. This pin is used for fine-tuning the LCD driving voltage by connecting resistors between VLC2 and VLCDC externally. 2.2.21 CAPH and CAPL These are booster capacitor connection pins for LCD drive voltage. Connect capacitors (recommended value: 0.47 F) between CAPH and CAPL. 2.2.22 RESET This is a low-level active system reset input pin. 2.2.23 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input the clock signal to X1 and its inverted signal to X2. 2.2.24 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation. For external clock supply, input the clock signal to XT1 and its inverted signal to XT2. 2.2.25 VDD0 and VDD1 VDD0 is a positive power supply port pin. VDD1 is a positive power supply pin other than port pin. 2.2.26 VSS0 and VSS1 VSS0 is a ground potential port pin. VSS1 is a ground potential pin other than port pin. 2.2.27 VPP (flash memory versions only) High-voltage apply pin for flash memory programming mode setting and program write/verify. Connect directly to VSS0 or VSS1 in the normal operating mode.
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2.2.28 IC (mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD780318, 780328, 780338 Subseries at delivery. Connect it directly to the VSS0 or VSS1 pin with the shortest possible wire in the normal operation mode. When a potential difference is produced between the IC pin and VSS0 pin or VSS1 pin, because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not operate normally. * Connect IC pins to VSS0 pins or VSS1 pins directly.
VSS0 or VSS1 IC
As short as possible
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the types of pin I/O circuit and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-1. Pin I/O Circuit Types (1/2)
Pin Name I/O Circuit Type 8-C I/O I/O Recommended Connection of Unused Pins
P00/INTP0 to P02/INTP2 P03/INTP3/ADTRG P04/INTP4 P05/INTP5/BUZ/PCL P10/ANI0 to P17/ANI7 P20/RXD0/SI3 P21/TXD0/SO3 P22/SCK3 P23/SI1 P24/SO1 P25/SCK1 P30/TO0 P31/TI00 P32/TI01 P33/TO50/TI50 P34/TO51/TI51 P40 to P47 P50 to P57 P60 to P63 (for mask ROM version) P60 to P63 (for flash memory version) P64 to P67 P70/TO4 P71/TI4 P72/TO52 P73/TI52
Input:
Independently connect to VSS0 via a resistor.
Output: Leave open.
25 8-C 5-H 8-C
Input I/O
Connect to VDD0 or VSS0. Input: Independently connect to VDD0 or VSS0 via a resistor.
Output: Leave open.
5-H 8-C 5-H 8-C
5-H
13-J
Input: Connect to VSS0. Output: Set to low-level output and leave open.
13-K
5-H
Input:
Independently connect to VDD0 or VSS0 via a resistor.
Output: Leave open. 8-C 5-H 8-C
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Table 2-1. Pin I/O Circuit Types (2/2)
Pin Name P80 to P87Note (for mask ROM version) P80/S32 to P87/S39 (for flash memory version) P90 to P97Note (for mask ROM version) P90/S24 to P97/S31 (for flash memory version) P120/AO0 31 Set to output and leave open. I/O Circuit Type 4-B I/O Recommended Connection of Unused Pins
Output
Leave open.
31
Set to output and leave open.
4-B
Leave open.
12-C
I/O
Input: Independently connect to VSS0 via a resistor. Output: Leave open. Connect to VDD0 or VSS0. Leave open.
ANI8, ANI9 S0 to S23Note S39Note
25 17-D
Input Output
S24 to (for mask ROM version) COM0 to COM3 SCOM0 VLC0 to VLC2 VLCDC CAPH, CAPL RESET XT1 XT2 AVREF0 AVREF1 AVSS0 IC VPP -- -- Input 2 16 Input Input -- Connect to VDD0 or VDD1. Leave open. Connect to VSS0 or VSS1. Connect to VDD0 or VDD1. Connect to VSS0 or VSS1. Connect to VSS0 or VSS1 directly. -- -- -- 18-B
Note
Ports 8 and 9 and segment signal output pins vary depending on the mask ROM version.
Port 8 Port 9 P90 to P97 None None Segment Signal Output S0 to S23 S0 to S31 S0 to S39
PD780316, 780318 PD780326, 780328 PD780336, 780338
P80 to P87
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Figure 2-1. Pin I/O Circuit List (1/2)
Type 2 Type 8-C
VDD0
Pull-up enable IN Data
P-ch VDD0 P-ch IN/OUT
Schmitt-triggered input with hysteresis characteristics
Output disable
N-ch VSS0
Type 4-B
Type 12-C VDD0 Pull-up enable VDD0 VDD0 Data P-ch OUT Output disable Input enable Analog output voltage P-ch IN/OUT N-ch VSS0 P-ch N-ch
P-ch
Data
Output disable
N-ch VSS0
Type 5-H
Type 13-K
VDD0 IN/OUT Pull-up enable Data P-ch VDD0 P-ch IN/OUT Output disable Input enable N-ch VSS0 Medium voltage input buffer RD P-ch Data Output disable VSS0 VDD0 N-ch
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Figure 2-1. Pin I/O Circuit List (2/2)
Type 13-J
Type 18-B
VDD0
Mask Option
VLC0 VLC1 IN/OUT
P-ch
N-ch P-ch N-ch OUT COM data VLC2 N-ch N-ch P-ch P-ch
Data Output disable VSS0 VDD0
N-ch
RD
P-ch
Medium voltage input buffer VSS1 Type 16 Type 25
Feedback cut-off P-ch
P-ch Comparator
+
N-ch VSS0 VREF (threshold voltage)
-
IN
XT1
XT2
Input enable
Type 17-D
Type 31 Data
VDD0 P-ch IN/OUT
VLC0 VLC1
P-ch Output disable N-ch P-ch VLC0 OUT VLC1 P-ch N-ch SEG data P-ch VLC2 N-ch N-ch VSS1 N-ch P-ch N-ch P-ch P-ch N-ch VSS0
SEG data
VLC2 N-ch
VSS1
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3.1 Memory Spaces
The PD780318, 780328, 780338 Subseries can each access a 64 KB memory space. Figures 3-1 to 3-3 show the memory maps. Caution In the case of the internal memory capacity, the initial values of the memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products (PD780318, 780328, and 780338 Subseries) are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below.
Set Value of IMS Set Value of IXS 09H
PD780316, 780326, 780336 PD780318, 780328, 780338 PD78F0338
CCH CFH Value corresponding to mask ROM version
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(1) PD780316, 780326, 780336 Set the value of the memory size switching register (IMS) to CCH, and the value of the internal expansion RAM size switching register (IXS) to 09H (default setting: IMS = CFH, IXS = 0CH). Figure 3-1. Memory Map (PD780316, 780326, 780336)
F F F FH Special function registers (SFRs) 256 x 8 bits General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits FB0 0H F A F FH Reserved FA2 8H FA2 7H Data memory space FA0 0H F 9 F FH F 8 0 0H F 7 F FH B F F FH LCD display RAM 40 x 8 bitsNote Reserved Internal expansion RAM 1,536 x 8 bits F 2 0 0H F 1 F FH C0 0 0H B F F FH Reserved 0 0 8 0H 0 0 7 FH Internal ROM 49,152 x 8 bits CALLT table area 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H 0 0 0 0H 1 0 0 0H 0 F F FH CALLF entry area 0 8 0 0H 0 7 F FH Program area Program area
FF 0 0H F E F FH F EE 0 H F ED F H
Program memory space
Note
The area that can be used as LCD display data varies depending on the product. The area not used as LCD display data can be used as normal RAM. * PD780316: FA00H to FA17H (24 bytes) * PD780326: FA00H to FA1FH (32 bytes) * PD780336: FA00H to FA27H (40 bytes)
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(2) PD780318, 780328, 780338 Set the value of the memory size switching register (IMS) to CFH, and the value of the internal expansion RAM size switching register (IXS) to 09H (default setting: IMS = CFH, IXS = 0CH). Figure 3-2. Memory Map (PD780318, 780328, 780338)
F F F FH Special function registers (SFRs) 256 x 8 bits General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits FB0 0H F A F FH Reserved FA2 8H FA2 7H Data memory space FA0 0H F 9 F FH F 8 0 0H F 7 F FH E F F FH LCD display RAM 40 x 8 bitsNote Reserved Internal expansion RAM 1,536 x 8 bits F 2 0 0H F 1 F FH F 0 0 0H E F F FH Reserved 0 0 8 0H 0 0 7 FH Internal ROM 61,440 x 8 bits CALLT table area 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H 0 0 0 0H 1 0 0 0H 0 F F FH CALLF entry area 0 8 0 0H 0 7 F FH Program area Program area
FF 0 0H F E F FH F EE 0 H F ED F H
Program memory space
Note
The area that can be used as LCD display data varies depending on the product. The area not used as LCD display data can be used as normal RAM. * PD780318: FA00H to FA17H (24 bytes) * PD780328: FA00H to FA1FH (32 bytes) * PD780338: FA00H to FA27H (40 bytes)
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(3) PD78F0338 Set the value of the memory size switching register (IMS) to value corresponding to mask ROM version, and the value of the internal expansion RAM size switching register (IXS) to 09H (default setting: IMS = CFH, IXS = 0CH). Figure 3-3. Memory Map (PD78F0338)
F F F FH Special function registers (SFRs) 256 x 8 bits General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits FB0 0H F A F FH Reserved FA2 8H FA2 7H Data memory space FA0 0H F 9 F FH F 8 0 0H F 7 F FH E F F FH LCD display RAM 40 x 8 bitsNote Reserved Internal expansion RAM 1,536 x 8 bits F 2 0 0H F 1 F FH F 0 0 0H E F F FH Reserved 0 0 8 0H 0 0 7 FH Flash memory 61,440 x 8 bits CALLT table area 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H 0 0 0 0H 1 0 0 0H 0 F F FH CALLF entry area 0 8 0 0H 0 7 F FH Program area Program area
FF 0 0H F E F FH F EE 0 H F ED F H
Program memory space
Note
The area that can be used as LCD display data varies if P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as port output or segment output. The area not used as LCD display data can be used as normal RAM. * P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as port output: * P80/S32 to P87/S39 or P90/S24 to P97/S31 is used as port output: FA00H to FA17H (24 bytes) FA00H to FA1FH (32 bytes)
* P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as segment output: FA00H to FA27H (40 bytes)
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3.1.1 Internal program memory space The internal program memory space contains the program and table data. Normally, it is addressed with the program counter (PC). The PD780318, 780328, and 780338 Subseries products incorporate an internal ROM (or flash memory), as listed below. Table 3-1. Internal Memory Capacity
Part Number Structure Mask ROM Capacity 49,152 x 8 bits (0000H to BFFFH) 61,440 x 8 bits (0000H to EFFFH) Flash memory
PD780316, 780326, 780336 PD780318, 780328, 780338 PD78F0338
The internal program memory space is divided into the following three areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16bit address, lower 8 bits are stored at even addresses and higher 8 bits are stored at odd addresses. Table 3-2. Vector Table
Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H Interrupt Source RESET input INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTKR INTSER0 INTSR0 INTST0 Vector Table Address 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 003EH Interrupt Source INTCSI1 INTCSI3 INTWTNI0 INTTM00 INTTM01 INTTM4 INTTM50 INTTM51 INTTM52 INTAD0 INTWTN0 BRK
(2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
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3.1.2 Internal data memory space The PD780318, 780328, and 780338 Subseries products incorporate the following RAM. (1) Internal high-speed RAM This RAM is assigned to FB00H to FEFFH (1,024 bytes). The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks configured of eight 8bit registers as one bank. Instructions cannot be written and executed using this RAM as a program area. The internal high-speed RAM can also be used as a stack memory. (2) Internal expansion RAM The area F200H to F7FFH (1,536 bytes) is assigned to the internal expansion RAM. The internal expansion RAM can be used as a normal data area in the same way as the internal high-speed RAM. This RAM can also be used for writing and executing instructions as a program area. (3) LCD display RAM The area FA00H to FA27H (40 x 8 bits) is assigned to the LCD display RAM. Among this space, the area that can be used as LCD display data varies depending on the product, as described in Table 3-3. LCD display RAM can also be used as normal RAM. Therefore, the area not used as LCD display data can be used as normal RAM. Table 3-3. Area That Can Be Used as LCD Display Data
Part Number Area That Can Be Used as LCD Display Data FA00H to FA17H (24 bytes) FA00H to FA1FH (32 bytes) FA00H to FA27H (40 bytes) * P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as port output: FA00H to FA17H (24 bytes) * P80/S32 to P87/S39 or P90/S24 to P97/S31 is used as port output: FA00H to FA1FH (32 bytes) * P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as segment output: FA00H to FA27H (40 bytes)
PD780316, 780318 PD780326, 780328 PD780336, 780338 PD78F0338
3.1.3 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to Table 3-4 Special Function Register List in 3.2.3 Special function register (SFR)). Caution Do not access addresses where an SFR is not assigned.
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3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the PD780318, 780328, and 780338 Subseries, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Data memory and its corresponding addressing are illustrated in Figures 3-4 to 3-6. For the details of each addressing mode, see 3.4 Operand Address Addressing. Figure 3-4. Data Memory Addressing (PD780316, 780326, 780336)
F F F FH FF 2 0H F F 1 FH FF 0 0H F E F FH F EE 0 H F ED F H FF 2 0H F E 1 FH FB0 0H F A F FH FA2 8H FA2 7H FA0 0H F 9 F FH F 8 0 0H F 7 F FH
Special function registers (SFRs) 256 x 8 bits SFR addressing
General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits
Register addressing
Short direct addressing
Reserved LCD display RAM 40 x 8 bitsNote Reserved Internal expansion RAM 1,536 x 8 bits F 2 0 0H F 1 F FH C0 0 0H B F F FH Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing
Internal ROM 49,152 x 8 bits
0 0 0 0H
Note
The area that can be used as LCD display data varies depending on the product. The area not used as LCD display data can be used as normal RAM. * PD780316: FA00H to FA17H (24 bytes) * PD780326: FA00H to FA1FH (32 bytes) * PD780336: FA00H to FA27H (40 bytes)
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Figure 3-5. Data Memory Addressing (PD780318, 780328, 780338)
F F F FH
Special function registers (SFRs) 256 x 8 bits SFR addressing FF 2 0H F F 1 FH FF 0 0H F E F F H General-purpose registers Register addressing 32 x 8 bits F EE 0 H F E D F H Internal high-speed RAM FF 2 0H F E 1 FH FB0 0H F A F FH FA2 8H FA2 7H FA0 0H F 9 F FH F 8 0 0H F 7 F FH 1,024 x 8 bits
Short direct addressing
Reserved LCD display RAM 40 x 8 bitsNote Reserved Internal expansion RAM 1,536 x 8 bits F 2 0 0H F 1 F FH F 0 0 0H E F F FH Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing
Internal ROM 61,440 x 8 bits
0 0 0 0H
Note
The area that can be used as LCD display data varies depending on the product. The area not used as LCD display data can be used as normal RAM. * PD780318: FA00H to FA17H (24 bytes) * PD780328: FA00H to FA1FH (32 bytes) * PD780338: FA00H to FA27H (40 bytes)
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Figure 3-6. Data Memory Addressing (PD78F0338)
F F F FH FF 2 0H F F 1 FH FF 0 0H F E F FH F EE 0 H F ED F H FF 2 0H F E 1 FH FB0 0H F A F FH FA2 8H FA2 7H FA0 0H F 9 F FH F 8 0 0H F 7 F FH
Special function registers (SFRs) 256 x 8 bits SFR addressing
General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits
Register addressing
Short direct addressing
Reserved LCD display RAM 40 x 8 bitsNote Reserved Internal expansion RAM 1,536 x 8 bits F 2 0 0H F 1 F FH F 0 0 0H E F F FH Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing
Flash memory 61,440 x 8 bits
0 0 0 0H
Note
The area that can be used as LCD display data varies if P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as port output or segment output. The area not used as LCD display data can be used as normal RAM. * P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as port output: * P80/S32 to P87/S39 or P90/S24 to P97/S31 is used as port output: FA00H to FA17H (24 bytes) FA00H to FA1FH (32 bytes)
* P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as segment output: FA00H to FA27H (40 bytes)
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3.2 Processor Registers
The PD780318, 780328, and 780338 Subseries products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-7. Program Counter Format
15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0
(2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI, and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-8. Program Status Word Format
7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY
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(a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to the disable interrupt (DI) state, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to the enable interrupt (EI) state and interrupt request acknowledge enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag. The IE is reset to (0) upon DI instruction execution or interrupt acknowledgement and is set to (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified with a priority specification flag register (PR0L, PR0H, PR1L) (refer to 18.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) are disabled for acknowledgement. Actual request acknowledgement is controlled with the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FB00H to FEFFH) can be set as the stack area.
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Figure 3-9. Stack Pointer Format
15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 3-10 and 3-11. Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before use. Figure 3-10. Data to Be Saved to Stack Memory
Interrupt and BRK instructions SP SP SP _ 2 SP _ 2 SP _ 1 SP Register pair lower Register pair upper SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP
PUSH rp instruction
CALL, CALLF, and CALLT instructions
PC7 to PC0 PC15 to PC8 PSW
Figure 3-11. Data to Be Restored from Stack Memory
RETI and RETB instructions
POP rp instruction
RET instruction
SP SP + 1 SP SP + 2
Register pair lower Register pair upper SP
SP SP + 1 SP + 2
PC7 to PC0 PC15 to PC8
SP SP + 1 SP + 2 SP SP + 3
PC7 to PC0 PC15 to PC8 PSW
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3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. They consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL). They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-12. General-Purpose Register Configuration (a) Absolute name
16-bit processing FEFFH R7 BANK0 FEF8H RP3 R6 R5 BANK1 FEF0H RP1 R2 R1 BANK3 FEE0H 15 0 7 0 RP0 R0 RP2 R4 R3 BANK2 FEE8H 8-bit processing
(b) Function name
16-bit processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H BC C A BANK3 FEE0H 15 0 7 0 AX X DE E B BANK2 FEE8H 8-bit processing
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3.2.3 Special function register (SFR) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the FF00H to FFFFH area. The special function registers can be manipulated like general-purpose registers, with operation, transfer and bit manipulation instructions. Manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved in the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved in the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved in the assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, describe an even address. Table 3-4 gives a list of special function registers. The meaning of items in the table is as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined via the header file "sfrbit.h" in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: W: Read only Write only
* Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon RESET input.
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Table 3-4. Special Function Register List (1/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset 1 Bit FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF07H FF08H FF09H FF0CH FF0EH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH 8-bit timer compare register 50 8-bit timer compare register 51 8-bit timer counter 50 8-bit timer counter 51 Serial I/O shift register 3 Transmit shift register 0 Receive buffer register 0 CR50 CR51 TM50 TM51 SIO3 TXS0 RXB0 R/W R/W R R R/W W R -- -- -- -- -- -- -- -- -- -- -- -- -- -- Undefined Undefined 00H 00H Undefined FFH FFH 16-bit timer counter 0 TM0 R -- -- 0000H 16-bit timer capture/compare register 01 CR01 R/W -- -- Undefined 16-bit timer capture/compare register 00 CR00 R/W -- -- Undefined Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port Port 8Note 1 9Note 2 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P12 ADCR0 R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R -- 8 Bits 16 Bits -- -- -- -- -- -- -- -- -- -- -- -- 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0000H
Port 12 A/D conversion result register 0
Notes 1. PD780316, 780318, 780326, 780328, 78F0338 only 2. PD780316, 780318, 78F0338 only
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Table 3-4. Special Function Register List (2/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset 1 Bit FF20H FF22H FF23H FF24H FF25H FF26H FF27H FF28H FF29H FF2CH FF30H FF32H FF33H FF34H FF35H FF36H FF37H FF38H FF39H FF3AH FF3BH FF3CH FF40H FF41H FF42H FF47H FF48H FF49H FF58H FF59H Pull-up resistor option register 12 Clock output select register Watch timer operation mode register 0 Watchdog timer clock select register Memory expansion mode register External interrupt rising edge enable register External interrupt falling edge enable register Pin function switching register Pin function switching register 8Note 2 9Note 2 PU12 CKS WTNM0 WDCS MEM EGP EGN PF8 PF9 R/W R/W R/W R/W R/W R/W R/W W W -- -- -- -- -- -- -- -- -- -- -- -- 00H 00H 00H 00H 00H 00H 00H 00H 00H Correction address register 1 CORAD1 R/W -- -- 0000H Port mode register 0 Port mode register 2 Port mode register 3 Port mode register 4 Port mode register 5 Port mode register 6 Port mode register 7 Port mode register Port mode register 8Note 1 9Note 1 PM0 PM2 PM3 PM4 PM5 PM6 PM7 PM8 PM9 PM12 PU0 PU2 PU3 PU4 PU5 PU6 PU7 CORAD0 R/W R/W R/W R/W R/W R/W R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- -- 8 Bits 16 Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FFH FFH FFH FFH FFH FFH FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 00H 0000H
Port mode register 12 Pull-up resistor option register 0 Pull-up resistor option register 2 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 6 Pull-up resistor option register 7 Correction address register 0
Notes 1. PD78F0338 only. 2. PD78F0338 only. PF8 and PF9 can only be set once after reset. To change the value, reset the register.
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Table 3-4. Special Function Register List (3/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset 1 Bit FF60H FF61H FF62H FF63H FF64H FF65H FF66H FF67H FF68H FF70H FF71H FF73H FF74H FF76H FF77H FF79H FF7AH FF80H FF81H FF82H FF83H FF8AH FF8FH FF90H FF91H FF92H FFA0H FFA1H FFA2H FFAFH FFB0H FFB1H FFB2H FFB4H 16-bit timer mode control register 4 8-bit timer mode control register 50 Timer clock select register 50 8-bit timer mode control register 51 Timer clock select register 51 8-bit timer mode control register 52 Timer clock select register 52 8-bit timer compare register 52 8-bit timer counter 52 A/D converter mode register 0 Analog input channel specification register 0 D/A converter mode register 0 D/A conversion value setting register 0 Correction control register Key return switching register LCD display mode register 3 LCD clock control register 3 Static/dynamic display switching register 3 Asynchronous serial interface mode register 0 Asynchronous serial interface status register 0 Baud rate generator control register 0 Serial operation mode register 3 Serial operation mode register 1 Serial clock select register 1 Serial I/O shift register 1 Transmit buffer register 1 TMC4 TMC50 TCL50 TMC51 TCL51 TMC52 TCL52 CR52 TM52 ADM0 ADS0 DAM0 DA0 CORCN KRSEL LCDM3 LCDC3 SDSEL3 ASIM0 ASIS0 BRGC0 CSIM3 CSIM1 CSIC1 SIO1 SOTB1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/WNote R/W R/W R/W R/W R R/W R/W R/W R/W R R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 00H 00H 00H 00H 00H 00H 00H Undefined 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 10H Undefined Undefined 16-bit timer counter 4 TM4 -- -- -- -- Undefined 16-bit timer mode control register 0 Prescaler mode register 0 Capture/compare control register 0 16-bit timer output control register 0 16-bit timer compare register 4 TMC0 PRM0 CRC0 TOC0 CR4 R/W R/W R/W R/W R/W -- -- 8 Bits 16 Bits -- -- -- -- -- 00H 00H 00H 00H Undefined
Note
KRSEL can be accessed but its read value is not guaranteed.
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Table 3-4. Special Function Register List (4/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset 1 Bit FFE0H FFE1H FFE2H FFE4H FFE5H FFE6H FFE8H FFE9H FFEAH FFF0H FFF4H FFF9H FFFAH FFFBH Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Priority specification flag register 0L Priority specification flag register 0H Priority specification flag register 1L Memory size switching registerNote 1 registerNote 2 PR1L IMS IXS WDTM OSTS PCC MK1L PR0 PR0L PR0H IF1L MK0 MK0L MK0H IF0 IF0L IF0H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- 8 Bits 16 Bits -- -- -- -- -- -- -- -- 00H 00H 00H FFH FFH FFH FFH FFH FFH CFH 0CH 00H 04H 04H
Internal expansion RAM size switching Watchdog timer mode register
Oscillation stabilization time select register Processor clock control register
Notes 1. Although the default value of this register is CFH, set the value corresponding to each product as indicated below.
PD780316, 780326, 780336: CCH PD780318, 780328, 780338: CFH PD78F0338:
Value for mask ROM version 2. Although the default value of this register is 0CH, use this register with a setting of 09H.
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3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists in relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration]
15 PC + 15 8 7 S jdisp8 15 PC 0 6 0 0 ... PC indicates the start address of the instruction after the BR instruction.
When S = 0, all bits of are 0. When S = 1, all bits of are 1.
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3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions
7 CALL or BR Low Addr. High Addr. 0
15 PC
87
0
In the case of CALLF !addr11 instruction
76 fa10-8 fa7-0 4 3 CALLF 0
15 PC 0 0 0 0
11 10 1
87
0
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3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. [Illustration]
7 Operation code 1
6 1
5 ta4-0
1
0 1
15 Effective address 0 0 0 0 0 0 0
8 0
7 0
6 1
5
10 0
7
Memory (table) Low addr.
0
Effective address + 1
High addr.
15 PC
8
7
0
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3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]
7 rp A 0 7 X 0
15 PC
8
7
0
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3.4 Operand Address Addressing
The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general-purpose register is automatically (implicitly) addressed. Of the PD780318, 780328, and 780338 Subseries instruction words, the following instructions employ implied addressing.
Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to Be Specified by Implied Addressing A register for multiplicand and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values which become decimal correction targets A register for storage of digit data which undergoes digit rotation
[Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing.
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3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register specify code (Rn and RPn) of an instruction word in the registered bank specified with the register bank select flag (RBS0 and RBS1). Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format]
Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL
`r' and `rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r Operation code 01100010 Register specify code INCW DE; when selecting DE register pair as rp Operation code 10000100 Register specify code
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3.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format]
Identifier addr16 Description Label or 16-bit immediate data
[Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 10001110 00000000 11111110 [Illustration]
7 OP code addr16 (lower) addr16 (upper) 0
OP code 00H FEH
Memory
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3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. If the SFR area (FF00H to FF1FH) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to the [Illustration] on the next page. [Operand format]
Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only)
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[Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 00010001 00110000 01010000 [Illustration]
7 OP code saddr-offset 0
OP code 30H (saddr-offset) 50H (immediate data)
Short direct memory 15 Effective address 1 1 1 1 1 1 1 87 0
When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1
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3.4.5 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format]
Identifier sfr sfrp Description Special function register name 16-bit manipulatable special function register name (even address only)
[Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 11110110 00100000 [Illustration] OP code 20H (sfr-offset)
7 OP code sfr-offset
0
SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0
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3.4.6 Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory to be manipulated. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- [DE], [HL] Description
[Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code [Illustration]
16 DE D 87 E The memory address specified with the register pair DE 0
10000101
7 The contents of the memory addressed are transferred. 7 A 0
Memory
0
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3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- [HL + byte] Description
[Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 10101110 00010000
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3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- [HL + B], [HL + C] Description
[Description example] In the case of MOV A, [HL + B] Operation code 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only. [Description example] In the case of PUSH DE Operation code 10110101 10101011
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4.1 Port Functions
The PD780318, 780328, and 780338 Subseries products incorporate input port, output port, and I/O port as listed in Table 4-1. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware I/O pins. Table 4-1. Port Types
Input Pin Output Pin 16 8 None I/O Pin 46
PD780316, 780318, 78F0338 PD780326, 780328 PD780336, 780338
8
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Figure 4-1. Port Types
P50
P00
Port 0 Port 5
P05 P57 P60 P10
Port 1 Port 6
P17 P67 P70 P20
Port 2
P25 P30
Port 7
P73 P80
Note 1
Port 3 Port 8
Note 1
P34 P87Note 1 P90Note 2 P40
Port 4
Port 9Note 2
P47 P97Note 2
Port 12
P120
Notes 1. The PD780336 and 780338 do not incorporate port 8. 2. The PD780326, 780328, 780336, and 780338 do not incorporate port 9.
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Table 4-2. Port Functions (1/2)
Pin Name I/O Function After Reset Alternate Function INTP0 INTP1 INTP2 INTP3/ADTRG INTP4 INTP5/BUZ/PCL Input Port 1 8-bit input only port. Port 2 6-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. Input ANI0 to ANI7
P00 P01 P02 P03 P04 P05 P10 to P17
I/O
Port 0 6-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
P20 P21 P22 P23 P24 P25 P30 P31 P32 P33 P34 P40 to P47
I/O
Input
RXD0/SI3 TXD0/SO3 SCK3 SI1 SO1 SCK1
I/O
Port 3 5-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
TO0 TI00 TI01 TO50/TI50 TO51/TI51
I/O
Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. Interrupt request flag (KRIF) is set to 1 by falling edge detection. Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
--
P50 to P57
I/O
Input
--
P60 to P63
I/O
P64 to P67
Port 6 8-bit I/O port Input/output mode can be specified in 1bit units. LEDs can be driven directly.
Medium-voltage N-ch open-drain I/ O port On-chip pull-up resistor can be specified by mask option. An on-chip pull-up resistor can be used by setting software.
Input
--
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Table 4-2. Port Functions (2/2)
Pin Name
I/O
Function
After Reset
Alternate Function TO4 TI4 TO52 TI52
P70 P71 P72 P73 P80 to P87Note P90 to P97Note
I/O
Port 7 4-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
Output
Port 8 8-bit output only port Port 9 8-bit output only port Port 12 1-bit I/O port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Output
S32 to S39Note S24 to S31Note
Output
Output
P120
I/O
Input
AO0
Note Ports 8 and 9 vary depending on the product.
Port 8 Port 9 P90 to P97 (without alternate pin) None None P80/S32 to P87/S39 P90/S24 to P97/S31
PD780316, 780318 PD780326, 780328 PD780336, 780338 PD78F0338
P80 to P87 (without alternate pin)
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4.2 Port Configuration
A port consists of the following hardware. Table 4-3. Port Configuration
Item Control registers Configuration Port mode register (PMm: m = 0, 2 to 7, 8Note, 9Note, 12) Pull-up resistor option register (PUm: m = 0, 2 to 7, 12) Memory expansion register (MEM) Key return switching register (KRSEL) Pin function switching registers 8 and 9 (PF8 and PF9)Note * PD780316, 780318, 78F0338 Total: 70 (input: 8, output: 16, I/O: 46) * PD780326, 780328 Total: 62 (input: 8, output: 8, I/O: 46) * PD780336, 780338 Total: 54 (input: 8, I/O: 46) Pull-up resistor * Mask ROM version Total: 46 (software control: 42, mask option: 4) * Flash memory version Total: 42 (software control: 42)
Ports
Note PD78F0338 only 4.2.1 Port 0 Port 0 is a 6-bit I/O port with output latch. Input/output mode can be specified for pins P00 to P05 in 1-bit units using port mode register 0 (PM0). An on-chip pull-up resistor can be used for the P00 to P05 pins in 1-bit units using pull-up resistor option register 0 (PU0). This port can also be used as an external interrupt request input, A/D converter external trigger input, clock output, and buzzer output. RESET input sets port 0 to input mode. Figures 4-2 and 4-3 show block diagrams of port 0. Caution Because port 0 also serves as an external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1.
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Figure 4-2. P00 to P04 Block Diagram
VDD0 WRPU
PU00 to PU04
P-ch
Alternate function RD
Internal bus
WRPORT Output latch (P00 to P04) WRPM P00/INTP0 to P02/INTP2, P03/INTP3/ADTRG, P04/INTP4
PM00 to PM04
PU: Pull-up resistor option register PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal
Selector
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Figure 4-3. P05 Block Diagram
VDD0 WRPU
PU05
P-ch
Alternate function RD
Internal bus
WRPORT Output latch (P05) WRPM
Selector
P05/INTP5/BUZ/PCL
PM05
Alternate function
PU: Pull-up resistor option register PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal 4.2.2 Port 1 Port 1 is an 8-bit input-only port. This port can also be used as an A/D converter analog input. Figure 4-4 shows a block diagram of port 1. Figure 4-4. P10 to P17 Block Diagram
RD
Internal bus
P10/ANI0 to P17/ANI7
RD: Port 1 read signal
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4.2.3 Port 2 Port 2 is a 6-bit I/O port with output latch. Input/output mode can be specified for pins P20 to P25 in 1-bit units using port mode register 2 (PM2). An on-chip pull-up resistor can be used for the P20 to P25 pins in 1-bit units using pull-up resistor option register 2 (PU2). This port has also alternate functions as serial interface data I/O and clock I/O. RESET input sets port 2 to input mode. Figures 4-5 and 4-6 show block diagrams of port 2. Figure 4-5. P20, P22, P23, P25 Block Diagram
VDD0 WRPU PU20, PU22, PU23, PU25
P-ch
Alternate function RD
Internal bus
WRPORT Output latch (P20, P22, P23, P25) WRPM PM20, PM22, PM23, PM25 P20/RxD0/SI3, P22/SCK3, P23/SI1, P25/SCK1
PU: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal
Selector
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Figure 4-6. P21, P24 Block Diagram
VDD0
WRPU PU21, PU24 RD P-ch
Selector
Internal bus
WRPORT Output latch (P21, P24) P21/TXD0/SO3, P24/SO1
WRPM PM21, PM24
Alternate function
PU: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal
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4.2.4 Port 3 Port 3 is a 5-bit I/O port with output latch. Input/output mode can be specified for pins P30 to P34 in 1-bit units using port mode register 3 (PM3). An on-chip pull-up resistor can be used for the P30 to P34 pins in 1-bit units using pull-up resistor option register 3 (PU3). This port has also alternate functions as timer I/O. RESET input sets port 3 to input mode. Figures 4-7 to 4-9 show block diagrams of port 3. Figure 4-7. P30 Block Diagram
VDD0
WRPU PU30 RD P-ch
Selector
Internal bus
WRPORT Output latch (P30)
P30/TO0
WRPM PM30
Alternate function
PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal
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Figure 4-8. P31, P32 Block Diagram
VDD0 WRPU
PU31, PU32
P-ch
Alternate function RD
Internal bus Selector
WRPORT Output latch (P31, P32) WRPM P31/TI00, P32/TI01
PM31, PM32
PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal
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Figure 4-9. P33, P34 Block Diagram
VDD0 WRPU
PU33, PU34
P-ch
Alternate function RD
Selector
Internal bus
WRPORT Output latch (P33, P34) WRPM
P33/TO50/TI50, P34/TO51/TI51
PM33, PM34
Alternate function
PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal
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4.2.5 Port 4 Port 4 is an 8-bit I/O port with output latch. Input/output mode can be specified for pins P40 to P47 in 1-bit units using port mode register 4 (PM4). An on-chip pull-up resistor can be used for the P40 to P47 pins in 1-bit units using pull-up resistor option register 4 (PU4). The interrupt request flag (KRIF) can be set to 1 by falling edge detection. The number of ports to detect the falling edge can be selected as either four (P40 to P43) or eight (P40 to P47) by setting bit 0 (KRSEL0) of the key return switching register (KRSEL). RESET input sets port 4 to input mode. Figure 4-10 shows a block diagram of port 4 and Figure 4-11 shows a block diagram of the falling edge detector. Cautions 1. When using the falling edge detection interrupt (INTKR), be sure to set the memory expansion mode register (MEM) to 01H. 2. If the number of key returns is set to four, the key return function cannot be evaluated with an in-circuit emulator. Figure 4-10. P40 to P47 Block Diagram
VDD0
WRPU PU40 to PU47 RD P-ch
Selector
Internal bus
WRPORT Output latch (P40 to P47) P40 to P47
WRPM PM40 to PM47
PU: Pull-up resistor option register PM: Port mode register RD: Port 4 read signal WR: Port 4 write signal
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Figure 4-11. Falling Edge Detector Block Diagram
KRSEL0 Bit 0 of key return switching register (KRSEL)
P47 P46 P45 P44 P43 P42 P41 "1" when MEM = 01H P40 Falling edge detector INTKR
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4.2.6 Port 5 Port 5 is an 8-bit I/O port with output latch. Input/output mode can be specified for pins P50 to P57 in 1-bit units using port mode register 5 (PM5). An on-chip pull-up resistor can be used for the P50 to P57 pins in 1-bit units using pull-up resistor option register 5 (PU5). RESET input sets port 5 to input mode. Figure 4-12 shows a block diagram of port 5. Figure 4-12. P50 to P57 Block Diagram
VDD0
WRPU PU50 to PU57 RD P-ch
Selector
Internal bus
WRPORT Output latch (P50 to P57) P50 to P57
WRPM PM50 to PM57
PU: Pull-up resistor option register PM: Port mode register RD: Port 5 read signal WR: Port 5 write signal
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4.2.7 Port 6 Port 6 is an 8-bit I/O port with output latch. Input/output mode can be specified for pins P60 to P67 in 1-bit units using port mode register 6 (PM6). This port has the following functions for pull-up resistors. These functions differ depending on the port's higher 4 bits/lower 4 bits, and whether the product is a mask ROM version or a flash memory version. Table 4-4. Pull-Up Resistor of Port 6
Higher 4 Bits (P64 to P67 Pins) Mask ROM version An on-chip pull-up resistor can be used in 1-bit units by PU6 Lower 4 Bits (P60 to P63 Pins) On-chip pull-up resistor can be specified in 1-bit units by mask option On-chip pull-up resistor is not provided
Flash memory version
PU6: Pull-up resistor option register 6 The P60 to P67 pins can drive LEDs directly. RESET input sets port 6 to input mode. Figures 4-13 and 4-14 show block diagrams of port 6. Figure 4-13. P60 to P63 Block Diagram
VDD0 RD Mask option resistor
Mask ROM version only No pull-up resistor for flash memory version
Selector
Internal bus
WRPORT Output latch (P60 to P63) P60 to P63
WRPM PM60 to PM63
PM: Port mode register RD: Port 6 read signal WR: Port 6 write signal
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Figure 4-14. P64 to P67 Block Diagram
VDD0
WRPU PU64 to PU67 RD P-ch
Selector
Internal bus
WRPORT Output latch (P64 to P67) P64 to P67
WRPM PM64 to PM67
PU: Pull-up resistor option register PM: Port mode register RD: Port 6 read signal WR: Port 6 write signal
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4.2.8 Port 7 Port 7 is a 4-bit I/O port with output latches. Input/output mode can be specified in 1-bit units using port mode register 7 (PM7). An on-chip pull-up resistor can be used for the P70 to P73 pins in 1-bit units using pull-up resistor option register 7 (PU7). This port can also be used as a timer I/O. RESET input sets port 7 to input mode. Figures 4-15 and 4-16 show block diagrams of port 7. Figure 4-15. P70, P72 Block Diagram
VDD0
WRPU PU70, PU72 RD P-ch
Selector
Internal bus
WRPORT Output latch (P70, P72) P70/TO4, P72/TO52
WRPM PM70, PM72
Alternate function
PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal
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Figure 4-16. P71, P73 Block Diagram
VDD0 WRPU
PU71, PU73
P-ch
Alternate function RD
Internal bus
WRPORT Output latch (P71, P73) WRPM P71/TI4, P73/TI52
PM71, PM73
PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal
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4.2.9 Ports 8 and 9 (mask ROM version) Ports 8 and 9 are 8-bit output-only ports. Ports 8 and 9 vary depending on the product. Table 4-5. Ports 8 and 9 of Mask ROM Version
Port 8 Port 9 P90 to P97 (without alternate pin) None None
PD780316, 780318 PD780326, 780328 PD780336, 780338
P80 to P87 (without alternate pin)
Figure 4-17 shows a block diagram of ports 8 and 9. Figure 4-17. P80 to P87 and P90 to P97 Block Diagram (Mask ROM Version)
RD
Internal bus
WRPORT Output latch (P80 to P87, P90 to P97) P80 to P87, P90 to P97
RD: Ports 8 and 9 read signal WR: Ports 8 and 9 write signal
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4.2.10 Ports 8 and 9 (flash memory version) Ports 8 and 9 are 8-bit output-only ports. These ports can also be used as an LCD controller/driver segment output. Figure 4-18 shows a block diagram of ports 8 and 9. Figure 4-18. P80 to P87 and P90 to P97 Block Diagram (Flash Memory Version)
RD
WRPORT Output latch (P80 to P87, P90 to P97)
Selector
Internal bus
WRPM PM80 to PM87, PM90 to PM97 WRLCD Segment output WRPF PF80 to PF87, PF90 to PF97
P80/S32 to P87/S39, P90/S24 to P97/S31
PF:
Pin function switching register
PM: Port mode register RD: Ports 8 and 9 read signal WR: Ports 8 and 9 write signal Caution When ports 8 and 9 are used as dedicated output ports, set the pin function switching registers (PF8, PF9) of the port used to FFH and set the port mode registers (PM8, PM9) to 00H.
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4.2.11 Port 12 Port 12 is a 1-bit I/O port with output latch. Input/output mode can be specified for P120 in 1-bit units using port mode register 12 (PM12). An on-chip pull-up resistor can be used for the P120 pin in 1-bit units using pull-up resistor option register 12 (PU12). This port also has an alternate function as the D/A converter analog output. RESET input sets port 12 to input mode. Figure 4-19 shows a block diagram of port 12. Figure 4-19. P120 Block Diagram
VDD0
WRPU PU120 RD P-ch
Selector
Internal bus
WRPORT Output latch (P120)
P120/AO0
WRPM PM120
Alternate function
PU: Pull-up resistor option register PM: Port mode register RD: Port 12 read signal WR: Port 12 write signal Caution Set port mode register 12 (PM12) and pull-up resistor option register 12 (PU12) as follows when used as D/A converter analog output. * Bit 0 (PM120) of PM12 to 1, input mode * Bit 0 (PU120) of PU12 to 0, disconnect pull-up resistor
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4.3 Port Function Control Registers
The following five types of registers control the ports. * * * * * Port mode registers (PM0, PM2 to PM7, PM8Note, PM9Note, PM12) Pull-up resistor option registers (PU0, PU2 to PU7, PU12) Memory expansion register (MEM) Key return switching register (KRSEL) Pin function switching registers 8 and 9 (PF8, PF9)Note
Note PD78F0338 only (1) Port mode registers (PM0, PM2 to PM7, PM8Note, PM9Note, PM12) These registers are used to set port input/output in 1-bit units. PM0, PM2 to PM7, and PM12 are independently set by a 1-bit or 8-bit memory manipulation instruction. PM8 and PM9 are independently set by an 8-bit memory manipulation instruction. RESET input sets the values of these registers to FFH. Note
PD78F0338 only.
Cautions 1. Pins P10 to P17 are input-only pins. 2. As port 0 has an alternate function as an external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. If a port has an alternate function pin and it is used as an alternate output function, set the output latches (P0, P2 to P7, and P12) to 0.
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Figure 4-20. Port Mode Registers (PM0, PM2 to PM9, PM12) Format
Address: FF20H After reset: FFH Symbol PM0 7 1 6 1 R/W 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00
Address: FF22H After reset: FFH Symbol PM2 7 1 6 1
R/W 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20
Address: FF23H After reset: FFH Symbol PM3 7 1 6 1
R/W 5 1 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30
Address: FF24H After reset: FFH Symbol PM4 7 PM47 6 PM46
R/W 5 PM45 4 PM44 3 PM43 2 PM42 1 PM41 0 PM40
Address: FF25H After reset: FFH Symbol PM5 7 PM57 6 PM56
R/W 5 PM55 4 PM54 3 PM53 2 PM52 1 PM51 0 PM50
Address: FF26H After reset: FFH Symbol PM6 7 PM67 6 PM66
R/W 5 PM65 4 PM64 3 PM63 2 PM62 1 PM61 0 PM60
Address: FF27H After reset: FFH Symbol PM7 7 1 6 1
R/W 5 1 4 1 3 PM73 2 PM72 1 PM71 0 PM70
Address: FF28H After reset: FFH Symbol PM8Note 7 PM87 6 PM86
W 5 PM85 4 PM84 3 PM83 2 PM82 1 PM81 0 PM80
Address: FF29H After reset: FFH Symbol PM9Note 7 PM97 6 PM96
W 5 PM95 4 PM94 3 PM93 2 PM92 1 PM91 0 PM90
Address: FF2CH After reset: FFH Symbol PM12 7 1 6 1
R/W 5 1 4 1 3 1 2 1 1 1 0 PM120
PMmn 0 1
Pmn pin I/O mode selection (m = 0, 2 to 9, 12: n = 0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF)
Note
PD78F0338 only. When ports 8 and 9 of the PD78F0338 are used as dedicated output ports, set the
pin function switching registers (PF8, PF9) of the port used to FFH and set the port mode registers (PM8, PM9) to 00H.
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(2) Pull-up resistor option registers (PU0, PU2 to PU7, PU12) These registers are used to set whether to use an on-chip pull-up resistor at each port or not. By setting PU0, PU2 to PU7, and PU12, the on-chip pull-up resistors of the port pins corresponding to the bits in PU0, PU2 to PU7, and PU12 can be used. PU0, PU2 to PU7, and PU12 are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the values of these registers to 00H. Cautions 1. The P10 to P17 pins do not incorporate a pull-up resistor. 2. Pins P60 to P63 can be used with pull-up resistor by mask option only for mask ROM version. 3. When PUm is set to 1, the on-chip pull-up resistor is connected irrespective of the input/ output mode. When using in output mode, therefore, set the bit of PUm to 0 (m = 0, 2 to 7, 12).
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Figure 4-21. Pull-Up Resistor Option Registers (PU0, PU2 to PU7, PU12) Format
Address: FF30H After reset: 00H Symbol PU0 7 0 6 0 R/W 5 PU05 4 PU04 3 PU03 2 PU02 1 PU01 0 PU00
Address: FF32H After reset: 00H Symbol PU2 7 0 6 0
R/W 5 PU25 4 PU24 3 PU23 2 PU22 1 PU21 0 PU20
Address: FF33H After reset: 00H Symbol PU3 7 0 6 0
R/W 5 0 4 PU34 3 PU33 2 PU32 1 PU31 0 PU30
Address: FF34H After reset: 00H Symbol PU4 7 PU47 6 PU46
R/W 5 PU45 4 PU44 3 PU43 2 PU42 1 PU41 0 PU40
Address: FF35H After reset: 00H Symbol PU5 7 PU57 6 PU56
R/W 5 PU55 4 PU54 3 PU53 2 PU52 1 PU51 0 PU50
Address: FF36H After reset: 00H Symbol PU6 7 PU67 6 PU66
R/W 5 PU65 4 PU64 3 0 2 0 1 0 0 0
Address: FF37H After reset: 00H Symbol PU7 7 0 6 0
R/W 5 0 4 0 3 PU73 2 PU72 1 PU71 0 PU70
Address: FF3CH After reset: 00H Symbol PU12 7 0 6 0
R/W 5 0 4 0 3 0 2 0 1 0 0 PU120
PUmn 0 1
Pmn pin internal pull-up resistor selection (m = 0, 2 to 7, 12: n = 0 to 7) On-chip pull-up resistor not used On-chip pull-up resistor used
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(3) Memory expansion mode register (MEM) This register is used to set the mode of port 4. MEM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 4-22. Memory Expansion Mode Register (MEM) Format
Address: FF47H After reset: 00H R/W Symbol MEM 7 0 6 0 5 0 4 0 3 0 2 MM2 1 MM1 0 MM0
MM2 0 0
MM1 0 0 Other than above
MM0 0 1
Single-chip/key return mode selection Single-chip mode (used as port pin) Key return mode (used as key input pinNote) Setting prohibited
Note
P44 to P47 pins can be used as port pins if bit 0 (KRSEL0) of key return switching register (KRSEL) is set to 1. At this time, key return function cannot be evaluated with in-circuit emulator.
Caution Be sure to set MM1 and MM2 to 0. (4) Key return switching register (KRSEL) This register is used to set the pins used as key return signals (port 4 falling edge detection). KRSEL is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 4-23. Key Return Switching Register (KRSEL) Format
Address: FF8FH After reset: 00H R/W Symbol KRSEL 7 0 6 0
Note 1
5 0
4 0
3 0
2 0
1 0
0 KRSEL0
KRSEL0 0 1
Setting the pin used for port 4 falling edge detection P40 to P47 are used as key return signal (port 4 falling edge detection) P40 to P43 are used as key return signal (port 4 falling edge detection)Note 2
Notes 1. KRSEL can be accessed but its read value is not guaranteed. 2. P44 to P47 can be used as port pins. Caution KRSEL0 can only be set once after reset. To change the value, reset the register.
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(5) Pin function switching registers 8 and 9 (PF8, PF9)Note These registers are used to select if ports 8 and 9 are used as port pins or segment pins. PF8 and PF9 are set by an 8-bit memory manipulation instruction. RESET input sets the values of these registers to 00H. Note
PD78F0338 only
Figure 4-24. Pin Function Switching Registers 8 and 9 (PF8, PF9) Format
Address: FF58H After reset: 00H W Symbol PF8 7 PF87 6 PF86 5 PF85 4 PF84 3 PF83 2 PF82 1 PF81 0 PF80
Address: FF59H After reset: 00H W Symbol PF9 7 PF97 6 PF96 5 PF95 4 PF94 3 PF93 2 PF92 1 PF91 0 PF90
PFn7 0
PFn6 0
PFn5 0
PFn4 0
PFn3 0
PFn2 0
PFn1 0
PFn0 0
Pin settings Segment output (n = 8: S32 to S39, n = 9: S24 to S31) Output-only port (n = 8: P87 to P80, n = 9: P97 to P90)
1
1
1
1
1
1
1
1
Other than above
Setting prohibited
Cautions 1. PF8 and PF9 can only be set to 00H or FFH once after reset. Do not set any values other than 00H and FFH. To change values, reset the register. 2. When ports 8 and 9 are used as dedicated output ports, set the pin function switching registers (PF8, PF9) of the port used to FFH and set the port mode registers (PM8, PM9) to 00H.
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
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4.5 Selection of Mask Option
The following mask option is provided in the mask ROM version. The flash memory versions have no mask options. Table 4-6. Comparison Between Mask ROM Version and Flash Memory Version
Pin Name Mask option for pins P60 to P63 Mask ROM Version On-chip pull-up resistors can be specified in 1-bit units Flash Memory Version Cannot specify an on-chip pull-up resistor
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CLOCK GENERATOR
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 10 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). (2) Subsystem clock oscillator The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock oscillator is not used, the internal feedback resistor can be disabled by the processor clock control register (PCC). This enables to reduce the power consumption in the STOP mode.
5.2 Clock Generator Configuration
The clock generator consists of the following hardware. Table 5-1. Clock Generator Configuration
Item Control register Oscillators Configuration Processor clock control register (PCC) Main system clock oscillator Subsystem clock oscillator
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Figure 5-1. Clock Generator Block Diagram
FRC
XT1 XT2
Subsystem clock oscillator
fXT
Prescaler 1/2 X1 X2 Main system clock oscillator fXT 2
Watch timer, clock output function
Prescaler fX fX 2 fX 22 fX 23 fX 24
Clock to peripheral hardware
Selector
Standby controller
Wait controller
CPU clock (fCPU)
3
STOP
MCC FRC
CLS
CSS PCC2 PCC1 PCC0 Processor clock control register (PCC)
Internal bus
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5.3 Clock Generator Control Register
The clock generator is controlled by the processor clock control register (PCC). The PCC sets the CPU clock selection, the division ratio, main system clock oscillator operation/stop and whether to use the subsystem clock oscillator internal feedback resistor. The PCC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of the PCC to 04H. Figure 5-2. Subsystem Clock Feedback Resistor
FRC P-ch Feedback resistor
XT1
XT2
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Figure 5-3. Processor Clock Control Register (PCC) Format
Address: FFFBH After reset: 04H Symbol PCC 7 MCC 6 FRC R/WNote 1 5 CLS 4 CSS 3 0 2 PCC2 1 PCC1 0 PCC0
MCC 0 1 Oscillation possible Oscillation stopped
Main system clock oscillation controlNote 2
FRC 0 1
Subsystem clock feedback resistor selectionNote 3 Internal feedback resistor used Internal feedback resistor not used
CLS 0 1 Main system clock Subsystem clock
CPU clock status
CSS 0
PCC2 0 0 0 0 1
PCC1 0 0 1 1 0 0 0 1 1 0
PCC0 0 1 0 1 0 0 1 0 1 0 fX fX/2 fX/22 fX/23 fX/24 fXT/2
CPU clock (fCPU) selection
1
0 0 0 0 1
Other than above
Setting prohibited
Notes 1. Bit 5 is a read-only bit. 2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock oscillation. A STOP instruction should not be used. 3. The feedback resistor is necessary for adjusting the bias point of the oscillation waveform close to the medium level of the supply voltage. The current consumption in the STOP mode can be further suppressed by setting FRC to 1 only when the subsystem clock is not used. Cautions 1. Be sure to set bit 3 to 0. 2. When the external clock is input, MCC should not be set. This is because the X2 pin is connected to VDD1 via a pull-up resistor. Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
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The fastest instructions of PD780318, 780328, and 780338 Subseries are carried out in two CPU clocks. The relationship of CPU clock (fCPU) and minimum instruction execution time is shown in Table 5-2. Table 5-2. Relationship of CPU Clock and Min. Instruction Execution Time
CPU Clock (fCPU) fX fX/2 fX/22 fX/23 fX/24 fXT/2 0.2 s 0.4 s 0.8 s 1.6 s 3.2 s 122 s Min. Instruction Execution Time: 2/(fCPU)
fX = 10 MHz, fXT = 32.768 kHz fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency
5.4 System Clock Oscillator
5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (10 MHz TYP.) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an inverted-phase clock signal to the X2 pin. Figure 5-4 shows an external circuit of the main system clock oscillator. Figure 5-4. External Circuit of Main System Clock Oscillator (a) Crystal and ceramic oscillation
IC X2
(b) External clock
X2
VSS1 Crystal resonator or ceramic resonator
X1
External clock
X1
Caution Do not execute the STOP instruction and do not set MCC (bit 7 of processor clock control register (PCC)) to 1 if an external clock is input. This is because when the STOP instruction or MCC is set to 1, the main system clock operation stops and the X2 pin is connected to VDD1 via a pullup resistor.
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5.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (32.768 kHz TYP.) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and an inverted-phase clock signal to the XT2 pin. Figure 5-5 shows an external circuit of the subsystem clock oscillator. Figure 5-5. External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation (b) External clock
IC XT1 32.768 kHz VSS1 XT2
External clock
XT1
XT2
Cautions are listed on the next page.
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Cautions 1. When using the main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken-line area in Figures 5-4 and 5-5 to prevent any effects from wiring capacitance. * Minimize the wiring length. * Do not allow wiring to intersect with other signal lines. Do not route the wiring in the vicinity of a line through which a high-fluctuating current flows. * Always keep the ground of the capacitor of the oscillator at the same potential as VSS1. Do not ground a capacitor to a ground pattern where high-current flows. * Do not fetch signals from the oscillator. Take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. Figure 5-6 shows examples of incorrect resonator connection. Figure 5-6. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line
PORTn (n = 0 to 7)
IC
X2
X1
IC
X2
X1
VSS1
VSS1
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2.
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Figure 5-6. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates)
VDD0
Pmn IC X2 X1
High current
IC
X2
X1
A VSS1
B High current
C
VSS1
(e) Signals are fetched
IC
X2
X1
VSS1
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. To prevent that from occurring, it is recommended to wire X2 and XT1 so that they are not in parallel.
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5.4.3 Divider The divider divides the main system clock oscillator output (fX) and generates various clocks. 5.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. XT1: Connect to VDD0 XT2: Open In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. To minimize leakage current, the above internal feedback resistor can be removed with bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins as described above.
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5.5 Clock Generator Operations
The clock generator generates the following various types of clocks and controls the CPU operation mode including the standby mode. * Main system clock * Subsystem clock * CPU clock fCPU fX fXT
* Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC). (a) Upon generation of RESET signal, the lowest speed mode of the main system clock (3.2 s @10 MHz operation) is selected (PCC = 04H). Main system clock oscillation stops while low level is applied to RESET pin. (b) With the main system clock selected, one of the five minimum instruction execution time types (0.2 s, 0.4 s, 0.8 s, 1.6 s, 3.2 s, @10 MHz operation) can be selected by setting the PCC. (c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. To reduce current consumption in the STOP mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock. (d) The PCC can be used to select the subsystem clock and to operate the system with low-current consumption (122 s @32.768 kHz operation). (e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT mode can be used. However, the STOP mode cannot be used (subsystem clock oscillation cannot be stopped). (f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to the watch timer and clock output functions only. Thus the watch function and the clock output function can also be continued in the standby state. However, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock operation).
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5.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC. (b) If bit 7 (MCC) of the PCC is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. When bit 4 (CSS) of the PCC is set to 1 and the operation is switched to subsystem clock operation (CLS = 1) after that, the main system clock oscillation stops (see Figure 5-7). Figure 5-7. Main System Clock Stop Function (1/2) (a) Operation when MCC is set after setting CSS with main system clock operation
MCC
CSS
CLS
Main system clock oscillation
Subsystem clock oscillation
CPU clock
(b) Operation when MCC is set in case of main system clock operation
MCC
CSS
L
CLS
L Oscillation does not stop.
Main system clock oscillation
Subsystem clock oscillation
CPU clock
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Figure 5-7. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation
MCC
CSS
CLS
Main system clock oscillation
Subsystem clock oscillation
CPU clock
5.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 s @32.768 kHz operation) irrespective of bits 0 to 2 (PCC0 to PCC2) of the PCC. (b) Watchdog timer counting stops. Caution Do not execute the STOP instruction while the subsystem clock is in operation.
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5.6 Changing System Clock and CPU Clock Settings
5.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the pre-switchover clock for several instructions (see Table 5-3). Determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (CLS) of the PCC register. Table 5-3. Maximum Time Required for CPU Clock Switchover
Set Value Before Switchover Set Value After Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x
16 instructions
16 instructions
16 instructions
16 instructions
fX/2fXT instruction (153 instructions) fX/4fXT instruction (77 instructions) fX/8fXT instruction (39 instructions) fX/16fXT instruction (20 instructions) fX/32fXT instruction (10 instructions)
0
0
1
8 instructions
8 instructions
8 instructions
8 instructions
0
1
0
4 instructions
4 instructions
4 instructions
4 instructions
0
1
1
2 instructions
2 instructions
2 instructions
2 instructions
1 x
0 x
0 x
1 instruction
1 instruction
1 instruction
1 instruction
1
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
Remarks 1. One instruction is the minimum instruction execution time with the pre-switchover CPU clock. 2. Figures in parentheses are for operation with fX = 10 MHz and fXT = 32.768 kHz. Caution Selection of the CPU clock cycle division rate (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle division rate (PCC0 to PCC2) and switch over from the subsystem clock to the main system clock (changing CSS from 1 to 0).
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5.6.2 System clock and CPU clock switching procedure This section describes switching procedure between the system clock and CPU clock. Figure 5-8. System Clock and CPU Clock Switching
VDD
RESET
Interrupt request signal
System clock CPU clock
fX Lowestspeed operation
fX Highestspeed operation
fXT Subsystem clock operation
fX High-speed operation
Wait (13.1 ms: @10 MHz operation) Internal reset operation
<1> The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation stabilization time (217/fX) is secured automatically. After that, the CPU starts executing the instruction at the minimum speed of the main system clock (3.2 s @10 MHz operation). <2> After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds, the PCC is rewritten and maximum-speed operation is carried out. <3> Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). <4> Upon detection of VDD voltage reset due to an interrupt, 0 is set to bit 7 (MCC) of the PCC and oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation, the PCC is rewritten and the maximum-speed operation is resumed. Caution When subsystem clock is being operated while the main system clock is stopped, if switching to the main system clock is done again, be sure to switch after securing oscillation stabilization time by program.
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CHAPTER 6
16-BIT TIMER/EVENT COUNTER 0
6.1 Outline of 16-Bit Timer/Event Counter 0
16-bit timer/event counter 0 can be used as an interval timer, PPG output, pulse width measurement (infrared ray remote control receive function), external event counter, or square wave output of any frequency.
6.2 16-Bit Timer/Event Counter 0 Functions
16-bit timer/event counter 0 has the following functions. * Interval timer * PPG output * Pulse width measurement * External event counter * Square-wave output (1) Interval timer Generates an interrupt request at the preset time interval. (2) PPG output Can output a square wave whose frequency and output pulse can be set freely. (3) Pulse width measurement Can measure the pulse width of an externally input signal. (4) External event counter Can measure the number of pulses of an externally input signal. (5) Square-wave output Can output a square wave with any selected frequency.
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6.3 16-Bit Timer/Event Counter 0 Configuration
16-bit timer/event counter 0 consists of the following hardware. Table 6-1. 16-Bit Timer/Event Counter 0 Configuration
Item Timer/counter Register Timer output Control registers 16 bits x 1 (TM0) 16-bit timer capture/compare register: 16 bits x 2 (CR00, CR01) 1 (TO0) 16-bit timer mode control register 0 (TMC0) Capture/compare control register 0 (CRC0) 16-bit timer output control register 0 (TOC0) Prescaler mode register 0 (PRM0) Port mode register 3 (PM3)Note Configuration
Note
Refer to Figure 4-7 P30 Block Diagram and Figure 4-8 P31, P32 Block Diagram.
Figure 6-1 shows a block diagram. Figure 6-1. 16-Bit Timer/Event Counter 0 Block Diagram
Internal bus Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00
Selector
INTTM00
Selector
TI01/P32
Noise eliminator
16-bit timer capture/compare register 00 (CR00) Match
Selector
fX fX/22 fX/26
16-bit timer counter 0 (TM0) Match
Clear
Output controller
TO0/P30
fX/23
Noise eliminator
2 Noise eliminator 16-bit timer capture/compare register 01 (CR01)
Selector
TI00/P31
INTTM01
CRC02 PRM01PRM00 Prescaler mode register 0 (PRM0) TMC03 TMC02 TMC01 OVF0 TOC04 LVS0 LVR0 TOC01 TOE0 16-bit timer output 16-bit timer mode control register 0 control register 0 (TOC0) (TMC0) Internal bus
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(1) 16-bit timer counter 0 (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of an input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. The count value is reset to 0000H in the following cases: <1> At RESET input <2> If TMC03 and TMC02 are cleared <3> If valid edge of TI00 is input in the clear & start mode by inputting valid edge of TI00 <4> If TM0 and CR00 match with each other in the clear & start mode on match between TM0 and CR00 (2) 16-bit timer capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0 (CRC0). * When CR00 is used as a compare register The value set in the CR00 is constantly compared with the 16-bit timer counter 0 (TM0) count value, and an interrupt request (INTTM00) is generated if they match. It can also be used as the register which holds the interval time when TM0 is set to interval timer operation. * When CR00 is used as a capture register It is possible to select the valid edge of the TI00/P31 pin or the TI01/P32 pin as the capture trigger. Setting of the TI00 or TI01 valid edge is performed by means of prescaler mode register 0 (PRM0). If CR00 is specified as a capture register and capture trigger is specified to be the valid edge of the TI00/P31 pin, the situation is as shown in Table 6-2. On the other hand, when capture trigger is specified to be the valid edge of the TI01/P32 pin, the situation is as shown in Table 6-3. Table 6-2. TI00/P31 Pin Valid Edge and CR00, CR01 Capture Trigger
ES01 0 0 1 1 ES00 0 1 0 1 TI00/P31 Pin Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges CR00 Capture Trigger Rising edge Falling edge Setting prohibited No capture operation CR01 Capture Trigger Falling edge Rising edge Setting prohibited Both rising and falling edges
Table 6-3. TI01/P32 Pin Valid Edge and CR00 Capture Trigger
ES11 0 0 1 1 ES10 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges TI01/P32 Pin Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges CR00 Capture Trigger
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CR00 is set by a 16-bit memory manipulation instruction. The value of this register is undefined when RESET is input. Cautions 1. In the clear & start mode on match between TM0 and CR00, set a value other than 0000H in CR00. However, in the free-running mode and in the clear mode using the valid edge of TI00, if 0000H is set to CR00, an interrupt request (INTTM00) is generated following overflow (FFFFH). 2. If the new value of CR00 is less than the value of 16-bit timer counter 0 (TM0), TM0 continues counting, overflows, and then start counting from 0 again. If the new value of CR00 is less than the old value, therefore, the timer must be reset and restarted after the value of CR00 is changed. (3) 16-bit timer capture/compare register 01 (CR01) CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register 0 (CRC0). * When CR01 is used as a compare register The value set in the CR01 is constantly compared with the 16-bit timer counter 0 (TM0) count value, and an interrupt request (INTTM01) is generated if they match. * When CR01 is used as a capture register It is possible to select the valid edge of the TI00/P31 pin as the capture trigger. The TI00/P31 valid edge is set by means of prescaler mode register 0 (PRM0). Table 6-2 shows the setting when the valid edge of the TI00/P31 pin is specified as the capture trigger. CR01 is set by a 16-bit memory manipulation instruction. The value of this register is undefined when RESET is input. Caution In the clear & start mode on match between TM0 and CR00, set a value other than 0000H in CR01. However, in the free-running mode and in the clear mode using the valid edge of TI00, if 0000H is set to CR01, an interrupt request (INTTM01) is generated following overflow (FFFFH).
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6.4 Registers to Control 16-Bit Timer/Event Counter 0
The following five types of registers are used to control 16-bit timer/event counter 0. * 16-bit timer mode control register 0 (TMC0) * Capture/compare control register 0 (CRC0) * 16-bit timer output control register 0 (TOC0) * Prescaler mode register 0 (PRM0) * Port mode register 3 (PM3) (1) 16-bit timer mode control register 0 (TMC0) This register sets the 16-bit timer operation mode, the 16-bit timer counter 0 (TM0) clear mode, and output timing, and detects an overflow. TMC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Caution The 16-bit timer counter 0 (TM0) starts operation at the moment a value other than 0, 0 (operation stop mode) is set in TMC02 to TMC03, respectively. Set 0, 0 in TMC02 to TMC03 to stop the operation.
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Figure 6-2. 16-Bit Timer Mode Control Register 0 (TMC0) Format
Address: FF60H Symbol TMC0 7 0 6 0 After reset: 00H 5 0 4 0 R/W 3 2 1 0
TMC03 TMC02 TMC01 OVF0
TMC03
TMC02
TMC01
Operation mode and clear mode selection Operation stop (TM0 cleared to 0) Free-running mode
TO0 output timing selection
Interrupt request generation
0 0 0
0 0 1
0 1 0
No change
Not generated
Match between TM0 and CR00 or match between TM0 and CR01 Match between TM0 and CR00, match between TM0 and CR01 or TI00 valid edge
0
1
1
Generated on match between TM0 and CR00, or match between TM0 and CR01
1 1 1
0 0 1
0 1 0
Clear & start on TI00 valid edge Clear & start on match between TM0 and CR00
--
Match between TM0 and CR00 or match between TM0 and CR01 Match between TM0 and CR00, match between TM0 and CR01 or TI00 valid edge
1
1
1
OVF0 0 1 Overflow not detected Overflow detected
16-bit timer counter 0 (TM0) overflow detection
Cautions 1. Be sure to stop timer operation before writing to bits other than the OVF0 flag. 2. Set the valid edge of the TI00/P31 pin with prescaler mode register 0 (PRM0). 3. If clear & start mode on match between TM0 and CR00 is selected, when the set value of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, OVF0 flag is set to 1. Remarks 1. TO0: 2. TI00: 3. TM0: 16-bit timer/event counter 0 output pin 16-bit timer/event counter 0 input pin 16-bit timer counter 0
4. CR00: 16-bit timer capture/compare register 00 5. CR01: 16-bit timer capture/compare register 01
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(2) Capture/compare control register 0 (CRC0) This register controls the operation of 16-bit timer capture/compare registers 00 and 01 (CR00, CR01). CRC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 6-3. Capture/Compare Control Register 0 (CRC0) Format
Address: FF62H Symbol CRC0 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 CRC02 1 CRC01 0 CRC00
CRC02 0 1
CR01 operation mode selection Operates as compare register Operates as capture register
CRC01 0 1
CR00 capture trigger selection Captures on valid edge of TI01 Captures on valid edge of TI00 by reverse phase
CRC00 0 1
CR00 operation mode selection Operates as compare register Operates as capture register
Cautions 1. Be sure to stop timer operation before setting CRC0. 2. When clear & start mode on a match between TM0 and CR00 is selected with the 16-bit timer mode control register 0 (TMC0), CR00 should not be specified as a capture register. 3. If both the rising and falling edges have been selected as the valid edges of TI00, capture is not performed. 4. To surely perform the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 (PRM0).
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(3) 16-bit timer output control register 0 (TOC0) This register controls the operation of the 16-bit timer/event counter 0 output controller. It sets R-S type flipflop (LV0) setting/resetting, output inversion enabling/disabling, and 16-bit timer/event counter 0 timer output enabling/disabling. TOC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 6-4 shows the TOC0 format. Figure 6-4. 16-Bit Timer Output Control Register 0 (TOC0) Format
Address: FF63H Symbol TOC0 7 0 After reset: 00H 6 0 R/W 5 0 4 TOC04 3 LVS0 2 LVR0 1 TOC01 0 TOE0
TOC04 0 1
Timer output F/F control by match of CR01 and TM0 Inversion operation disabled Inversion operation enabled
LVS0 0 0 1 1
LVR0 0 1 0 1
16-bit timer/event counter 0 timer output F/F status setting No change Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
TOC01 0 1
Timer output F/F control by match of CR00 and TM0 Inversion operation disabled Inversion operation enabled
TOE0 0 1
16-bit timer/event counter 0 output control Output disabled (output set to level 0) Output enabled
Cautions 1. Be sure to stop timer operation before setting TOC0. 2. If LVS0 and LVR0 are read after data is set, they will be 0. 3. Be sure to set bits 5, 6 and 7 to 0.
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(4) Prescaler mode register 0 (PRM0) This register is used to set the 16-bit timer counter 0 (TM0) count clock and TI00, TI01 input valid edges. PRM0 is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 6-5. Prescaler Mode Register 0 (PRM0) Format
Address: FF61H Symbol PRM0 7 ES11 After reset: 00H 6 ES10 R/W 5 ES01 4 ES00 3 0 2 0 1 PRM01 0 PRM00
ES11 0 0 1 1
ES10 0 1 0 1 Falling edge Rising edge Setting prohibited
TI01 valid edge selection
Both falling and rising edges
ES01 0 0 1 1
ES00 0 1 0 1 Falling edge Rising edge Setting prohibited
TI00 valid edge selection
Both falling and rising edges
PRM01 0 0 1 1
PRM00 0 1 0 1 fX (10 MHz) fX/22 (2.5 MHz) fX/26 (156.25 kHz) TI00 valid edgeNote
Count clock selection
Note The external clock requires a pulse two times longer than the internal clock (fX/23). Cautions 1. If the valid edge of TI00 is to be set to the count clock, do not set the clear & start mode and the capture trigger at the valid edge of TI00. 2. Be sure to stop timer operation before setting data to PRM0. 3. If the TI00 or TI01 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI00 pin or TI01 pin to enable the operation of 16-bit timer counter 0 (TM0). Please be careful when pulling up the TI00 pin or the TI01 pin. Note that, when re-enabling operation after the operation has been stopped once, the rising edge is not detected. Remarks 1. fX: Main system clock oscillation frequency 2. TI00, TI01: 16-bit timer/event counter 0 input pin 3. Figures in parentheses are for operation with fX = 10 MHz.
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(5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and the output latch of P30 to 0. PM3 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to FFH. Figure 6-6. Port Mode Register 3 (PM3) Format
Address: FF23H Symbol PM3 7 1 6 1 After reset: FFH 5 1 4 R/W 3 2 1 0
PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin I/O mode selection (n = 0 to 4) Output mode (output buffer ON) Input mode (output buffer OFF)
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6.5 16-Bit Timer/Event Counter 0 Operations
6.5.1 Interval timer operations Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-7 allows operation as an interval timer. An interrupt request is generated repeatedly using the count value set in 16-bit timer capture/compare register 00 (CR00) beforehand as the interval. When the count value of 16-bit timer counter 0 (TM0) matches the value set to CR00, counting continues with the TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated. Count clock of 16-bit timer/event counter 0 can be selected with bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). See 6.6 16-Bit Timer/Event Counter 0 Cautions (2) about the operation when the compare register value is changed during timer count operation. Figure 6-7. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clears and starts on match between TM0 and CR00.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 as compare register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See Figures 6-2 and 6-3.
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Figure 6-8. Interval Timer Configuration Diagram
16-bit timer capture/compare register 00 (CR00)
INTTM00 fX fX/22 fX/26 TI00/P31 Noise eliminator fX/23
Selector
16-bit timer counter 0 (TM0)
OVF0
Clear circuit
Figure 6-9. Timing of Interval Timer Operation
t
Count clock TM0 count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N N
Count start CR00 INTTM00 N
Interrupt request acknowledged TO0 Interval time Interval time
Interrupt request acknowledged
Interval time
Remark Interval time = (N + 1) x t N = 0001H to FFFFH
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6.5.2 PPG output operations Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-10 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit timer capture/compare register 01 (CR01) and in 16bit timer capture/compare register 00 (CR00), respectively. Figure 6-10. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0 0 Clears and starts on match between TM0 and CR00.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0 x 0 CR00 as compare register CR01 as compare register
(c) 16-bit timer output control register 0 (TOC0)
TOC04 LVS0 LVR0 TOC01 TOE0 TOC0 0 0 0 1 0/1 0/1 1 1 Enables TO0 output Reverses output on match between TM0 and CR00 Specifies initial value of TO0 output F/F Reverses output on match between TM0 and CR01
Cautions 1. Values in the following range should be set in CR00 and CR01: 0000H < CR01 < CR00 FFFFH 2. The cycle of the pulse generated through PPG output (CR00 setting value + 1) has a duty of (CR01 setting value + 1)/(CR00 setting value + 1). Remark x: don't care
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6.5.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P31 pin and TI01/P32 pin using 16-bit timer counter 0 (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P31 pin. (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-11), and the edge specified by prescaler mode register 0 (PRM0) is input to the TI00/P31 pin, the value of TM0 is taken into 16-bit timer capture/compare register 01 (CR01) and an external interrupt request signal (INTTM01) is set. Any of three edges can be selected--rising, falling, or both edges--specified by means of bits 4 and 5 (ES00 and ES01) of PRM0. Sampling is performed at the count clock selected by PRM0, and a capture operation is only performed when a valid level of the TI00/P31 pin or TI01/P32 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-11. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 0/1 0 CR00 as compare register CR01 as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See Figures 6-2 and 6-3.
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Figure 6-12. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
fX fX/22 fX/2
6
Selector
16-bit timer counter 0 (TM0)
OVF0
TI00/P31
16-bit timer capture/compare register 01 (CR01) INTTM01 Internal bus
Figure 6-13. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified)
t
Count clock TM0 count value TI00 pin input CR01 capture value INTTM01 OVF0 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3
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(2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-14), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P31 pin and the TI01/ P32 pin. When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the TI00/P31 pin, the value of TM0 is taken into 16-bit timer capture/compare register 01 (CR01) and an interrupt request signal (INTTM01) is set. Also, when the edge specified by bits 6 and 7 (ES10 and ES11) of PRM0 is input to the TI01/P32 pin, the value of TM0 is taken into 16-bit timer capture/compare register 00 (CR00) and an interrupt request signal (INTTM00) is set. Any of three edges can be selected--rising, falling, or both edges--as the valid edges for the TI00/P31 pin and the TI01/P32 pin specified by means of bits 4 and 5 (ES00 and ES01) and bits 6 and 7 (ES10 and ES11) of PRM0, respectively. Sampling is performed at the interval selected by means of prescaler mode register 0 (PRM0), and a capture operation is only performed when a valid level of the TI00/P31 pin or TI01/P32 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-14. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 0 1 CR00 as capture register Captures valid edge of TI01/P32 pin to CR00 CR01 as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See Figure 6-2.
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* Capture operation (free-running mode) Capture register operation in capture trigger input is shown. Figure 6-15. Capture Operation of CR01 with Rising Edge Specified
Count clock TM0 TI00 Rising edge detection CR01 INTTM01 n n-3 n-2 n-1 n n+1
Figure 6-16. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified)
t
Count clock TM0 count value TI00 pin input CR01 capture value INTTM01 TI01 pin input CR00 capture value INTTM00 OVF0 D1 D2 + 1 D0 D1 D2 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
(10000H - D1 + (D2 + 1)) x t
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(3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-17), it is possible to measure the pulse width of the signal input to the TI00/P31 pin. When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the TI00/P31 pin, the value of TM0 is taken into 16-bit timer capture/compare register 01 (CR01) and an interrupt request signal (INTTM01) is set. Also, on the inverse edge input of that of the capture operation into CR01, the value of TM0 is taken into 16bit timer capture/compare register 00 (CR00). Either of two edges can be selected--rising or falling--as the valid edges for the TI00/P31 pin specified by means of bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0). Sampling is performed at the interval selected by means of prescaler mode register 0 (PRM0), and a capture operation is only performed when a valid level of the TI00/P31 pin is detected twice, thus eliminating noise with a short pulse width. Caution If the valid edge of TI00/P31 pin is specified to be both rising and falling edges, 16-bit timer capture/compare register 00 (CR00) cannot perform the capture operation. Figure 6-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 1 1 CR00 as capture register Captures to CR00 at edge reverse to valid edge of TI00/P31. CR01 as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details.
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Figure 6-18. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
t
Count clock TM0 count value TI00 pin input CR01 capture value CR00 capture value INTTM01 OVF0 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3
(4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P31 pin is detected, the count value of 16-bit timer counter 0 (TM0) is taken into 16-bit timer capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P31 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 6-19). The edge specification can be selected from two types, rising and falling edges, by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0). In a valid edge detection, the sampling is performed by a cycle selected by prescaler mode register 0 (PRM0) and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Caution If the valid edge of TI00/P31 pin is specified to be both rising and falling edges, 16-bit timer capture/compare register 00 (CR00) cannot perform the capture operation.
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Figure 6-19. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 0 0/1 0 Clears and starts at valid edge of TI00/P31 pin.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 1 1 CR00 as capture register Captures to CR00 at edge reverse to valid edge of TI00/P31.
CR01 as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See Figure 6-2. Figure 6-20. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified)
t
Count clock TM0 count value TI00 pin input CR01 capture value CR00 capture value INTTM01 D1 x t D2 x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H
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6.5.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P31 pin with 16bit timer counter 0 (TM0). TM0 is incremented each time the valid edge specified with prescaler mode register 0 (PRM0) is input. When the TM0 counted value matches the 16-bit timer capture/compare register 00 (CR00) value, TM0 is cleared to 0 and an interrupt request signal (INTTM00) is generated. Input a value other than 0000H to CR00. (A count operation with a pulse cannot be carried out.) The rising edge, the falling edge, or both edges can be selected with bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0). Because capture operation is carried out only after the valid edge of the TI00/P31 pin is detected twice by sampling with the internal clock (fX/23), noise with short pulse widths can be eliminated. Figure 6-21. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clears and starts on match between TM0 and CR00.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 as compare register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See Figures 6-2 and 6-3.
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Figure 6-22. External Event Counter Configuration Diagram
16-bit timer capture/compare register 00 (CR00) Match INTTM00 fX fX/26 fX/23 Valid edge of TI00 Noise eliminator Noise eliminator 16-bit timer capture/compare register 01 (CR01) Clear
Selector
fX/22
16-bit timer counter 0 (TM0)
OVF0
Internal bus
Figure 6-23. External Event Counter Operation Timings (with Rising Edge Specified)
TI00 pin input TM0 count value CR00 INTTM00 0000H 0001H 0002H 0003H 0004H 0005H N N-1 N 0000H 0001H 0002H 0003H
Caution When reading the external event counter count value, TM0 should be read. 6.5.5 Square-wave output operation A square wave with any selected frequency can be output at intervals of the count value preset to 16-bit timer capture/compare register 00 (CR00). The TO0 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of 16-bit timer output control register 0 (TOC0) to 1. This enables a square wave with any selected frequency to be output.
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Figure 6-24. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clears and starts on match between TM0 and CR00.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 as compare register
(c) 16-bit timer output control register 0 (TOC0)
TOC04 LVS0 LVR0 TOC01 TOE0 TOC0 0 0 0 0 0/1 0/1 1 1 Enables TO0 output. Reverses output on match between TM0 and CR00. Specifies initial value of TO0 output F/F. Does not reverse output on match between TM0 and CR01.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See Figures 6-2, 6-3, and 6-4. Figure 6-25. Square-Wave Output Operation Timing
Count clock TM0 count value CR00 INTTM00 TO0 pin output 0000H 0001H 0002H N N-1 N 0000H 0001H 0002H N-1 N 0000H
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6.6 16-Bit Timer/Event Counter 0 Cautions
(1) Timer start errors An error of up to one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 0 (TM0) is started asynchronously to the count clock. Figure 6-26. 16-Bit Timer Counter 0 (TM0) Start Timing
Count clock
TM0 count value
0000H
0001H
0002H
0003H
0004H
Timer start
(2) 16-bit timer compare register setting (in the clear & start mode on match between TM0 and CR00) Set other than 0000H to 16-bit timer capture/compare registers 00, 01 (CR00, CR01). This means 1-pulse count operation cannot be performed when it is used as the event counter. (3) Operation after compare register change during timer count operation If the value after 16-bit timer capture/compare register 00 (CR00) is changed is smaller than that of 16-bit timer counter 0 (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR00 change is smaller than that (N) before the change, it is necessary to reset and restart the timer after changing CR00. Figure 6-27. Timings After Change of Compare Register During Timer Count Operation
Count clock
CR00
N
M
TM0 count value
X-1
X
FFFFH
0000H
0001H
0002H
Remark N > X > M
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(4) Capture register data retention timings If the valid edge of the TI00/P31 pin is input during 16-bit timer capture/compare register 01 (CR01) read, CR01 carries out capture operation but the captured value at this time is not guaranteed. However, the interrupt request signal (TMIF01) is set upon detection of the valid edge. Figure 6-28. Capture Register Data Retention Timing
Count clock TM0 count value Edge input INTTM01 Capture read signal CR01 interrupt value X Capture operation N+1 Capture operation is performed but the captured value is not guaranteed. N N+1 N+2 M M+1 M+2
(5) Valid edge setting Set the valid edge of the TI00/P31 pin after setting bits 2 and 3 (TMC02 and TMC03) of 16-bit timer mode control register 0 (TMC0) to 0, 0, respectively, and then stopping timer operation. The valid edge is set with bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0).
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(6) Operation of OVF0 flag <1> OVF0 flag is set to 1 in the following case. Select any of the clear & start mode entered on a match between TM0 and CR00, the mode in which the timer is cleared and started by the valid edge of TI00, and the free-running mode. CR00 is set to FFFFH. When TM0 is counted up from FFFFH to 0000H. Figure 6-29. Operation Timing of OVF0 Flag
Count clock CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFFH 0000H 0001H
<2> Even if the OVF0 flag is cleared before the next count clock (before TM0 becomes 0001H) after the occurrence of TM0 overflow, the OVF0 flag is reset newly and clear is disabled. (7) Contending operations <1> The contending operations between the read time of the 16-bit timer capture/compare register (CR00/ CR01) and capture trigger input (CR00/CR01 used as capture register) Capture trigger input is prior to the other. The data read from CR00/CR01 is not defined. <2> The match timing of contending operations between the write period of the 16-bit timer capture/compare register (CR00/CR01) and 16-bit timer counter 0 (TM0) (CR00/CR01 used as a compare register) The match discriminant is not performed normally. Do not write any data to CR00/CR01 near the match timing.
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(8) Timer operation <1> Even if 16-bit timer counter 0 (TM0) is read, the value is not captured by 16-bit timer capture/compare register 01 (CR01). <2> Regardless of the CPU's operation mode, when the timer stops, the signals input to pins TI00/TI01 are not acknowledged. (9) Capture operation <1> If TI00 is specified as the valid edge of the count clock, capture operation by the capture register specified as the trigger for TI00 is not possible. <2> If both the rising and falling edges are selected as the valid edges of TI00, capture is not performed. <3> To ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 (PRM0). <4> The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n), however, is generated at the rise of the next count clock. (10) Compare operation <1> The INTTM0 may not be generated if the set value of 16-bit timer capture registers 00, 01 (CR00, CR01) and the count value of 16-bit timer counter 0 (TM0) match and CR00 and CR01 are overwritten at the timing of INTTM0 generation. Therefore, do not overwrite CR00 and CR01 frequently even if overwriting the same value. <2> Capture operation may not be performed for CR00/CR01 set in compare mode even if a capture trigger has been input.
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(11) Edge detection <1> If the TI00 pin or the TI01 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge for the TI00 pin or TI01 pin to enable 16-bit timer counter 0 (TM0) operation, a rising edge is detected immediately after. Be careful when pulling up the TI00 pin or the TI01 pin. However, the rising edge is not detected at restart after the operation has been stopped once. <2> The sampling clock used to eliminate noise differs when the TI00 pin valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fX/23, and in the latter case the count clock is selected by prescaler mode register 0 (PRM0). The capture operation is only started after a valid edge is detected twice by sampling, therefore noise with a short pulse width can be eliminated.
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7.1 Outline of 16-Bit Timer/Event Counter 4
16-bit timer/event counter 4 can be used to serve as an interval timer, square wave output with any selected frequency, and an external event counter.
7.2 16-Bit Timer/Event Counter 4 Functions
16-bit timer/event counter 4 has the following functions. * Interval timer * Square wave output * External event counter (1) Interval timer Generates an interrupt request at the preset time interval. (2) Square wave output Can output a square wave with any selected frequency. (3) External event counter Can measure the number of pulses (TI4) of an externally input signal.
7.3 16-Bit Timer/Event Counter 4 Configuration
16-bit timer/event counter 4 consists of the following hardware. Table 7-1. 16-Bit Timer/Event Counter 4 Configuration
Item Timer/counter Register Timer output Control registers 16 bits x 1 (TM4) 16-bit timer compare register 4: 16 bits x 1 (CR4) 1 (TO4) 16-bit timer mode control register 4 (TMC4) Port mode register 7 (PM7)Note Configuration
Note Refer to Figure 4-15 P70, P72 Block Diagram and Figure 4-16 P71, P73 Block Diagram.
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Figure 7-1 shows a block diagram. Figure 7-1. 16-Bit Timer/Event Counter 4 Block Diagram
Internal bus
Output control
16-bit timer compare register 4 (CR4)
TO4/P70
TI4/P71 fX fX/25 fX/2
7
Match
Selector
16-bit timer counter 4 (TM4)
Clear control
Selector
INTTM4
OVF Clear Selector 2 TCE4 TMM4 TMO4 LVS4 OVF4 TCL41 TCL40 16-bit timer mode control register 4 (TMC4) Internal bus
(1) 16-bit timer counter 4 (TM4) TM4 is a 16-bit register that counts count pulses. The counter is incremented in synchronization with the rising edge of an input clock. TM4 cannot be read or written to. The value of this register is undefined when RESET is input. The count value is reset to 0000H in the following cases. <1> If TCE4 is cleared <2> If TM4 and CR4 match with each other in clear & start mode on match between TM4 and CR4 <3> Immediately after TM4 overflowed in free-running mode (2) 16-bit timer compare register 4 (CR4) This register always compares the value set in CR4 and the count value of 16-bit timer counter 4 (TM4). If the two values match, CR4 generates an interrupt request (INTTM4). If TM4 is specified as an interval timer, this register can be used to hold the interval time. CR4 is set by a 16-bit memory manipulation instruction. The value of this register is undefined when RESET is input. Caution Do not write values to CR4 during TM4 count operation. Stop the count operation first if overwriting the same value.
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7.4 Registers to Control 16-Bit Timer/Event Counter 4
The following two registers are used to control 16-bit timer/event counter 4. * 16-bit timer mode control register 4 (TMC4) * Port mode register 7 (PM7)
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(1) 16-bit timer mode control register 4 (TMC4) This register controls the 16-bit timer counter 4 (TM4) count operation and timer output (TO4), selects the operation mode, specifies the TO4 initial value, and sets the TM4 count clock and valid edge of TI4 input. TMC4 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 7-2. 16-Bit Timer Mode Control Register 4 (TMC4) Format
Address: FF68H After reset: 00H Symbol TMC4 7 TCE4 6 TMM4 R/WNote 1 5 TMO4 4 LVS4 3 OVF4 2 0 1 TCL41 0 TCL40
TCE4 0 1
TM4 count operation control Count operation stop (TM4 cleared to 0) Count operation start
TMM4 0
TM4 operation mode selection Clear & start on match between TM4 and CR4Note 2 Free-running mode
INTTM4 generation timing Match between TM4 and CR4
1
INTTM4 not generated
TMO4 0 1
Timer output (TO4) control Output disabled (output level is fixed at 0) Output enabled
LVS4 0 1 Low level High level
Timer output (TO4) initial value setting
OVF4
The value of OVF4 reversed each time an overflow occurs (reset value: OVF4 = 0).
TCL41 0 0 1 1
TCL40 0 1 0 1 fX (10 MHz) fX/25 (312.5 kHz) fX/27 (78.125 kHz) Rising edge of TI4
Count clock selection
Notes 1. Bit 3 is a read-only bit. 2. Overflow is not detected if clear & start mode is selected by match between TM4 and CR4. Caution Be sure to stop timer operation (TCE4 = 0) before setting TMC4. Remarks 1. The initial value of TO4 is the timer output value of TO4 when timer output is enabled (TMO4 = 1) and the count operation is stopped (TCE4 = 0). 2. fX: Main system clock oscillation frequency 3. Figures in parentheses are for operation with fX = 10 MHz.
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(2) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the TO4/P70 pin for timer output, set PM70 and the output latch of P70 to 0. PM7 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to FFH. Figure 7-3. Port Mode Register 7 (PM7) Format
Address: FF27H After reset: FFH Symbol PM7 7 1 6 1 R/W 5 1 4 1 3 PM73 2 PM72 1 PM71 0 PM70
PM7n 0 1
PM7n pin I/O mode selection (n = 0 to 3) Output mode (output buffer ON) Input mode (output buffer OFF)
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7.5 16-Bit Timer/Event Counter 4 Operations
7.5.1 Interval timer operation 16-bit timer/event counter 4 operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 16-bit timer compare register 4 (CR4). When the count value of 16-bit timer counter 4 (TM4) matches the value set to CR4, counting continues with the TM4 value cleared to 0 and an interrupt request signal (INTTM4) is generated. The count clock of TM4 can be selected with bits 0 and 1 (TCL40 and TCL41) of 16-bit timer mode control register 4 (TMC4). [Setting] <1> Set the registers. * TCL41, TCL40: Set count clock. * CR4: * TMM4: * TMO4: Compare value Clear & start mode by match of TM4 and CR4 (TMM4 = 0) Timer output is set to disable (TMO4 = 0).
<2> After TCE4 = 1 is set, count operation starts. <3> If the values of TM4 and CR4 match, INTTM4 is generated (TM4 is cleared to 0000H). <4> INTTM4 generates repeatedly at the same interval. Set TCE4 to 0 to stop count operation. Cautions 1. INTTM4 is fixed to high level after count start when CR4 = 0000H is set. Therefore, only the first rising edge is valid for INTTM4. 2. The rising edge of the first clock immediately after setting TCE4 to 1 is not counted. Count operation is started from the rising edge of the second clock.
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Figure 7-4. Interval Timer Operation Timings (1/2) (a) Basic operation
t Count clock TM4 count value 0000H 0001H Start count CR4 TCE4 INTTM4 Interrupt request acknowledged TO4 Interval time Interval time Interval time Interrupt request acknowledged N N 0000H 0001H N 0000H 0001H N
Clear N
Clear N N
Remark Interval time = (N + 1) x t N = 0000H to FFFFH
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Figure 7-4. Interval Timer Operation Timings (2/2) (b) When CR4 = 0000H
t Count clock TM4 0000H CR4 TCE4 INTTM4 TO4 0000H 0000H 0000H 0000H
Interval time
(c) When CR4 = FFFFH
t Count clock TM4 CR4 TCE4 INTTM4 Interrupt request acknowledged TO4 Interval time Interrupt request acknowledged 0001H FFFFH FFFEH FFFFH 0000H FFFFH FFFEH FFFFH 0000H FFFFH
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7.5.2 Square-wave output operation A square wave with any selected frequency is output at intervals of the value preset to 16-bit timer compare register 4 (CR4). TO4 pin output status is reversed at intervals of the count value preset to CR4 by setting bit 7 (TCE4) of 16-bit timer mode control register 4 (TMC4) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). [Setting] <1> Set each register. * Set port latch and port mode register to 0. * TCL41, 40: Select count clock * CR4: * TMM4: * LVS4: Compare value Clear & start mode by match of TM4 and CR4 (TMM4 = 0) Set initial status of timer output (TO4)
Initial output = 1 LVS4 = 1 Initial output = 0 LVS4 = 0 * TMO4: Timer output is set to enable (TMO4 = 1) <2> After TCE4 = 1 is set, count operation starts. <3> Timer output F/F is reversed by match of TM4 and CR4. After INTTM4 is generated, TM4 is cleared to 00H. <4> Timer output F/F is reversed at the same interval and square wave is output from TO4. Caution The rising edge of the first clock immediately after setting TCE4 to 1 is not counted. Count operation is started from the rising edge of the second clock. Figure 7-5. Square-Wave Output Operation Timing
Count clock
TM4 count value
0000H TCE4 = 1
0001H
N-1
N
0000H 0001H 0002H
N-1
N
0000H
CR4
N
TO4
Note
Note TO4 output initial value can be set by bit 4 (LVS4) of 16-bit timer mode control register 4 (TMC4).
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7.5.3 External event counter operation The external event counter counts the number of external clock pulses to be input to TI4 by 16-bit timer counter 4 (TM4). TM4 is incremented each time the rising edge of TI4 specified with 16-bit timer mode control register 4 (TMC4) is input. When the TM4 counted values match the values of 16-bit timer compare register 4 (CR4), TM4 is cleared to 0 and the interrupt request signal (INTTM4) is generated. Whenever the TM4 counted value matches the value of CR4, INTTM4 is generated. Caution The rising edge of the first clock immediately after setting TCE4 to 1 is not counted. Count operation is started from the rising edge of the second clock. Figure 7-6. External Event Counter Operation Timing
TI4 TM4 count value CR4 INTTM4 0000H 0001H 0002H 0003H 0004H 0005H N-1 N 0000H 0001H 0002H 0003H N
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7.6 16-Bit Timer/Event Counter 4 Cautions
(1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 4 (TM4) is started asynchronously to the count clock. Figure 7-7. 16-Bit Timer Counter 4 (TM4) Start Timing
Count clock
TM4 count value
0000H
0001H
0002H
0003H
Timer start
(2) 16-bit timer compare register setting Set other than 0000H to 16-bit timer compare register 4 (CR4). This means a 1-pulse count operation cannot be performed when it is used as the event counter. (3) Operation after compare register change during timer count operation If the value after 16-bit timer compare register 4 (CR4) is changed is smaller than that of 16-bit timer counter 4 (TM4), TM4 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR4 change is smaller than that (N) before the change, it is necessary to reset and restart the timer after changing CR4. Figure 7-8. Timings After Change of Compare Register During Timer Count Operation
Count clock
CR4
N
M
TM4 count value
X-1
X
FFFFH
0000H
0001H
0002H
Remark N > X > M (4) Contending operations If the match timing between the write period of 16-bit timer compare register 4 (CR4) and 16-bit timer counter 4 (TM4) conflicts, the match discriminant is not performed normally. Do not write any data to CR4 near the match timing. (5) Timer operation Regardless of the CPU's operation mode, when the timer stops, the input signal to pin TI4 is not acknowledged.
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8.1 Outline of 8-Bit Timer/Event Counters 50, 51, and 52
8-bit timer/event counters 50, 51, and 52 can be used to serve as an interval timer, an external event counter, to output square wave output with any selected frequency, and PWM output.
8.2 8-Bit Timer/Event Counters 50, 51, and 52 Functions
8-bit timer/event counters 50, 51, and 52 have the following functions. * Interval timer * External event counter * Square wave output * PWM output (1) Interval timer These counters generate interrupt requests at the preset time interval. (2) External event counter These counters can measure the number of pulses of an externally input signal. (3) Square wave output These counters can output a square wave with any selected frequency. (4) PWM output These counters can output PWM. Figures 8-1 to 8-3 show 8-bit timer/event counter block diagrams.
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Figure 8-1. 8-Bit Timer/Event Counter 50 Block Diagram
Internal bus
Mask circuit
8-bit timer compare register 50 (CR50) TI50/TO50/P33 fX fX/22 fX/24 fX/26 fX/28 fX/210 Match
Selector
Selector
INTTM50
8-bit timer OVF counter 50 (TM50) Clear
Selector
S Q INV R
TO50/TI50/P33
3 Selector
S R
Invert level
TCL502 TCL501 TCL500 Timer clock select register 50 (TCL50)
TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus
Figure 8-2. 8-Bit Timer/Event Counter 51 Block Diagram
Internal bus
Mask circuit
8-bit timer compare register 51 (CR51)
Selector
INTTM51
TI51/TO51/P34 fX fX/22 fX/24 fX/26 fX/28 fX/210
Match
Selector
8-bit timer OVF counter 51 (TM51)
Selector
S Q INV R
TO51/TI51/P34
Clear 3 Selector S R Invert level
TCL512 TCL511 TCL510 Timer clock select register 51 (TCL51)
TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus
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Figure 8-3. 8-Bit Timer/Event Counter 52 Block Diagram
Internal bus
Mask circuit
8-bit timer compare register 52 (CR52) TI52/P73 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Match
Selector
Selector
INTTM52
8-bit timer counter 52 (TM52)
OVF
Selector
S Q INV R
TO52/P72
Clear 3 Selector S R Invert level
TCL522 TCL521 TCL520 Timer clock select register 52 (TCL52)
TCE52 TMC526 LVS52 LVR52 TMC521 TOE52 8-bit timer mode control register 52 (TMC52) Internal bus
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8.3 8-Bit Timer/Event Counters 50, 51, and 52 Configurations
8-bit timer/event counters 50, 51, and 52 consist of the following hardware. Table 8-1. 8-Bit Timer/Event Counters 50, 51, and 52 Configuration
Item Timer register Register Timer output Control registers Configuration 8-bit timer counter 5n (TM5n) 8-bit timer compare register 5n (CR5n) 3 (TO5n) Timer clock select register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode registers 3, 7 (PM3, PM7)Note
Note See Figure 4-9 P33, P34 Block Diagram, Figure 4-15 P70, P72 Block Diagram, and Figure 4-16 P71, P73 Block Diagram. Remark n = 0 to 2 (1) 8-bit timer counter 5n (TM5n: n = 0 to 2) TM5n is an 8-bit read-only register which counts the count pulses. A counter is incremented in synchronization with the rising edge of a count clock. When count value is read during operation, count clock input is temporary stopped, and then the count value is read. In the following situations, count value is set to 00H. <1> RESET input <2> When TCE5n is cleared <3> When TM5n and CR5n match in clear & start mode if this mode was entered upon match of TM5n and CR5n values. Remark n = 0 to 2 (2) 8-bit timer compare register 5n (CR5n: n = 0 to 2) The value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match (except PWM mode). It is possible to rewrite the value of CR5n within 00H to FFH during count operation. Remark n = 0 to 2
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8.4 Registers to Control 8-Bit Timer/Event Counters 50, 51, and 52
The following three types of registers are used to control 8-bit timer/event counters 50, 51, and 52. * Timer clock select register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) * Port mode registers 3, 7 (PM3, PM7) Remark n = 0 to 2 (1) Timer clock select register 5n (TCL5n: n = 0 to 2) This register sets count clocks of 8-bit timer/event counter 5n and the valid edge of TI5n input. TCL5n is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 8-4. Timer Clock Select Register 50 (TCL50) Format
Address: FF71H Symbol TCL50 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL502 1 TCL501 0 TCL500
TCL502 0 0 0 0 1 1 1 1
TCL501 0 0 1 1 0 0 1 1
TCL500 0 1 0 1 0 1 0 1 TI50 falling edge TI50 rising edge fX (10 MHz) fX/22 (2.5 MHz) fX/24 (625 kHz) fX/26 (156.2 kHz) fX/28 (39.1 kHz) fX/210 (9.77 kHz)
Count clock selection
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand. 2. Be sure to set bits 3 to 7 to 0. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz
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Figure 8-5. Timer Clock Select Register 51 (TCL51) Format
Address: FF74H Symbol TCL51 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL512 1 TCL511 0 TCL510
TCL512 0 0 0 0 1 1 1 1
TCL511 0 0 1 1 0 0 1 1
TCL510 0 1 0 1 0 1 0 1 TI51 falling edge TI51 rising edge fX (10 MHz) fX/22 (2.5 MHz) fX/24 (625 kHz) fX/26 (156.2 kHz) fX/28 (39.1 kHz) fX/210 (9.77 kHz)
Count clock selection
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand. 2. Be sure to set bits 3 to 7 to 0. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz
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Figure 8-6. Timer Clock Select Register 52 (TCL52) Format
Address: FF77H Symbol TCL52 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL522 1 TCL521 0 TCL520
TCL522 0 0 0 0 1 1 1 1
TCL521 0 0 1 1 0 0 1 1
TCL520 0 1 0 1 0 1 0 1 TI52 falling edge TI52 rising edge fX/2 (5 MHz) fX/23 (1.25 MHz) fX/25 (312.5 kHz) fX/27 (78.1 kHz) fX/29 (19.5 kHz) fX/211 (4.88 kHz)
Count clock selection
Cautions 1. When rewriting TCL52 to other data, stop the timer operation beforehand. 2. Be sure to set bits 3 to 7 to 0. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz (2) 8-bit timer mode control register 5n (TMC5n: n = 0 to 2) TMC5n is a register which sets the following five types. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operation mode selection <3> Timer output F/F (flip flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode. <5> Timer output control TMC5n is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 8-7 shows the TMC5n format.
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Figure 8-7. 8-Bit Timer Mode Control Register 5n (TMC5n) Format
Address: FF70H (TMC50) Symbol TMC5n 7 TCE5n FF73H (TMC51) 6 TMC5n6 5 0 FF76H (TMC52) 4 0 After reset: 00H 3 LVS5n 2 LVR5n R/W 1 TMC5n1 0 TOE5n
TCE5n 0 1
TM5n count operation control After clearing to 0, count operation disabled (prescaler disabled) Count operation start
TMC5n6 0 1
TM5n operation mode selection Clear and start mode by matching between TM5n and CR5n PWM (free-running) mode
LVS5n 0 0 1 1
LVR5n 0 1 0 1 No change
Timer output F/F status setting
Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
TMC5n1
In other modes (TMC5n6 = 0) Timer F/F control
In PWM mode (TMC5n6 = 1) Active level selection Active high Active low
0 1
Inversion operation disabled Inversion operation enabled
TOE5n 0 1 Output disabled (port mode) Output enabled
Timer output control
Remarks 1. In PWM mode, PWM output will be inactive because of TCE5n = 0. 2. If LVS5n and LVR5n are read after data is set, 0 is read. 3. n = 0 to 2
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(3) Port mode registers 3 and 7 (PM3, PM7) These registers set ports 3 and 7 input/output in 1-bit units. When using the P33/TO50/TI50, P34/TO51/TI51, and P72/TO52 pins for timer output, set PM33, PM34, PM72 and the output latches of P33, P34, and P72 to 0. PM3 and PM7 are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the values of these registers to FFH. Figure 8-8. Port Mode Registers 3, 7 (PM3, PM7) Format
Address: FF23H Symbol PM3 7 1 After reset: FFH 6 1 5 1 R/W 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30
Address: FF27H Symbol PM7 7 1
After reset: FFH 6 1 5 1
R/W 4 1 3 PM73 2 PM72 1 PM71 0 PM70
PMmn
Pmn pin I/O mode selection (m = 3: n = 0 to 4, m = 7: n = 0 to 3) Output mode (output buffer ON) Input mode (output buffer OFF)
0 1
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8.5 8-Bit Timer/Event Counters 50, 51, and 52 Operations
8.5.1 Interval timer operation The 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock select register 5n (TCL5n). See 8.6 8-Bit Timer/Event Counters 50, 51, and 52 Cautions (2) about the operation when the compare register value is changed during timer count operation. [Setting] <1> Set the registers. * TCL5n: Select count clock. * CR5n: Compare value (TMC5n = 0000xxx0B x = don't care) <2> After TCE5n = 1 is set, count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> INTTM5n generates repeatedly at the same interval. Set TCE5n to 0 to stop count operation. Remark n = 0 to 2 Figure 8-9. Interval Timer Operation Timings (1/3) (a) Basic operation
t Count clock TM5n count value 00H 01H N 00H 01H N 00H 01H N
* TMC5n: Clear and start mode by match of TM5n and CR5n.
Start count CR5n TCE5n INTTM5n N
Clear N
Clear N N
Interrupt request acknowledged TO5n Interval time Interval time
Interrupt request acknowledged
Interval time
Remarks 1. Interval time = (N + 1) x t N = 00H to FFH 2. n = 0 to 2
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Figure 8-9. Interval Timer Operation Timings (2/3) (b) When CR5n = 00H
t Count clock TM5n 00H CR5n TCE5n INTTM5n TO5n 00H 00H 00H 00H
Interval time
(c) When CR5n = FFH
t Count clock TM5n CR5n TCE5n INTTM5n Interrupt request acknowledged TO5n Interval time Interrupt request acknowledged FF 01 FE FF FF 00 FE FF FF 00
Remark n = 0 to 2
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Figure 8-9. Interval Timer Operation Timings (3/3) (d) Operated by CR5n transition (M < N)
Count clock TM5n N 00H CR5n TCE5n H INTTM5n TO5n CR5n transition TM5n overflows since M < N N M N FFH 00H M M 00H
(e) Operated by CR5n transition (M > N)
Count clock TM5n CR5n TCE5n H INTTM5n TO5n CR5n transition N-1 N N 00H 01H N M-1 M M 00H 01H
Remark n = 0 to 2
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8.5.2 External event counter operation The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified with timer clock select register 5n (TCL5n) is input. Either the rising or falling edge can be selected. When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Whenever the TM5n count value matches the value of CR5n, INTTM5n is generated. Remark n = 0 to 2 Figure 8-10. External Event Counter Operation Timing (with Rising Edge Specified)
TI5n TM5n count value CR5n INTTM5n 00 01 02 03 04 05 N-1 N N 00 01 02 03
Remark n = 0 to 2
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8.5.3 Square-wave output operation A square wave with any selected frequency is output at intervals of the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is reversed at intervals of the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). [Setting] <1> Set each register. * Set port latch and port mode register to 0. * TCL5n: Select count clock * CR5n: Compare value * TMC5n: Clear and start mode by match of TM5n and CR5n
LVS5n 1 0 LVR5n 0 1 Timer Output F/F Status Setting High-level output Low-level output
Timer output F/F reverse enable Timer output enable TOE5n = 1 <2> After TCE5n = 1 is set, count operation starts. <3> Timer output F/F is reversed by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is cleared to 00H. <4> Timer output F/F is reversed at the same interval and a square wave is output from TO5n. Remark n = 0 to 2 Figure 8-11. Square-Wave Output Operation Timing
Count clock
TMn count value
00H
01H
02H
N-1
N
00H
01H
02H
N-1
N
00H
Count start CR5n N
TO5n
Note
Note TO5n output initial value can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n). Remark n = 0 to 2
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8.5.4 PWM output operation The 8-bit timer/event counter operates as PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty rate pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n, and the active level can be selected with bit 1 (TMC5n1) of TMC5n. The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock select register 5n (TCL5n). Enable/disable for PWM output can be selected with bit 0 (TOE5n) of TMC5n. Caution CR5n can be rewritten only once a cycle in PWM mode. Remark n = 0 to 2 (1) PWM output basic operation [Setting] <1> Set the port latches (P33, P34, and P72) and port mode registers 3, 7 (PM33, PM34, and PM72) to 0. <2> Set the active level width with the 8-bit timer compare register (CR5n). <3> Select the count clock with timer clock select register 5n (TCL5n). <4> Set the active level with bit 1 (TMC5n1) of TMC5n. <5> The count operation starts when bit 7 (TCE5n) of TMC5n is set to 1. Set TCE5n to 0 to stop the count operation. [PWM output operation] <1> PWM output (output from TO5n) outputs an inactive level after the count operation starts until overflow is generated. <2> When overflow is generated, the active level set in <1> of [Setting] is output. The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> After CR5n matches the count value, PWM output outputs the inactive level again until overflow is generated. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE5n = 0, PWM output changes to the inactive level. Remark n = 0 to 2
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Figure 8-12. PWM Output Operation Timing (a) Basic operation (active level = H)
Count clock TM5n CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level 00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H
(b) CR5n = 0
Count clock TM5n CR5n TCE5n INTTM5n TO5n L Inactive level Inactive level 00H 01H 00H FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H
(c) CR5n = FFH
TM5n CR5n TCE5n INTTM5n TO5n
00H 01H FFH
FFH 00H 01H 02H
N N+1 N+2
FFH 00H 01H 02H
M 00H
Inactive level
Active level
Active level Inactive level
Inactive level
Remark n = 0 to 2
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(2) Operated by CR5n transition Figure 8-13. Timing of Operation by CR5n Transition (a) CR5n value transits from N to M before overflow of TM5n
Count clock TM5n CR5n TCE5n INTTM5n TO5n CR5n transition (N M) H N N+1 N+2 N FFH 00H 01H 02H M M M+1 M+2 FFH 00H 01H 02H M M+1 M+2
(b) CR5n value transits from N to M after overflow of TM5n
Count clock TM5n CR5n TCE5n INTTM5n TO5n CR5n transition (N M) H N N+1 N+2 N FFH 00H 01H 02H 03H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2
(c) CR5n value transits from N to M between two clocks (00H and 01H) after overflow of TM5n
Count clock TM5n CR5n TCE5n INTTM5n TO5n CR5n transition (N M) H N N+1 N+2 N FFH 00H 01H 02H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2
Remark n = 0 to 2
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8.6 8-Bit Timer/Event Counters 50, 51, and 52 Cautions
(1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counter 5n (TM5n) is started asynchronously to the count pulse. Figure 8-14. 8-Bit Timer Counter Start Timing
Count pulse TM5n count value 00H Timer start 01H 02H 03H 04H
Remark n = 0 to 2 (2) Operation after compare register transition during timer count operation If the value after 8-bit timer compare register 5n (CR5n) is changed is smaller than the value of 8-bit timer counter 5n (TM5n), TM5n continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR5n change is smaller than value (N) before the change, it is necessary to restart the timer after changing CR5n. Figure 8-15. Timing After Compare Register Change During Timer Count Operation
Count pulse CR5n TM5n count value N X-1 X FFH M 00H 01H 02H
Caution Except when the TI5n input is selected, always set TCE5n = 0 before setting the stop state. Remarks 1. N > X > M 2. n = 0 to 2 (3) TM5n (n = 0 to 2) reading during timer operation When reading TM5n during operation, select a count clock with a high/low level waveform longer than two cycles of the CPU clock because the count clock stops temporarily. For example, in the case where the CPU clock (fCPU) is fX, when the selected count clock is fX/4 or below, it can be read. Remark n = 0 to 2
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WATCH TIMER
9.1 Outline of Watch Timer
The watch timer generates interrupt requests (INTWTN0 and INTWTNI0) at the preset time interval.
9.2 Watch Timer Functions
The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 9-1 shows the watch timer block diagram. Figure 9-1. Watch Timer Block Diagram
Clear
Selector
fX/28 fXT
fW
Selector
11-bit prescaler fW fW fW fW fW fW fW 24 25 26 27 28 210 211 fW 29
5-bit counter fW fW fW fW 24 25 213 214
Clear
Selector
INTWTN0
Selector
INTWTNI0
3
WTNM07 WTNM06 WTNM05 WTNM04 WTNM03 WTNM02 WTNM01 WTNM00 Watch timer operation mode register 0 (WTNM0)
Internal bus
Remark fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency
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(1) Watch timer By using the main system clock or subsystem clock, interrupt requests (INTWTN0) are generated at preset intervals. Table 9-1. Watch Timer Interrupt Request Time
Interrupt Request Time 24/fW 25/fW 213/fW 214/fW When Operated at fX = 10 MHz 409.6 s 819.2 s 0.2 s 0.41 s When Operated at fXT = 32.768 kHz 488 s 977 s 0.25 s 0.5 s
Remark fW: Watch timer clock frequency (fX/28 or fXT) fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency (2) Interval timer By using the main system clock or subsystem clock, interrupt requests (INTWTNI0) are generated at preset intervals. Table 9-2. Interval Timer Interval Time
Interrupt Request Time 24/fW 25/fW 26/fW 27/fW 28/fW 29/fW 210/fW 211/fW When Operated at fX = 10 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.56 ms 13.1 ms 26.2 ms 52.4 ms When Operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.2 ms 62.4 ms
Remark fW: Watch timer clock frequency (fX/28 or fXT) fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency
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9.3 Watch Timer Configuration
The watch timer consists of the following hardware. Table 9-3. Watch Timer Configuration
Item Prescaler Control register 11 bits x 1, 5 bits x 1 Watch timer operation mode register 0 (WTNM0) Configuration
9.4 Register to Control Watch Timer
Watch timer operation mode register 0 (WTNM0) is a register to control the watch timer. * Watch timer operation mode register 0 (WTNM0) This register sets the watch timer enable/disable operation, 11-bit prescaler interval time, and 5-bit counter operation control. WTNM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
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Figure 9-2. Watch Timer Operation Mode Register 0 (WTNM0) Format
Address: FF41H Symbol WTNM0 7 WTNM07 WTNM07 0 1 WTNM06 fX/28 (39.1 kHz) After reset: 00H 6 WTNM06 R/W 5 WTNM05 4 WTNM04 3 WTNM03 2 WTNM02 1 WTNM01 0 WTNM00
Watch timer count clock selection
fXT (32.768 kHz) WTNM05 WTNM04 11-bit prescaler interval time selection WTNM07 = 0 WTNM07 = 1 24/fXT 25/fXT 26/fXT 27/fXT 28/fXT 29/fXT (488 s) (977 s) (1.95 ms) (3.91 ms) (7.81 ms) (15.6 ms) (31.2 ms) (62.4 ms)
0 0 0 0 1 1 1 1 WTNM03
0 0 1 1 0 0 1 1 WTNM02
0 1 0 1 0 1 0 1
24/fW 25/fW 26/fW 27/fW 28/fW 29/fW 210/fW 211/fW
212/fX 213/fX 214/fX 215/fX 216/fX 217/fX 218/fX 219/fX
(409.6 s) (819.2 s) (1.64 ms) (3.28 ms) (6.56 ms) (13.1 ms) (26.2 ms) (52.4 ms)
210/fXT 211/fXT
Selection of interrupt request time of the watch timer WTNM07 = 0 WTNM07 = 1 214/fXT 213/fXT 25/fXT 26/fXT (0.5 s) (0.25 s)
0 0 1 1 WTNM01 0 1 WTNM00 0 1
0 1 0 1
214/fW 213/fW 25/fW 24/fW
222/fX 221/fX 213/fX 212/fX
(0.41 s) (0.2 s) (819.2 s) (409.6 s)
(977 s) (488 s)
5-bit counter operation control Clear after operation stop Start Watch timer operation enable Operation stop (clear both 11-bit prescaler and 5-bit counter) Operation enable
Caution Do not change the count clock, interval time, and interrupt request time (by using bits 2 to 7 (WTNM02 to WTNM07) of WTNM0) while the watch timer is operating. Remarks 1. fW: Watch timer clock frequency (fX/28 or fXT) fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 10 MHz, fXT = 32.768 kHz.
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9.5 Watch Timer Operations
9.5.1 Watch timer operation By using the main system clock or subsystem clock, it operates as a watch timer with preset timing intervals. Bits 2, 3, and 7 (WTNM02, WTNM03, and WTNM07) of watch timer operation mode register 0 (WTNM0) enable the selection of the timing for the watch timer. The watch timer generates an interrupt request (INTWTN0) at a fixed time interval. If bit 0 (WTNM00) and bit 1 (WTNM01) of watch timer operation mode register 0 (WTNM0) are set to 1, the count operation starts. If set to 0, the 5-bit counter is cleared and the count operation stops. For simultaneous operation of the interval timer, a zero-second start can be achieved by setting WTNM01 to 0. However, in this case, since the 11-bit prescaler is not cleared, at the first overflow (INTWTN0) after the watch timer's zero-second start, an error up to 211 x 1/fW seconds is generated. 9.5.2 Interval timer operation The watch timer operates as an interval timer which generates interrupt requests (INTWTNI0) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 and 7 (WTNM04 to WTNM06 and WTNM07) of watch timer operation mode register 0 (WTNM0). Figure 9-3. Operation Timing of Watch Timer/Interval Timer
Watch timer 0H Start Count clock Watch timer interrupt INTWTN0 Interrupt time of watch timer Interval timer interrupt INTWTNI0 Interval time (T) nxT T nxT Interrupt time of watch timer Overflow Overflow
Caution If the watch timer and 5-bit counter are enabled by watch timer operation mode register 0 (WTNM0) (by setting bits 0 (WTNM00) and 1 (WTNM01) of WTNM0 to 1), the time from this setting to the occurrence of the first interrupt request (INTWTN0) is not exactly the value set by bits 2 and 3 (WTNM02 and WTNM03) of WTNM0. This is because the 5-bit counter is late by one output cycle of the 11-bit prescaler in starting to count. The second INTWTN0 signal and those that follow are generated exactly at the set time. Remark n: The number of times of interval timer operations
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WATCHDOG TIMER
10.1 Outline of Watchdog Timer
The watchdog timer can also be used to generate a non-maskable interrupt request, maskable interrupt request, or RESET signal at the preset time intervals.
10.2 Watchdog Timer Functions
The watchdog timer has the following functions. * Watchdog timer * Interval timer * Oscillation stabilization time selection Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM). (The watchdog timer and the interval timer cannot be used simultaneously.) Figure 10-1 shows a block diagram of the watchdog timer. Figure 10-1. Watchdog Timer Block Diagram
fX
fX/28
Clock input controller
Divider
Divided clock selector
Output controller
INTWDT RESET
RUN
Division mode selector
3 WDT mode signal
OSTS2 OSTS1 OSTS0 Oscillation stabilization time select register (OSTS)
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Watchdog timer clock select register (WDCS) Internal bus
Watchdog timer mode register (WDTM)
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(1) Watchdog timer mode A runaway is detected. Upon detection of the runaway, a non-maskable interrupt request or RESET can be generated. Table 10-1. Watchdog Timer Runaway Detection Time
Runaway Detection Time 212 213 214 215 216 217 x 1/fX (410 s) x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms) x 1/fX (13.1 ms)
218 x 1/fX (26.2 ms) 220 x 1/fX (105 ms)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 10-2. Interval Time
Interval Time 212 213 214 215 216 x 1/fX (410 s) x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms)
217 x 1/fX (13.1 ms) 218 x 1/fX (26.2 ms) 220 x 1/fX (105 ms)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz
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10.3 Watchdog Timer Configuration
The watchdog timer consists of the following hardware. Table 10-3. Watchdog Timer Configuration
Item Control registers Configuration Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Oscillation stabilization time select register (OSTS)
10.4 Registers to Control Watchdog Timer
The following three types of registers are used to control the watchdog timer. * Watchdog timer clock select register (WDCS) * Watchdog timer mode register (WDTM) * Oscillation stabilization time select register (OSTS)
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(1) Watchdog timer clock select register (WDCS) This register sets overflow time of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 10-2. Watchdog Timer Clock Select Register (WDCS) Format
Address: FF42H Symbol WDCS 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 WDCS2 1 WDCS1 0 WDCS0
WDCS2 0 0 0 0 1 1 1 1
WDCS1 0 0 1 1 0 0 1 1
WDCS0 0 1 0 1 0 1 0 1 212/fX 213/fX 214/fX 215/fX 216/fX
Overflow time of watchdog timer/interval timer (410 s) (819 s) (1.64 ms) (3.28 ms) (6.55 ms)
217/fX (13.1 ms) 218/fX (26.2 ms) 220/fX (105 ms)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz
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(2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operation mode and enables/disables counting. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 10-3. Watchdog Timer Mode Register (WDTM) Format
Address: FFF9H Symbol WDTM 7 RUN RUN 0 1 Count stop Counter is cleared and counting starts After reset: 00H 6 0 R/W 5 0 4 WDTM4 3 WDTM3 2 0 1 0 0 0
Watchdog timer operation mode selectionNote 1
WDTM4 0
WDTM3 x 0
Watchdog timer operation mode selectionNote 2 Interval timer modeNote 3 (Maskable interrupt request occurs upon generation of an overflow) Watchdog timer mode 1 (Non-maskable interrupt request occurs upon generation of an overflow) Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow)
1
1
1
Notes 1. Once set to 1, RUN cannot be cleared to 0 by software. Thus, once counting starts, it can only be stopped by RESET input. 2. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software. 3. The watchdog timer starts operations as the interval timer when 1 is set to RUN. Caution When 1 is set to RUN so that the watchdog timer is cleared, the actual overflow time is up to 28/fX seconds shorter than the time set by watchdog timer clock select register (WDCS). Remark x: don't care
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(3) Oscillation stabilization time select register (OSTS) A register to select oscillation stabilization time from reset time or STOP mode released time to the time when oscillation is stabilized. OSTS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 04H. Thus, when releasing the STOP mode by RESET input, the time required to release is 217/fX. Figure 10-4. Oscillation Stabilization Time Select Register (OSTS) Format
Address: FFFAH Symbol OSTS 7 0 After reset: 04H 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0
OSTS2 0 0 0 0 1
OSTS1 0 0 1 1 0
OSTS0 0 1 0 1 0 212/fX 214/fX 215/fX 216/fX 217/fX
Selection of oscillation stabilization time (410 s) (1.64 ms) (3.28 ms) (6.55 ms) (13.1 ms)
Other than the above
Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz
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10.5 Watchdog Timer Operations
10.5.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The runaway detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS). Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the set runaway time interval. The watchdog timer can be cleared and counting is started by setting RUN to 1. If RUN is not set to 1 and the runaway detection time is exceeded, system reset or a non-maskable interrupt request is generated according to WDTM bit 3 (WDTM3) value. The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction. Cautions 1. The actual runaway detection time may be shorter than the set time by a maximum of 28/fX seconds. 2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is stopped. Table 10-4. Watchdog Timer Runaway Detection Time
Runaway Detection Time 212 x 1/fX (410 s) 213 x 1/fX (819 s) 214 x 1/fX (1.64 ms) 215 x 1/fX (3.28 ms) 216 x 1/fX (6.55 ms) 217 x 1/fX (13.1 ms) 218 x 1/fX (26.2 ms) 220 x 1/fX (105 ms)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz.
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10.5.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. The interval time of interval timer is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS). When 1 is set to bit 7 (RUN) of WDTM, the watchdog timer operates as the interval timer. When the watchdog timer operated as the interval timer, the interrupt mask flag (WDTMK) and priority specify flag (WDTPR) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupts, INTWDT has the highest priority at default. The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (this selects the watchdog timer mode), the interval timer mode is not set unless RESET input is applied. 2. The interval time just after setting by WDTM may be shorter than the set time by a maximum of 28/fX seconds. 3. When the subsystem clock is selected for CPU clock, watchdog timer count operation is stopped. Table 10-5. Interval Timer Interval Time
Interval Time 212 213 214 215 216 217 x 1/fX (410 s) x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms) x 1/fX (13.1 ms)
218 x 1/fX (26.2 ms) 220 x 1/fX (105 ms)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz.
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CLOCK OUTPUT/BUZZER OUTPUT CONTROLLERS
11.1 Outline of Clock Output/Buzzer Output Controllers
The clock output circuit supplies other devices with the divided main system clock and the subsystem clock, and buzzer output supplies the buzzer frequency with the divided main system clock.
11.2 Clock Output/Buzzer Output Controller Functions
The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output select register (CKS) is output. In addition, the buzzer output is intended for square wave output of the buzzer frequency selected with CKS. Figure 11-1 shows the block diagram of clock output/buzzer output controllers. Figure 11-1. Clock Output/Buzzer Output Controller Block Diagram
fX
Prescaler 8 4 fX/2
10
Selector
BUZ/PCL/INTP5/P05
to fX/2
13
BCS0, BCS1 BZOE fX to fX/27
Selector
Clock controller
PCL/BUZ/INTP5/P05
fXT
CLOE
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output select register (CKS) Internal bus
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11.3 Clock Output/Buzzer Output Controller Configuration
The clock output/buzzer output controllers consist of the following hardware. Table 11-1. Clock Output/Buzzer Output Controllers Configuration
Item Control registers Configuration Clock output select register (CKS) Port mode register 0 (PM0)Note
Note See Figure 4-3 P05 Block Diagram.
11.4 Registers to Control Clock Output/Buzzer Output Controllers
The following two types of registers are used to control the clock output/buzzer output controllers. * Clock output select register (CKS) * Port mode register 0 (PM0) (1) Clock output select register (CKS) This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
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Figure 11-2. Clock Output Select Register (CKS) Format
Address: FF40H After reset: 00H R/W Symbol CKS 7 BZOE 6 BCS1 5 BCS0 4 CLOE 3 CCS3 2 CCS2 1 CCS1 0 CCS0
BZOE 0 1
BUZ output enable/disable specification Stop clock divider operation. BUZ fixed to low level. Enable clock divider operation. BUZ output enabled.
BCS1 0 0 1 1
BCS0 0 1 0 1 fX/210 fX/211 fX/212 fX/213 (9.77 kHz) (4.88 kHz) (2.44 kHz) (1.22 kHz)
BUZ output clock selection
CLOE 0 1
PCL output enable/disable setting Stop clock divider operation. PCL fixed to low level Enable clock divider operation. PCL output enabled.
CCS3 0 0 0 0 0 0 0 0 1
CCS2 0 0 0 0 1 1 1 1 0
CCS1 0 0 1 1 0 0 1 1 0
CCS0 0 1 0 1 0 1 0 1 0
PCL output clock selection fX (10 MHz) fX/2 (5 MHz) fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (312.5 kHz) fX/26 (156.3 kHz) fX/27 (78.1 kHz) fXT (32.768 kHz) Setting prohibited
Other than above
Remarks 1. fX:
Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency 3. Figures in parentheses are for operation with fX = 10 MHz, fXT = 32.768 kHz.
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(2) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the PCL/BUZ/INTP5/P05 pin for clock output or for buzzer output, set PM05 and the output latch of P05 to 0. PM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to FFH. Figure 11-3. Port Mode Register 0 (PM0) Format
Address: FF20H Symbol PM0 7 1 After reset: FFH 6 1 5 PM05 R/W 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00
PM0n 0 1
P0n pin I/O mode selection (n = 0 to 5) Output mode (output buffer ON) Input mode (output buffer OFF)
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11.5 Clock Output/Buzzer Output Controller Operations
11.5.1 Operation as clock output The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output select register (CKS) (clock pulse output in disabled status). <2> Set bit 4 (CLOE) of CKS to 1, and enable clock output. Remark The clock output controller is designed not to output pulses with a small width during output enable/ disable switching of the clock output. As shown in Figure 11-4, be sure to start output from the low period of the clock (marked with * in the figure). When stopping output, do so after securing high level of the clock. Figure 11-4. Remote Control Output Application Example
CLOE * Clock output *
11.5.2 Operation as buzzer output The buzzer frequency is output as the following procedure. <1> Select the buzzer output frequency with bits 5 and 6 (BCS0, BCS1) of the clock output select register (CKS) (buzzer output in disabled status). <2> Set bit 7 (BZOE) of CKS to 1 to enable buzzer output.
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12.1 A/D Converter Functions
The A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. It can control up to 10 analog input channels (ANI0 to ANI9). (1) Hardware start Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can be specified). (2) Software start Conversion is started by setting A/D converter mode register 0 (ADM0). Select one channel for analog input from ANI0 to ANI9 to start A/D conversion. In the case of hardware start, the A/D converter stops when A/D conversion is completed, and an interrupt request (INTAD0) is generated. In the case of software start, A/D conversion is repeated. Each time an A/D conversion operation ends, an interrupt request (INTAD0) is generated. Figure 12-1. A/D Converter Block Diagram
Series resistor string ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 ANI8 ANI9 Sample & hold circuit VDD1
Selector
Successive approximation register (SAR)
Tap selector
Voltage comparator
AVREF0
AVSS0
ADTRG/INTP3/P03
Edge detector
Controller
INTAD0 INTP3
4
Edge detector Note Trigger enable
A/D conversion result register 0 (ADCR0)
ADS03 ADS02 ADS01 ADS00 ADCS0 TRG0 FR02 FR01 FR00 EGA01 EGA00 ADCE0 Analog input channel specification register 0 (ADS0) Internal bus A/D converter mode register 0 (ADM0)
Note The valid edge is specified by bit 3 of the EGP and EGN registers (see Figure 18-5 External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Format).
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12.2 A/D Converter Configuration
The A/D converter consists of the following hardware. Table 12-1. A/D Converter Configuration
Item Analog input Registers Configuration 10 channels (ANI0 to ANI9) Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) A/D converter mode register 0 (ADM0) Analog input channel specification register 0 (ADS0) External interrupt rising edge enable register (EGP) External interrupt falling edge enable register (EGN)
Control registers
(1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to A/D conversion result register 0 (ADCR0). (2) A/D conversion result register 0 (ADCR0) This is a 16-bit register which stores the A/D conversion results. The lower 6 bits are fixed to 0. Each time A/ D conversion ends, the conversion result is loaded from the successive approximation register. ADCR0 is read by a 16-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Symbol ADCR0
FF0FH 0
FF0EH 0 0 0 0 0
Address FF0EH, FF0FH
After reset 0000H
R/W R
Caution When writing is performed to A/D converter mode register 0 (ADM0) and analog input channel specification register 0 (ADS0), the contents of ADCR0 may become undefined. Read the conversion result following conversion completion before writing to ADM0, ADS0. Using a timing other than the above may cause an incorrect conversion result to be read. (3) Sample & hold circuit The sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage. (5) Series resistor string The series resistor string is connected between AVREF0 and AVSS0, and generates a voltage to be compared to the analog input.
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(6) ANI0 to ANI9 pins These ten analog input pins are used to input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI7 can be used as input ports except for the pins specified as analog input by analog input channel specification register 0 (ADS0). Cautions 1. Use the ANI0 to ANI9 input voltages within the specification range. If a voltage higher than AVREF0 or lower than AVSS0 is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. 2. Analog input (ANI0 to ANI7) pins are alternate function pins that can also be used as input port (P10 to P17) pins. When A/D conversion is performed by selecting any one of ANI0 through ANI7, do not execute any input instruction to port 1 during conversion. It may cause a lower conversion resolution. When a digital pulse is applied to a pin adjacent to the pin in the process of A/D conversion, A/D conversion values may not be obtained as expected due to coupling noise. Thus, do not apply any pulse to a pin adjacent to the pin in the process of A/D conversion. (7) AVREF0 pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI9 into digital signals according to the voltage applied between AVREF0 and AVSS0. Caution A series resistor string is connected between the AVREF0 and AVSS0 pins. Therefore, when output impedance of the reference voltage is too high, it seems as if the AVREF0 pin and the series resistor string are connected in series. This may cause a greater reference voltage error. (8) AVSS0 pin This is the GND potential pin of the A/D converter. Always keep it at the same potential as the VSS0 pin when not using the A/D converter. (9) VDD1 pin This is the positive power supply pin, except for the port block.
12.3 Registers to Control A/D Converter
The following four types of registers are used to control the A/D converter. * A/D converter mode register 0 (ADM0) * Analog input channel specification register 0 (ADS0) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) (1) A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, conversion start/stop, and external trigger. ADM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
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Figure 12-2. A/D Converter Mode Register 0 (ADM0) Format
Address: FF80H After reset: 00H R/W Symbol ADM0 7 ADCS0 6 TRG0 5 FR02 4 FR01 3 FR00 2 EGA01 1 EGA00 0 ADCE0
ADCS0 0 1 Stop conversion operation.
A/D conversion operation control
Enable conversion operation.
TRG0 0 1 Software start Hardware start
Software start/hardware start selection
FR02 0 0 0 1 1 1
FR01 0 0 1 0 0 1 Other than above
FR00 0 1 0 0 1 0
Conversion time selectionNote 1 144/fX (14.4 s) 120/fX (Setting prohibitedNote 2) 96/fX (Setting prohibitedNote 2) 576/fX (57.6 s) 480/fX (48.0 s) 384/fX (38.4 s) Setting prohibited
EGA01 0 0 1 1
EGA00 0 1 0 1
External trigger signal, edge specification No edge detection Falling edge detection Rising edge detection Both falling and rising edge detection Control of voltage booster for A/D converter circuitNote 3
ADCE0 0 1
Stops operation. Enables operation.
Notes 1. Set so that the A/D conversion time is 14 s or more. 2. Setting prohibited because A/D conversion time is less than 14 s. 3. Before executing A/D conversion (ADCS0 = 1), be sure to start the voltage booster (ADCE0 = 1). Cautions 1. When rewriting FR00 to FR02 to other than the same data, stop A/D conversion operations once before performing it. 2. Make sure by using software that a wait time of 14 s (MIN.) elapses between when ADCE0 is set and when ADCS0 is set. 3. Before clearing ADCE0, clear ADCS0. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz.
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(2) Analog input channel specification register 0 (ADS0) This register specifies the analog voltage input port for A/D conversion. ADS0 is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 12-3. Analog Input Channel Specification Register 0 (ADS0) Format
Address: FF81H After reset: 00H R/W Symbol ADS0 7 0 6 0 5 0 4 0 3 ADS03 2 ADS02 1 ADS01 0 ADS00
ADS03 0 0 0 0 0 0 0 0 1 1
ADS02 0 0 0 0 1 1 1 1 0 0
ADS01 0 0 1 1 0 0 1 1 0 0
ADS00 0 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9
Analog input channel specification
Other than above
Setting prohibited
(3) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP5. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the values of these registers to 00H. Figure 12-4. External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Format
Address: FF48H After reset: 00H R/W Symbol EGP 7 0 6 0 5 EGP5 4 EGP4 3 EGP3 2 EGP2 1 EGP1 0 EGP0
Address: FF49H After reset: 00H R/W Symbol EGN 7 0 6 0 5 EGN5 4 EGN4 3 EGN3 2 EGN2 1 EGN1 0 EGN0
EGPn 0 0 1 1
EGNn 0 1 0 1
INTPn pin valid edge selection (n = 0 to 5) Interrupt disabled Falling edge Rising edge Both rising and falling edges
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12.4 A/D Converter Operation
12.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using analog input channel specification register 0 (ADS0). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation is ended. <4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF0 by the tap selector. <5> The voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF0, the MSB of SAR remains set. If the analog input is smaller than (1/2) AVREF0, the MSB is reset. <6> Next, bit 8 of SAR is automatically set, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF0 * Bit 9 = 0: (1/4) AVREF0 The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <7> Comparison is continued in this way up to bit 0 of SAR. <8> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to and latched in A/D conversion result register 0 (ADCR0). At the same time, the A/D conversion end interrupt request (INTAD0) can also be generated. Caution The first A/D conversion value just after A/D conversion operations start may not fall within the rating.
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Figure 12-5. Basic Operation of A/D Converter
Conversion time Sampling time
A/D converter operation
Sampling
A/D conversion
SAR Undefined
Conversion result
ADCR0
Conversion result
INTAD0
A/D conversion operations are performed continuously until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If a write operation is performed to the ADM0 or the analog input channel specification register 0 (ADS0) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS0 bit is set (1), conversion starts again from the beginning. RESET input sets A/D conversion result register 0 (ADCR0) to 00H.
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12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI9) and the A/D conversion result (stored in A/D conversion result register 0 (ADCR0)) is shown by the following expression. VIN AVREF0
ADCR0 = INT ( or
x 1,024 + 0.5)
(ADCR0 - 0.5) x
AVREF0 1,024
VIN < (ADCR0 + 0.5) x
AVREF0 1,024
where, INT( ): VIN:
Function which returns integer part of value in parentheses Analog input voltage
AVREF0: AVREF0 pin voltage ADCR0: A/D conversion result register 0 (ADCR0) value Figure 12-6 shows the relationship between the analog input voltage and the A/D conversion result. Figure 12-6. Relationship Between Analog Input Voltage and A/D Conversion Result
1,023
1,022
1,021 A/D conversion result (ADCR0) 3
2
1
0 1 1 3 2 5 3 2,048 1,024 2,048 1,024 2,048 1,024 2,043 1,022 2,045 1,023 2,047 1 2,048 1,024 2,048 1,024 2,048
Input voltage/AVREF0
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12.4.3 A/D converter operation mode Select one analog input channel from among ANI0 to ANI9 using analog input channel specification register 0 (ADS0) to start A/D conversion. A/D conversion can be started in either of the following two ways. * Hardware start: Conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges specified). * Software start: Conversion is started by specifying A/D converter mode register 0 (ADM0).
The A/D conversion result is stored in A/D conversion result register 0 (ADCR0), and the interrupt request signal (INTAD0) is simultaneously generated. (1) A/D conversion by hardware start When bit 6 (TRG0) and bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) are set to 1 after bit 0 (ADCE0) is set to 1, the A/D conversion standby state is set. When the external trigger signal (ADTRG) is input, A/D conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ADS0) starts. Upon the end of the A/D conversion, the conversion result is stored in A/D conversion result register 0 (ADCR0), and the interrupt request signal (INTAD0) is generated. After one A/D conversion operation is started and ended, the next conversion operation is not started until a new external trigger signal is input. If ADS0 is rewritten during A/D conversion operation, the converter suspends A/D conversion and waits for a new external trigger signal to be input. When the external trigger input signal is reinput, A/D conversion is carried out from the beginning. If ADS0 is rewritten during A/D conversion waiting, A/D conversion starts when the following external trigger input signal is input. If data with ADCS0 set to 0 is written to ADM0 during A/D conversion, the A/D conversion operation stops immediately. Caution When P03/INTP3/ADTRG is used as the external trigger input (ADTRG), specify the valid edge by bits 1, 2 (EGA00, EGA01) of A/D converter mode register 0 (ADM0) and set the interrupt mask flag (PMK3) to 1.
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Figure 12-7. A/D Conversion by Hardware Start (When Falling Edge Is Specified)
ADTRG ADM0 set ADCE0 = 1, ADCS0 = 1, TRG0 = 1
Standby state
ADS0 rewrite
A/D conversion
Standby state
ANIn
ANIn
ANIn
Standby state
ANIm
ANIm
ANIm
ADCR0
ANIn
ANIn
ANIn
ANIm
ANIm
INTAD0
Remarks 1. n = 0, 1, ......, 9 2. m = 0, 1, ......, 9
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(2) A/D conversion by software start When bit 6 (TRG0) and bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) are set to 0 and 1 after bit 0 (ADCE0) is set to 1, respectively, A/D conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ADS0) starts. Upon the end of the A/D conversion, the conversion result is stored in A/D conversion result register 0 (ADCR0), and the interrupt request signal (INTAD0) is generated. After one A/D conversion operation is started and ended, the next conversion operation is immediately started. A/D conversion operations are repeated until new data is written to ADS0. If ADS0 is rewritten during A/D conversion, the converter suspends A/D conversion operation and A/D conversion of the new selected analog input channel starts. If data with ADCS0 set to 0 is written to ADM0 during A/D conversion, the A/D conversion operation stops immediately. Figure 12-8. A/D Conversion by Software Start
ADM0 set ADCE0 = 1, ADCS0 = 1, TRG0 = 0
ADS0 rewrite
ADCS0 = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion suspended; Conversion results are not stored
Stop
ADCR0
ANIn
ANIn
ANIm
INTAD0
Remarks 1. n = 0, 1, ......, 9 2. m = 0, 1, ......, 9
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12.5 How to Read the A/D Converter Characteristics Table
Here we will explain the special terms unique to A/D converters. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per 1 bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). When the resolution is 10 bits, 1LSB = 1/210 = 1/1,024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero scale error, full scale error, integral linearity error, differential linearity error and errors which are combinations of these express overall error. Note that, quantization error is not included in overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero scale error, full scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 12-9. Overall Error Figure 12-10. Quantization Error
1......1
1......1
Ideal line
Digital output Digital output
Overall error
1/2LSB
Quantization error 1/2LSB
0......0 0 Analog input AVREF0
0......0 0 Analog input AVREF0
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(4) Zero scale error This shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0......000 to 0......001. If the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. (5) Full scale error This shows the difference between the actual measured value of the analog input voltage and the theoretical value (full scale -3/2 LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measured value and the ideal straight line when the zero scale error and full scale error are 0. (7) Differential linearity error The ideal width to output a certain code is 1LSB. The following shows the difference between the actual measurement values and ideal values of the width when outputting a certain code. Figure 12-11. Zero Scale Error Figure 12-12. Full Scale Error
111
Digital output (lower 3 bits)
Digital output (lower 3 bits)
Full scale error 111 110 101 000
Ideal line 011
010 001 000 0 1 2 3 AVREF0 Analog input (LSB)
Ideal line
Zero scale error
0
AVREF0-3 AVREF0-2 AVREF0-1 AVREF0 Analog input (LSB)
Figure 12-13. Integral Linearity Error
Figure 12-14. Differential Linearity Error
1......1 Ideal line
Digital output
1......1 Ideal width of 1LSB
Digital output
0......0 0
Integral linearity error AVREF0 Analog input
Differential linearity error 0......0 0 Analog input AVREF0
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(8) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. Sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample and hold circuit.
Sampling time
Conversion time
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12.6 A/D Converter Cautions
(1) Current consumption in standby mode The A/D converter stops operating in the standby mode. At this time, the current consumption can be reduced by stopping the conversion operation (by setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) to 0). Figure 12-15 shows how to reduce current consumption in the standby mode. Figure 12-15. Example of Method of Reducing Current Consumption in Standby Mode
AVREF0
P-ch
ADCS0
Series resistor string AVSS0
(2) Input range of ANI0 to ANI9 The input voltages of ANI0 to ANI9 should be within the specification range. In particular, if a voltage higher than AVREF0 or lower than AVSS0 is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) Contending operations <1> Contention between A/D conversion result register 0 (ADCR0) write and ADCR0 read by instruction upon the end of conversion ADCR0 read is given priority. After the read operation, the new conversion result is written to ADCR0. <2> Contention between ADCR0 write and external trigger signal input upon the end of conversion The external trigger signal is not accepted during A/D conversion. Therefore, the external trigger signal is not accepted during ADCR0 write. <3> Contention between ADCR0 write and A/D converter mode register 0 (ADM0) write or analog input channel specification register 0 (ADS0) write upon the end of conversion ADM0 or ADS0 write is given priority. ADCR0 write is not performed, nor is the conversion end interrupt request signal (INTAD0) generated.
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(4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF0 and ANI0 to ANI9 pins. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 12-16 to reduce noise. Figure 12-16. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than AVREF0 or equal to or lower than AVSS0 may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF0
ANI0 to ANI9 C = 100 to 1,000 pF VDD1 AVSS0 VSS0
(5) ANI0 to ANI9 The analog input pins (ANI0 to ANI9) also function as port pins. When A/D conversion is performed with any of pins ANI0 to ANI9 selected, do not execute an input instruction to port 1 while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to other analog input pins during A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to other analog input pins during A/D conversion. (6) AVREF0 pin input impedance A series resistor string is connected between the AVREF0 pin and the AVSS0 pin. Therefore, when the output impedance of the reference voltage is too high, it seems as if the AVREF0 pin and the series resistor string are connected in series. This may cause a greater reference voltage error.
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(7) Interrupt request flag (ADIF0) The interrupt request flag (ADIF0) is not cleared even if analog input channel specification register 0 (ADS0) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS0 rewrite. Caution is therefore required since, at this time, when ADIF0 is read immediately just after the ADS0 rewrite, ADIF0 is set despite the fact that the A/D conversion for the post-change analog input has not ended. When A/D conversion is restarted after it is stopped, clear ADIF0 before restarting. Figure 12-17. A/D Conversion End Interrupt Request Generation Timing
ADM0 rewrite (start of ANIn conversion) ADS0 rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR0
ANIn
ANIn
ANIm
ANIm
INTAD0
Remarks 1. n = 0, 1, ......, 9 2. m = 0, 1, ......, 9 (8) Conversion results just after A/D conversion start If bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is set to 1 without setting bit 0 (ADCE0) to 1, the first A/D conversion value immediately after A/D conversion has been started may not satisfy the rated value. Polling A/D conversion end interrupt request (INTAD0) and take measures such as removing the first conversion results. The same may apply if ADCS0 is set to 1 without the lapse of the wait time of 14 s (MIN.) after ADCE0 has been set to 1. Make sure that the specified wait time elapses. (9) A/D conversion result register 0 (ADCR0) read operation When writing is performed to A/D converter mode register 0 (ADM0) and analog input channel specification register 0 (ADS0), the contents of ADCR0 may become undefined. Read the conversion result following conversion completion before writing to ADM0, ADS0. Using a timing other than the above may cause an incorrect conversion result to be read.
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(10) Timing at which A/D conversion result is undefined The A/D conversion value may be undefined if the timing of completion of A/D conversion and the timing of stopping the A/D conversion conflict with each other. Therefore, read the A/D conversion result during the A/ D conversion operation. To read the conversion result after stopping the A/D conversion operation, be sure to stop the A/D conversion before the next conversion ends. Figures 12-18 and 12-19 show the timing of reading the conversion result. Figure 12-18. Timing of Reading Conversion Result (When Conversion Result Is Undefined)
A/D conversion ends
A/D conversion ends
ADCR0
Normal conversion result
Undefined value
INTAD0
ADCS0
Normal conversion result is read.
A/D conversion is stopped.
Undefined value is read.
Figure 12-19. Timing of Reading Conversion Result (When Conversion Result Is Normal)
A/D conversion ends
ADCR0
Normal conversion result
INTAD0
ADCS0
A/D conversion is stopped.
Normal conversion result is read.
(11) Notes on board design Locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. In particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. characteristics may be affected by the noise of the digital line. Connect AVSS0 and VSS0 at one location on the board where the voltages are stable. Otherwise, the A/D conversion
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(12) VDD1 pin and AVREF0 pin Connect a capacitor to the VDD1 and AVREF0 pins to minimize conversion errors due to noise. If an A/D conversion operation has been stopped and then started, the voltage applied to the VDD1 and AVREF0 pins becomes unstable, causing the accuracy of the A/D conversion to drop. To prevent this, also connect a capacitor to the VDD1 and AVREF0 pins. Figure 12-20 shows an example of connecting capacitors. Figure 12-20. Example of Connecting Capacitor to VDD1 and AVREF0 Pins
VDD1 C1 C3 AVREF0 C2 C4 AVSS0
Remark C1, C2 : 4.7 F to 10 F (reference value) C3, C4 : 0.01 F to 0.1 F (reference value) Connect C3 and C4 as close to the pin as possible. (13) Internal equivalent circuit of ANI0 to ANI9 pins and permissible signal source impedance To complete sampling within the sampling time with sufficient A/D conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. Figure 12-21 shows the internal equivalent circuit of the ANI0 to ANI9 pins. If the impedance of the signal source is high, connect capacitors with a high capacitance to the ANI0 to ANI9 pins. An example of this is shown in Figure 12-22. In this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created. To convert a high-speed analog signal or to convert an analog signal in scan mode, insert a low-impedance buffer.
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Figure 12-21. Internal Equivalent Circuit of ANI0 to ANI9 Pins
R1 ANIn R2
C1
C2
C3
Remark n = 0 to 9 Table 12-2. Resistances and Capacitances of Equivalent Circuit (Reference Values)
VDD1 1.8 V 2.7 V 4.5 V R1 75 k 12 k 4 k R2 30 k 8 k 2.7 k C1 8 pF 8 pF 8 pF C2 4 pF 3 pF 1.4 pF C3 2 pF 2 pF 2 pF
Caution The resistances and capacitances in Table 12-2 are not guaranteed values. Figure 12-22. Example of Connection If Signal Source Impedance Is High

Output impedance of sensor
R0 C0 0.1 F
ANIn
R1
R2
C0
C1
C2
C3
Lowpass filter is created.
Remark n = 0 to 9
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13.1 D/A Converter Functions
The D/A converter converts the digital input into analog values and consists of one channel of voltage output D/ A converters with 8-bit resolution. The conversion method is a R-2R resistor ladder. Set DACE of D/A converter mode register 0 (DAM0) to start the D/A conversion. After D/A conversion, the analog voltage is immediately output.
13.2 D/A Converter Configuration
The D/A converter consists of the following hardware. Table 13-1. D/A Converter Configuration
Item Register Control register Configuration D/A conversion value setting register 0 (DA0) D/A converter mode register 0 (DAM0)
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Figure 13-1. D/A Converter Block Diagram
Internal bus D/A converter mode register 0 (DAM0) DACE D/A conversion value setting register 0 (DA0)
2R AO0/P120 2R AVREF1 R
Selector
2R
R
AVSS1 2R
(1) D/A conversion value setting register 0 (DA0) The DA0 register sets the analog voltage that is output to the AO0 pin. The analog voltage is held until new data are set in DA0. DA0 is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. The analog voltage output by the AO0 pin is determined by the following equation. DA0 256
AO0 output voltage = AVREF1 x
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13.3 Register to Control D/A Converter
(1) D/A converter mode register 0 (DAM0) The D/A converter is controlled by D/A converter mode register 0 (DAM0). This register enables or stops the operation of the D/A converter. DAM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 13-2. D/A Converter Mode Register 0 (DAM0) Format
Address: FF82H After reset: 00H Symbol DAM0 7 0 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 DACE
DACE 0 1 Stop conversion Enable conversion
D/A converter control
Cautions 1. When the D/A converter is used, set the alternate-function port pins to the input mode and disconnect the pull-up resistors. 2. Be sure to set bits 1 to 7 to 0. 3. The output when the D/A converter operation has stopped enters high impedance state.
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13.4 D/A Converter Operation
13.4.1 Basic operations of D/A converter <1> Set the data that corresponds to the analog voltage that is output to AO0/P120 pin of D/A conversion value setting register 0 (DA0). <2> Set bit 0 (DACE) of D/A converter mode register 0 (DAM0) to start D/A conversion. <3> After D/A conversion, the analog voltage is immediately output to AO0/P120 pin. <4> The output analog voltages are held until new data are set in DA0. Caution Set DACE after data are set in DA0. 13.4.2 Operation during standby mode D/A converter operation is retained during standby mode. The values in D/A converter mode register 0 (DAM0) and D/A conversion value setting register 0 (DA0) are retained. Caution Set bit 0 (DACE) of DAM0 to 0 and stop DA0 before entering standby mode in order to reduce current consumption during standby mode. 13.4.3 Operation at reset Reset input initializes DA0, stops D/A conversion operation, and put analog output to high-impedance state. In addition, D/A converter mode register 0 (DAM0) and D/A conversion value setting register 0 (DA0) are cleared to 00H.
13.5 D/A Converter Cautions
(1) Output impedance of the D/A converter Since the output impedance of the D/A converter is high, the current cannot be taken from the AO0 pin. If the input impedance of the load is low, insert a buffer amp between the load and the AO0 pin. In addition, use the shortest possible wire from the buffer amp or load (to increase the output impedance). If the wire is long, surround it with a ground pattern.
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Figure 13-3. Buffer Amp Insertion Example (a) Inverting Amp
PD780338
C
R2 R1 AO0 - +
* The input impedance of the buffer amp is R1.
(b) Voltage follower
PD780338
R AO0 R1 C + -
* The input impedance of the buffer amp is R1. * If there is no R1 and RESET is low, the output is undefined.
(2) Output voltages of the D/A converters Since the output voltages of the D/A converter change in stages, use the signals output from the D/A converter after passing them through a low-pass filter.
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Serial interface UART0/SIO3 can be used in the asynchronous serial interface (UART) mode or 3-wire serial I/ O mode. Caution Do not enable UART0 and SIO3 at the same time.
14.1
Serial Interface UART0 Functions
Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates. The UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). For details, see 14.4.2 Asynchronous serial interface (UART) mode. Figure 14-1 shows a block diagram of the serial interface UART0.
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Figure 14-1. Serial Interface UART0 Block Diagram
Internal bus Asynchronous serial interface mode register 0 (ASIM0) Receive buffer register 0 (RXB0) Asynchronous serial interface status register 0 (ASIS0) PE0 FE0 OVE0 TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0
RxD0/SI3/P20
Receive shift register 0 (RX0)
Transmit shift register 0 (TXS0)
TxD0/SO3/P21
Receive controller (parity check)
INTSER0 INTSR0
Transmit controller (parity addition)
INTST0
Baud rate generatorNote
fX/2 to fX/27
Note For the configuration of the baud rate generator, refer to Figure 14-2. Figure 14-2. Baud Rate Generator Block Diagram
Start bit sampling clock
Selector
TXE0
5-bit counter Transmit clock 1/2 Match
fX/2 to fX/27
Decoder Receive clock 1/2 Match
5-bit counter 3 4
RXE0 Start bit detection
TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 Baud rate generator control register 0 (BRGC0) Internal bus
Remark TXE0: Bit 7 of asynchronous serial interface mode register 0 (ASIM0) RXE0: Bit 6 of asynchronous serial interface mode register 0 (ASIM0)
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14.2
Serial Interface UART0 Configuration
Serial interface UART0 consists of the following hardware. Table 14-1. Serial Interface (UART0) Configuration
Item Registers Configuration Transmit shift register 0 (TXS0) Receive shift register 0 (RX0) Receive buffer register 0 (RXB0) Asynchronous serial interface mode register 0 (ASIM0) Asynchronous serial interface status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0)
Control registers
(1) Transmit shift register 0 (TXS0) This is the register for setting transmit data. Data written to TXS0 is transmitted as serial data. When the data length is set as 7 bits, bits 0 to 6 of the data written to TXS0 are transferred as transmit data. Writing data to TXS0 starts the transmit operation. TXS0 can be written by an 8-bit memory manipulation instruction. It cannot be read. RESET input sets the value of this register to FFH. Caution Do not write to TXS0 during a transmit operation. The same address is assigned to TXS0 and the receive buffer register 0 (RXB0). A read operation reads values from RXB0. (2) Receive shift register 0 (RX0) This register converts serial data input via the RxD0 pin to parallel data. When one byte of data is received at this register, the receive data is transferred to receive buffer register 0 (RXB0). RX0 cannot be manipulated directly by a program. (3) Receive buffer register 0 (RXB0) This register is used to hold receive data. When one byte of data is received, one byte of new receive data is transferred from the receive shift register (RX0). When the data length is set as 7 bits, receive data is transferred to bits 0 to 6 of RXB0. In this case, the MSB of RXB0 always becomes 0. RXB0 can be read by an 8-bit memory manipulation instruction. It cannot be written to. RESET input sets the value of this register to FFH. Caution The same address is assigned to RXB0 and the transmit shift register 0 (TXS0). During a write operation, values are written to TXS0. (4) Transmit controller The transmit controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register 0 (TXS0), based on the values set to asynchronous serial interface mode register 0 (ASIM0).
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(5) Receive controller The receive controller controls receive operations based on the values set to asynchronous serial interface mode register 0 (ASIM0). During a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register 0 (ASIS0) according to the type of error that is detected.
14.3
Registers to Control Serial Interface UART0
Serial interface UART0 is controlled by the following three types of registers. * Asynchronous serial interface mode register 0 (ASIM0) * Asynchronous serial interface status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) (1) Asynchronous serial interface mode register 0 (ASIM0) This is an 8-bit register that controls serial interface UART0's serial transfer operations. ASIM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 14-3 shows the format of ASIM0. Caution In UART mode, set the port mode register (PMXX) as follows. Set the output latch of the port set to output mode (PMXX = 0) to 0. * During receive operation Set P20 (RXD0) to input mode (PM20 = 1) * During transmit operation Set P21 (TXD0) to output mode (PM21 = 0) * During transmit/receive operation Set P20 to input mode, and P21 to output mode
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Figure 14-3. Asynchronous Serial Interface Mode Register 0 (ASIM0) Format
Address: FFA0H After reset: 00H Symbol ASIM0 7 TXE0 6 RXE0 R/W 5 PS01 4 PS00 3 CL0 2 SL0 1 ISRM0 0 0
TXE0 0 0
RXE0 0 1
Operation mode Operation stop UART mode (receive only) UART mode (transmit only) UART mode (transmit and receive)
RxD0/P20 pin function Port function (P20) Serial function (RxD0)
TxD0/P21 pin function Port function (P21)
1
0
Port function (P20)
Serial function (TxD0)
1
1
Serial function (RxD0)
PS01 0 0
PS00 0 1 No parity
Parity bit specification
Zero parity always added during transmission No parity detection during reception (parity errors do not occur) Odd parity Even parity
1 1
0 1
CL0 0 1 7 bits 8 bits
Character length specification
SL0 0 1 1 bit 2 bits
Stop bit length specification for transmit data
ISRM0 0 1
Receive completion interrupt control when error occurs Receive completion interrupt request is issued when an error occurs Receive completion interrupt request is not issued when an error occurs
Caution Do not switch the operation mode until the current serial transmit/receive operation has stopped.
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(2) Asynchronous serial interface status register 0 (ASIS0) When a receive error occurs during UART mode, this register indicates the type of error. ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 14-4. Asynchronous Serial Interface Status Register 0 (ASIS0) Format
Address: FFA1H After reset: 00H Symbol ASIS0 7 0 6 0 R 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0
PE0 0 1 No parity error Parity error (Transmit data parity not matched)
Parity error flag
FE0 0 1 No framing error Framing errorNote 1 (Stop bit not detected)
Framing error flag
OVE0 0 1 No overrun error
Overrun error flag
Overrun errorNote 2 (Next receive operation was completed before data was read from receive buffer register 0 (RXB0))
Notes 1. Even if a stop bit length is set to 2 bits by setting bit 2 (SL0) in asynchronous serial interface mode register 0 (ASIM0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of receive buffer register 0 (RXB0) when an overrun error has occurred. Until the contents of RXB0 are read, further overrun errors will occur when receiving data. (3) Baud rate generator control register 0 (BRGC0) This register sets the serial clock for serial interface. BRGC0 is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 14-5 shows the format of BRGC0.
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Figure 14-5. Baud Rate Generator Control Register 0 (BRGC0) Format
Address: FFA2H After reset: 00H Symbol BRGC0 7 0 6 TPS02 R/W 5 TPS01 4 TPS00 3 MDL03 2 MDL02 1 MDL01 0 MDL00
TPS02 0 0 0 0 1 1 1 1
TPS01 0 0 1 1 0 0 1 1
TPS00 0 1 0 1 0 1 0 1
Source clock selection for 5-bit counter Setting prohibited fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27
n -- 1 2 3 4 5 6 7
MDL03 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
MDL02 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
MDL01 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
MDL00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Input clock selection for baud rate generator fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 Setting prohibited
k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 --
Caution Writing to BRGC0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGC0 during a communication operation. Remarks 1. fSCK: Source clock for 5-bit counter 2. n: 3. k: Value set via TPS00 to TPS02 (1 n 7) Value set via MDL00 to MDL03 (0 k 14)
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14.4
Serial Interface UART0 Operations
This section explains the two modes of serial interface UART0. 14.4.1 Operation stop mode Because serial transfer is not performed during this mode, the power consumption can be reduced. In addition, pins can be used as normal ports. (1) Register settings Operation stop mode is set by asynchronous serial interface mode register 0 (ASIM0). ASIM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Address: FFA0H After reset: 00H Symbol ASIM0 7 TXE0 6 RXE0 R/W 5 PS01 4 PS00 3 CL0 2 SL0 1 ISRM0 0 0
TXE0 0 0
RXE0 0 1
Operation mode Operation stop UART mode (receive only)
RxD0/P20 pin function Port function (P20) Serial function (RxD0)
TxD0/P21 pin function Port function (P21)
1
0
UART mode (transmit only) UART mode (transmit and receive)
Port function (P20)
Serial function (TxD0)
1
1
Serial function (RxD0)
Caution Do not switch the operation mode until the current serial transmit/receive operation has stopped.
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14.4.2 Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates. The UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). (1) Register settings UART mode settings are performed by asynchronous serial interface mode register 0 (ASIM0), asynchronous serial interface status register 0 (ASIS0), and baud rate generator control register 0 (BRGC0). (a) Asynchronous serial interface mode register 0 (ASIM0) ASIM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Caution In UART mode, set the port mode register (PMXX) as follows. Set the output latch of the port set to output mode (PMXX = 0) to 0. * During receive operation Set P20 (RXD0) to input mode (PM20 = 1) * During transmit operation Set P21 (TXD0) to output mode (PM21 = 0) * During transmit/receive operation Set P20 to input mode, and P21 to output mode
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Address: FFA0H After reset: 00H Symbol ASIM0 7 TXE0 6 RXE0
R/W 5 PS01 4 PS00 3 CL0 2 SL0 1 ISRM0 0 0
TXE0 0 0
RXE0 0 1
Operation mode Operation stop UART mode (receive only) UART mode (transmit only) UART mode (transmit and receive)
RxD0/P20 pin function Port function (P20) Serial function (RxD0)
TxD0/P21 pin function Port function (P21)
1
0
Port function (P20)
Serial function (TxD0)
1
1
Serial function (RxD0)
PS01 0 0
PS00 0 1 No parity
Parity bit specification
Zero parity always added during transmission No parity detection during reception (parity errors do not occur) Odd parity Even parity
1 1
0 1
CL0 0 1 7 bits 8 bits
Character length specification
SL0 0 1 1 bit 2 bits
Stop bit length specification for transmit data
ISRM0 0 1
Receive completion interrupt control when error occurs Receive completion interrupt request is issued when an error occurs Receive completion interrupt request is not issued when an error occurs
Caution Do not switch the operation mode until the current serial transmit/receive operation has stopped.
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(b) Asynchronous serial interface status register 0 (ASIS0) ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Address: FFA1H After reset: 00H Symbol ASIS0 7 0 6 0 R 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0
PE0 0 1 No parity error Parity error (Transmit data parity not matched)
Parity error flag
FE0 0 1 No framing error Framing errorNote 1 (Stop bit not detected)
Framing error flag
OVE0 0 1 No overrun error
Overrun error flag
Overrun errorNote 2 (Next receive operation was completed before data was read from receive buffer register 0 (RXB0))
Notes 1. Even if a stop bit length is set to 2 bits by setting bit 2 (SL0) in asynchronous serial interface mode register 0 (ASIM0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of receive buffer register 0 (RXB0) when an overrun error has occurred. Until the contents of RXB0 are read, further overrun errors will occur when receiving data.
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(c) Baud rate generator control register 0 (BRGC0) BRGC0 is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Address: FFA2H After reset: 00H Symbol BRGC0 7 0 6 TPS02 R/W 5 TPS01 4 TPS00 3 MDL03 2 MDL02 1 MDL01 0 MDL00
TPS02 0 0 0 0 1 1 1 1
TPS01 0 0 1 1 0 0 1 1
TPS00 0 1 0 1 0 1 0 1
Source clock selection for 5-bit counter Setting prohibited fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27
n -- 1 2 3 4 5 6 7
MDL03 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
MDL02 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
MDL01 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
MDL00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Input clock selection for baud rate generator fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 Setting prohibited
k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 --
Caution Writing to BRGC0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGC0 during a communication operation. Remarks 1. fSCK: Source clock for 5-bit counter 2. n: 3. k: Value set via TPS00 to TPS02 (1 n 7) Value set via MDL00 to MDL03 (0 k 14)
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The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. * Transmit/receive clock generation for baud rate by using main system clock The main system clock is divided to generate the transmit/receive clock. The baud rate generated from the main system clock is determined according to the following formula. [Baud rate] = fX 2
n+1
(k + 16)
[Hz]
fX: Main system clock oscillation frequency n: Value set via TPS00 to TPS02 (1 n 7) For details, see Table 14-2. k: Value set via MDL00 to MDL03 (0 k 14) Table 14-2 shows the relationship between the 5-bit counter's source clock assigned to bits 4 to 6 (TPS00 to TPS02) of BRGC0 and the "n" value in the above formula and Table 14-3 shows the relationship between the main system clock and the baud rate. Table 14-2. Relationship Between 5-Bit Counter's Source Clock and "n" Value
TPS02 0 0 0 0 1 1 1 1 TPS01 0 0 1 1 0 0 1 1 TPS00 0 1 0 1 0 1 0 1 5-Bit Counter's Source Clock Selected Setting prohibited fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 n -- 1 2 3 4 5 6 7
Remark fX: Main system clock oscillation frequency
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Table 14-3. Relationship Between Main System Clock and Baud Rate
Baud Rate (bps) 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 76,800 115,200 153,600 fX = 10 MHz BRGC0 - - 70H 60H 50H 40H 34H 30H 20H 16H 10H ERR (%) - - 1.73 1.73 1.73 1.73 0.00 1.73 1.73 -1.36 1.73 fX = 9.8304 MHz BRGC0 - - 70H 60H 50H 40H 34H 30H 20H 16H 10H ERR (%) - - 0.00 0.00 0.00 0.00 -1.70 0.00 0.00 -3.03 0.00 fX = 8.386 MHz BRGC0 - 7BH 6BH 5BH 4BH 3BH 31H 2BH 1BH 12H - ERR (%) - 1.10 1.10 1.10 1.10 1.10 -3.14 1.10 1.10 1.10 - fX = 8 MHz BRGC0 - 7AH 6AH 5AH 4AH 3AH 30H 2AH 1AH 11H - ERR (%) - 0.16 0.16 0.16 0.16 0.16 0.00 0.16 0.16 2.12 -
Baud Rate (bps) 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 76,800 115,200 153,600
fX = 7.3728 MHz BRGC0 - 78H 68H 58H 48H 38H 2DH 28H 18H 10H - ERR (%) - 0.00 0.00 0.00 0.00 0.00 1.69 0.00 0.00 0.00 -
fX = 5 MHz BRGC0 - 70H 60H 50H 40H 30H 24H 20H 10H - - ERR (%) - 1.73 1.73 1.73 1.73 1.73 0.00 1.73 1.73 - -
fX = 4.194304 MHz BRGC0 7BH 6BH 5BH 4BH 3BH 2BH 21H 1BH - - - ERR (%) 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 - - -
Remark fX: Main system clock oscillation frequency n: Value set via TPS00 to TPS02 (1 n 7) k: Value set via MDL00 to MDL03 (0 k 14)
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* Error tolerance range for baud rate The tolerance range for the baud rate depends on the number of bits per frame and the counter's division rate [1/(16 + k)]. Figure 14-6 shows an example of a baud rate error tolerance range. Figure 14-6. Baud Rate Error Tolerance (When k = 0), Including Sampling Errors
Ideal sampling point
32T 64T 256T 288T 320T 352T
304T Basic timing (clock cycle T) High-speed clock (clock cycle T') enabling normal reception Low-speed clock (clock cycle T") enabling normal reception START D0 D7 P
15.5T
336T
STOP
START 30.45T START
D0 60.9T D0 33.55T 67.1T
D7
P
STOP
304.5T
15.5T
Sampling error 0.5T
STOP
D7 301.95T
P
335.5T
Remark T: 5-bit counter's source clock cycle Baud rate error tolerance (when k = 0) = 15.5 320 x 100 = 4.8438 (%)
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(2) Communication operations (a) Data format Figure 14-7 shows the format of the transmit/receive data. Figure 14-7. Format of Transmit/Receive Data in Asynchronous Serial Interface
1 data frame Start bit Parity bit Stop bit
D0
D1
D2
D3
D4
D5
D6
D7
Character bits
1 data frame consists of the following bits. * Start bit ............. 1 bit * Character bits ... 7 bits or 8 bits * Parity bit ........... Even parity, odd parity, zero parity, or no parity * Stop bit(s) ......... 1 bit or 2 bits Asynchronous serial interface mode register 0 (ASIM0) is used to set the character bit length, parity selection, and stop bit length within each data frame. When "7 bits" is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to "0". ASIM0 and baud rate generator control register 0 (BRGC0) are used to set the serial transfer rate. If a receive error occurs, information about the receive error can be recognized by reading asynchronous serial interface status register 0 (ASIS0).
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(b) Parity types and operations The parity bit is used to detect bit errors in communication data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. When zero parity or no parity is set, errors are not detected. (i) Even parity * During transmission The number of bits in transmit data that includes a parity bit is controlled so that there are an even number of bits whose value is 1. The value of the parity bit is as follows. If the transmit data contains an odd number of bits whose value is 1: the parity bit is "1" If the transmit data contains an even number of bits whose value is 1: the parity bit is "0" * During reception The number of bits whose value is 1 is counted among the receive data that include a parity bit, and a parity error occurs when the counted result is an odd number. (ii) Odd parity * During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of bits whose value is 1. The value of the parity bit is as follows. If the transmit data contains an odd number of bits whose value is 1: the parity bit is "0" If the transmit data contains an even number of bits whose value is 1: the parity bit is "1" * During reception The number of bits whose value is 1 is counted among the receive data that include a parity bit, and a parity error occurs when the counted result is an even number. (iii) Zero parity During transmission, the parity bit is set to "0" regardless of the transmit data. During reception, the parity bit is not checked. Therefore, no parity errors will occur regardless of whether the parity bit is a "0" or a "1". (iv) No parity No parity bit is added to the transmit data. During reception, receive data is regarded as having no parity bit. Since there is no parity bit, no parity errors will occur.
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(c) Transmission The transmit operation is enabled if bit 7 (TXE0) of asynchronous serial interface mode register 0 (ASIM0) is set to 1, the transmit operation is started when transmit data is written to transmit shift register 0 (TXS0). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS0, thereby emptying TXS0, after which a transmit completion interrupt request (INTST0) is issued. The timing of the transmit completion interrupt request is shown in Figure 14-8. Figure 14-8. Timing of Asynchronous Serial Interface Transmit Completion Interrupt Request (i) Stop bit length: 1 bit
TxD0 (output)
START
D0
D1
D2
D6
D7
Parity
STOP
INTST0
(ii) Stop bit length: 2 bits
TxD0 (output)
START
D0
D1
D2
D6
D7
Parity
STOP
INTST0
Caution Do not rewrite to asynchronous serial interface mode register 0 (ASIM0) during a transmit operation. Rewriting ASIM0 register during a transmit operation may disable further transmit operations (in such cases, enter a RESET to restore normal operation). Whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt request (INTST0) or the interrupt request flag (STIF0) that is set by INTST0.
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(d) Reception The receive operation is enabled when "1" is set to bit 6 (RXE0) of asynchronous serial interface mode register 0 (ASIM0), and input via the RxD0 pin is sampled. The serial clock specified by BRGC0 is used to sample the RxD0 pin. When the RxD0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. If sampling the RxD0 pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. After the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. Once reception of one data frame is completed, the receive data in the shift register is transferred to receive buffer register 0 (RXB0) and a receive completion interrupt request (INTSR0) occurs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXB0. When ASIM0 bit 1 (ISRM0) is cleared (0) upon occurrence of an error, INTSR0 occurs (see Figure 14-10). When ISRM0 bit is set (1), INTSR0 does not occur. If the RXE0 bit is reset (to "0") during a receive operation, the receive operation is stopped immediately. At this time, the contents of RXB0 and ASIS0 do not change, nor does INTSR0 or INTSER0 occur. Figure 14-9 shows the timing of the asynchronous serial interface receive completion interrupt request. Figure 14-9. Timing of Asynchronous Serial Interface Receive Completion Interrupt Request
RxD0 (input)
START
D0
D1
D2
D6
D7
Parity
STOP
INTSR0
Caution Be sure to read the contents of receive buffer register 0 (RXB0) even when a receive error has occurred. Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXB0 are read.
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(e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of data reception, an error flag is set to asynchronous serial interface status register 0 (ASIS0), a receive error interrupt request (INTSER0) will occur. Receive error interrupt requests are generated before receive completion interrupt request (INTSR0). Table 14-4 lists the causes behind receive errors. As part of receive error interrupt request (INTSER0) servicing, the contents of ASIS0 can be read to determine which type of error occurred during the receive operation (see Table 14-4 and Figure 14-10). The contents of ASIS0 are reset (to "0") when receive buffer register 0 (RXB0) is read or when the next data is received (if the next data contains an error, its error flag will be set). Table 14-4. Causes of Receive Errors
Receive Error Parity error Framing error Overrun error Cause Parity specified during transmission does not match parity of receive data Stop bit was not detected Reception of the next data was completed before data was read from receive buffer register 0 (RXB0) ASIS0 Value 04H 02H 01H
Figure 14-10. Receive Error Timing
RxD0 (input)
START
D0
D1
D2
D6
D7
Parity
STOP
INTSR0Note
INTSER0 (When framing/overrun error occurs)
INTSER0 (When parity error occurs)
Note If a receive error occurs when the ISRM0 bit has been set (1), INTSR0 does not occur. Cautions 1. The contents of asynchronous serial interface status register 0 (ASIS0) are reset (to "0") when receive buffer register 0 (RXB0) is read or when the next data is received. To obtain information about the error, be sure to read the contents of ASIS0 before reading RXB0. 2. Be sure to read the contents of receive buffer register 0 (RXB0) even when a receive error has occurred. Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXB0 are read.
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Serial interface UART0/SIO3 can be used in the asynchronous serial interface (UART) mode or 3-wire serial I/ O mode. Caution Do not enable UART0 and SIO3 at the same time.
15.1
Serial Interface SIO3 Functions
Serial interface SIO3 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 15.4.1 Operation stop mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3), serial output line (SO3), and serial input line (SI3). Since simultaneous transmit and receive operations are enabled in 3-wire serial I/O mode, the processing time for data transfers is reduced. The first bit of the serial transferred 8-bit data is fixed as the MSB. 3-wire serial I/O mode is useful for connection to a peripheral I/O incorporating a clocked serial interface, or a display controller, etc. For details, see 15.4.2 3-wire serial I/O mode. Figure 15-1 shows a block diagram of the serial interface SIO3. Figure 15-1. Serial Interface SIO3 Block Diagram
Internal bus 8 SI3/RXD0/P20 Serial I/O shift register 3 (SIO3)
SO3/TXD0/P21 SCK3/P22 Serial clock counter Serial clock controller Interrupt request signal generator INTCSI3 fX/23 fX/25 fX/27
Selector
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15.2
Serial Interface SIO3 Configuration
Serial interface SIO3 consists of the following hardware. Table 15-1. Serial Interface SIO3 Configuration
Item Register Control register Configuration Serial I/O shift register 3 (SIO3) Serial operation mode register 3 (CSIM3)
(1) Serial I/O shift register 3 (SIO3) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. SIO3 is set by an 8-bit memory manipulation instruction. When "1" is set to bit 7 (CSIE3) of serial operation mode register 3 (CSIM3), a serial operation can be started by writing data to or reading data from SIO3. When transmitting, data written to SIO3 is output to the serial output (SO3). When receiving, data is read from the serial input (SI3) and written to SIO3. The value of this register is undefined when RESET is input. Caution Do not access SIO3 during a transfer operation unless the access is triggered by a transfer start (read operation is disabled when MODE = 0 and write operation is disabled when MODE = 1).
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15.3
Register to Control Serial Interface SIO3
Serial interface SIO3 is controlled by serial operation mode register 3 (CSIM3). (1) Serial operation mode register 3 (CSIM3) This register is used to enable or disable SIO3's serial clock, operation modes, and specific operations. CSIM3 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Caution In 3-wire serial I/O mode, set the port mode register (PMXX) as follows. Set the output latch of the port set to output mode (PMXX = 0) to 0.
During serial clock output (master transmission or master reception) During serial clock input (slave transmission or slave reception) Transmit/receive mode
PM22 = 0; Sets P22 (SCK3) to output mode P22 = 0; Sets output latch of P22 to 0 PM22 = 1; Sets P22 (SCK3) to input mode
PM21 = 0; Sets P21 (SO3) to output mode P21 = 0; Sets output latch of P21 to 0 PM20 = 1; Sets P20 (SI3) to input mode
Receive mode
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Figure 15-2. Serial Operation Mode Register 3 (CSIM3) Format
Address: FFAFH After reset: 00H Symbol CSIM3 7 CSIE3 6 0 R/W 5 0 4 0 3 0 2 MODE 1 SCL31 0 SCL30
CSIE3
Enable/disable specification for SIO3 Shift register operation Serial counter Clear Count operation enable Port Port functionNote 1 Serial function + port functionNote 2
0 1
Operation stop Operation enable
MODE Operation mode 0 1
Transfer operation modes and flags Transfer start trigger Write to SIO3 Read from SIO3 SO3 output Normal output Fixed at low level
Transmit/transmit and receive mode Receive-only mode
SCL31 0 0 1 1
SCL30 0 1 0 1 External clock input to SCK3 fX/23 (1.25 MHz) fX/25 (312.5 kHz) fX/27 (78.125 kHz)
Clock selection
Notes 1. When CSIE3 = 0 (SIO3 operation stop status), the pins SI3, SO3, and SCK3 can be used for port functions. 2. When CSIE3 = 1 (SIO3 operation enabled status), the SI3 pin can be used as a port pin if only the transmit function is used, and the SO3 pin can be used as a port pin if only the receive-only mode is used. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz.
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15.4
Serial Interface SIO3 Operations
This section explains the two modes of serial interface SIO3. 15.4.1 Operation stop mode Because serial transfer is not performed in this mode, the power consumption can be reduced. In addition, pins can be used as normal I/O ports. (1) Register settings Operation stop mode is set by serial operation mode register 3 (CSIM3). CSIM3 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Address: FFAFH After reset: 00H Symbol CSIM3 7 CSIE3 6 0 R/W 5 0 4 0 3 0 2 MODE 1 SCL31 0 SCL30
CSIE3
SIO3 operation enable/disable specification Shift register operation Serial counter Clear Count operation enable Port Port functionNote 1 Serial function + port functionNote 2
0 1
Operation stop Operation enable
Notes 1. When CSIE3 = 0 (SIO3 operation stop status), the pins SI3, SO3, and SCK3 can be used for port functions. 2. When CSIE3 = 1 (SIO3 operation enabled status), the SI3 pin can be used as a port pin if only the transmit function is used, and the SO3 pin can be used as a port pin if only the receive-only mode is used.
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15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection to a peripheral I/O incorporating a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK3), serial output line (SO3), and serial input line (SI3). (1) Register settings 3-wire serial I/O mode is set by serial operation mode register 3 (CSIM3). CSIM3 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Caution In 3-wire serial I/O mode, set the port mode register (PMXX) as follows. Set the output latch of the port set to output mode (PMXX = 0) to 0.
During serial clock output (master transmission or master reception) During serial clock input (slave transmission or slave reception) Transmit/receive mode
PM22 = 0; Sets P22 (SCK3) to output mode P22 = 0; Sets output latch of P22 to 0 PM22 = 1; Sets P22 (SCK3) to input mode
PM21 = 0; Sets P21 (SO3) to output mode P21 = 0; Sets output latch of P21 to 0
Receive mode
PM20 = 1; Sets P20 (SI3) to input mode
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Address: FFAFH After reset: 00H Symbol CSIM3 7 CSIE3 6 0
R/W 5 0 4 0 3 0 2 MODE 1 SCL31 0 SCL30
CSIE3
Enable/disable specification for SIO3 Shift register operation Serial counter Clear Count operation enable Port Port functionNote 1 Serial function + port functionNote 2
0 1
Operation stop Operation enable
MODE Operation mode 0 1
Transfer operation modes and flags Transfer start trigger Write to SIO3 Read from SIO3 SO3 output Normal output Fixed at low level
Transmit/transmit and receive mode Receive-only mode
SCL31 0 0 1 1
SCL30 0 1 0 1 External clock input to SCK3 fX/23 (1.25 MHz) fX/25 (312.5 kHz) fX/27 (78.125 kHz)
Clock selection
Notes 1. When CSIE3 = 0 (SIO3 operation stop status), the pins SI3, SO3, and SCK3 can be used for port functions. 2. When CSIE3 = 1 (SIO3 operation enabled status), the SI3 pin can be used as a port pin if only the transmit function is used, and the SO3 pin can be used as a port pin if only the receive-only mode is used. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses are for operation with fX = 10 MHz.
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(2) Communication operations In the 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is transmitted or received in synchronization with the serial clock. Serial I/O shift register 3 (SIO3) is shifted in synchronization with the falling edge of the serial clock. Transmit data is held in the SO3 latch and is output from the SO3 pin. Data that is received via the SI3 pin in synchronization with the rising edge of the serial clock is latched to SIO3. Completion of an 8-bit transfer automatically stops operation of SIO3 and sets the interrupt request flag (CSIIF3). Figure 15-3. Timing of 3-Wire Serial I/O Mode
SCK3 SI3 SO3 CSIIF3
1 DI7 DO7
2 DI6 DO6
3 DI5 DO5
4 DI4 DO4
5 DI3 DO3
6 DI2 DO2
7 DI1 DO1
8 DI0 DO0
Transfer completion Transfer starts in synchronization with the SCK3 falling edge
(3) Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set (or read) to serial I/O shift register 3 (SIO3). * SIO3 operation control bit (CSIE3) = 1 * After an 8-bit serial transfer, either the internal serial clock is stopped or SCK3 is set to high level. * Transmit/transmit and receive mode When CSIE3 = 1 and MODE = 0, transfer starts when writing to SIO3. * Receive-only mode When CSIE3 = 1 and MODE = 1, transfer starts when reading from SIO3. Caution After data has been written to SIO3, transfer will not start even if the CSIE3 bit value is set to "1". Completion of an 8-bit transfer automatically stops the serial transfer operation and the interrupt request flag (CSIIF3) is set.
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16.1
Serial Interface CSI1 Functions
Serial interface CSI1 has the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed. In this mode, the power consumption can be reduced. (2) 3-wire serial I/O mode (MSB/LSB first selectable) This mode is used to transfer 8-bit data by using three lines: a serial clock line (SCK1) and two serial data lines (SI1 and SO1). The processing time of data transfer can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed in this mode. In addition, whether 8-bit data is transferred with the MSB or LSB first can be specified, so this interface can be connected to any device. The 3-wire serial I/O mode is useful for connecting peripheral I/Os and display controllers having a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series.
16.2
Serial Interface CSI1 Configuration
Serial interface CSI1 consists of the following hardware. Table 16-1. Serial Interface CSI1 Configuration
Item Registers Configuration Transmit buffer register 1 (SOTB1) Serial I/O shift register 1 (SIO1) Serial operation mode register 1 (CSIM1) Serial clock select register 1 (CSIC1)
Control registers
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Figure 16-1. Serial Interface CSI1 Block Diagram
Internal bus 8 SI1/P23 Serial I/O shift register 1 (SIO1) 8 Transmit buffer register 1 (SOTB1) Output selector SO1/P24
Transmit data controller
Output latch
Transmit controller
fX/22 to fX/28 SCK1/P25
Selector
Clock start/stop controller & clock phase controller
INTCSI1
(1) Transmit buffer register 1 (SOTB1) This register sets transmit data. Transmission/reception is started by writing data to SOTB1 when bit 6 (TRMD1) of serial operation mode register 1 (CSIM1) is 1. The data written to SOTB1 is converted from parallel data into serial data by serial I/O shift register 1, and output to the serial output (SO1) pin. SOTB1 can be written or read by an 8-bit memory manipulation instruction. RESET input makes the value of this register undefined. Caution Do not access SOTB1 when CSOT1 = 1 (during serial communication). (2) Serial I/O shift register 1 (SIO1) This is an 8-bit register that converts data from parallel into serial or vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO1 if bit 6 (TRMD1) of serial operation mode register 1 (CSIM1) is 0. During reception, the data is read from the serial input pin (SI1) to SIO1. RESET input makes the value of this register undefined. Caution Do not access SIO1 when CSOT1 = 1 (during serial communication).
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16.3
Registers to Control Serial Interface CSI1
Serial interface CSI1 is controlled by the following two registers. * Serial operation mode register 1 (CSIM1) * Serial clock select register 1 (CSIC1) (1) Serial operation mode register 1 (CSIM1) This register is used to select an operation mode and enable or disable the operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 16-2. Serial Operation Mode Register 1 (CSIM1) Format
Address: FFB0H Symbol CSIM1 After reset: 00H R/WNote 1 7 CSIE1 6 TRMD1 5 0 4 DIR1 3 0 2 0 1 0 0 CSOT1
CSIE1 0
Operation control in 3-wire serial I/O mode Stops operation (SI1/P23, SO1/P24, and SCK1/P25 pins can be used as general-purpose port pins). Enables operation (SI1/P23, SO1/P24, and SCK1/P25 pins are at active level).
1
TRMD1Note 2 0Note 3 1
Transmit/receive mode selection Receive mode (transmission disabled). Transmit/receive mode
DIR1Note 4 0 1 MSB LSB
First bit specification
CSOT1Note 5 0 1 Communication is stopped. Communication is in progress.
Operation mode flag
Notes 1. Bit 0 is a read-only bit. 2. Do not rewrite TRMD1 when CSOT1 = 1 (during serial communication). 3. The SO1 pin is fixed to the low level when TRMD1 is 0. Reception is started when data is read from SIO1. 4. Do not overwrite these bits when CSOT1 = 1 (during serial communication). 5. CSOT1 is cleared if CSIE1 is cleared to 0 (operation stops). Caution Be sure to set bit 5 to 0.
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(2) Serial clock select register 1 (CSIC1) This register is used to select the phase of the data clock and a count clock. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 10H. Figure 16-3. Serial Clock Select Register 1 (CSIC1) Format
Address: FFB1H Symbol CSIC1 After reset: 10H R/W 7 0 6 0 5 0 4 CKP1 3 DAP1 2 CKS12 1 CKS11 0 CKS10
CKP1 0
DAP1 0
Data clock phase selection
Type 1
SCK1 SO1 SI1 input timing
0 1 2
D7 D6 D5 D4 D3 D2 D1 D0
SCK1 SO1 SI1 input timing
1 0
SCK1 SO1 SI1 input timing D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
3
1
1
SCK1 SO1 SI1 input timing D7 D6 D5 D4 D3 D2 D1 D0
4
CKS12 0 0 0 0 1 1 1 1
CKS11 0 0 1 1 0 0 1 1
CKS10 0 1 0 1 0 1 0 1 fX/22 fX/23 fX/24 fX/25 fX/26 (2.5 MHz) (1.25 MHz) (625 kHz) (312.5 kHz) (156.25 kHz)
Count clock CSI1 selection
fX/27 (78.125 kHz) fX/28 (39.0625 kHz) External clock
Cautions 1. 2.
Do not write CSIC1 when CSIE1 = 0 (operation stops). The phase type of the data clock is type 3 after reset.
Remark Figures in parentheses are for operation with fX = 10 MHz
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16.4
Serial Interface CSI1 Operations
Serial interface CSI1 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 16.4.1 Operation stop mode Serial transfer is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P23/SI1, P24/SO1, and P25/SCK1 pins can be used as normal I/O port pins in this mode. (1) Register setting The operation stop mode is set by serial operation mode register 1 (CSIM1). (a) Serial operation mode register 1 (CSIM1) This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Address: FFB0H Symbol CSIM1 After reset: 00H R/W 7 CSIE1 6 TRMD1 5 0 4 DIR1 3 0 2 0 1 0 0 CSOT1
CSIE1 0
Operation control in 3-wire serial I/O mode Stops operation (SI1/P23, SO1/P24, and SCK1/P25 pins can be used as general-purpose port pins). Enables operation (SI1/P23, SO1/P24, and SCK1/P25 pins are at active level).
1
16.4.2
3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connecting peripheral I/Os and display controllers having a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series. In this mode, communication is executed by using three lines: serial clock (SCK1), serial output (SO1), and serial input (SI1) lines. (1) Register setting The 3-wire serial I/O mode is set by using serial operation mode register 1 (CSIM1) and serial clock select register 1 (CSIC1).
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(a) Serial operation mode register 1 (CSIM1) This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Address: FFB0H Symbol CSIM1 After reset: 00H R/WNote 1 7 CSIE1 6 TRMD1 5 0 4 DIR1 3 0 2 0 1 0 0 CSOT1
CSIE1 0
Operation control in 3-wire serial I/O mode Stops operation (SI1/P23, SO1/P24, and SCK1/P25 pins can be used as general-purpose port pins). Enables operation (SI1/P23, SO1/P24, and SCK1/P25 pins are at active level).
1
TRMD1Note 2 0Note 3 1
Transmit/receive mode selection Receive mode (transmission disabled). Transmit/receive mode
DIR1Note 4 0 1 MSB LSB
First bit specification
CSOT1Note 5 0 1 Communication is stopped. Communication is in progress.
Operation mode flag
Notes 1. Bit 0 is a read-only bit. 2. Do not rewrite TRMD1 when CSOT1 = 1 (during serial communication). 3. The SO1 pin is fixed to the low level when TRMD1 is 0. Reception is started when data is read from SIO1. 4. Do not overwrite these bits when CSOT1 = 1 (during serial communication). 5. CSOT1 is cleared if CSIE1 is cleared to 0 (operation stops). Caution Be sure to set bit 5 to 0.
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(b) Serial clock select register 1 (CSIC1) This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 10H.
Address: FFB1H Symbol CSIC1 After reset: 10H R/W 7 0 6 0 5 0 4 CKP1 3 DAP1 2 CKS12 1 CKS11 0 CKS10
CKP1 0
DAP1 0
Data clock phase selection
Type 1
SCK1 SO1 SI1 input timing
0 1 2
D7 D6 D5 D4 D3 D2 D1 D0
SCK1 SO1 SI1 input timing
1 0
SCK1 SO1 SI1 input timing D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
3
1
1
SCK1 SO1 SI1 input timing D7 D6 D5 D4 D3 D2 D1 D0
4
CKS12 0 0 0 0 1 1 1 1
CKS11 0 0 1 1 0 0 1 1
CKS10 0 1 0 1 0 1 0 1 fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (312.5 kHz) fX/26 (156.25 kHz) fX/27 (78.125 kHz)
Count clock CSI1 selection
fX/28 (39.0625 kHz) External clock
Cautions 1. 2.
Do not write CSIC1 when CSIE1 = 0 (operation stops). The phase type of the data clock is type 3 after reset.
Remark Figures in parentheses are for operation with fX = 10 MHz
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(2) Setting of port <1> Transmit/receive mode (a) To use externally input clock as system clock (SCK1) Bit 3 (PM23) of port mode register 2: Set to 1 Bit 4 (PM24) of port mode register 2: Cleared to 0 Bit 5 (PM25) of port mode register 2: Set to 1 Bit 4 (P24) of port 2: Cleared to 0 (b) To use internal clock as system clock (SCK1) Bit 3 (PM23) of port mode register 2: Set to 1 Bit 4 (PM24) of port mode register 2: Cleared to 0 Bit 5 (PM25) of port mode register 2: Cleared to 0 Bit 4 (P24) of port 2: Cleared to 0 Bit 5 (P25) of port 2: Cleared to 0 <2> Receive mode (with transmission disabled) (a) To use externally input clock as system clock (SCK1) Bit 3 (PM23) of port mode register 2: Set to 1 Bit 5 (PM25) of port mode register 2: Set to 1 (b) To use internal clock as system clock (SCK1) Bit 3 (PM23) of port mode register 2: Set to 1 Bit 5 (PM25) of port mode register 2: Cleared to 0 Bit 5 (P25) of port 2: Cleared to 0 Remark The transmit/receive mode or receive mode is selected by using bit 6 (TRMD1) of serial operation mode register 1 (CSIM1).
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(3) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1) of serial operation mode register 1 (CSIM1) is 1. Transmission/reception is started when a value is written to transmit buffer register 1 (SOTB1). Data can be received if bit 6 (TRMD1) of serial operation mode register 1 (CSIM1) is 0. Reception is started when data is read from serial I/O shift register 1 (SIO1). After communication has been started, bit 0 (CSOT1) of CSIM1 is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt flag (CSIIF1) is set, and CSOT1 is cleared to 0. Then the next communication is enabled. Caution Do not access the control register and data register when CSOT1 = 1 (during serial communication). Figure 16-4. Timing in 3-Wire Serial I/O Mode (1/2) (1) Transmission/reception timing (Type 1; TRMD1 = 1, DIR1 = 0, CKP1 = 0, DAP1 = 0)
SCK1
Read/write trigger
SOTB1
55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH
SIO1
CSOT1
INTCSI1
CSIIF1
SI1 (receive AAH)
SO1
55H is written to STOB1.
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Figure 16-4. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD1 = 1, DIR1 = 0, CKP1 = 0, DAP1 = 1)
SCK1
Read/write trigger
SOTB1
55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH
SIO1
CSOT1
INTCSI1
CSIIF1
SI1 (input AAH)
SO1
55H is written to STOB1.
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Figure 16-5. Timing of Clock/Data Phase (a) Type 1; CKP1 = 0, DAP1 = 0
SCK1 SI1 capture SO1 Writing to STOB1 or reading from SIO1 CSIIF1 CSOT1 D7 D6 D5 D4 D3 D2 D1 D0
(b) Type 2; CKP1 = 0, DAP1 = 1
SCK1 SI1 capture SO1 Writing to STOB1 or reading from SIO1 CSIIF1 CSOT1 D7 D6 D5 D4 D3 D2 D1 D0
(c) Type 3; CKP1 = 1, DAP1 = 0
SCK1 SI1 capture SO1 Writing to STOB1 or reading from SIO1 CSIIF1 CSOT1 D7 D6 D5 D4 D3 D2 D1 D0
(d) Type 4; CKP = 1, DAP1 = 1
SCK1 SI1 capture SO1 Writing to STOB1 or reading from SIO1 CSIIF1 CSOT1 D7 D6 D5 D4 D3 D2 D1 D0
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(4) Timing of output to SO1 pin (first bit) When communication is started, the value of transmit buffer register 1 (SOTB1) is output from the SO1 pin. The output operation of the first bit at this time is explained below. Figure 16-6. Output Operation of First Bit (1) CKP1 = 0, DAP1 = 0 (or CKP1 = 1, DAP1 = 0)
SCK1 Writing to STOB1 or reading from SIO1 SOTB1 SIO1 Output latch SO1 First bit Second bit
The first bit is directly latched to the output latch from the SOTB1 register at the falling (or rising) edge of SCK1, and is output from the SO1 pin via the output selector. At the next rising (or falling) edge of SCK1, the value of the SOTB1 register is transferred to the SIO1 register and shifted by 1 bit. At the same time, the first bit of the receive data is stored in the SIO1 register via the SI1 pin. The second and subsequent bits are latched to the output latch from SIO1 at the next falling (or rising) edge of SCK1 and the data is output from the SO1 pin. (2) CKP1 = 0, DAP1 = 1 (or CKP1 = 1, DAP1 = 1)
SCK1 Writing to STOB1 or reading from SIO1 SOTB1 SIO1 Output latch SO1 First bit Second bit Third bit
The first bit is directly output from the SOTB1 register to the SO1 pin via the output selector at the falling edge of the write signal of SOTB1 or the read signal of the SIO1 register. At the next falling (or rising) edge of SCK1, the value of the SOTB1 register is transferred to the SIO1 register and shifted by 1 bit. At the same time, the first bit of the received data is stored in the SIO1 register via the SI1 pin. The second and subsequent bits are latched to the output latch from SIO1 at the next rising (or falling) edge of SCK1 and the data is output from the SO1 pin.
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(5) Output value of SO1 pin (last bit) After communication has been completed, the SO1 pin holds the output value of the last bit. Figure 16-7. Output Value of SO1 Pin (Last Bit) (1) Type 1; CKP1 = 0 and DAP1 = 0 (or CKP1 = 1, DAP1 = 0)
SCK1 Writing to STOB1 or reading from SIO1 SOTB1 SIO1 Output latch SO1 Last bit ( Next request is issued.)
(2) Type 2; CKP1 = 0 and DAP1 = 1 (or CKP1 = 1, DAP1 = 1)
SCK1 Writing to STOB1 or reading from SIO1 SOTB1 SIO1 Output latch SO1 Last bit ( Next request is issued.)
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(6) SCK1 pin The status of the SCK1 pin is as follows if bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is cleared to 0. Table 16-2. SCK1 Pin Status
CKP1 CKP1 = 0 CKS12 to 10 CKS12, 11, 10 1, 1, 1 CKS12, 11, 10 = 1, 1, 1 CKP1 = 1Note CKS12, 11, 10 1, 1, 1Note SCK1 Pin Outputs high level. Outputs high level. Outputs low levelNote. Outputs high level.
CKS12, 11, 10 = 1, 1, 1
Note (7) SO1 pin
Status after reset
The status of the SO1 pin is as follows if bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is cleared to 0. Table 16-3. SO1 Pin Status
TRMD1 TRMD1 = 0Note TRMD1 = 1 DAP1 - DAP1 = 0 DIR1 - - SO1 Pin Outputs low levelNote. Value of SO1 latch (low-level output) Value of bit 7 of SOTB1 Value of bit 0 of SOTB1
DAP1 = 1
DIR1 = 0 DIR1 = 1
Note Status after reset Caution If a value is written to TRMD1, DAP1, and DIR1, the output value of the SO1 pin changes.
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17.1 LCD Controller/Driver Functions
The internal LCD controller/driver of the PD780318, 780328, and 780338 Subseries has the following functions: (1) Automatic output of segment signals and common signals by automatically reading display data memory (2) Internal booster circuit employed for LCD driver reference voltage generator (x3 only). Therefore, LCD can be stably displayed even if the supply voltage drops because the battery voltage drops. In addition, the LCD driver reference voltage can be changed by using an external resistor to adjust the brightness. (3) Three display modes selectable * Static (up to 12 lines) * 1/3 duty (1/3 bias) * 1/4 duty (1/3 bias) (4) Four types of frame frequencies selectable in each display mode (5) The number of segment signal output lines differs depending on the model as shown in Table 17-1. Table 17-1. Segment Signals and Common Signals
Part Number Maximum Number of Segment Signals 24 lines (S0 to S23), of which 12 (S0 to S11) are selectable for static display. 32 lines (S0 to S31), of which 12 (S0 to S11) are selectable for static display. 40 lines (S0 to S39), of which 12 (S0 to S11) are selectable for static display. 40 lines (S0 to S39), of which 12 (S0 to S11) are selectable for static display, and 16 (S24 to S39) are also used with output port lines (P80 to P87 and P90 to P97)Note. Common Signals Dynamic display: COM0 to COM3 Static display: SCOM0
PD780316, 780318 PD780326, 780328 PD780336, 780338 PD78F0338
Note The operation mode of the alternate-function pins can be switched between the port mode and segment signal mode in 8-bit units by using pin function switching registers 8 and 9 (PF8 and PF9). (6) Simultaneous driving of static display (up to 12 segments) and dynamic display. The operation mode of the alternate-function pins (S0 to S11) can be switched between the static display mode and dynamic display mode in 4-bit units. (7) Blinking of LCD (only when subsystem clock is used). Whether each segment blinks or not can be selected. The blinking cycle can be selected from 0.5 s or 1.0 s. (8) Operation with subsystem clock (9) Operating voltage range: 1.8 to 5.5 V
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Table 17-2 shows the maximum number of pixels that can be displayed in each display mode. Table 17-2. Maximum Number of Pixels Displayed
Part Number Bias Mode -- 1/3 Time Division Static 3 4 Common Signals SCOM0 COM0 to COM2 COM0 to COM3 SCOM0 COM0 to COM2 COM0 to COM3 SCOM0 COM0 to COM2 COM0 to COM3 Maximum Number of Pixels 12 (12 segment x 1 common) 72 (24 segment x 3 common) 96 (24 segment x 4 common) 12 (12 segment x 1 common) 96 (32 segment x 3 common) 128 (32 segment x 4 common) 12 (12 segment x 1 common) 120 (40 segment x 3 common) 160 (40 segment x 4 common)
PD780316, 780318, 78F0338
PD780326, 780328
1/3
--
Static 3 4
PD780336, 780338
1/3
--
Static 3 4
17.2 LCD Controller/Driver Configuration
The LCD controller/driver consists of the following hardware. Table 17-3. LCD Controller/Driver Configuration
Item Display output Configuration
PD780316, 780318
Dynamic/static alternated: 12 lines Dynamic display segment: 12 lines Common signal: 4 lines (for dynamic display) 1 line (for static display) Dynamic/static alternated: 12 lines Dynamic display segment: 20 lines Common signal: 4 lines (for dynamic display) 1 line (for static display) Dynamic/static alternated: 12 lines Dynamic display segment: 28 lines Common signal: 4 lines (for dynamic display) 1 line (for static display) Segment signal: Dynamic/static alternated: 12 lines Dynamic display segment: 12 lines Segment/output port: 16 lines Common signal: 4 lines (for dynamic display) 1 line (for static display) 40 lines Segment signal: 40 lines Segment signal: 32 lines
Segment signal:
24 lines
PD780326, 780328
PD780336, 780338
PD78F0338
Control register
LCD display mode register 3 (LCDM3) LCD clock control register 3 (LCDC3) Static/dynamic display switching register 3 (SDSEL3) Pin function switching register 8 (PF8)Note Pin function switching register 9 (PF9)Note
Note PD78F0338 only
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LCD display mode register 3 (LCDM3)
LCDON SCOC VLCON BLSEL BLON LCDM0
Figure 17-1. LCD Controller/Driver Block Diagram
LCD clock control register 3 (LCDC3) LCDC LCDC LCDC LCDC 33 32 31 30
Internal bus Static/dynamic display switching register 3 (SDSEL3) 4 bits
SEGREG0
SEGREG1
SEGREG2
SEGREG3
SEGREG39
SDSEL SDSEL SDSEL 32 31 30
Segment Segment Segment driver 1 driver 2 driver 0 (S8 to S11) (S4 to S7) (S0 to S3)
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
Segment Buffer driver
Blinking source clock Blinking control cycle selector Booster circuit control signal
fXT fX/26 fX/27 fX/28
LCD source fLCD clock selector
Segment driver SEGREG12 to 15 SEGREG24 to 27 SEGREG32 to 35 SEGREG36 to 38
Timing controller Blinking clock
LCD frame frequency selector
SEGREG0 to 3
Timing control signal
Common driver (for static display) Segment driver 0 Segment driver 3 Segment driver 6 Segment driver 8 Segment driver 9
Pin function switching register 9 (PF9) Pin function switching register 8 (PF8)
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fLCD
Booster clock generator
Common driver (for time division)
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Booster circuit Booster clock
VLC0, VLC1, VLC2
Buffer
COM0
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
S12
Buffer
S13
Buffer
S14
Buffer
S15
Buffer
P90/S24
Buffer
P91/S25
Buffer
P92/S26
Buffer
P93/S27
Buffer
P80/S32
Buffer
P81/S33
Buffer
P82/S34
Buffer
P83/S35
Buffer
Buffer
Buffer
Buffer
VLC2 VLC1 VLC0 VLCDC CAPL CAPH
COM1
COM2
COM3
SCOM0
S0
Static/dynamic display alternately
S1
S2
S3
P84/S36
P85/S37
P86/S38
P87/S39
Dynamic display only
Port/segment alternatelyNote
Port/segment alternatelyNote
Note PD78F0338 only
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17.3 Registers to Control LCD Controller/Driver
The LCD controller/driver can be controlled by using the following three types of registers (the LCD controller/driver of the PD78F0338 is controlled by five types of registers). * LCD display mode register 3 (LCDM3) * LCD clock control register 3 (LCDC3) * Static/dynamic display switching register 3 (SDSEL3) * Pin function switching register 8 (PF8)Note * Pin function switching register 9 (PF9)Note Note PD78F0338 only (1) LCD display mode register 3 (LCDM3) This register enables or disables display, controls the booster circuit and blinking display, and selects a display mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
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Figure 17-2. LCD Display Mode Register 3 (LCDM3) Format
Address: FF90H After reset: 00H Symbol LCDM3 7 LCDON 6 SCOC R/W 5 VLCON 4 BLSEL 3 BLON 2 0 1 0 0 LCDM0
LCDON 0 1
Display control (enables output of display data) Display OFF (All segment output pins output unselect signals.) Display ON
SCOC 0 1
Output control of segment/common pins Outputs GND level to segment/common pins. Outputs select signal to segment/common pins.
VLCON 0 1 Stops booster circuit. Operates booster circuit
Booster circuit control
BLSELNote 1 0 1 Blinking cycle of 0.5 s Blinking cycle of 1.0 s
Blinking clock cycle selection
BLONNote 2 0 1Note 3 Blinking display OFF Blinking display ON
Blinking display control
LCDM0Note 4 Dynamic/static display alternate pinsNotes 5, 6 Time division 0 1 4 3 Bias mode 1/3 1/3
Dynamic pin Time division 4 3 Bias mode 1/3 1/3
Notes 1. The BLSEL bit is valid only when the subsystem clock is used. 2. The corresponding segment pin can be blinked only if the blinking data memory (higher 4 bits of FA00 to FA27H) is set to 1. 3. Do not change the contents of the blinking data memory while BLON = 1. 4. Do not change LCDM0 while the LCD is in operation. Be sure to set this bit while LCDON = 0, SCOC = 0, and VLCON = 0. 5. The dynamic/static display alternate pins are in the static display mode when this mode is selected by the static/dynamic display switching register 3 (SDSEL3). 6. When static display is not used, the static display common output pin (SCOM0) outputs the GND potential.
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Cautions 1. Set the LCDON, SCOC, and VLCON bits in the following sequence: * To display LCD while LCD booster circuit stops (1) Set VLCON to 1. All the segment and common pins are in the GND output mode (SCOC = 0). (2) Set VLCON to 1 and wait 500 ms or longer with software. (3) Set SCOC to 1. All the segment and common pins output an unselect waveform and are in unselect display mode. (4) Set LCDON to 1. The value of the display RAM is reflected on the segment output waveform, and all segment and common pins are in select display mode. * To stop LCD booster circuit while LCD displays (1) Clear LCDON to 0. All the segment and common pins are in unselect display mode. (2) Clear SCOC to 0. All the segment and common pins are in GND output mode. (3) Clear VLCON to 0. The LCD booster circuit stops. 2. The blinking cycle is generated using the interval time (0.5 s at 32.768 kHz) of the watch timer. When the blinking function is not used (BLON = 0), the LCD lights or extinguishes depending on the setting of the display RAM, as shown in Figure 17-3. To use the blinking function (BLON = 1), the LCD lights or extinguishes depending on the status of the internal blinking clock signal (set value of BLSEL), i.e., it lights if the internal blinking clock signal is "1" and extinguishes if the signal is "0". Figure 17-3. Blinking Function
0.5 s 0.5 s 0.5 s 0.5 s
Watch timer Interrupt internal blinking Clock signal display RAM
BLON
Display status
Extinguishes
Lights Display RAM
Extinguishes
Lights
Internal blinking clock signal
3. When using the blinking function, the LCD does not blink even if the data is rewritten while the LCD is in the extinguishing cycle (0.5 s or 1.0 s), unless the LCD is in the lighting cycle.
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(2) LCD clock control register 3 (LCDC3) This register is used to select an LCD source clock and frame frequency. It is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 17-4. LCD Clock Control Register 3 (LCDC3) Format
Address: FF91H After reset: 00H Symbol LCDC3 7 0 6 0 R/W 5 0 4 0 3 LCDC33 2 LCDC32 1 LCDC31 0 LCDC30
LCDC33 0 0 1 1
LCDC32 0 1 0 1 fXT fX/26 fX/27 fX/28 (32.768 kHz) (156.25 kHz) (78.125 kHz) (39.0625 kHz)
Source clock selection (fLCD)
LCDC31 0 0 1 1
LCDC30 0 1 0 1 fLCD/26 fLCD/27 fLCD/28 fLCD/29
Selection of reference clock generating frame frequency
Caution Do not rewrite LCDC3 while LCD is operating. Be sure to set this bit while LCDON = 0, SCOC = 0, and VLCON = 0. Remark Figures in parentheses are for operation with fX = 10 MHz or fXT = 32.768 kHz Table 17-4 shows the frame frequency if fXT (32.768 kHz) is used as the source clock (fLCD), and Figure 17-5 shows the relationship between the reference clock that generates the frame frequency, and the frame frequency. Table 17-4. Frame Frequency
Reference Clock Generating Frame Frequency Frame Frequency Display duty Static 1/3 duty 1/4 duty 64 Hz 21 Hz 16 Hz 128 Hz 43 Hz 32 Hz 256 HzNote 85 Hz 64 Hz 512 HzNote 171 HzNote 128 Hz fXT/29 fXT/28 fXT/27 fXT/26
Note Set so that the frame frequency is 128 Hz or less.
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Figure 17-5. Relationship Between Reference Clock Generating Frame Frequency, and Frame Frequency
tLCD
fLCD Static 3-time division 4-time division tFLAME tFLAME tFLAME
Remark fLCD: tLCD:
Reference clock that generates frame frequency LCD clock period
tFLAME: Frame period (3) Static/dynamic display switching register 3 (SDSEL3) This register is used to select the static or dynamic display mode of the segment pins (S0 to S11). It can be set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
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Figure 17-6. Static/Dynamic Display Switching Register 3 (SDSEL3) Format
Address: FF92H After reset: 00H Symbol SDSEL3 7 0 6 0 R/W 5 0 4 0 3 0 2 SDSEL32 1 SDSEL31 0 SDSEL30
Part Number
SDSEL32
SDSEL31
SDSEL30
Number of Segments (for Static Mode)
Number of Segments (for Dynamic Mode) S0 to S23 S4 to S23 S8 to S23 S12 to S23 --
PD780316,
780318
0 0 0 1
0 0 1 1
0 1 1 1 S0 to S3 S0 to S7 S0 to S11
--
Setting other than above is prohibited.
PD780326,
780328
0 0 0 1
0 0 1 1
0 1 1 1 S0 to S3 S0 to S7 S0 to S11
--
S0 to S31 S4 to S31 S8 to S31 S12 to S31 --
Setting other than above is prohibited.
PD780336,
780338, 78F0338
0 0 0 1
0 0 1 1
0 1 1 1 S0 to S3 S0 to S7 S0 to S11
--
S0 to S39 S4 to S39 S8 to S39 S12 to S39 --
Setting other than above is prohibited.
Caution Do not rewrite SDSEL while the LCD is operating. Be sure to set this bit while LCDON = 0, SCOC = 0, and VLCON = 0. Note that SDSEL can be set only once after reset.
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(4) Pin function switching registers 8 and 9 (PF8 and PF9)Note These registers are used to select whether the pins of ports 8 and 9 are used as port pins or segment pins. These registers can be set by an 8-bit memory manipulation instruction. RESET input sets the values of these registers to 00H. Note PD78F0338 only Figure 17-7. Pin Function Switching Registers 8 and 9 (PF8 and PF9) Format
Address: FF58H After reset: 00H Symbol PF8 7 PF87 6 PF86 5 PF85 W 4 PF84 3 PF83 2 PF82 1 PF81 0 PF80
Address: FF59H After reset: 00H Symbol PF9 7 PF97 6 PF96 5 PF95
W 4 PF94 3 PF93 2 PF92 1 PF91 0 PF90
PFn7 0
PFn6 0
PFn5 0
PFn4 0
PFn3 0
PFn2 0
PFn1 0
PFn0 0
Setting of pin Segment output (n = 8: S32 to S39, n = 9: S24 to S31)
1
1
1
1
1
1
1
1
Output port (n = 8: P87 to P80, n = 9: P97 to P90) Setting prohibited
Other than above
Caution PF8 and PF9 can be set to 00H or FFH only once after reset. Do not set any value other than 00H and FFH to these registers. Before changing the setting of these registers, reset the device.
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17.4 LCD Display RAM
The LCD display data and the LCD blinking select bits corresponding to LCD display data are mapped to addresses FA00H to FA27H. The lower 4 bits of each of these addresses are an LCD display data area, and the higher 4 bits are an LCD blinking select bit area. The LCD blinking select bits correspond to the LCD display data (i.e., LCD blinking select bit 0 corresponds to bit 4 of the LCD display data, bit 1 to bit 5, bit 2 to bit 6, and bit 3 to bit 7). The addresses and capacity of the area that can be used for LCD display differs depending on the product, as follows: * PD780316, 780318: * PD780326, 780328: FA00H to FA17A (24 bytes) FA00H to FA1FH (32 bytes)
* PD780336, 780338, 78F0338: FA00H to FA27H (40 bytes) The data stored to the LCD display data area can be displayed on the LCD panel. For example, bit 3 (shaded portion in Figure 17-8) of address FA01H is output to pin S1 at the timing of COM3. The LCD blinking select bit is used to blink the corresponding segment by setting 1 to the bit to blink, and 1 to bit 3 (BLON) of LCD display mode register 3 (LCDM3). In this case, however, the display data of the corresponding segment must be 1. Figure 17-8 shows the relationship between the LCD display data, contents of the blinking select bits, and segment/ common output signals. The area not used for display can be used as a normal RAM area. Figure 17-8. Relationship Between LCD Display Data, Contents of Blinking Select Bits, and Segment/Common Output Signals (4-Time Division)
LCD blinking select bit area
LCD display data area
Address FA00H FA01H FA02H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 S0 S1 S2
FA17H
FA1FH
FA26H FA27H
Caution The higher 4 bits (LCD blinking select bit area) of each address, FA00H to FA27H, correspond to the lower 4 bits (LCD display data area). When the LCD does not blink, therefore, be sure to clear the corresponding bit in the blinking select bit area to 0.

Example: The LCD blinking select bit corresponding to bit 0 at address FA00H is bit 4 at address FA00H.
S23
S31
S38 S39
COM3
COM2
COM1
COM0 SCOM0
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17.5 LCD Controller/Driver Settings
Set the LCD controller/driver as follows: (1) (2) (3) When using the PD78F0338, specify whether P80/S32 to P87/S39 and P90/S24 to P97/S31 are used as segment output pins or port output pins, by using pin function switching registers 8 and 9 (PF8 and PF9). Specify the display mode of the segment output pins (S0 to S11) by using static/dynamic display switching register 3 (SDSEL3). Set the displayed default value to the LCD display data area (bits 0 to 3) of the LCD display RAM. The addresses and capacity of the LCD display RAM that can be used in each device are as follows: * PD780316, 780318: * PD780326, 780328: FA00H to FA17H (24 bytes) FA00H to FA1FH (32 bytes)
* PD780336, 780338, 78F0338: FA00H to FA27H (40 bytes) To use the blinking function, set the corresponding bit of the blinking select bit area (bits 4 to 7) in the LCD display RAM to 1. (4) (5) (6) (7) (8) (9) Specify the display mode using bit 0 (LCDM0) of LCD display mode register 3 (LCDM3). Select the source clock and frame frequency of the LCD using LCD clock control register 3 (LCDC3). Set bit 5 (VLCON) of LCD display mode register 3 (LCDM3) to 1 to start the operation of the booster circuit. Make sure that a wait time of 500 ms or longer elapses with software. Set bit 6 (SCOC) of LCD display mode register 3 (LCDM3) to 1 so that unselect waveform is output to the segment pins and common pins. To use the blinking function, select a blinking cycle of 0.5 s or 1.0 s by using bit 4 (BLSEL) of LCD display mode register 3 (LCDM3). (10) Set bit 7 (LCDON) of LCD display mode register 3 (LCDM3) to 1 to set the display to ON. To blink the LCD, set bit 3 (BLON) of LCD display mode register 3 (LCDM3) to 1 to set the display to ON. Then, set data to the display data memory and timing of the blinking display according to the data to be displayed.
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17.6 Common Signals and Segment Signals
An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (depending on the panel), and extinguishes when the potential difference drops lower than VLCD. (1) Common signals For common signals, the selection timing order is as shown in Table 17-5 according to the number of time divisions set, and operations are repeated with these as the cycle. In the static mode, the same signal is output to SCOM0. With 3-time-division operation, the COM3 pin is left open. Table 17-5. COM Signals
COM Signal Time Division Static 3-time division 4-time division - - - - Open - - COM0 COM1 COM2 COM3 SCOM0
(2) Segment signals Segment signals correspond to a 40-byte LCD display RAM (FA00H to FA27HNote). Each display data memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the SCOM0/COM0, COM1, COM2 and COM3 timings respectively, and if the value of the bit is 1, it is converted to the selection voltage. If the value of the bit is 0, it is converted to the non-selection voltage and output to a segment pin (S0 to S39Note). Consequently, it is necessary to check what combination of front surface electrodes (corresponding to the segment signals) and rear surface electrodes (corresponding to the common signals) of the LCD display to be used form the display pattern, and then write bit data corresponding on a one-to-one basis with the pattern to be displayed. In addition, because LCD display RAM bits 1 to 3 are not used with the static method, these can be used for other than display purposes. LCD display RAM bits 4 to 7 are bits for LCD blinking selection. To use the LCD blinking function, set the relevant bit to 1. Note The segment signal output pins or the area that can be used as the LCD display data vary depending on the product.
Part Number Segment Signal Output Pins S0 to S23 S0 to S31 S0 to S39 S0 to S39 (S24 to S31, S32 to S39 are alternate with P90 to P97 and P80 to P87, respectively) Area That Can Be Used as LCD Display Data FA00H to FA17H FA00H to FA1FH FA00H to FA27H FA00H to FA27H (when ports 8 and 9 are used as the segment signal outputs)
PD780316, 780318 PD780326, 780328 PD780336, 780338 PD78F0338
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(3) Common signal and segment signal output waveforms The voltages shown in Figures 17-9 and 17-10 are output in the common signals and segment signals. The VLCD ON voltage is only produced when the common signal and segment signal are both at the selection voltage; other combinations produce the OFF voltage. Figure 17-9. Common Signal Waveform (a) Static display mode
VLCD0 SCOM0 (Static) VSS TF = T VLCD
T: One LCDCL cycle TF: Frame frequency (b) Dynamic display mode (1/3 bias method)
VLCD0 COMn (Divided by 3) VLCD1 VLCD VLCD2 VSS TF = 3 x T VLCD0 COMn (Divided by 4) VLCD1 VLCD2 VSS TF = 4 x T VLCD
T: One LCDCL cycle TF: Frame frequency
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Figure 17-10. Common Signal and Segment Signal Voltages and Phases (a) Static display mode
Selected Not selected VLCD0 Common signal VSS VLCD0 Segment signal VSS T T VLCD VLCD
Remark T: One LCDCL cycle (b) Dynamic display mode (1/3 bias method)
Selected
Not selected VLCD0 VLCD1 VLCD VLCD2 VSS VLCD0 VLCD1 VLCD VLCD2 VSS
Common signal
Segment signal
T
T
Remark
T: One LCDCL cycle
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17.7 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
The PD780338 contains a booster circuit (x3 only) to generate a supply voltage to drive the LCD. The internal LCD reference voltage (VLCD2) is output from the VLC2 pin. A voltage two times higher than that on VLCD2 is output from the VLC1 pin and a voltage three times higher than that on VLCD2 is output from the VLC0 pin. The LCD reference voltage (VLCD2) can be varied by connecting external resistors as shown in Figure 17-11. In addition, the PD780338 requires an external capacitor (recommended value: 0.47 F) because it employs a capacitance division method to generate a supply voltage to drive the LCD. Table 17-6. Output Voltages of VLC0 to VLC2 Pins
Output Voltage VLC0 pin VLC1 pin VLC2 pin 3 x VLCD2 2 x VLCD2 VLCD2
Cautions 1. When using the LCD function, do not open the VLCDC, VLC0, VLC1, and VLC2 pins. Refer to Figure 17-11 for connection. 2. A constant LCD drive voltage can be supplied regardless of changes in VDD. Remark For the LCD reference voltage (VLCD2), refer to LCD controller/driver characteristics in CHAPTER 24 ELECTRICAL SPECIFICATIONS. Figure 17-11. Example of Circuit to Adjust LCD Driver Reference Voltage
VLC0 VLC1 VLC2 R1 VLCDC R2 C2 C3 C4
CAPH C1 CAPL
C1 = C2 = C3 = C4 = 0.47 F External pin
Remark Use a capacitor with as little leakage as possible. Use a non-polarity capacitor as C1.
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External resistors (R1 and R2) must be connected as shown in Figure 17-11. The recommended resistance and capacitance are shown in the table below. To adjust the brightness, the user must adjust the ratio of R1 to R2 depending on the LCD panel to be used. * R1 + R2 = 3 [M] * C1 = C2 = C3 = C4 = 0.47 [F] VLCD2 can be adjusted by the division ratio of resistors R1 and R2. * VLCD2 = (R1 + R2)/R2 [V] * VLCD1 = 2 x VLCD2 [V] * VLCD0 = 3 x VLCD2 [V] Table 17-7. Recommended Constants of External Circuit
VLCD2 [V] VLCD0 = 3 [V] VLCD0 = 4.5 [V] 1 1.5 VLCD1 [V] 2 3 VLCD0 [V] 3 4.5 R1 [M] 0 1 R2 [M] 3 2
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17.8 Display Modes
17.8.1 Static display example Figure 17-13 shows the connection of a static type 1-digit LCD panel with the display pattern shown in Figure 1712 with the PD780338 Subseries segment (S0 to S11) and common (SCOM0) signals. The display example is "5", and the display data memory contents (addresses FA00H to FA07H) correspond to this. In accordance with the display pattern in Figure 17-12, selection and non-selection voltages must be output to pins S0 to S7 as shown in Table 17-8 at the SCOM0 common signal timing. At this time, set the SDSEL3 register to 03H to set pins S0 to S7 to the static display mode. Table 17-8. Selection and Non-Selection Voltages (SCOM0)
Segment Common SCOM0 NS S NS S S S NS S S0 S1 S2 S3 S4 S5 S6 S7
S: Selection, NS: Non-selection From this, it can be seen that 01011101 must be prepared in the bit 0 of the display data memory (addresses FA00H to FA07H) corresponding to S0 to S7. The LCD drive waveforms for S1, S2, and SCOM0 are shown in Figure 17-14. When S1 is at the selection voltage at the timing for selection with SCOM0, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Figure 17-12. Static LCD Panel Display Pattern and Electrode Connections
S3
S4
S2 S5 SCOM0
S6
S1 S0
S7
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Figure 17-13. Static LCD Panel Connection Example (SDSEL3n = 1: n = 0, 1)
Timing strobe
SCOM0
BIT3 BIT2 BIT1 BIT0
FA00H
Data memory address
0
x
x
x
S0 S1 S2 S3 S4 S5 S6 S7
LCD panel
2 3 4 5 6 7
296
1
x
x
x
0
x
x
x
1
x
x
x
1
x
x
x
1
x
x
x
01
xx
xx
xx
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Figure 17-14. Static LCD Drive Waveform Examples
TF VLC0 SCOM0 VSS0
VLC0 S1 VSS0
VLC0 S2 VSS0
+VLCD Display waveform SCOM0-S1 0 -VLCD
+VLCD Non-display waveform SCOM0-S2 0 -VLCD
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17.8.2 3-time-division display example Figure 17-16 shows the connection of a 3-time-division type 13-digit LCD panel with the display pattern shown in Figure 17-15 with the PD780338 Subseries segment signals (S0 to S38) and common signals (COM0 to COM2). The display example is "123456.7890123," and the display data memory contents (addresses FA00H to FA26H) correspond to this. An explanation is given here taking the example of the eighth digit "6." ( the COM0 to COM2 common signal timings. Table 17-9. Selection and Non-Selection Voltages (COM0 to COM2)
Segment Common COM0 COM1 COM2 NS S S S S S S S -- S21 S22 S23
). In accordance with the display pattern
in Figure 17-15, selection and non-selection voltages must be output to pins S21 to S23 as shown in Table 17-9 at
S: Selection, NS: Non-selection From this, it can be seen that x110 must be prepared in the display data memory (address FA15H) corresponding to S21. Examples of the LCD drive waveforms between S21 and the common signals are shown in Figure 17-17 (1/3 bias method). When S21 is at the selection voltage at the COM1 selection timing, and S21 is at the selection voltage at the COM2 selection timing, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Figure 17-15. 3-Time-Division LCD Display Pattern and Electrode Connections
S3n + 1 COM0
S3n + 2
Remark n = 0 to 12
; ; ;; ; ;; ;
S3n
;;;; ;;;; ;; ;;;;
COM1 COM2
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Figure 17-16. 3-Time-Division LCD Panel Connection Example (SDSEL3n = 0: n = 0 to 2)
Timing strobes
COM3 COM2 COM1 COM0
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BIT3 0 BIT2 1 BIT1 1 BIT0
Open
FA00H 1 2 3 4 5 6 7 8 9 A B C D E
Data memory addresses
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38
LCD panel
0 X' 1 0 X' 0 0 X' 1 0 X' 1 0 X' 0
1 0 0 0 1 0 1 1 1 111 0 1 0
0 X' 1 11
111
F FA10H 1 2 3 4 5 6 7 8 9 A B C D E F FA20H 1 2 3 4 5 6 FA27H
1
1
1
1
1
1
0
0
1
0
1
1
0
1
S17
1 X' 0 0 X' 1 0 X' 0 0 X' 1 0 X' 1 0 X' 1 X' 0
1 0 0 1 1 1 1 1 0 11 0 1 01 0 1 1 1 0 0
Remarks 1. X': Irrelevant bits because they have no corresponding segment in the LCD panel 2. X: Irrelevant bits because this is a 3-time-division display
0
0
1
0
1
1
01
1
1
01
1
1
0
1
1
0
1
1
1
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Figure 17-17. 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
TF VLC0 COM0 VLC1 VLC2 VSS
VLC0 COM1 VLC1 VLC2 VSS
VLC0 COM2 VLC1 VLC2 VSS
VLC0 S21 VLC1 VLC2 VSS
+VLCD
+1/3VLCD COM0-S21 0 -1/3VLCD
-VLCD
+VLCD
+1/3VLCD COM1-S21 0 -1/3VLCD
-VLCD
+VLCD
+1/3VLCD COM2-S21 0 -1/3VLCD
-VLCD
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17.8.3 4-time-division display example Figure 17-19 shows the connection of a 4-time-division type 20-digit LCD panel with the display pattern shown in Figure 17-18 with the PD780338 Subseries segment signals (S0 to S39) and common signals (COM0 to COM3). The display example is "123456.78901234567890," and the display data memory contents (addresses FA00H to FA27H) correspond to this. An explanation is given here taking the example of the 15th digit "6." ( at the COM0 to COM3 common signal timings. Table 17-10. Selection and Non-Selection Voltages (COM0 to COM3)
Segment Common COM0 COM1 COM2 COM3 S NS S S S S S S S28 S29
). In accordance with the display pattern
in Figure 17-18, selection and non-selection voltages must be output to pins S28 and S29 as shown in Table 17-10
S: Selection, NS: Non-selection From this, it can be seen that 1101 must be prepared in the display data memory (address FA1CH) corresponding to S28. Examples of the LCD drive waveforms between S28 and the COM0 and COM1 signals are shown in Figure 1720 (for the sake of simplicity, waveforms for COM2 and COM3 have been omitted). When S28 is at the selection voltage at the COM0 selection timing, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Figure 17-18. 4-Time-Division LCD Display Pattern and Electrode Connections
S2n
Remark n = 0 to 18
;; ; ;;;;; ;;;;
S2n + 1
COM0
COM2
;; ;; ;; ;;
COM1
COM3
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Figure 17-19. 4-Time-Division LCD Panel Connection Example (SDSEL3n = 0, n = 0 to 2)
Timing strobes
COM3 COM2 COM1 COM0
BIT3 BIT2 BIT1 BIT0
FA00H 1 2 3 4 5 6 7 8 9 A B C D E
Data memory addresses
0
1
1
1
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39
LCD panel
1
1 1 0 1 1 1 0 1 11 0 1 0 1 100
0 1 1 1 1 1 0 0 01 1 1 1 1 111
0
0
0
1
0
0
0
01
1
0
0
0
101
010
F FA10H 1 2 3 4 5 6 7 8 9 A B C D E F FA20H 1 2 3 4 5 6 FA27H
1
1
0
1
11
1
1
1
1
1
1
1
1
S17
0
1 0 1 1 1 0 1 1 1 10 1 1 10 0 1 0 0 1 1 0
0
1 0 1 0 1 1 1 1 1 00 1 0 11 1 1 1 1 1 1 0
0
1
0
0
0
1
0
10
1
0
01
0
0
1
0
1
0
0
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0
1
1
01
1
1
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1
1
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Figure 17-20. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
COM0
; ;
TF
; ;
VLC0 VLC1 VLC2 VSS
VLC0 COM1 VLC1 VLC2 VSS
VLC0 COM2 VLC1 VLC2 VSS
VLC0 COM3 VLC1 VLC2 VSS
VLC0 S28 VLC1 VLC2 VSS
+VLCD
+1/3VLCD COM0-S28 0 -1/3VLCD
-VLCD
+VLCD
+1/3VLCD COM1-S28 0 -1/3VLCD
-VLCD
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17.8.4 Simultaneous driving of static display and dynamic display Simultaneous driving of static display (S0 to S11) and dynamic display is possible with the PD780338. Refer to Figure 17-6 for register settings.
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18.1 Interrupt Function Types
The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in an interrupt disabled state. It does not undergo priority control and is given top priority over all other interrupt requests. A standby release signal is generated. One interrupt request from the watchdog timer is incorporated as a non-maskable interrupt. (2) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L). Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (see Table 18-1). A standby release signal is generated. Seven external interrupt requests and 15 internal interrupt requests are incorporated as maskable interrupts. (3) Software interrupt This is a vectored interrupt to be generated by executing the BRK instruction. It is acknowledged even in an interrupt disabled state. The software interrupt does not undergo interrupt priority control.
18.2 Interrupt Sources and Configuration
A total of 24 interrupt sources exist among non-maskable, maskable, and software interrupts (see Table 18-1). Remark As the watchdog timer interrupt source (INTWDT), a non-maskable interrupt or maskable interrupt (internal) can be selected.
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Table 18-1. Interrupt Source List
Interrupt Type Default PriorityNote 1 Name Nonmaskable Maskable -- INTWDT Interrupt Source Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H Detection of port 4 falling edge Serial interface (UART0) reception error generation End of serial interface (UART0) reception End of serial interface (UART0) transmission End of serial interface (CSI1) transfer End of serial interface (SIO3) transfer Reference time interval signal from watch timer Match between TM00 and CR00 (when CR00 is specified as compare register) Detection of TI01 valid edge (when CR00 is specified as capture register) Match between TM00 and CR01 (when CR01 is specified as compare register) Detection of TI00 valid edge (when CR01 is specified as capture register) Match between TM4 and CR4 (when clear & start mode is selected by match between TM4 and CR4) Match between TM50 and CR50 Match between TM51 and CR51 Match between TM52 and CR52 End of A/D converter conversion Watch timer overflow BRK instruction execution -- Internal 0012H 0014H (D) (B) Internal Internal/ External Vector Table Address 0004H Basic Configuration TypeNote 2 (A)
0
INTWDT
(B)
1 2 3 4 5 6 7 8
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTKR INTSER0
(C)
9 10 11 12 13 14
INTSR0 INTST0 INTCSI1 INTCSI3 INTWTNI0 INTTM00
0016H 0018H 001AH 001CH 001EH 0020H
15
INTTM01
0022H
16
INTTM4
0024H
17 18 19 20 21 Software --
INTTM50 INTTM51 INTTM52 INTAD0 INTWTN0 BRK
0026H 0028H 002AH 002CH 002EH 003EH (E)
Notes 1. The default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 21 is the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 18-1.
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Figure 18-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority controller
Vector table address generator
Standby release signal
(C) External maskable interrupt (INTP0 to INTP5)
Internal bus
External interrupt edge enable register (EGP, EGN)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority controller
Vector table address generator
Standby release signal
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Figure 18-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (INTKR)
Internal bus
MK
IE
PR
ISP
Interrupt request
Falling edge detector
IF
Priority controller
Vector table address generator
"1" when MEM = 01H Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator
IF: IE: ISP: MK: PR:
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
MEM: Memory expansion mode register
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18.3 Interrupt Function Control Registers
The following six types of registers are used to control the interrupt functions. * * * * * * Interrupt request flag registers (IF0L, IF0H, IF1L) Interrupt mask flag registers (MK0L, MK0H, MK1L) Priority specification flag registers (PR0L, PR0H, PR1L) External interrupt rising edge enable register (EGP) External interrupt falling edge enable register (EGN) Program status word (PSW)
Table 18-2 gives a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 18-2. Flags Corresponding to Interrupt Request Sources
Interrupt Source Interrupt Request Flag Register INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTKR INTSER0 INTSR0 INTST0 INTCSI1 INTCSI3 INTWTNI0 INTTM00 INTTM01 INTTM4 INTTM50 INTTM51 INTTM52 INTAD0 INTWTN0 WDTIFNote PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 KRIF SERIF0 SRIF0 STIF0 CSIIF1 CSIIF3 WTNIIF0 TMIF00 TMIF01 TMIF4 TMIF50 TMIF51 TMIF52 ADIF0 WTNIF0 IF1L IF0H IF0L WDTMKNote PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 KRMK SERMK0 SRMK0 STMK0 CSIMK1 CSIMK3 WTNIMK0 TMMK00 TMMK01 TMMK4 TMMK50 TMMK51 TMMK52 ADMK0 WTNMK0 MK1L MK0H Interrupt Mask Flag Register MK0L WDTPRNote PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 KRPR SERPR0 SRPR0 STPR0 CSIPR1 CSIPR3 WTNIPR0 TMPR00 TMPR01 TMPR4 TMPR50 TMPR51 TMPR52 AD0 WTNPR0 PR1L PR0H Priority Specification Flag Register PR0L
Note Interrupt control flag when the watchdog timer is used as interval timer
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are combined to form 16-bit register IF0, they are set by a 16-bit memory manipulation instruction. RESET input sets the values of these registers to 00H. Figure 18-2. Interrupt Request Flag Registers (IF0L, IF0H, IF1L) Format
Address: FFE0H After reset: 00H R/W Symbol IF0L 7 KRIF 6 PIF5 5 PIF4 4 PIF3 3 PIF2 2 PIF1 1 PIF0 0 WDTIF
Address: FFE1H After reset: 00H R/W Symbol IF0H 7 TMIF01 6 TMIF00 5 WTNIIF0 4 CSIIF3 3 CSIIF1 2 STIF0 1 SRIF0 0 SERIF0
Address: FFE2H After reset: 00H R/W Symbol IF1L 7 0 6 0 5 WTNIF0 4 ADIF0 3 TMIF52 2 TMIF51 1 TMIF50 0 TMIF4
XXIFX 0 1
Interrupt request flag No interrupt request signal is generated Interrupt request signal is generated, interrupt request status
Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as the interval timer. If watchdog timer mode 1 is used, set the WDTIF flag to 0. 2. Be sure to set bits 6 and 7 of IF1L to 0. 3. When operating a timer, serial interface, or A/D converter after standby release, run it once after clearing an interrupt request flag. An interrupt request flag may be set by noise. 4. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is started.
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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt service. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register MK0, they are set by a 16-bit memory manipulation instruction. RESET input sets the values of these registers to FFH. Figure 18-3. Interrupt Mask Flag Registers (MK0L, MK0H, MK1L) Format
Address: FFE4H After reset: FFH R/W Symbol MK0L 7 KRMK 6 PMK5 5 PMK4 4 PMK3 3 PMK2 2 PMK1 1 PMK0 0 WDTMK
Address: FFE5H After reset: FFH R/W Symbol MK0H 7 TMMK01 6 TMMK00 5 WTNIMK0 4 CSIMK3 3 CSIMK1 2 STMK0 1 SRMK0 0 SERMK0
Address: FFE6H After reset: FFH R/W Symbol MK1L 7 1 6 1 5 WTNMK0 4 ADMK0 3 TMMK52 2 TMMK51 1 TMMK50 0 TMMK4
XXMKX 0 1 Interrupt servicing enabled Interrupt servicing disabled
Interrupt servicing control
Cautions 1. If the watchdog timer is used in watchdog timer mode 1, the contents of the WDTMK flag become undefined when read. 2. Because port 0 pins have an alternate function as external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. Be sure to set bits 6 and 7 of MK1L to 1.
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(3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction. RESET input sets the values of these registers to FFH. Figure 18-4. Priority Specification Flag Registers (PR0L, PR0H, PR1L) Format
Address: FFE8H After reset: FFH R/W Symbol PR0L 7 KRPR 6 PPR5 5 PPR4 4 PPR3 3 PPR2 2 PPR1 1 PPR0 0 WDTPR
Address: FFE9H After reset: FFH R/W Symbol PR0H 7 TMPR01 6 TMPR00 5 WTNIPR0 4 CSIPR3 3 CSIPR1 2 STPR0 1 SRPR0 0 SERPR0
Address: FFEAH After reset: FFH R/W Symbol PR1L 7 1 6 1 5 WTNPR0 4 ADPR0 3 TMPR52 2 TMPR51 1 TMPR50 0 TMPR4
XXPRX 0 1 High priority level Low priority level
Priority level selection
Cautions 1. When the watchdog timer is used in the watchdog timer mode 1, set 1 in the WDTPR flag. 2. Be sure to set bits 6 and 7 of PR1L to 1.
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(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP5. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the values of these registers to 00H. Figure 18-5. External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Format
Address: FF48H After reset: 00H R/W Symbol EGP 7 0 6 0 5 EGP5 4 EGP4 3 EGP3 2 EGP2 1 EGP1 0 EGP0
Address: FF49H After reset: 00H R/W Symbol EGN 7 0 6 0 5 EGN5 4 EGN4 3 EGN3 2 EGN2 1 EGN1 0 EGN0
EGPn 0 0 1 1
EGNn 0 1 0 1
INTPn pin valid edge selection (n = 0 to 5) Interrupt disable Falling edge Rising edge Both rising and falling edges
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(5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for an interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control nesting processing are mapped. Besides 8-bit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are reset from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets the value of PSW to 02H. Figure 18-6. Program Status Word Format
7 PSW IE 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY After reset 02H Used when normal instruction is executed ISP 0 Priority of interrupt currently being serviced High-priority interrupt servicing (Low-priority interrupt disable) Interrupt request not acknowledged, or lowpriority interrupt servicing (All maskable interrupts enable)
1
IE 0 1
Interrupt request acknowledge enable/disable Disable Enable
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18.4 Interrupt Servicing Operations
18.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag and ISP flag are reset (0), and the contents of the vector table are loaded into PC and branched. A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following RETI instruction execution) and one main routine instruction is executed. However, if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one nonmaskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program execution. Figures 18-7, 18-8, and 18-9 show the flowchart of the non-maskable interrupt request generation through acknowledge, acknowledge timing of non-maskable interrupt request, and acknowledge operation at multiple nonmaskable interrupt request generation, respectively.
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Figure 18-7. Non-Maskable Interrupt Request Generation to Acknowledge Flowchart
Start
WDTM4 = 1 (with watchdog timer mode selected)?
No Interval timer
Yes
Overflow in WDT?
No
Yes
WDTM3 = 0 (with non-maskable interrupt selected)?
No Reset processing
Yes Interrupt request generation
WDT interrupt servicing? Yes Interrupt control register not accessed? Yes Start of interrupt servicing WDTM: Watchdog timer mode register WDT: Watchdog timer
No
Interrupt request held pending
No
Figure 18-8. Non-Maskable Interrupt Request Acknowledge Timing
PSW and PC save, jump to interrupt servicing Interrupt service program
CPU processing
Instruction
Instruction
WDTIF Interrupt request generated during this interval is acknowledged at WDTIF: Watchdog timer interrupt request flag .
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Figure 18-9. Non-Maskable Interrupt Request Acknowledge Operation (a) If a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution
Main routine
NMI request <1> NMI request <2> Execution of 1 instruction
Execution of NMI request <1> NMI request <2> held pending
Servicing of NMI request <2> that was pended
(b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution
Main routine
NMI request <1> NMI request <2> Execution of 1 instruction NMI request <3>
Execution of NMI request <1> NMI request <2> held pending NMI request <3> held pending
Servicing of NMI request <2> that was pended
NMI request <3> not acknowledged (Although two or more NMI requests have been generated, only one request is acknowledged.)
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18.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt enable state (when IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 18-3 below. For the interrupt request acknowledge timing, see Figures 18-11 and 18-12. Table 18-3. Times from Generation of Maskable Interrupt Until Servicing
Minimum Time When xxPR = 0 When xxPR = 1 7 clocks 8 clocks Maximum TimeNote 32 clocks 33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more maskable interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 18-10 shows the interrupt request acknowledge algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded into PC and branched. Return from an interrupt is possible with the RETI instruction.
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Figure 18-10. Interrupt Request Acknowledge Processing Algorithm
Start
No
xxIF = 1? Yes (Interrupt request generation)
No
xxMK = 0? Yes
Interrupt request held pending Yes (High priority)
xxPR = 0? No (Low priority)
Yes
Any high-priority interrupt request among those simultaneously generated with xxPR = 0?
Interrupt request held pending No No IE = 1? Yes
Any high-priority interrupt request among those simultaneously generated with xxPR = 0?
Yes
No
Any high-priority interrupt request among those simultaneously generated?
Interrupt request held pending
Yes
Interrupt request held pending
No Vectored interrupt servicing IE = 1? Yes ISP = 1? Yes
Interrupt request held pending No
Interrupt request held pending No
Interrupt request held pending
Vectored interrupt servicing
xxIF:
Interrupt request flag
xxMK: Interrupt mask flag xxPR: Priority specification flag IE: ISP: Flag that controls acknowledge of maskable interrupt request (1 = enable, 0 = disable) Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledged, or low-priority interrupt servicing)
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Figure 18-11. Interrupt Request Acknowledge Timing (Minimum Time)
6 clocks CPU processing xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks Instruction Instruction
PSW and PC save, jump to interrupt servicing
Interrupt servicing program
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
Figure 18-12. Interrupt Request Acknowledge Timing (Maximum Time)
25 clocks CPU processing xxIF (xxPR = 1) 33 clocks xxIF (xxPR = 0) 32 clocks Instruction Divide instruction 6 clocks
PSW and PC save, jump to interrupt servicing
Interrupt servicing program
Remark 1 clock: 1/fCPU (fCPU: CPU clock) 18.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into PC and branched. Return from a software interrupt is possible with the RETB instruction. Caution Do not use the RETI instruction for returning from the software interrupt.
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18.4.4 Nesting processing Nesting occurs when another interrupt request is acknowledged during execution of an interrupt. Nesting does not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except nonmaskable interrupts). Also, when an interrupt request is acknowledged, interrupt request acknowledge becomes disabled (IE = 0). Therefore, to enable nesting, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledge. Moreover, even if interrupts are enabled, nesting may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for nesting. In the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for nesting. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for nesting. Interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending. When servicing of the current interrupt ends, the pended interrupt request is acknowledged following execution of one main processing instruction execution. Nesting is not possible during non-maskable interrupt servicing. Table 18-4 shows interrupt requests enabled for nesting and Figure 18-13 shows nesting examples. Table 18-4. Interrupt Request Enabled for Nesting During Interrupt Servicing
Nesting Request Non-Maskable Interrupt Request Maskable Interrupt Request PR = 0 Interrupt Being Serviced Non-maskable interrupt Maskable interrupt ISP = 0 ISP = 1 Software interrupt x IE = 1 x IE = 0 x x x x PR = 1 IE = 1 x x IE = 0 x x x x
Remarks 1.
: Nesting enabled
2. x: Nesting disabled 3. ISP and IE are flags contained in PSW. ISP = 0: An interrupt with higher priority is being serviced. ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0: IE = 1: PR = 0: PR = 1: Interrupt request acknowledge is disabled. Interrupt request acknowledge is enabled. Higher priority level Lower priority level
4. PR is a flag contained in PR0L, PR0H, and PR1L.
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Figure 18-13. Nesting Examples (1/2) Example 1. Nesting occurs twice
Main processing INTxx servicing INTyy servicing INTzz servicing
EI
IE = 0 EI INTyy (PR = 0)
IE = 0 EI INTzz (PR = 0)
IE = 0
INTxx (PR = 1)
RETI
RETI
RETI
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and nesting takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledge. Example 2. Nesting does not occur due to priority control
Main processing INTxx servicing INTyy servicing
EI
IE = 0 EI
INTxx (PR = 0)
INTyy (PR = 1)
RETI
1 instruction execution
IE = 0
RETI
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and nesting does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: Interrupt request acknowledge disabled
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Figure 18-13. Nesting Examples (2/2) Example 3. Nesting does not occur because interrupt is not enabled
Main processing IE = 0 EI INTyy (PR = 0) RETI INTxx servicing INTyy servicing
INTxx (PR = 0)
1 instruction execution
IE = 0
RETI
Interrupt is not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and nesting does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level IE = 0: Interrupt request acknowledge disabled
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18.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. * * * * * * * * * * * * * * * * * * * * MOV PSW, #byte MOV A, PSW MOV PSW, A MOV1 PSW.bit, CY MOV1 CY, PSW.bit AND1 CY, PSW.bit OR1 CY, PSW.bit XOR1 CY, PSW.bit SET1 PSW.bit CLR1 PSW.bit RETB RETI PUSH PSW POP PSW BT PSW.bit, $addr16 BF PSW.bit, $addr16 BTCLR PSW.bit, $addr16 EI DI Manipulate instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L registers.
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. However, a non-maskable interrupt request is acknowledged. Figure 18-14 shows the timing with which interrupt requests are held pending. Figure 18-14. Interrupt Request Hold
Save PSW and PC, jump to interrupt servicing Interrupt servicing program
CPU processing
Instruction N
Instruction M
xxIF
Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request).
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STANDBY FUNCTION
19.1 Standby Function and Configuration
19.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating. In this mode, current consumption is not decreased as much as in the STOP mode. However, the HALT mode is effective to restart operation immediately upon interrupt request and to carry out intermittent operations such as watch applications. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU power consumption. Data memory low-voltage hold (down to VDD = 1.6 V) is possible. Thus, the STOP mode is effective to hold data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure an oscillation stabilization time after the STOP mode is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latch and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). The HALT mode can be used with either the main system clock or the subsystem clock. 2. When operation is transferred to the STOP mode, be sure to stop the peripheral hardware operation and execute the STOP instruction. 3. The following sequence is recommended for power consumption reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS0) of the A/D converter mode register 0 (ADM0) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction.
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19.1.2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 04H. Figure 19-1. Oscillation Stabilization Time Select Register (OSTS) Format
Address: FFFAH After reset: 04H R/W Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0
OSTS2 0 0 0 0 1
OSTS1 0 0 1 1 0 Other than above
OSTS0 0 1 0 1 0
Oscillation stabilization time selection 212/fX (410 s) 214/fX (1.64 ms) 215/fX (3.28 ms) 216/fX (6.55 ms) 217/fX (13.1 ms) Setting prohibited
Caution The wait time after the STOP mode is cleared does not include the time (see "a" in the illustration below) from STOP mode clear to clock oscillation start. The time is not included either by RESET input or by interrupt request generation.
STOP mode clear X1 pin voltage waveform a VSS
Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses are for operation with fX = 10 MHz.
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19.2 Standby Function Operations
19.2.1 HALT mode (1) HALT mode setting and operating statuses The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating statuses in the HALT mode are described below. Table 19-1. HALT Mode Operating Statuses
HALT Mode Setting During HALT Instruction Execution Using Main System Clock Without Subsystem ClockNote 1 With Subsystem ClockNote 2 During HALT Instruction Execution Using Subsystem Clock With Main System Clock Oscillation With Main System Clock Oscillation Stopped
Item Clock generator CPU Port (output latch) 16-bit timer/event counter 0 16-bit timer/event counter 4 8-bit timer/event counters 50, 51, 52
Both main system clock and subsystem clock can be oscillated. Clock supply to CPU stops. Operation stops. Status before HALT mode setting is held. Operable Operation stops.
Operable
Operable when TI4 is selected as count clock. Operable when TI50, TI51, and TI52 are selected as count clock. Operable Operable when fXT is selected as count clock. Operation stops. Operable when fXT is selected as count clock. Operation stops.
Operable
Watch timer
Operable when fX/28 is selected as count clock. Operable Operable
Watchdog timer Clock output
Buzzer output A/D converter D/A converter Serial interface UART0 Serial interface CSI1 Serial interface SIO3 LCD controller/driver Operable when fX/26 to fX/28 is selected as count clock. Operable Operation stops. Operation stops. Operable
Operation stops.
Operable with external SCK. Operable when fXT is selected as count clock.
Notes 1. Including case when external clock is not supplied. 2. Including case when external clock is supplied.
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(2) HALT mode release The HALT mode can be released with the following three types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledge is enabled, vectored interrupt service is carried out. If interrupt acknowledge is disabled, the next address instruction is executed. Figure 19-2. HALT Mode Release by Interrupt Request Generation
Interrupt request HALT instruction Standby release signal Operation mode HALT mode Oscillation Wait Operation mode Wait
Clock
Remarks 1. The broken line indicates the case when the interrupt request which has released the standby mode is acknowledged. 2. Wait times are as follows: * When vectored interrupt service is carried out: 8 or 9 clocks * When vectored interrupt service is not carried out: 2 or 3 clocks (b) Release by non-maskable interrupt request When a non-maskable interrupt request is generated, the HALT mode is released and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled.
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(c) Release by RESET input When RESET signal is input, HALT mode is released. And, as in the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 19-3. HALT Mode Release by RESET Input
Wait (217/fX: 13.1 ms)
HALT instruction
RESET signal Operation mode HALT mode Oscillation Reset period Oscillation stop Oscillation stabilization wait status Oscillation Operation mode
Clock
Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses are for operation with fX = 10 MHz. Table 19-2. Operation After HALT Mode Release
Release Source Maskable interrupt request MKxx 0 0 0 0 0 1 Non-maskable interrupt request RESET input -- -- PRxx 0 0 1 1 1 x -- -- IE 0 1 0 x 1 x x x ISP x x 1 0 1 x x x Interrupt service execution HALT mode hold Interrupt service execution Reset processing Operation Next address instruction execution Interrupt service execution Next address instruction execution
x: Don't care
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19.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD1 via a pull-up resistor to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait set using the oscillation stabilization time select register (OSTS), the operation mode is set. The operating statuses in the STOP mode are described below. Table 19-3. STOP Mode Operating Statuses
STOP Mode Setting Item Clock generator CPU Port (output latch) 16-bit timer/event counter 0 16-bit timer/event counter 4 8-bit timer/event counters 50, 51, 52 Watch timer Only main system clock oscillation is stopped. Operation stops. Status before STOP mode setting is held. Operation stops. Operable when TI4 is selected as count clock. Operable when TI50, TI51, and TI52 are selected as count clock. Operable when fXT is selected as count clock. Operation stops. PCL is low BUZ is low Operation stops. Operation stops. With Subsystem Clock Without Subsystem Clock
Watchdog timer Clock output Buzzer output A/D converter D/A converter Serial interface UART0
Operation stops (transmit shift register 0 (TXS0), receive shift register 0 (RX0), and receive buffer register 0 (RXB0) hold the value just before the clock stop). Operable only when externally input clock is selected as serial clock.
Serial interface CSI1 Serial interface SIO3 LCD controller/driver
Operable when fXT is selected as count clock.
Operation stops.
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(2) STOP mode release The STOP mode can be released by the following two types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt acknowledge is disabled, the next address instruction is executed. Figure 19-4. STOP Mode Release by Interrupt Request Generation
Interrupt request STOP instruction Standby release signal Operation mode Oscillation STOP mode Oscillation stop Oscillation stabilization wait status Oscillation Operation mode
Wait (Time set by OSTS)
Clock
Remark The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged.
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(b) Release by RESET input The STOP mode is released when RESET signal is input, and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 19-5. STOP Mode Release by RESET Input
Wait (217/fX: 13.1 ms)
STOP instruction
RESET signal Operation mode Oscillation STOP mode Oscillation stop Reset period Oscillation stabilization wait status Oscillation Operation mode
Clock
Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses are for operation with fX = 10 MHz. Table 19-4. Operation After STOP Mode Release
Release Source Maskable interrupt request MKxx 0 0 0 0 0 1 RESET input -- PRxx 0 0 1 1 1 x -- IE 0 1 0 x 1 x x ISP x x 1 0 1 x x Interrupt service execution STOP mode hold Reset processing Operation Next address instruction execution Interrupt service execution Next address instruction execution
x: Don't care
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RESET FUNCTION
20.1 Reset Function
The following two operations are available to generate the reset signal. (1) (2) External reset input via RESET pin Internal reset by watchdog timer runaway time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in Table 20-1. Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217/fX. The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 217/fX (see Figures 20-2 to 20-4). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pin becomes high-impedance. Figure 20-1. Reset Function Block Diagram
RESET
Reset controller
Reset signal
Count clock
Watchdog timer Stop
Overflow
Interrupt function
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Figure 20-2. Timing of Reset by RESET Input
X1 Reset period (Oscillation stop) Oscillation stabilization time wait Normal operation (Reset processing)
Normal operation RESET
Internal reset signal Delay Port pin Delay Hi-Z
Figure 20-3. Timing of Reset Due to Watchdog Timer Overflow
X1 Reset period (Oscillation stop) Oscillation stabilization time wait Normal operation (Reset processing)
Normal operation Watchdog timer overflow Internal reset signal
Port pin
Hi-Z
Figure 20-4. Timing of Reset in STOP Mode by RESET Input
X1
STOP instruction execution
Normal operation RESET
Stop status (Oscillation stop)
Reset period (Oscillation stop)
Oscillation stabilization time wait
Normal operation (Reset processing)
Internal reset signal Delay Port pin Delay Hi-Z
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Table 20-1. Hardware Statuses After Reset (1/2)
Hardware Program counter (PC)Note 1 Status After Reset Contents of reset vector table (0000H, 0001H) are set. Undefined 02H Data memory General-purpose register Port (output latch) Port mode registers 0, 2 to 7, 8Note 5, 9Note 5, 12 (PM0, PM2 to PM7, PM8Note 5, PM9Note 5, PM12) Pull-up resistor option registers 0, 2 to 7, 12 (PU0, PU2 to PU7, PU12) Processor clock control register (PCC) Memory size switching register (IMS) Internal expansion RAM size switching register (IXS) Memory expansion mode register (MEM) Key return switching register (KRSEL) Pin function switching registers 8, 9 (PF8, PF9)Note 5 UndefinedNote 2 UndefinedNote 2 00H FFH 00H 04H CFHNote 3 0CHNote 4 00H 00H 00H 04H 0000H Undefined 00H 00H 00H 00H Undefined Undefined 00H 00H Undefined 00H 00H
Stack pointer (SP) Program status word (PSW) RAM
Oscillation stabilization time select register (OSTS) 16-bit timer/event counter 0 Timer counter 0 (TM0) Capture/compare registers 00, 01 (CR00, CR01) Prescaler mode register 0 (PRM0) Mode control register 0 (TMC0) Capture/compare control register 0 (CRC0) Output control register 0 (TOC0) 16-bit timer/event counter 4 Timer counter 4 (TM4) Compare register 4 (CR4) Mode control register 4 (TMC4) 8-bit timer/event counters 50 to 52 Timer counters 50 to 52 (TM50 to TM52) Compare registers 50 to 52 (CR50 to CR52) Clock select registers 50 to 52 (TCL50 to TCL52) Mode control registers 50 to 52 (TMC50 to TMC52)
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. When a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. Although the initial value is CFH, use the following value to be set for each version.
PD780316, 780326, 780336: CCH PD780318, 780328, 780338: CFH PD78F0338:
5. PD78F0338 only. Value for mask ROM versions 4. Although the initial value is 0CH, use this register with a setting of 09H.
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Table 20-1. Hardware Statuses After Reset (2/2)
Hardware Watch timer Watchdog timer Operation mode register 0 (WTNM0) Clock select register (WDCS) Mode register (WDTM) Clock output/buzzer output controller A/D converter Conversion result register 0 (ADCR0) Mode register 0 (ADM0) Analog input channel specification register 0 (ADS0) D/A converter Conversion value setting register 0 (DA0) Mode register 0 (DAM0) Serial interface UART0 Asynchronous serial interface mode register 0 (ASIM0) Asynchronous serial interface status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Transmit shift register 0 (TXS0) Receive buffer register 0 (RXB0) Serial interface CSI1 Shift register 1 (SIO1) Transmit buffer register 1 (SOTB1) Operation mode register 1 (CSIM1) Clock select register 1 (CSIC1) Serial interface SIO3 Shift register 3 (SIO3) Operation mode register 3 (CSIM3) LCD controller/driver Operation/display mode register 3 (LCDM3) Clock control register 3 (LCDC3) Static/dynamic display switching register 3 (SDSEL3) Interrupt Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L) Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L) Priority specification flag registers 0L, 0H, 1L (PR0L, PR0H, PR1L) External interrupt rising edge enable register (EGP) External interrupt falling edge enable register (EGN) ROM correction Correction address registers 0, 1 (CORAD0, CORAD1) Correction control register (CORCN) Undefined Undefined 00H 10H Undefined 00H 00H 00H 00H 00H FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H FFH Clock output select register (CKS) Status After Reset 00H 00H 00H 00H
00H 00H 0000H 00H
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21.1 ROM Correction Function
The PD780318, 780328, 780338 Subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using ROM correction. ROM correction can be used to correct two places (max.) of the internal ROM (program). Caution ROM correction cannot be emulated by the in-circuit emulator (IE-78K0-NS).
21.2 ROM Correction Configuration
ROM correction consists of the following hardware. Table 21-1. ROM Correction Configuration
Item Registers Control register Configuration Correction address registers 0 and 1 (CORAD0, CORAD1) Correction control register (CORCN)
Figure 21-1 shows a block diagram of ROM correction. Figure 21-1. ROM Correction Block Diagram
Program counter (PC)
Comparator
Match
Correction branch request signal (BR !F7FDH)
Correction address register n (CORADn)
CORENn CORSTn Correction control register Internal bus
Remark n = 0, 1
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(1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1. If only one place needs to be corrected, set the address to either of the registers. ROM correction for the start address specified in CORAD0 and CORAD1 is valid when bit 1 (COREN0) and bit 3 (COREN1) of the correction control register (CORCN) is 1. CORAD0 and CORAD1 are set by a 16-bit memory manipulation instruction. RESET input sets CORAD0 and CORAD1 to 0000H. Figure 21-2. Correction Address Registers 0 and 1 Format
After reset 0000H
Symbol CORAD0
15
0
Address FF38H/FF39H
R/W R/W
CORAD1
FF3AH/FF3BH
0000H
R/W
Cautions 1. Set the CORAD0 and CORAD1 when bit 1 (COREN0) and bit 3 (COREN1) of the correction control register (CORCN) are 0. 2. Only start addresses where operation codes are stored can be set in CORAD0 and CORAD1. 3. Do not set the following addresses to CORAD0 and CORAD1. * Address value in table area of table reference instruction (CALLT instruction): 0040H to 007FH * Address value in vector table area: 0000H to 003FH (2) Comparator The comparator always compares the correction address value set in correction address registers 0 and 1 (CORAD0, CORAD1) with the fetch address value. When bit 1 (COREN0) or bit 3 (COREN1) of the correction control register (CORCN) is 1 and the correction address matches the fetch address value, the correction branch request signal (BR !F7FDH) is generated from the ROM correction circuit.
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21.3
ROM Correction Control Register
ROM correction is controlled by the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. The correction control register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1). The correction enable flags enable or disable the comparator match detection signal, and correction status flags show the values are matched. CORCN is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 21-3. Correction Control Register (CORCN) Format
Address: FF8AH After reset: 00H Symbol CORCN 7 0 6 0 R/WNote 5 0 4 0 3 COREN1 2 CORST1 1 COREN0 0 CORST0
COREN1 0 1
Correction address register 1 and fetch address match detection control Disabled Enabled
CORST1 0 1
Correction address register 1 and fetch address match detection flag Not detected Detected
COREN0 0 1
Correction address register 0 and fetch address match detection control Disabled Enabled
CORST0 0 1
Correction address register 0 and fetch address match detection flag Not detected Detected
Note Bits 0 and 2 are read-only bits. Bits 0 and 2 are set (1) only when a match is detected by comparator. Do not set these bits to 1 in software.
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21.4 ROM Correction Application
(1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROMTM) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to correction address register 0, 1 (CORAD0 or CORAD1) generates the correction branch. Figure 21-4. Storing Example to EEPROM (When One Place Is Corrected)
EEPROM
00H 01H 02H 00 10 0D 02 9B 02 10 RA78K0
Source program
CSEG AT 1000H ADD BR A, #2 !1002H
FFH
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(2) Assemble in advance the initialization routine as shown in Figure 21-5 to correct the program. Figure 21-5. Initialization Routine
Initialization ROM correction
Is ROM Note correction used? Yes Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled
No
Main program
Note
Whether ROM correction is used or not should be judged by the port input level. For example, when the P20 input level is high, the ROM correction is used, otherwise, it is not used.
(3) After reset, store the contents that have been previously stored in the external nonvolatile memory with initialization routine for ROM correction of the user to internal expansion RAM (see Figure 21-5). Set the start address of the instruction to be corrected to CORAD0 and CORAD1, and set bits 1 and 3 (COREN0, COREN1) of the correction control register (CORCN) to 1. (4) Set the entire-space branch instruction (BR !addr16) to the specified address (F7FDH) of the internal expansion RAM with the main program. (5) After the main program is started, the fetch address value and the values set in CORAD0 and CORAD1 are always compared by the comparator in the ROM correction circuit. When these values match, the correction branch request signal is generated. Simultaneously the corresponding correction status flag (CORST0 or CORST1) is set to 1. (6) Branch to the address F7FDH by the correction branch request signal. (7) Branch to the internal expansion RAM address set with the main program by the entire-space branch instruction of the address F7FDH. (8) When one place is corrected, the correction program is executed. When two places are corrected, the correction status flag is checked with the branch destination judgment program, and branches to the correction program.
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Figure 21-6. ROM Correction Operation
Internal ROM program start
Does fetch address match with correction address? Yes
No
ROM correction
Set correction status flag
Correction branch (branch to address F7FDH)
Correction program execution
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21.5 ROM Correction Example
An example of ROM correction when the instruction at address 1000H "ADD A, #1" is changed to "ADD A, #2" is shown below. Figure 21-7. ROM Correction Example
Internal ROM 0000H 0080H Program start
Internal expansion RAM F400H
F702H (3) 1000H 1002H ADD A, #1 MOV B, A (1)
ADD A, #2 BR !1002H (2)
F7FDH BR !F702H F7FFH
EFFFH
(1) Branches to address F7FDH when the preset value 1000H in the correction address register 0, 1 (CORAD0, CORAD1) matches the fetch address value after the main program is started. (2) Branches to any address (address F702H in this example) by setting the entire-space branch instruction (BR !addr16) to address F7FDH with the main program. (3) Returns to the internal ROM program after executing the substitute instruction ADD A, #2.
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21.6 Program Execution Flow
Figures 21-8 and 21-9 show the program transition diagrams when ROM correction is used. Figure 21-8. Program Transition Diagram (When One Place Is Corrected)
FFFFH F7FFH BR !JUMP F7FDH Internal expansion RAM (2)
Correction program JUMP
(1) (3) Internal ROM
Correction place xxxxH Internal ROM 0000H
(1) Branches to address F7FDH when fetch address matches correction address (2) Branches to correction program (3) Returns to internal ROM program Caution Do not use internal high-speed RAM and LCD display RAM for the ROM correction area. Remark JUMP: Correction program start address
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Figure 21-9. Program Transition Diagram (When Two Places Are Corrected)
FFFFH F7FFH BR !JUMP F7FDH Correction program 2 yyyyH Internal expansion RAM Correction program 1 xxxxH Branch destination judgment program (3) (8) (4) (7) (2) (6)
JUMP
(5) Internal ROM Correction place 2 Internal ROM Correction place 1 (1)
Internal ROM 0000H
(1) Branches to address F7FDH when fetch address matches correction address (2) Branches to branch destination judgment program (3) Branches to correction program 1 by branch destination judgment program (BTCLR !CORST0, $xxxxH) (4) Returns to internal ROM program (5) Branches to address F7FDH when fetch address matches correction address (6) Branches to branch destination judgment program (7) Branches to correction program 2 by branch destination judgment program (BTCLR !CORST1, $yyyyH) (8) Returns to internal ROM program Caution Do not use internal high-speed RAM and LCD display RAM for the ROM correction area. Remark JUMP: Correction program start address
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21.7 Cautions on ROM Correction
(1) Address values set in correction address registers 0 and 1 (CORAD0 and CORAD1) must be addresses where instruction codes are stored. In addition, address values to be set must be the start address of the instruction code. (2) Correction address registers 0 and 1 (CORAD0 and CORAD1) should be set when the correction enable flags (COREN0, COREN1) are "0" (when correction branch processing is disabled). If address is set to CORAD0 or CORAD1 when COREN0 or COREN1 is 1 (when the correction branch is in enabled state), the correction branch may start with the different address from the set address value. (3) Do not set the address value of instruction immediately after the instruction that sets the correction enable flag (COREN0, COREN1) to 1, to correction address register 0 or 1 (CORAD0, CORAD1); the correction branch may not start. (4) Do not set the address value in table area of table reference instruction (CALLT instruction) (0040H to 007FH), and the address value in vector table area (0000H to 003FH) to correction address registers 0 and 1 (CORAD0, CORAD1). (5) Do not set two addresses immediately after the instructions shown below to correction address registers 0 and 1 (CORAD0, CORAD1) (that is, when the mapped terminal address of these instructions is N, do not set the address values of N+1 and N+2). * RET * RETI * RETB * BR $addr16 * STOP * HALT (6) Do not set the address value set to the correction address registers 0 and 1 (CORAD0 and CORAD1) to F7FDH.
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CHAPTER 22 PD78F0338
The PD78F0338 is provided as the flash memory version of the PD780318, 780328, and 780338 Subseries. The PD78F0338 incorporates flash memory on which a program can be written, erased and overwritten while mounted on the board. Data can be written to the flash memory with the memory mounted on the target system (on-board). To do this, connect the dedicated flash programmer to the target system. Using flash memory in a development environment or application enables the following. * Software can be modified after soldering the PD78F0338 to the target system. * Many products can be produced in small quantities by distinguishing the software of each. * Data can be easily adjusted when mass-production is started. Table 22-1 lists the differences between the PD78F0338 and the mask ROM versions. Table 22-1. Differences Between PD78F0338 and Mask ROM Versions
Item
PD78F0338
Mask ROM Versions
PD780318 Subseries PD780328 Subseries PD780338 Subseries
Internal ROM structure Internal ROM capacity Flash memory 60 KBNote 1 Mask ROM
PD780316, 780326, 780336: 48 KB PD780318, 780328, 780338: 60 KB
70 24 max. 62 32 max. 54 40 max.
I/O port Segment signal output pin for LCD controller/driver Mask option to specify the on-chip pull-up resistors of pins P60 to P63 IC pin VPP pin Electrical specifications
70Note 2 40 max.Note 2
Not possible
Possible
Not provided Provided
Provided Not provided
Refer to data sheet of each product.
Notes 1. The same capacity as the mask ROM versions can be specified by means of the memory size switching register (IMS). 2. The same I/O port and segment signal output pin can be specified by means of the pin function switching registers 8 and 9 (PF8 and PF9). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version.
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22.1 Memory Size Switching Register
The PD78F0338 allows users to select the internal memory capacity using the memory size switching register (IMS) so that the same memory map as that of mask ROM versions with a different size of internal memory capacity can be achieved. IMS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to CFH. Caution Be sure to set IMS to CCH or CFH as the initial setting of the program. Reset input initializes IMS to CFH. Be sure to set IMS to CCH or CFH after reset. Figure 22-1. Memory Size Switching Register (IMS) Format
Address: FFF0H After reset: CFH R/W Symbol IMS 7 RAM2 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0
RAM2 1
RAM1 1 Other than above
RAM0 0
Internal high-speed RAM capacity selection 1,024 bytes Setting prohibited
ROM3 1 1
ROM2 1 1
ROM1 0 1
ROM0 0 1 48 KB 60 KB
Internal ROM capacity selection
Other than above
Setting prohibited
The IMS settings to obtain the same memory map as mask ROM versions are shown in Table 22-2. Table 22-2. Memory Size Switching Register Settings
Target Mask ROM Versions IMS Setting CCH CFH
PD780316, 780326, 780336 PD780318, 780328, 780338
Caution When using the mask ROM versions, be sure to set the value indicated in Table 22-2 to IMS.
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22.2 Internal Expansion RAM Size Switching Register
The internal expansion RAM size switching register (IXS) is used to set the internal expansion RAM capacity. IXS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 0CH. Caution Be sure to set IXS to 09H as the initial setting of the program. Reset input initializes IXS to 0CH. Be sure to set IXS to 09H after reset. Set the mask ROM versions in the same manner. Figure 22-2. Internal Expansion RAM Size Switching Register (IXS) Format
Address: FFF4H Symbol IXS 7 0 After reset: 0CH 6 0 R/W 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0
IXRAM3 1
IXRAM2 0
IXRAM1 0
IXRAM0 1
Internal expansion RAM capacity selection 1,536 bytes Setting prohibited
Other than above
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22.3 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FLPR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the target system (on-board). A flash memory writing adapter (FA adapter), which is a target board used exclusively for programming, is also provided. Remark FL-PR3, FL-PR4, and the flash memory writing adapter are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). Programming using flash memory has the following advantages. * Software can be modified after soldering the PD78F0338 to the target system. * Many products can be produced in small quantities by distinguishing the software of each. * Data can be easily adjusted when mass-production is started. 22.3.1 Programming environment The following shows the environment required for PD78F0338 flash memory programming. When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1). For details, refer to the manuals for Flashpro III/Flashpro IV. Remark USB is supported by Flashpro IV only. Figure 22-3. Environment for Writing Program to Flash Memory
VPP RS-232C USB Dedicated flash programmer Host machine VDD VSS RESET SIO/CSI/UART
PD78F0338
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22.3.2 Communication mode Use the communication mode shown in Table 22-3 to perform communication between the dedicated flash programmer and PD78F0338. Table 22-3. Communication Mode List
Communication Mode 3-wire serial I/O (SIO3) COMM PORT SIO Clock TYPE SettingNote 1 CPU CLOCK Optional Flash Clock 1 to 10 MHz
Note 2
Pins used Multiple Rate 1.0
Number of VPP Pulses
SIO ch-0 100 Hz to (3-wire, sync) 1.25 MHz
Note 2
SI3/RXD0/P20 0 SO3/TXD0/P21 SCK3/P22 SI1/P23 SO1/P24 SCK1/P25 1
3-wire serial I/O (CSI1)
SIO ch-1 100 Hz to 2 (3-wire, sync) MHzNote 2
Optional
1 to 10 MHz
Note 2
1.0
UART (UART0)
UART ch-0
4,800 to 76,800 bps
Notes 2, 3
Optional
1 to 10 MHz
Note 2
1.0
RxD0/SI3/P20 8 TxD0/SO3/P21
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)). 2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 24 ELECTRICAL SPECIFICATIONS. 3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. Figure 22-4. 3-Wire Serial I/O (SIO3)
Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLK GND VPP VDD0, 1/AVREF0, 1 RESET SCK3 SI3 SO3 X1 VSS0, 1/AVSS0
PD78F0338
Figure 22-5. 3-Wire Serial I/O (CSI1)
Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLK GND VPP VDD0, 1/AVREF0, 1 RESET SCK1 SI1 SO1 X1 VSS0, 1/AVSS0
PD78F0338
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Figure 22-6. UART (UART0)
Dedicated flash programmer VPP1 VDD RESET SO (TXD) SI (RXD) CLK GND VPP VDD0, 1/AVREF0, 1 RESET RXD0 TXD0 X1 VSS0, 1/AVSS0
PD78F0338
Remark CLK can be supplied on-board. It does not have to be connected to the dedicated flash programmer. VDD can also be supplied on-board but it must be connected to the dedicated flash programmer. In addition, the voltage must be supplied before starting programming. If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the PD78F0338. For details, refer to the manual of Flashpro III/Flashpro IV. Table 22-4. Pin Connection List
Signal Name VPP1 VPP2 VDD GND CLK RESET SI (RXD) SO (TXD) SCK HS I/O - Output Output Input Output Output - I/O Output - Write voltage - VDD voltage generation/voltage monitoring Ground Clock output Reset signal Reception signal Transmit signal Transfer clock - Pin Function Pin Name VPP - VDD0/VDD1/AVREF VSS0/VSS1/AVSS X1 RESET SO3/SO1/TXD0 SI3/SI1/RXD0 SCK3/SCK1 - x x x x x
Note
SIO3
CSI1
UART0
x
Note
x
Note
Note VDD voltage must be supplied before programming is started. Remark : Pin must be connected. : If the signal is supplied on the target board, pin need not be connected. x: Pin need not be connected.
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22.3.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin, so perform the following. (1) Connect a pull-down resistor (RVPP = 10 k) to the VPP pin. (2) Use the jumper on the board to switch the VPP pin input to either the writer or directly to GND. A VPP pin connection example is shown below. Figure 22-7. VPP Pin Connection Example
PD78F0338
Connection pin of dedicated flash programmer VPP
Pull-down resistor (RVPP)
The following shows the pins used by the serial interface.
Serial Interface 3-wire serial I/O (SIO3) 3-wire serial I/O (CSI1) UART (UART0) Pins Used SI3/SO3/SCK3 SI1/SO1/SCK1 RXD0/TXD0
When connecting the dedicated flash programmer to a serial interface pin that is connected to another device onboard, signal conflict or abnormal operation of the other devices may occur. Care must therefore be taken with such connections.
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(1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 22-8. Signal Conflict (Input Pin of Serial Interface)
PD78F0338
Signal conflict Input pin
Connection pin of dedicated flash programmer Other device Output pin
In the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device.
(2) Abnormal operation of other device If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. Figure 22-9. Abnormal Operation of Other Device
PD78F0338
Connection pin of dedicated flash programmer Other device Input pin
Pin
If the signal output by the PD78F0338 affects another device in the flash memory programming mode, isolate the signals of the other device.
PD78F0338
Connection pin of dedicated flash programmer Other device Input pin
Pin
If the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device.
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If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash programmer. Figure 22-10. Signal Conflict (RESET Pin)
PD78F0338
Signal conflict RESET
Connection pin of dedicated flash programmer Reset signal generator Output pin
The signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator.
When the PD78F0338 enters the flash memory programming mode, all the pins other than those that communicate in flash memory programming are in the same status as immediately after reset. If the external device does not recognize initial statuses such as the output high impedance status, therefore, connect the external device to VDD0 or VSS0 via a resistor. When using the on-board clock, connect X1, X2, XT1, and XT2 as required in the normal operation mode. When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main oscillator on-board, and leave the X2 pin open. The subclock conforms to the normal operation mode. To use the power output from the flash programmer, connect the VDD0 and VDD1 pins to VDD of the flash programmer, and the VSS0 and VSS1 pins to GND of the flash programmer. To use the on-board power supply, make connections that accord with the normal operation mode. However, because the voltage is monitored by the flash programmer, be sure to connect VDD0 and VDD1 to VDD of the flash programmer. Supply the same power as in the normal operation mode to the other power supply pins (AVREF0, AVREF1, and AVSS0). Process the other pins (S0 to S39, COM0 to COM3, SCOMO, VLC0 to VLC2, VLCDC, CAPH, and CAPL) in the same manner as in the normal operation mode.
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CHAPTER 23
INSTRUCTION SET
This chapter lists each instruction set of the PD780318, 780328, and 780338 Subseries in table form. For details of its operation and operation code, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E).
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23.1 Conventions
23.1.1 Operand identifiers and specification methods Operands are written in "Operand" column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and must be written as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for specification. Table 23-1. Operand Identifiers and Specification Methods
Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Specification Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbolNote Special function register symbol (16-bit manipulatable register even addresses only)Note FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even address only) 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special function register symbols, refer to Table 3-4 Special Function Register List.
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23.1.2 Description of "operation" column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: RBS: IE: NMIS: ( ): : : : : jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non-maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data Signed 8-bit data (displacement value)
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
addr16: 16-bit immediate data or label
23.1.3 Description of "flag operation" column (Blank): Not affected 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
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23.2 Operation List
Instruction Mnemonic Group 8-bit data transfer MOV Operands Byte Clock
Note 1 Note 2
Operation
Flag Z AC CY
r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A
Note 3 Note 3
2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1
Note 3
4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8
- 7 7 - - 5 5 5 5 9+n 9+m 7 5 5 5+n 5+m 5+n 5+m 9+n 9+m 7+n 7+m 7+n 7+m - 6 6
r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A (HL + B) (HL + B) A A (HL + C) (HL + C) A Ar A (saddr) A sfr A (DE) A (HL) x x x x x x
XCH
A, r A, saddr A, sfr A, !addr16 A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
1 2 2 3 1 1 2 2 2
10 + n + m A (addr16) 6+n+m 6+n+m
10 + n + m A (HL + byte) 10 + n + m A (HL + B) 10 + n + m A (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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Instruction Mnemonic Group 16-bit data transfer MOVW
Operands
Byte
Clock
Note 1 Note 2
Operation
Flag Z AC CY
rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX
Note 3 Note 3
3 4 4 2 2 2 2 1 1 3 3
Note 3
6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 10 10 8 8 8 8 - -
rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX
12 + 2n AX (addr16) 12 + 2m (addr16) AX - - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
XCHW 8-bit operation ADD
AX, rp A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
1 2 3
Note 4
2 2 2 3 1 2 2 2 2 3
ADDC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 4
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Only when rp = BC, DE or HL 4. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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Instruction Mnemonic Group 8-bit operation SUB
Operands
Byte
Clock
Note 1 Note 2
Operation
Flag Z AC CY
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 3 2 2 2 3 1 2 2 2 2 3
Note 3
4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n
A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY AA AA rr AA AA AA AA AA AA A (saddr) (addr16) (HL) (HL + byte) (HL + B) (HL + C) byte byte (saddr) (saddr) r
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x
SUBC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
2 2 2 3 1 2 2 2 2 3
AND
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from.
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Instruction Mnemonic Group 8-bit operation OR
Operands
Byte
Clock
Note 1 Note 2
Operation
Flag Z AC CY
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 3 2 2 2 3 1 2 2 2 2 3
Note 3
4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n
A A byte (saddr) (saddr) byte AA r rr A A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) AA AA rr AA AA AA AA AA AA A - byte (saddr) - byte A-r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C) A (saddr) (addr16) (HL) (HL + byte) (HL + B) (HL + C) byte byte (saddr) (saddr) r
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
XOR
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
2 2 2 3 1 2 2 2 2 3
CMP
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from.
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Instruction Mnemonic Group 16-bit operation ADDW SUBW CMPW Multiply/ divide MULU DIVUW
Operands
Byte
Clock
Note 1 Note 2
Operation
Flag Z AC CY
AX, #word AX, #word AX, #word X C r saddr r saddr
3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2 2 2
6 6 6 16 25 2 4 2 4 4 4 2 2 2 2 10 10 4 4 6 - 4 - 6 6 - 4 - 6
- - - - - - 6 - 6 - - - - - -
AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time (HL)3 - 0 (HL)7 - 4
x x x
x x x
x x x
Increment/ INC decrement DEC
x x x x
x x x x
INCW DECW Rotate ROR ROL RORC ROLC ROR4 ROL4 BCD adjust ADJBA ADJBS Bit manipulate MOV1
rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL]
x x x x
12 + n + m A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, 12 + n + m A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0,
(HL)7 - 4 (HL)3 - 0 - - 7 7 - 7 7+n 8 8 - 8
8+n+m
Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit CY
x x
x x
x x x x x x x
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY
3 3 2 3 2 3 3 2 3 2
x
x
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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Instruction Mnemonic Group Bit manipulate AND1
Operands
Byte
Clock
Note 1 Note 2
Operation
Flag Z AC CY
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1
6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2
7 7 - 7 7+n 7 7 - 7 7+n 7 7 - 7 7+n 6 8 - 6
CY CY CY CY CY CY CY CY CY CY
(saddr.bit) sfr.bit A.bit PSW.bit (HL).bit
x x x x x x x x x x x x x x x
OR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY CY CY CY CY CY CY CY CY sfr.bit 1 A.bit 1 PSW.bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 CY 1 CY 0 CY CY x x x x (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit
XOR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
SET1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
(saddr.bit) 1
x
8 + n + m (HL).bit 1
CLR1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
6 8 - 6
x
8 + n + m (HL).bit 0
SET1 CLR1 NOT1
CY CY CY
- - -
1 0 x
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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Instruction Mnemonic Group Call/return CALL CALLF
Operands
Byte
Clock
Note 1 Note 2
Operation
Flag Z AC CY
!addr16 !addr11
3 2
7 5
- -
(SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 R R R R R R
CALLT
[addr5]
1
6
-
BRK
1
6
-
RET RETI
1 1
6 6
- -
RETB Stack manipulate PUSH PSW rp POP PSW rp MOVW SP, #word SP, AX AX, SP Unconditional branch BR !addr16 $addr16 AX $addr16 $addr16 $addr16 $addr16
1 1 1 1 1 4 2 2 3 2 2 2 2 2 2
6 2 4 2 4 - - - 6 6 8 6 6 6 6
- - - - - 10 8 8 - - - - - - -
R
R
R
Conditional BC branch BNC BZ BNZ
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to internal ROM program.
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Instruction Mnemonic Group Conditional branch BT
Operands
Byte
Clock
Note 1 Note 2
Operation
Flag Z AC CY
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
3 4 3 3 3 4 4 3 4 3 4 4 3 4 3 2 2 3 2 1 2 2 2 2
8 - 8 - 10 10 - 8 - 10 10 - 8 - 10 6 6 8 4 2 - - 6 6
9 11 - 9 11 + n 11 11 - 11 11 + n 12 12 - 12
PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit then reset (HL).bit x x x
BF
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
BTCLR
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
12 + n + m PC PC + 3 + jdisp8 if (HL).bit = 1
DBNZ
B, $addr16 C, $addr16 saddr, $addr16
- - 10 - - 6 6 - -
B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode
CPU control
SEL NOP EI DI HALT STOP
RBn
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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23.3 Instructions Listed by Addressing Type
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
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Second Operand First Operand A
#byte
A
rNote
sfr
saddr !addr16 PSW
[DE]
[HL]
[HL + byte] $addr16 [HL + B] [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV MOV XCH XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
INC DEC
B, C sfr saddr MOV MOV
DBNZ
MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP
DBNZ
INC DEC
!addr16 PSW MOV
MOV MOV PUSH POP
[DE] [HL]
MOV MOV ROR4 ROL4
[HL + byte] [HL + B] [HL + C] X C
MOV
MULU DIVUW
Note Except r = A
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(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand AX ADDW SUBW CMPW rp MOVW MOVWNote INCW DECW PUSH POP MOVW XCHW MOVW MOVW MOVW MOVW #word AX rpNote sfrp saddrp !addr16 SP None
sfrp saddrp !addr16 SP
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand First Operand A.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
sfr.bit
MOV1
SET1 CLR1
saddr.bit
MOV1
SET1 CLR1
PSW.bit
MOV1
SET1 CLR1
[HL].bit
MOV1
SET1 CLR1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
SET1 CLR1 NOT1
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(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ AX !addr16 !addr11 [addr5] $addr16
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
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ELECTRICAL SPECIFICATIONS
Absolute maximum ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VPPNote 1 AVREF0 AVREF1 AVSS0 AVSS1 Input voltage VI1 P00 to P05, P10 to P17, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P64 to P67, P70 to P73, P120, X1, X2, XT1, XT2, RESET P60 to P63 N-ch open-drain N-ch open-drain, mask option Output voltage Analog input voltage Output current, high VO VAN P10 to P17, ANI8, ANI9 Analog input pin -0.3 to VDD + 0.3Note 2 V -0.3 to +0.3 V Conditions Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + 0.3Note 2 Unit V V V
VI2
-0.3 to +13 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3Notes 2, 3
V V V V
AVSS - 0.3 to AVREF0 + 0.3 and -0.3 to VDD + 0.3 -10
IOH
Per pin for P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P64 to P67, P70 to P73, P80 to P87, P90 to P97, P120 Total for P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P64 to P67, P70 to P73 Total for P80 to P87, P90 to P97, P120
mA
-15
mA
-15 20
mA mA
Output current, low
IOL
Per pin for P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P70 to P73, P80 to P87, P90 to P97, P120 Per pin for P60 to P63 Per pin for P64 to P67 Total for P80 to P87, P90 to P97, P120 Total for P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P60 to P67, P70 to P73
30 30 20 170
mA mA mA mA C C
Operating ambient temperature Storage temperature
TA
-40 to +85
Tstg
-65 to +150
Notes 1. PD78F0338 only 2. 6.5 V or less 3. -0.3 to VLC0 + 0.3 V for common and segment pins Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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Main system clock oscillator characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit
X1 C1 X2 IC C2
Parameter Oscillation frequency (fX)Note 1
Conditions
MIN. 1.0
TYP.
MAX. 10
Unit MHz
Oscillation After VDD reaches oscilstabilization timeNote 2 lation voltage range MIN. Oscillation frequency (fX)Note 1 Oscillation VDD = 4.5 to 5.5 V stabilization timeNote 2 VDD = 1.8 to 5.5 V X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH, tXL) VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V 42.5 85 1.0 1.0
4
ms
Crystal resonator
10
MHz
X1 C1
X2 IC C2
10 30 10 5.0 500 500
ms ms MHz MHz ns ns
External clock
X1
X2
Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.
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Subsystem clock oscillator characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note 1 Oscillation VDD = 4.5 to 5.5 V stabilization timeNote 2 VDD = 1.8 to 5.5 V XT1 input frequency (fXT)Note 1 32 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz
XT2 R C4
XT1 IC
C3
1.2
2 10 38.5
s s kHz
External clock
XT2
XT1
XT1 input high-/low-level width (tXTH, tXTL)
5
15
s
Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN Conditions f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P00 P30 P50 P70 to to to to P05, P34, P57, P73, P20 to P25, P40 to P47, P64 to P67, P120 MIN. TYP. MAX. 15 Unit pF
COUT
15
pF
CIO
15
pF
P60 to P63
20
pF
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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Recommended Oscillator Constants (1) PD780316, 780318, 780326, 780328, 780336, 780338 Main system clock: Ceramic resonator (TA = -40 to +85C)
Manufacturer Part Number Frequency (MHz) Recommended Circuit Constant Oscillation Voltage Range MIN. 1.9 MAX. 5.5
C1 (pF) Murata Mfg. Co., Ltd. CSBFB1M00J58-R1 CSBLA1M00J58-B0 CSTCC2M00G56-R0 CSTLS2M00G56-B0 CSTCR4M00G53-R0 CSTLS4M00G53-B0 CSTCC8M38G53093-R0 CSTLS8M38G53093-B0 CSTCC8M38G53-R0 CSTLS8M38G53-B0 CSTCC10M0G53093-R0 CSTLS10M00G53093-B0 CSTCC10M0G53-R0 CSTLS10M00G53-B0 Internal 10 Internal Internal 8.38 Internal 4.00 Internal 2.00 Internal 1.00 150
C2 (pF) 150
Rd (k) 1
Internal
0
1.8
5.5
Internal
0
1.8
5.5
Internal
0
1.8
5.5
Internal
0
1.9
5.5
Internal
0
1.8
5.5
Internal
0
2.0
5.5
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator to be used.
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(2) PD78F0338 Main system clock: Ceramic resonator (TA = -40 to +85C)
Manufacturer Part Number Frequency (MHz) Recommended Circuit Constant Oscillation Voltage Range MIN. 2.1 MAX. 5.5
C1 (pF) Murata Mfg. Co., Ltd. CSBFB1M00J58-R1 CSBLA1M00J58-B0 CSTCC2M00G56-R0 CSTLS2M00G56-B0 CSTCR4M00G53093-R0 CSTLS4M00G53093-B0 CSTCR4M00G53-R0 CSTLS4M00G53-B0 CSTCC8M38G53U-R0 CSTLS8M38G53U-B0 CSTCC8M38G53-R0 CSTLS8M38G53-B0 CSTCC10M0G53U-R0 CSTLS10M00G53U-B0 CSTCC10M0G53-R0 CSTLS10M00G53-B0 Internal 10 Internal Internal 8.38 Internal Internal 4.00 Internal 2.00 Internal 1.00 150
C2 (pF) 150
Rd (k) 1
Internal
0
1.9
5.5
Internal
0
1.8
5.5
Internal
0
1.9
5.5
Internal
0
1.9
5.5
Internal
0
2.1
5.5
Internal
0
2.0
5.5
Internal
0
2.2
5.5
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator to be used.
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DC characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current, high Symbol IOH Conditions Per pin for P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P64 to P67, P70 to P73, P80 to P87, P90 to P97, P120 All pins Output current, low IOL Per pin for P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P70 to P73, P80 to P87, P90 to P97, P120 Per pin for P60 to P63 Per pin for P64 to P67 Total for P80 to P87, P90 to P97, P120 Total for P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P70 to P73 Total for P60 to P63 Total for P64 to P67 Input voltage, high VIH1 P10 to P17, P21, P24, P30, P40 to P47, P50 to P57, P64 to P67, P70, P72 VIH2 P00 to P05, P20, P22, P23, P25, P31 to P34, P71, P73, RESET VIH3 P60 to P63 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V VIH4 X1, X2 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V VIH5 XT1, XT2 4.5 V VDD 5.5 V 1.8 V VDD 5.5 V VIH6 P120 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V Input voltage, low VIL1 P10 to P17, P21, P24, P30, P40 to P47, P50 to P57, P64 to P67, P70, P72 VIL2 P00 to P05, P20, P22, P23, P25, P31 to P34, P71, P73, RESET VIL3 P60 to P63 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V VIL4 X1, X2 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V VIL5 XT1, XT2 4.5 V VDD 5.5 V 1.8 V VDD 5.5 V VIL6 P120 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD VDD - 0.5 VDD - 0.2 0.8VDD 0.9VDD 0.8VDD 0.85VDD 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. TYP. MAX. -1 Unit mA
-20 10
mA mA
15 15 20 10
mA mA mA mA
60 60 VDD VDD VDD VDD 12 12 VDD VDD VDD VDD VDD VDD 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.4 0.2 0.2VDD 0.1VDD 0.2VDD 0.15VDD
mA mA V V V V V V V V V V V V V V V V V V V V V V V V V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output voltage, high Output voltage, low VOL1 Symbol VOH Conditions VDD = 4.0 to 5.5 V, IOH = -1 mA VDD = 1.8 to 5.5 V, IOH = -100 A P60 to P63 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA MIN. VDD - 1.0 VDD - 0.5 0.4 TYP. MAX. VDD VDD 1.0 Unit V V V
VOL2
P64 to P67
0.4
2.0
V
VOL3
P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P70 to P73, P80 to P87, P90 to P97, P120 IOL = 400 A VIN = VDD
0.4
V
VOL4 Input leakage current, high ILIH1
0.5 P00 to P05, P10 to P17, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P60 to P67, P70 to P73, P120, RESET X1, X2, XT1, XT2 3
V
A
ILIH2 ILIH3 Input leakage current, low ILIL1 VIN = 12 V VIN = 0 V
20 10 -3
A A A
P60 to P63 P00 to P05, P10 to P17, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P64 to P67, P70 to P73, P120, RESET X1, X2, XT1, XT2 P60 to P63 (N-ch open-drain)
ILIL2 ILIL3
-20 -3Note
A A A A
k
Output leakage current, high Output leakage current, low Mask option pull-up resistor (PD780316, 780318, 780326, 780328, 780336, 780338 only) Software pull-up resistor
ILOH
VOUT = VDD
3
ILOL
VOUT = 0 V
-3
R1
VIN = 0 V, P60, P61, P62, P63
20
40
90
R2
VIN = 0 V, P00 to P05, P20 to P25, P30 to P34, P40 to P47, P50 to P57, P64 to P67, P70 to P73, P120
15
30
90
k
Note During input instruction execution, the low-level input leakage current for P60 to P63 is -200 A (MAX.) only for 1 clock (no wait). During execution of other instructions, this value is -3 A (MAX.). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V): PD780316, 780318, 780326, 780328, 780336, 780338
Parameter Symbol Power supply currentNote 1 IDD1Note 2 10 MHz crystal VDD = 5.0 V oscillation operating mode 5.0 MHz crystal oscillation operating mode VDD = 2.0 V 10%Note 4 Conditions 10%Note 3 When A/D converter stopped When A/D converter is operating When A/D converter stopped When A/D converter is operating When A/D converter stopped When A/D converter is operating IDD2 10 MHz crystal oscillation HALT mode 5.0 MHz crystal oscillation HALT mode VDD = 2.0 V 10%Note 4 VDD = 3.0 V 10%Note 3 VDD = 5.0 V 10%Note 3 When peripheral function stopped When peripheral function is operating When peripheral function stopped When peripheral function is operating When peripheral function stopped When peripheral function is operating IDD3 32.768 kHz crystal VDD = 5.0 V 10% 40 20 10 When LCD stoppedNote 6 25 27 0.15 0.35 MIN. TYP. MAX. Unit 6.3 7.3 2.0 3.0 0.4 1.4 1.15 12.6 14.6 4.0 6.0 1.5 4.2 2.3 5.7 0.7 1.7 0.4 1.1 80 40 20 45 51 mA mA mA mA mA mA mA mA mA mA mA mA
VDD = 3.0 V 10%Note 3
A A A A A A A A A A A A A A A
oscillation operating VDD = 3.0 V 10% modeNote 5 VDD = 2.0 V 10% IDD4 32.768 kHz crystal oscillation HALT mode VDD = 5.0 V 10%
Only when LCD boost function is operatingNote 7 When LCD is operatingNote 8 VDD = 3.0 V 10% When LCD stoppedNote 6
30 6 7.5
60 18 23
Only when LCD boost function is operatingNote 7 When LCD is operatingNote 8 VDD = 2.0 V 10% When LCD stoppedNote 6
10 3 4
30 10 12
Only when LCD boost function is operatingNote 7 When LCD is operatingNote 8 IDD5 STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
6 0.1 0.05 0.05
18 30 10 10
Notes 1. Total current flowing in the internal power supply (VDD1, AVREF0). 2. Includes the peripheral operating current. However, the current flowing in the pull-up resistor on the port is not included. 3. When the processor clock control register (PCC) is set to 00H. 4. When PCC is set to 02H. 5. When the main system clock has been stopped. 6. Supply current when LCD is stopped (LCDON = 0, SCOC = 0, VLCON = 0) 7. Supply current only when the LCD boost function is operating (LCDON = 0, SCOC = 0, VLCON = 1) in the following status: * No load without LCD display panel connected * Capacitors C1 to C4 for boost: 0.47 F * When boosting is stabilized
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8. Supply current when the LCD is operating (LCDON = 1, SCOC = 1, VLCON = 1) in the following status: * No load without LCD display panel connected * Capacitors C1 to C4 for boost: 0.47 F * When boosting is stabilized
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DC characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V): PD78F0338
Parameter Symbol Power supply currentNote 1 IDD1Note 2 10 MHz crystal VDD = 5.0 V oscillation operating mode 5.0 MHz crystal oscillation operating mode VDD = 2.0 V 10%Note 4 Conditions 10%Note 3 When A/D converter stopped When A/D converter is operating When A/D converter stopped When A/D converter is operating When A/D converter stopped When A/D converter is operating IDD2 10 MHz crystal oscillation HALT mode 5.0 MHz crystal oscillation HALT mode VDD = 2.0 V 10%Note 4 VDD = 3.0 V 10%Note 3 VDD = 5.0 V 10%Note 3 When peripheral function stopped When peripheral function is operating When peripheral function stopped When peripheral function is operating When peripheral function stopped When peripheral function is operating IDD3 32.768 kHz crystal VDD = 5.0 V 10% 115 95 75 When LCD stoppedNote 6 25 27 0.2 0.4 MIN. TYP. MAX. Unit 15 16 4.5 5.5 2.8 3.8 1.25 30 32 9 11 5.6 7.6 2.5 5.7 0.8 1.7 0.4 1.1 230 190 150 45 51 mA mA mA mA mA mA mA mA mA mA mA mA
VDD = 3.0 V 10%Note 3
A A A A A A A A A A A A A A A
oscillation operating VDD = 3.0 V 10% modeNote 5 VDD = 2.0 V 10% IDD4 32.768 kHz crystal oscillation HALT mode VDD = 5.0 V 10%
Only when LCD boost function is operatingNote 7 When LCD is operatingNote 8 VDD = 3.0 V 10% When LCD stoppedNote 6
30 6 7.5
60 18 23
Only when LCD boost function is operatingNote 7 When LCD is operatingNote 8 VDD = 2.0 V 10% When LCD stoppedNote 6
10 3 4
30 10 12
Only when LCD boost function is operatingNote 7 When LCD is operatingNote 8 IDD5 STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
6 0.1 0.05 0.05
18 30 10 10
Notes 1. Total current flowing in the internal power supply (VDD1, AVREF0). 2. Includes the peripheral operating current. However, the current flowing in the pull-up resistor on the port is not included. 3. When the processor clock control register (PCC) is set to 00H. 4. When PCC is set to 02H. 5. When the main system clock has been stopped. 6. Supply current when LCD is stopped (LCDON = 0, SCOC = 0, VLCON = 0) 7. Supply current only when the LCD boost function is operating (LCDON = 0, SCOC = 0, VLCON = 1) in the following status: * No load without LCD display panel connected * Capacitors C1 to C4 for boost: 0.47 F * When boosting is stabilized
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8. Supply current when the LCD is operating (LCDON = 1, SCOC = 1, VLCON = 1) in the following status: * No load without LCD display panel connected * Capacitors C1 to C4 for boost: 0.47 F * When boosting is stabilized
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AC characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) Symbol TCY Conditions Operating with main system clock 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V Operating with subsystem clock TI00, TI01 input high-/low-level width tTIH0 tTIL0 2.7 V VDD < 3.5 V 1.8 V VDD < 2.7 V TI4 input frequency fTI4 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V TI4 input high-/low-level width TI50, TI51, TI52 input frequency TI50, TI51, TI52 input high-/low-level width Interrupt request input high-/low-level width RESET low-level width tTIH5 tTIL5 tINTH tINTL tRSL tTIH4 tTIL4 fTI5 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V INTP0 to INTP5, P40 to P47 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V 3.5 V VDD 5.5 V MIN. 0.2 0.4 1.6 103.9Note 1 2/fsam + 0.1Note 2 2/fsam + 0.2Note 2 2/fsam + 0.5Note 2 0 0 100 1.8 0 0 100 1.8 1 2 10 4 275 4 275 122 TYP. MAX. 16 16 16 125 Unit
s s s s s s s
MHz kHz ns
s
MHz kHz ns
s s s s
Notes 1. Value when using the external clock. When using a crystal resonator, the value becomes 114 s (MIN.). 2. Selection of fsam = fX, fX/4, fX/64 is available with bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
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TCY vs. VDD (with main system clock operation)
16.0 10.0 Cycle time TCY [ s] 5.0 Operation guaranteed range
2.0 1.6 1.0
0.4 0.2 0.1 0 1.0 1.8 2.0 2.7 Supply voltage VDD [V] 3.0 4.0 4.5 5.0 5.5 6.0
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(2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) SIO3 3-wire serial I/O mode (SCK3 ... internal clock output)
Parameter SCK3 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V SCK3 high-/low-level width SI3 setup time (to SCK3) tKH1 tKL1 tSIK1 4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V SI3 hold time (from SCK3) Delay time from SCK3 to SO3 output tKSI1 C = 100 pFNote MIN. 800 1,600 3,200 tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
tKSO1
300
ns
Note C is the load capacitance of the SCK3 and SO3 output lines. (b) SIO3 3-wire serial I/O mode (SCK3 ... external clock input)
Parameter SCK3 cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V SCK3 high-/low-level width tKH2 tKL2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V SI3 setup time (to SCK3) SI3 hold time (from SCK3) Delay time from SCK3 to SO3 output tKSO2 C = 100 pFNote 300 ns tSIK2 MIN. 800 1,600 3,200 400 800 1,600 100 TYP. MAX. Unit ns ns ns ns ns ns ns
tKSI2
400
ns
Note C is the load capacitance of the SO3 output line.
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(c) CSI1 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter SCK1 cycle time Symbol tKCY3 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V SCK1 high-/low-level width tKH3 tKL3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V SI1 setup time (to SCK1) SI1 hold time (from SCK1) Delay time from SCK1 to SO1 output tSIK3 MIN. 200 500 1 tKCY3/2 - 5 tKCY3/2 - 20 tKCY3/2 - 30 20 TYP. MAX. Unit ns ns
s
ns ns ns ns
tKSI3 C = 100 pFNote
110
ns
tKSO3
150
ns
Note C is the load capacitance of the SCK1 and SO1 output lines. (d) CSI1 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter SCK1 cycle time Symbol tKCY4 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V SCK1 high-/low-level width tKH4 tKL4 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V SI1 setup time (to SCK1) SI1 hold time (from SCK1) Delay time from SCK1 to SO1 output tKSI4 C = 100 pFNote 110 ns tSIK4 MIN. 200 500 1 100 250 500 25 TYP. MAX. Unit ns ns
s
ns ns ns ns
tKSO4
150
ns
Note C is the load capacitance of the SO1 output line. (e) UART0 (dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V MIN. TYP. MAX. 156,250 78,125 39,063 Unit bps bps bps
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AC timing test point (excluding X1, XT1 input)
0.8VDD 0.2VDD
Test points
0.8VDD 0.2VDD
Clock timing
1/fX tXL tXH
X1 input
VIH4 (MIN.) VIL4 (MAX.)
1/fXT tXTL tXTH
XT1 input
VIH5 (MIN.) VIL5 (MAX.)
TI timing
1/fTI4 tTIL4 tTIH4
TI4
1/fTI5 tTIL5 tTIH5
TI50, TI51, TI52
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Interrupt request input timing
tINTL
tINTH
INTP0 to INTP5
RESET input timing
tRSL
RESET
Serial transfer timing 3-wire serial I/O mode (SIO3, CSI1):
tKCYn tKLn tKHn
SCK1, SCK3
tSIKn
tKSIn
SI1, SI3
Input data
tKSOn
SO1, SO3
Output data
n = 1 to 4
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A/D converter characteristics (TA = -40 to +85C, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.05 V VDD < 2.7 V Conversion time tCONV 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.05 V VDD < 2.7 V Zero-scale errorNote 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.05 V VDD < 2.7 V Full-scale errorNote 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.05 V VDD < 2.7 V Integral linearity error 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.05 V VDD < 2.7 V Differential linearity error 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.05 V VDD < 2.7 V Analog input voltage Analog reference voltage Resistance between AVREF0 and AVSS VIAN AVREF0 RREF0 At A/D conversion operation 0 2.05 20 40 14 19 48 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 0.6 MAX. 10 0.4 0.6 1.2 100 100 100 0.4 0.6 1.2 0.4 0.6 1.2 2.5 4.5 8.5 1.5 2.0 3.5 AVREF VDD Unit bit %FSR %FSR %FSR
s s s
%FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB LSB V V k
Note Overall error excluding quantization error (1/2 LSB). It is indicated as a ratio (%FSR) to the full-scale value. D/A converter characteristics (TA = -40 to +85C, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 R = 2 MNote 2 R = 4 MNote 2 R = 10 MNote 2 Settling time C = 30 pF 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V Output resistance Analog reference voltage Resistance between AVREF1 and AVSS RO AVREF1 RREF1 DA0 = 55HNote 3 Note 3 1.8 4 8 10 VDD Symbol Conditions MIN. TYP. MAX. 8 1.2 0.8 0.6 10 15 20 Unit bit % % %
s s s
k V k
Notes 1. Overall error excluding quantization error (1/2 LSB). It is indicated as a ratio (%FSR) to the full-scale value. 2. R and C are the D/A converter output pin load resistance and load capacitance, respectively. 3. Value for one D/A converter channel
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LCD controller/driver characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter LCD reference voltage Symbol VLCD2 Conditions C1 to C4 = 0.47 F GainNote 1 GainNote 1 Gain adjustment Doubler output voltage Tripler output voltage Boost wait timeNote 2 VLCD1 VLCD0 tVAWAIT C1 to C4 = 0.47 F C1 to C4 = 0.47 F Gain = 1 4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V Gain = 1.5 LCD output (common) LCD output resistanceNote 3 (segment) ROVS 200 k resistanceNote 3 ROVC =1 = 1.5 MIN. 0.84 1.26 1.0 TYP. 1 1.5 MAX. 1.165 1.74 1.5 Unit V V Times V V s s s 40 k
2.0VLCD2 - 0.1 2.0VLCD2 2.0VLCD2 3.0VLCD2 - 0.15 3.0VLCD2 3.0VLCD2 4 0.5 0.5
Notes 1. The gain is a determined by R1 and R2 as follows. For details, refer to Remark. * Gain = (R1 + R2)/R2 2. The boost wait time is the wait time from when boosting is started to when display is enabled. 3. The output resistance is the resistance between one of the VLC0, VLC1, VLC2, VSS0, and VSS1 pins, and a segment signal output pin or common signal output pin.
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Remark C1, C2, C3, and C4 are the capacitors connected between CAPH and CAPL, VLC2 and GND, VLC1 and GND, and VLC0 and GND, respectively.
VLC0 VLC1 VLC2 R1 VLCDC R2 C2 C3 C4
CAPH C1 CAPL
External pin
* R1 + R2 = 3 [M] * C1 = C2 = C3 = C4 = 0.47 [F] VLCD2 can be adjusted according to the voltage division ratio of the resistance of R1 and R2. * VLCD2 = (R1 + R2)/R2 [V] * VLCD1 = 2 x VLCD2 [V] * VLCD0 = 3 x VLCD2 [V] Recommended values for external circuits are shown below.
VLCD2 (V) VLCD0 = 3 V (gain = 1) VLCD0 = 4.5 V (gain = 1.5) 1 1.5
VLCD1 (V) 2 3
VLCD0 (V) 3 4.5
R1 (M) 0 1
R2 (M) 3 2
Remark The above LCD output voltage applies when the wiring resistance and capacitance between the VLC0, VLC1, VLC2, VLCDC, CAPH, and CAPL pins and the external circuit is ignored.
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Characteristics curves of LCD controller/driver (reference values) (1) Characteristics curves of voltage boost stabilization time The following shows the characteristics curves of the time from the start of voltage boost (VLCON = 1) and the changes in the LCD output voltage (when gain = 1 (3 V boost mode), VDD = 4.5 to 5.5 V). LCD output voltage/voltage boost time (when gain = 1 (3 V boost mode), VDD = 4.5 to 5.5 V)
5.5 5 4.5 4 VDD = 4.5 V VDD = 5 V VDD = 5.5 V
LCD output voltage [V]
3.5 VLCD0 3 2.5 VLCD1 2 1.5 VLCD2 1 0.5 0
0
500
1,000
1,500
2,000
2,500
3,000
3,500
4,000
Voltage boost time [ms]
Remark The above characteristics curves are when the external resistance is R1 = 0 [M] and R2 = 3 [M].
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(2) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage. LCD output voltage/temperature (when gain = 1)
5
VLCD2
VLCD1
VLCD0
4
LCD output voltage [V]
3
2
1
0 -40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [C]
Remark The above characteristics curves are when the external resistance is R1 = 0 [M] and R2 = 3 [M]. LCD output voltage/temperature (when gain = 1.5)
5
VLCD2
VLCD1
VLCD0
4 LCD output voltage [V]
3
2
1
0 -40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [C]
Remark The above characteristics curves are when the external resistance is R1 = 1 [M] and R2 = 2 [M].
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ELECTRICAL SPECIFICATIONS
Data memory STOP mode low power supply voltage data retention characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Data retention power supply current Symbol VDDDR Conditions MIN. 1.6 TYP. MAX. 5.5 Unit V
IDDDR
VDDDR = 1.6 V (with subsystem clock stopped and feedback resistor disconnected)
0.1
10
A
Release signal set time Oscillation stabilization wait time
tSREL tWAIT Release by RESET Release by interrupt request
0 217/fX Note
s
s s
Note Selection of 212/fX, 214/fX, 215/fX, 216/fX, and 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fX: Main system clock oscillation frequency Data retention timing (STOP mode release by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
VDD STOP instruction execution
VDDDR
tSREL
RESET tWAIT
Data retention timing (standby release signal: STOP mode release by interrupt request signal)
HALT mode STOP mode Data retention mode Operating mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (Interrupt request) tWAIT
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Flash memory programming characteristics (TA = +10 to +40C, VDD = 1.8 to 5.5 V): PD78F0338 only (1) Write/erase characteristics
Parameter Operating frequency Symbol fX Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V VDD write supply currentNote IDDW When 10 MHz crystal VDD = 4.5 to 5.5 V VPP = VPP1 oscillation operating mode 5 MHz crystal oscillation operating mode VPP write supply currentNote IPPW When 10 MHz crystal VDD = 4.5 to 5.5 V VPP = VPP1 oscillation operating mode 5 MHz crystal oscillation operating mode VDD erase supply currentNote IDDE When 10 MHz crystal VDD = 4.5 to 5.5 V VPP = VPP1 oscillation operating mode 5 MHz crystal oscillation operating mode VPP erase supply currentNote Unit erase time Total erase time Number of rewriting times VPP supply voltage IPPE ter tera CWRT VPP0 VPP1 Where erase and write make up 1 cycle Normal operation mode Flash memory program 0 9.7 10.0 When VPP = VPP1 0.5 1 100 1 20 20 0.2VDD 10.3 mA s s Times V V VDD = 1.8 to 5.5 V 35 mA VDD = 1.8 to 5.5 V 39.5 mA VDD = 1.8 to 5.5 V MIN. 1 1 1 TYP. MAX. 10 5 1.25 35 mA Unit MHz
12
16.5
12
Note Excluding port current (including current flowing through on-chip pull-up resistor) (2) Write operation characteristics
Parameter VPP set time VPP set time from VDD RESET set time from VPP Symbol tPSRON tDRPSR tPSRRF Conditions VPP high voltage VPP high voltage VPP high voltage MIN. 1.0 1.0 1.0 1.0 2.0 8.0 40 TYP. MAX. Unit
s s s s
ms
VPP count start time from RESET tRFCF Count execution time tCOUNT
VPP counter high-/low-level width tCH, tCL VPP counter noise elimination width tNFW
s
ns
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Flash write mode setting timing
VDD VDD 0V tDRPSR tRFCF tCH
VPPH
VPP
VPP tCL tCOUNT
VPPL tPSRON tPSRRF
VDD RESET (input) 0V
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PACKAGE DRAWINGS
120-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
90 91 61 60
detail of lead end CD S P T
120 1
31 30
R Q
L U
F G H I
M
J
K
S
N
NOTE Each lead centerline is located within 0.07 mm of its true position (T.P.) at maximum material condition.-1
S
M
ITEM A B C D F G H I J K L M N P Q R S T MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.2 1.2 0.180.05 0.07 0.4 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.0 0.10.05 +4 3 -3 1.10.1 0.25 S120GC-40-9EB-1
Remark The dimensions and materials of the ES version are the same as those of the mass-produced version.
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PACKAGE DRAWINGS
120-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
90 91 61 60
detail of lead end S CD Q R
120 1
31 30
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.09 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.2 1.2 0.180.05 0.09 0.4 (T.P.) 1.00.2 0.50.2 0.1450.05 0.08 1.00.1 0.10.05 +7 3 -3 1.2 MAX. S120GC-40-9EV-1
Remark The dimensions and materials of the ES version are the same as those of the mass-produced version.
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CHAPTER 26
RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, please contact an NEC sales representative. Table 26-1. Surface Mounting Type Soldering Conditions
PD780316GC-xxx-9EB: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780316GC-xxx-9EV: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780318GC-xxx-9EB: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780318GC-xxx-9EV: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780326GC-xxx-9EB: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780326GC-xxx-9EV: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780328GC-xxx-9EB: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780328GC-xxx-9EV: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780336GC-xxx-9EB: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780336GC-xxx-9EV: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780338GC-xxx-9EB: 120-pin plastic TQFP (fine pitch) (14 x 14) PD780338GC-xxx-9EV: 120-pin plastic TQFP (fine pitch) (14 x 14) PD78F0338GC-9EB: PD78F0338GC-9EV:
Soldering Method
120-pin plastic TQFP (fine pitch) (14 x 14) 120-pin plastic TQFP (fine pitch) (14 x 14)
Soldering Conditions Recommended Condition Symbol IR35-103-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: 2 times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: 2 times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-103-2
Partial heating
--
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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APPENDIX A
DIFFERENCES BETWEEN PD780308, 780318, 780328, AND 780338 SUBSERIES
Table A-1 shows the major differences between PD780308, 780318, 780328, and 780338 Subseries. Table A-1. Major Differences Between PD780308, 780318, 780328, and 780338 Subseries (1/2)
Part Number Item I2C bus built-in model (Y Subseries) PROM (flash memory) version Power supply voltage ROM Provided
PD780308 Subseries
PD780318 Subseries
Not provided
PD780328 Subseries
PD780338 Subseries
PD78P0308
VDD = 2.0 to 5.5 V * PD780306: 48 KB * PD780308: 60 KB 1,024 bytes 1,024 bytes 40 x 4 bits 0.4 s/0.8 s/1.6 s/3.2 s/ 6.4 s/12.8 s (@fX = 5.0 MHz) 57 8 bits x 8 -- Bias: 1/2 and 1/3 can be selected
PD78F0338
VDD = 1.8 to 5.5 V * PD780316, 780326, 780336: 48 KB * PD780318, 780328, 780338: 60 KB
Internal high-speed RAM Internal expansion RAM LCD display RAM Minimum instruction execution time Number of I/O ports A/D converter D/A converter LCD controller/driver
1,536 bytes 40 x 8 bits 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (@fX = 10.0 MHz) 70 10 bits x 8 8 bits x 1 * Bias: 1/3 only * Internal booster circuit employed for LCD driver reference voltage generator (x3) * Blinking display possible (blinking period can be selected: 0.5 s or 1 s) 24 max. 32 max. 40 max. 62 54
Segment signal output Common signal output
40 max. 4 max. (for dynamic display only)
4 max. (for dynamic display) 1 max. (for static display) * 3-wire/UART: 1 * 3-wire: 1
Serial interface
Subseries without Y
* 3-wire/2-wire/SBI: 1 * 3-wire/UART: 1 * 3-wire: 1 * 3-wire/2-wire/I2C: 1 * 3-wire/UART: 1 * 3-wire: 1 * * * * 16-bit timer/event counter: 1 8-bit timer/event counter: 2 Watch timer: 1 Watchdog timer: 1
Y Subseries
--
Timer
* * * *
16-bit timer/event counter: 2 8-bit timer/event counter: 3 Watch timer: 1 Watchdog timer: 1
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APPENDIX A
DIFFERENCES BETWEEN PD780308, 780318, 780328, AND 780338 SUBSERIES
Table A-1. Major Differences Between PD780308, 780318, 780328, and 780338 Subseries (2/2)
Part Number Item Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (5.0 MHz with main system clock) Internal: 1, external: 1 * 100-pin plastic LQFP (fine pitch) (14 x 14) * 100-pin plastic QFP (14 x 20) Device file Emulation board Electrical specifications and recommended soldering conditions DF780308 IE-780308-NS-EM1 Refer to the document of each product. DF780338 IE-780338-NS-EM1
PD780308 Subseries
PD780318 Subseries
PD780328 Subseries
PD780338 Subseries
5 (8-bit PWM output: 3) 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz, 10 MHz (10 MHz with main system clock)
Test input Package
-- * 120-pin plastic TQFP (fine pitch) (14 x 14)
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APPENDIX B
DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the PD780318, 780328, and 780338 Subseries. Figure B-1 shows the development tool configuration.
*
Support for PC98-NX series Unless otherwise specified, products compatible with IBM PC/ATTM computers are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT computers.
*
Windows Unless otherwise specified, "Windows" means the following OSs. * Windows 3.1 * Windows 95, 98, 2000 * Windows NTTM Ver. 4.0
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APPENDIX B
DEVELOPMENT TOOLS
Figure B-1. Development Tool Configuration
Language processing software * Assembler package * C compiler package * C library source file * Device file
Debugging tool * System simulator * Integrated debugger * Device file
Embedded software * Real-time OS
Host machine (PC)
Interface adapter, PC card interface, etc.
Flash memory write environment Flash programmer
In-circuit emulator Emulation board I/O board Power supply unit
Flash memory write adapter
Performance board
On-chip flash memory version
Emulation probe
Conversion socket or conversion adapter Target system
Remark Items in broken line boxes differ according to the development environment. See B.3.1 Hardware.
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APPENDIX B
DEVELOPMENT TOOLS
B.1 Language Processing Software
SP78K0 78K/0 Series Software Package This is a software package that includes the development tools common to the 78K/0 Series. Part number: SxxxxSP78K0 RA78K0 Assembler Package This assembler converts programs written in mnemonics into object codes executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with an optional device file (DF780338). This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part number: SxxxxRA78K0 CC78K0 C Compiler Package This compiler converts programs written in C language into object codes executable with a microcontroller. This compiler should be used in combination with an optional assembler package and device file. This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part number: SxxxxCC78K0 DF780338Note Device File This file contains information peculiar to the device. This device file should be used in combination with an optional tool (RA78K0, CC78K0, SM78K0, and ID78K0-NS). Corresponding OS and host machine differ depending on the tool to be used with. Part number: SxxxxDF780338 CC78K0-L C Library Source File This is a source file of functions configuring the object library included in the C compiler package. This file is required to match the object library included in C compiler package to the customer's specifications. Operating environment for the source file is not dependent on the OS. Part number: SxxxxCC78K0-L
Note The DF780338 can be used in common with the RA78K0, CC78K0, SM78K0, and ID78K0-NS. Remark xxxx in the part number differs depending on the host machine and OS used.
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APPENDIX B
DEVELOPMENT TOOLS
SxxxxSP78K0
xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM
SxxxxRA78K0 SxxxxCC78K0
xxxx AB13 BB13 AB17 BB17 3P17 3K17 HP9000 series 700TM SPARCstationTM Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) HP-UXTM (Rel. 10.10) SunOSTM (Rel. 4.1.4), SolarisTM (Rel. 2.5.1) CD-ROM Supply Medium 3.5-inch 2HD FD
SxxxxDF780338 SxxxxCC78K0-L
xxxx AB13 BB13 3P16 3K13 3K15 Host Machine PC-9800 series, IBM PC/AT compatibles HP9000 series 700 SPARCstation OS Windows (Japanese version) Windows (English version) HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1) DAT 3.5-inch 2HD FD 1/4-inch CGMT Supply Medium 3.5-inch 2HD FD
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APPENDIX B
DEVELOPMENT TOOLS
B.2 Flash Memory Writing Tools
Flashpro III (part number: FL-PR3, PG-FP3) Flash Programmer FA-120GC Flash Memory Writing Adapter Flash programmer dedicated to microcontrollers with on-chip flash memory.
Flash memory writing adapter used connected to the Flashpro III. * FA-120GC: 120-pin plastic TQFP (GC-9EB, GC-9EV type)
Remark FL-PR3 and FA-120GC are products of Naito Densei Machida Mfg. Co., Ltd. Phone: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
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APPENDIX B
DEVELOPMENT TOOLS
B.3 Debugging Tools
B.3.1 Hardware
IE-78K0-NS In-Circuit Emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0-NS). This emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. This board is connected to the IE-78K0-NS to expand its functions. Adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. This is a combination of the IE-78K0-NS and IE-78K0-NS-PA.
IE-78K0-NS-PA Performance Board
IE-78K0-NS-A In-Circuit Emulator (with performance board) IE-70000-MC-PS-B Power Supply Unit IE-70000-98-IF-C Interface Adapter IE-70000-CD-IF-A PC Card Interface IE-70000-PC-IF-C Interface Adapter IE-70000-PCI-IF-A Interface Adapter IE-780338-NS-EM1 Emulation Board SWEX-120SE-1 Emulation Probe NQPACK120SE/ YQPACK120SE/ YQ-QUIDE Conversion Socket
This adapter is used for supplying power from a receptacle of 100 V to 240 VAC.
This adapter is required when using the PC-9800 series computer (except notebook type) as the IE-78K0-NS host machine (C bus compatible). This is PC card and interface cable required when using notebook computer as the IE-78K0-NS host machine (PCMCIA socket compatible). This adapter is required when using the IBM PC/AT compatible computers as the IE-78K0-NS host machine (ISA bus compatible). This adapter is required when using a computer with PCI bus as the IE-78K0-NS host machine. This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This probe is used to connect the in-circuit emulator to a target system and is designed for use with 120-pin plastic TQFP (GC-9EB, GC-9EV type). This conversion adapter connects the SWEX-120SE-1 to a target system board designed for a 120-pin plastic TQFP (GC-9EB, GC-9EV type).
Remark SWEX-120SE-1 and NQPACK120SE/YQPACK120SE/YQ-GUIDE are products of TOKYO ELETECH CORPORATION. Inquiry: Daimaru Kogyo, Ltd. Phone: Tokyo +81-3-3820-7112 Electronics Dept. Osaka +81-6-6244-6672 Electronics 2nd Dept.
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APPENDIX B
DEVELOPMENT TOOLS
B.3.2 Software (1/2)
SM78K0 System Simulator This system simulator is used to perform debugging at C source level or assembler level while simulating the operation of the target system on a host machine. This simulator runs on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with an optional device file (DF780338). Part number: SxxxxSM78K0
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxSM78K0
xxxx AB13 BB13 AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) CD-ROM Supply Medium 3.5-inch 2HD FD
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APPENDIX B
DEVELOPMENT TOOLS
B.3.2 Software (2/2)
ID78K0-NS Integrated Debugger (supporting in-circuit emulator IE-78K0-NS) This debugger is a control program to debug 78K/0 Series microcontrollers. It adopts a graphical user interface, which is equivalent visually and operationally to Windows or OSF/MotifTM. It also has an enhanced debugging function for C programs, and thus trace results can be displayed on screen in C level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. In addition, by incorporating function modules such as task debugger and system performance analyzer, the efficiency of debugging programs, which run on real-time OSs can be improved. It should be used in combination with the optional device file. Part number: SxxxxID78K0-NS
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxID78K0-NS
xxxx AB13 BB13 AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) CD-ROM Supply Medium 3.5-inch 2HD FD
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APPENDIX C
EMBEDDED SOFTWARE
For efficient development and maintenance of the PD780318, 780328, and 780338 Subseries, the following embedded products are available.
Real-Time OS
RX78K0 Real-Time OS RX78K0 is a real-time OS conforming to the ITRON specifications. Tool (configurator) for generating nucleus of RX78K0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K0) and device file (DF780338). The real-time OS is a DOS-based application. It should be used in the DOS Prompt when using in Windows. Part number: SxxxxRX78013-
Caution When purchasing the RX78K0, fill in the purchase application form in advance and sign the user agreement. Remark xxxx and in the part number differ depending on the host machine and OS used.
SxxxxRX78013-
001 100K 001M 010M S01 Source program Product Outline Evaluation object Mass-production object Maximum Number for Use in Mass Production Do not use for mass-produced product. 0.1 million units 1 million units 10 million units Source program for mass-produced object
xxxx AA13 AB13 BB13 3P16 3K13 3K15
Host Machine PC-9800 series IBM PC/AT compatibles
OS Windows (Japanese version)Note
Supply Medium 3.5-inch 2HD FD
Windows (Japanese version)Note 3.5-inch 2HD FD Windows (English version)Note
HP9000 series 700 SPARCstation
HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1)
DAT 3.5-inch 2HD FD 1/4-inch CGMT
Note Can also be operated in DOS environment.
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APPENDIX D
NOTES ON DESIGNING TARGET SYSTEM
The following figure shows the conditions when connecting the emulation probe to the conversion socket. Design the system taking into consideration the shapes and other conditions of the components to be mounted on the target system, and be sure to follow the configuration below. Figure D-1. Distance from In-Circuit Emulator to Conversion Socket
In-circuit emulator IE-78K0-NS or IE-78K0-NS-A Target system Emulation board IE-780338-NS-EM1 CN5 connection: 303 mm
Emulation probe SWEX-120SE-1 CN5
Conversion socket NQPACK120SE, YQPACK120SE, YQ-GUIDE
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APPENDIX D
NOTES ON DESIGNING TARGET SYSTEM
Figure D-2. Connection Condition of Target System
Emulation board IE-780338-NS-EM1 Emulation probe SWEX-120SE-1 48.5 mm 38.5 mm
13 mm
Conversion socket: NQPACK120SE, YQPACK120SE, YQ-GUIDE Pin 1 23 mm 38.5 mm 48.5 mm
Target system
Remark SWEX-120SE-1, NQPACK120SE, YQPACK120SE, and YQ-GUIDE are products of TOKYO ELETECH CORPORATION.
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APPENDIX E
REGISTER INDEX
E.1 Register Name Index
[A]
A/D conversion result register 0 (ADCR0) .......................................................................................................... 212 A/D converter mode register 0 (ADM0) ............................................................................................................... 213 Analog input channel specification register 0 (ADS0) ........................................................................................ 215 Asynchronous serial interface mode register 0 (ASIM0) .................................................................................... 239 Asynchronous serial interface status register 0 (ASIS0) .................................................................................... 241
[B]
Baud rate generator control register 0 (BRGC0) ................................................................................................ 241
[C]
Capture/compare control register 0 (CRC0) ....................................................................................................... 142 Clock output select register (CKS) ...................................................................................................................... 207 Correction address register 0 (CORAD0) ........................................................................................................... 338 Correction address register 1 (CORAD1) ........................................................................................................... 338 Correction control register (CORCN) .................................................................................................................. 339
[D]
D/A conversion value setting register 0 (DA0) ................................................................................................... 232 D/A converter mode register 0 (DAM0) ............................................................................................................... 233
[E]
8-bit timer compare register 50 (CR50) .............................................................................................................. 178 8-bit timer compare register 51 (CR51) .............................................................................................................. 178 8-bit timer compare register 52 (CR52) .............................................................................................................. 178 8-bit timer counter 50 (TM50) .............................................................................................................................. 178 8-bit timer counter 51 (TM51) .............................................................................................................................. 178 8-bit timer counter 52 (TM52) .............................................................................................................................. 178 8-bit timer mode control register 50 (TMC50) ..................................................................................................... 181 8-bit timer mode control register 51 (TMC51) ..................................................................................................... 181 8-bit timer mode control register 52 (TMC52) ..................................................................................................... 181 External interrupt falling edge enable register (EGN) ............................................................................... 215, 313 External interrupt rising edge enable register (EGP) ................................................................................ 215, 313
[I]
Internal expansion RAM size switching register (IXS) ....................................................................................... 349 Interrupt mask flag register 0H (MK0H) .............................................................................................................. 311 Interrupt mask flag register 0L (MK0L) ............................................................................................................... 311 Interrupt mask flag register 1L (MK1L) ............................................................................................................... 311 Interrupt request flag register 0H (IF0H) ............................................................................................................. 310 Interrupt request flag register 0L (IF0L) .............................................................................................................. 310 Interrupt request flag register 1L (IF1L) .............................................................................................................. 310
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APPENDIX E
REGISTER INDEX
[K]
Key return switching register (KRSEL) ................................................................................................................ 118
[L]
LCD clock control register 3 (LCDC3) ................................................................................................................. 284 LCD display mode register 3 (LCDM3) ............................................................................................................... 281
[M]
Memory expansion mode register (MEM) ........................................................................................................... 118 Memory size switching register (IMS) ................................................................................................................. 348
[O]
Oscillation stabilization time select register (OSTS) ................................................................................. 203, 326
[P]
Pin function switching register 8 (PF8) ...................................................................................................... 119, 287 Pin function switching register 9 (PF9) ...................................................................................................... 119, 287 Port 0 (P0) .............................................................................................................................................................. 96 Port 1 (P1) .............................................................................................................................................................. 98 Port 2 (P2) .............................................................................................................................................................. 99 Port 3 (P3) ............................................................................................................................................................ 101 Port 4 (P4) ............................................................................................................................................................ 104 Port 5 (P5) ............................................................................................................................................................ 106 Port 6 (P6) ............................................................................................................................................................ 107 Port 7 (P7) ............................................................................................................................................................ 109 Port 8 (P8) ................................................................................................................................................... 111, 112 Port 9 (P9) ................................................................................................................................................... 111, 112 Port 12 (P12) ........................................................................................................................................................ 113 Port mode register 0 (PM0) ........................................................................................................................ 114, 209 Port mode register 2 (PM2) ................................................................................................................................. 114 Port mode register 3 (PM3) ............................................................................................................... 114, 145, 183 Port mode register 4 (PM4) ................................................................................................................................. 114 Port mode register 5 (PM5) ................................................................................................................................. 114 Port mode register 6 (PM6) ................................................................................................................................. 114 Port mode register 7 (PM7) ............................................................................................................... 114, 168, 183 Port mode register 8 (PM8) ................................................................................................................................. 114 Port mode register 9 (PM9) ................................................................................................................................. 114 Port mode register 12 (PM12) ............................................................................................................................. 114 Prescaler mode register 0 (PRM0) ...................................................................................................................... 144 Priority specification flag register 0H (PR0H) ..................................................................................................... 312 Priority specification flag register 0L (PR0L) ...................................................................................................... 312 Priority specification flag register 1L (PR1L) ...................................................................................................... 312 Processor clock control register (PCC) ............................................................................................................... 124 Pull-up resistor option register 0 (PU0) ............................................................................................................... 116 Pull-up resistor option register 2 (PU2) ............................................................................................................... 116 Pull-up resistor option register 3 (PU3) ............................................................................................................... 116 Pull-up resistor option register 4 (PU4) ............................................................................................................... 116 Pull-up resistor option register 5 (PU5) ............................................................................................................... 116
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APPENDIX E
REGISTER INDEX
Pull-up resistor option register 6 (PU6) ............................................................................................................... 116 Pull-up resistor option register 7 (PU7) ............................................................................................................... 116 Pull-up resistor option register 12 (PU12) ........................................................................................................... 116
[S]
Serial clock select register 1 (CSIC1) ................................................................................................................. 267 Serial I/O shift register 1 (SIO1) .......................................................................................................................... 265 Serial I/O shift register 3 (SIO3) .......................................................................................................................... 257 Serial operation mode register 1 (CSIM1) .......................................................................................................... 266 Serial operation mode register 3 (CSIM3) .......................................................................................................... 258 16-bit timer capture/compare register 00 (CR00) .......................................................................................... 138 16-bit timer capture/compare register 01 (CR01) ............................................................................................... 139 16-bit timer compare register 4 (CR4) ................................................................................................................ 165 16-bit timer counter 0 (TM0) ................................................................................................................................ 138 16-bit timer counter 4 (TM4) ................................................................................................................................ 165 16-bit timer mode control register 0 (TMC0) ....................................................................................................... 140 16-bit timer mode control register 4 (TMC4) ....................................................................................................... 167 16-bit timer output control register 0 (TOC0) ...................................................................................................... 143 Static/dynamic display switching register 3 (SDSEL3) ....................................................................................... 285
[T]
Timer clock select register 50 (TCL50) ............................................................................................................... 179 Timer clock select register 51 (TCL51) ............................................................................................................... 179 Timer clock select register 52 (TCL52) ............................................................................................................... 179 Transmit buffer register 1 (SOTB1) ..................................................................................................................... 265 Transmit shift register 0 (TXS0) .......................................................................................................................... 238
[W]
Watch timer operation mode register 0 (WTNM0) .............................................................................................. 195 Watchdog timer clock select register (WDCS) .................................................................................................... 201 Watchdog timer mode register (WDTM) ............................................................................................................. 202
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APPENDIX E
REGISTER INDEX
E.2 Register Symbol Index [A]
ADCR0: ADM0: ADS0: ASIM0: ASIS0: A/D conversion result register 0 ......................................................................................................... 212 A/D converter mode register 0 ............................................................................................................ 213 Analog input channel specification register 0 .................................................................................... 215 Asynchronous serial interface mode register 0 ................................................................................. 239 Asynchronous serial interface status register 0 ................................................................................. 241
[B]
BRGC0: Baud rate generator control register 0 ............................................................................................... 241
[C]
CKS: CORAD0: CORAD1: CORCN: CR00: CR01: CR4: CR50: CR51: CR52: CRC0: CSIC1: CSIM1: CSIM3: Clock output select register ................................................................................................................ 207 Correction address register 0 ............................................................................................................. 338 Correction address register 1 ............................................................................................................. 338 Correction control register ................................................................................................................... 339 16-bit timer capture/compare register 00 ........................................................................................... 138 16-bit timer capture/compare register 01 ........................................................................................... 139 16-bit timer compare register 4 .......................................................................................................... 165 8-bit timer compare register 50 .......................................................................................................... 178 8-bit timer compare register 51 .......................................................................................................... 178 8-bit timer compare register 52 .......................................................................................................... 178 Capture/compare control register 0 .................................................................................................... 142 Serial clock select register 1 ............................................................................................................... 267 Serial operation mode register 1 ........................................................................................................ 266 Serial operation mode register 3 ........................................................................................................ 258
[D]
DA0: DAM0: D/A conversion value setting register 0 ............................................................................................. 232 D/A converter mode register 0 ............................................................................................................ 233
[E]
EGN: EGP: External interrupt falling edge enable register .......................................................................... 215, 313 External interrupt rising edge enable register ........................................................................... 215, 313
[I]
IF0H: IF0L: IF1L: IMS: IXS: Interrupt request flag register 0H ....................................................................................................... 310 Interrupt request flag register 0L ........................................................................................................ 310 Interrupt request flag register 1L ........................................................................................................ 310 Memory size switching register .......................................................................................................... 348 Internal expansion RAM size switching register ................................................................................ 349
[K]
KRSEL: Key return switching register .............................................................................................................. 118
[L]
LCDC3: LCDM3: LCD clock control register 3 ............................................................................................................... 284 LCD display mode register 3 .............................................................................................................. 281
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APPENDIX E
REGISTER INDEX
[M]
MEM: MK0H: MK0L: MK1L: Memory expansion mode register ...................................................................................................... 118 Interrupt mask flag register 0H ........................................................................................................... 311 Interrupt mask flag register 0L ............................................................................................................ 311 Interrupt mask flag register 1L ............................................................................................................ 311
[O]
OSTS: Oscillation stabilization time select register .............................................................................. 203, 326
[P]
P0: P1: P2: P3: P4: P5: P6: P7: P8: P9: P12: PCC: PF8: PF9: PM0: PM2: PM3: PM4: PM5: PM6: PM7: PM8: PM9: PM12: PR0H: PR0L: PR1L: PRM0: PU0: PU2: PU3: PU4: PU5: PU6: PU7: PU12: Port 0 ...................................................................................................................................................... 96 Port 1 ...................................................................................................................................................... 98 Port 2 ...................................................................................................................................................... 99 Port 3 .................................................................................................................................................... 101 Port 4 .................................................................................................................................................... 104 Port 5 .................................................................................................................................................... 106 Port 6 .................................................................................................................................................... 107 Port 7 .................................................................................................................................................... 109 Port 8 ........................................................................................................................................... 111, 112 Port 9 ........................................................................................................................................... 111, 112 Port 12 ................................................................................................................................................. 113 Processor clock control register ......................................................................................................... 124 Pin function switching register 8 ................................................................................................ 119, 287 Pin function switching register 9 ................................................................................................ 119, 287 Port mode register 0 ................................................................................................................... 114, 209 Port mode register 2 ............................................................................................................................ 114 Port mode register 3 .......................................................................................................... 114, 145, 183 Port mode register 4 ............................................................................................................................ 114 Port mode register 5 ............................................................................................................................ 114 Port mode register 6 ............................................................................................................................ 114 Port mode register 7 .......................................................................................................... 114, 168, 183 Port mode register 8 ............................................................................................................................ 114 Port mode register 9 ............................................................................................................................ 114 Port mode register 12 ......................................................................................................................... 114 Priority specification flag register 0H .................................................................................................. 312 Priority specification flag register 0L .................................................................................................. 312 Priority specification flag register 1L .................................................................................................. 312 Prescaler mode register 0 ................................................................................................................... 144 Pull-up resistor option register 0 ........................................................................................................ 116 Pull-up resistor option register 2 ........................................................................................................ 116 Pull-up resistor option register 3 ........................................................................................................ 116 Pull-up resistor option register 4 ........................................................................................................ 116 Pull-up resistor option register 5 ........................................................................................................ 116 Pull-up resistor option register 6 ........................................................................................................ 116 Pull-up resistor option register 7 ........................................................................................................ 116 Pull-up resistor option register 12 ...................................................................................................... 116
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APPENDIX E
REGISTER INDEX
[S]
SDSEL3: SIO1: SIO3: SOTB1: Static/dynamic display switching register 3 ....................................................................................... 285 Serial I/O shift register 1 ..................................................................................................................... 265 Serial I/O shift register 3 ..................................................................................................................... 257 Transmit buffer register 1 .................................................................................................................... 265
[T]
TCL50: TCL51: TCL52: TM0: TM4: TM50: TM51: TM52: TMC0: TMC4: TMC50: TMC51: TMC52: TOC0: TXS0: Timer clock select register 50 ............................................................................................................. 179 Timer clock select register 51 ............................................................................................................. 179 Timer clock select register 52 ............................................................................................................. 179 16-bit timer counter 0 .......................................................................................................................... 138 16-bit timer counter 4 .......................................................................................................................... 165 8-bit timer counter 50 .......................................................................................................................... 178 8-bit timer counter 51 .......................................................................................................................... 178 8-bit timer counter 52 .......................................................................................................................... 178 16-bit timer mode control register 0 ................................................................................................... 140 16-bit timer mode control register 4 ................................................................................................... 167 8-bit timer mode control register 50 ................................................................................................... 181 8-bit timer mode control register 51 ................................................................................................... 181 8-bit timer mode control register 52 ................................................................................................... 181 16-bit timer output control register 0 .................................................................................................. 143 Transmit shift register 0 ...................................................................................................................... 238
[W]
WDCS: WDTM: WTNM0: Watchdog timer clock select register ................................................................................................. 201 Watchdog timer mode register ............................................................................................................ 202 Watch timer operation mode register 0 .............................................................................................. 195
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APPENDIX F
REVISION HISTORY
The history of revisions up to this edition is shown below. "Applied to:" indicates the chapters to which the revision was applied. (1/3)
Edition 2nd edition Contents Addition of packages PD780316GC-xxx-9EV, 780318GC-xxx-9EV PD780326GC-xxx-9EV, 780328GC-xxx-9EV PD780336GC-xxx-9EV, 780338GC-xxx-9EV PD78F0338GC-9EV Change of block diagrams Figure 4-2 P00 to P04 Block Diagram Figure 4-3 P05 Block Diagram Figure 4-5 P20, P22, P23, P25 Block Diagram Figure 4-8 P31, P32 Block Diagram Figure 4-9 P33, P34 Block Diagram Figure 4-11 Falling Edge Detector Block Diagram Figure 4-16 P71, P73 Block Diagram Addition of Caution to Figure 4-24 Pin Function Switching Registers 8 and 9 (PF8, PF9) Format Addition of Note 3 to Figure 5-3 Processor Clock Control Register (PCC) Format CHAPTER 5 CLOCK GENERATOR CHAPTER 6 16BIT TIMER/EVENT COUNTER 0 Applied to: Throughout
CHAPTER 4 PORT FUNCTIONS
Change of Figure 6-13 Timing of Pulse Width Measurement Operation by FreeRunning Counter and One Capture Register (with Both Edges Specified)
Change of Figure 6-15 Capture Operation of CR01 with Rising Edge Specified Change of Figure 6-16 Timing of Pulse Width Measurement Operation with FreeRunning Counter (with Both Edges Specified) Change of Figure 6-18 Timing of Pulse Width Measurement Operation by FreeRunning Counter and Two Capture Registers (with Rising Edge Specified) Change of Figure 6-20 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) Change of following items in 6.6 16-Bit Timer/Event Counter 0 Cautions (2) 16-bit timer compare register setting (in the clear & start mode on match between TM0 and CR00) (3) Operation after compare register change during timer count operation (4) Capture register data retention timings (6) Operation of OVF0 flag <1> (11) Edge detection <2> Deletion of Caution in Figure 8-7 8-Bit Timer Mode Control Register 5n (TMC5n) Format CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51, 52 CHAPTER 12 A/D CONVERTER
Change of Figure 12-2 A/D Converter Mode Register 0 (ADM0) Format
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APPENDIX F
REVISION HISTORY
(2/3)
Edition 2nd edition Contents Applied to:
Deletion of infrared data transfer mode in CHAPTER 14 SERIAL INTERFACE UART0 CHAPTER 14 SERIAL INTERFACE UART0 Change of description in 16.4.2 3-wire serial I/O mode (3) Communication operation CHAPTER 16 SERIAL INTERFACE CSI1 Change of Figure 16-4 Timing in 3-Wire Serial I/O Mode Change of Figure 16-6 Output Operation of First Bit Change of Figure 16-7 Output Value of SO1 Pin (Last Bit) Addition of Figure 17-5 Relationship Between Reference Clock Generating Frame Frequency, and Frame Frequency CHAPTER 17 LCD CONTROLLER/ DRIVER Addition of Caution to Figure 18-2 Interrupt Request Flag Registers (IF0L, IF0H, IF1L) Format CHAPTER 18 INTERRUPT FUNCTIONS CHAPTER 22 PD78F0338 CHAPTER 24 ELECTRICAL SPECIFICATIONS CHAPTER 25 PACKAGE DRAWINGS CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS Change of APPENDIX B DEVELOPMENT TOOLS APPENDIX B DEVELOPMENT TOOLS APPENDIX C EMBEDDED SOFTWARE APPENDIX D NOTES ON DESIGNING TARGET SYSTEM CHAPTER 2 PIN FUNCTIONS
Addition of 22.3 Flash Memory Characteristics
Addition of CHAPTER 24 ELECTRICAL SPECIFICATIONS
Addition of CHAPTER 25 PACKAGE DRAWINGS
Addition of CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS
Change of APPENDIX C EMBEDDED SOFTWARE
Addition of APPENDIX D NOTES ON DESIGNING TARGET SYSTEM
3rd edition
Change of Recommended Connection of Unused Pins for the following pins in Table 2-1 Pin I/O Circuit Types * P60 to P63 * P80/S32 to P87/S39 (for flash memory version) * P90/S24 to P97/S31 (for flash memory version) Addition of description to (1) Internal high-speed RAM and (2) Internal expansion RAM in 3.1.2 Internal data memory space Change of Manipulatable Bit Unit for ports 8 and 9 in Table 3-4 Special Function Register List
CHAPTER 3 CPU ARCHITECTURE
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APPENDIX F
REVISION HISTORY
(3/3)
Edition 3rd edition Contents Change of Figure 4-18 P80 to P87 and P90 to P97 Block Diagram (Flash Memory Version) Modification of Caution in 4.2.11 Port 12 Modification of clear conditions in 7.3 (1) 16-bit timer counter 4 (TM4) Modification of Figure 7-1 16-Bit Timer/Event Counter 4 Block Diagram Modification of Note in Table 17-4 Frame Frequency CHAPTER 7 16-BIT TIMER/EVENT COUNTER 4 CHAPTER 17 LCD Applied to: CHAPTER 4 PORT FUNCTIONS
Modification of Figure 17-6 Static/Dynamic Display Switching Register 3 (SDSEL3) CONTROLLER/ DRIVER Format Switch in order between 17.4 LCD Controller/Driver Settings and 17.5 LCD Display RAM of previous edition Deletion of Table 17-7 LCD Drive Voltages of previous edition Standardization of abbreviations * Output voltage of VLC0 pin: VLCD0 * Output voltage of VLC1 pin: VLCD1 * Output voltage of VLC2 pin: VLCD2 Addition of description to 17.8.1 Static display example Modification of LCD panel connection example * Figure 17-13 Static LCD Panel Connection Example (SDSEL3n = 1: n = 0, 1) * Figure 17-16 3-Time-Division LCD Panel Connection Example (SDSEL3n = 0: n = 0 to 2) * Figure 17-19 4-Time-Division LCD Panel Connection Example (SDSEL3n = 0, n = 0 to 2) Change of emulation probe name SWEX-120SE SWEX-120SE-1 Modification of Figure D-1 Distance from In-Circuit Emulator to Conversion Socket Modification of Figure D-2 Connection Condition of Target System APPENDIX B DEVELOPMENT TOOLS APPENDIX D NOTES ON DESIGNING TARGET SYSTEM
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