D8.4 D8.0 D0.0 D1.0
D0.0
SA
L/T OP PARAM DATA PAD (42 Bytes)
00000000 FCS FCS[31:24] FCS[23:16] FCS[15:8] FCS[7:0]
D0.0 /T/ /R/ /I1/ or /I2/ /I2/ /I2/
PCS 8B
LSB MSB ABCDEFGH
[2]
Bytes Transmitted Notes: [1] [2] < > Means 10B encoded /I1/ or /I2/, depends on running disparity Bits Transmitted abcdefghij TX[0] RX[0] TX[9] RX[9] PCS 10B 10-Bit PHY Interface
MAC Control Frames
2-45
2.17.4 Reserved Multicast Address Disable
Receive pause frames are normally rejected as invalid if they do not have the reserved multicast address in the destination address field. Setting the MCFLTR bit in "Register 19-Flow Control 1" Section 4.3.16, programs the controller to accept receive pause frames regardless of the contents in the destination address field. When this bit is cleared, any value in the destination address field is accepted as a valid address.
2.17.5 MAC Control Frame AutoSend
The level of data in the receive FIFO also triggers the transmission of autogenerated pause frames. This feature is referred to as MAC control frame AutoSend. Appropriately setting the MCASEND[3:0] bits in "Register 19-Flow Control 1" Section 4.3.16, enable the AutoSend feature. When MAC control frame AutoSend is enabled, autogenerated pause frames are transmitted when the receive FIFO data exceeds a programmable threshold level called the MAC control AutoSend threshold. The MAC control AutoSend threshold can be set with the four MACSEND bits in "Register 19-Flow Control 1" Section 4.3.16. The automatic pause frame generation mechanism is described in more detail in Section 2.17.1, "Automatic Pause Frame Generation".
2.18 Reset
The controller has four resets which are described in Table 2.13. The controller should be ready for normal operation 1 s after the reset sequence has been completed for that bit.
2-46
Functional Description
Table 2.13
Name Controller Reset
Reset Description
Initiated By RESETn pin asserted LOW RST bit = 1 in Register 7 (Configuration i) Reset Action Reset datapath Flush transmit FIFO Flush receive FIFO Reset bits to default values Reset counters to 0
Transmit Reset
TXRST bit = 1 in Register 7 (Configuration 1)
Reset transmit data path Flush transmit FIFO Reset TX counters to 0
Receive Reset
RXRST bit = 1 in Register 7 (Configuration 1)
Reset receive data separate path Flush receive FIFO Reset RX counters to 0
AutoNegotiation Restart Counter Reset
ANRST bit = 1 in Register 7 (Configuration 1) CTRRST bit = 1 in Register 7 (Configuration 1)
Starts AutoNegotiation sequence Reset counters to 0
2.19 Counters
The controller has a set of 53 management counters. Each counter tabulates the number of times a specific event occurs. A complete list of all counters along with their definitions is shown in Table 2.14. and described in Chapter 4, Registers.These counters provide the necessary statistics to completely support the following specifications:
* * * *
RMON Statistics Group (IETF RFC1757) SNMP Interfaces Group (IETF RFC1213 and 1573) Ethernet-Like MIB (IETF RFC1643) Ethernet MIB (IEEE 802.3z, clause 30)
Counters
2-47
All counters are 32 bits wide. To obtain each 32-bit counter result, perform a read operation over the register interface. The address locations for each counter are shown in both Table 2.14 and Table 4.2. For the two 16-bit register locations associated with each 32-bit counter, the register with the lower value address always contains the least significant 16 bits of the counter result. Thus, C0 of the lower value address register is the counter LSB; C15 of the higher value address register is the counter MSB. When a counter read operation is initiated, the 32-bit counter result to be accessed is transferred to two internal 16-bit holding registers. These holding registers freeze and store the counter result for the duration of the read operation, while allowing the internal counter to continue to increment if needed. When a counter is read, the count can, under program control, be automatically reset to zero or remain unchanged. Counters can be programmed to either stop counting when they reach their maximum count or roll over. Burst reading is only supported for the low and high value address of the same counter. To read the value of multiple counters, either REGCSn or REGRDn must be deasserted then reasserted. Each counter has an associated status bit that is set when the counter becomes half full. These status bits can be individually programmed to cause an interrupt. The counter set in Table 2.14 includes the packet and octet statistics for the transmit and receive sides. The RMON specification literally states that packet and octet counters should only tabulate received information. This is sometimes interpreted to mean both transmitted and received information because Ethernet was originally a shared media protocol. As such, packet and octet counters for both transmit and receive are available in the controller, and the transmit and receive packet and octet counts can be summed together if desired. The exact correspondence of the actual MIB objects from the IETF and IEEE specifications to the actual controller counters locations is described in Chapter 5, Application Information.
2-48
Functional Description
Table 2.14
Counter Definition
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Size (Bits)
RMON Statistics Group MIB (RFC 1757)
Packets with receive FIFO overflow error. Bytes, exclusive of preamble, in good or bad packets. Bytes in packets with bad SFD are excluded.1 0b10000000 0b10000001
1
etherStatsDropEvents
RX
32
2
etherStatsOctets
RX
32
0b10000010 0b10000011 0b10000100 0b10000101 0b10000110 0b10000111 0b10001000 0b10001001
3
etherStatsPkts
RX
All packets, good or bad.1
32
4
etherStatsBroadcastPkts
RX
Broadcast packets, good only.1
32
5
etherStatsMulticastPkts
RX
Multicast packets, good only.1 Packets of legal-length with CRC error or alignment error. There are no alignment errors in 8B10B Gigabit Ethernet, so this counter will only count CRC errors for legal length packets. Packets of length < 64 bytes with no other errors. Packets of length > Max_Packet_Length with no other errors. Packets of length < 64 bytes with CRC error or alignment error. There are no alignment errors in 8B10B Gigabit Ethernet, so this counter will only count CRC errors with length < 64. Packets of length > Max_Packet_Length with CRC error or alignment error.
32
6
etherStatsCRCAlignErrors
RX
32
0b10001010 0b10001011 0b10001100 0b10001101 0b10001110 0b10001111
7
etherStatsUndersizePkts
RX
32
8
etherStatsOversizePkts
RX
32
9
etherStatsFragments
RX
32
0b10010000 0b10010001
10
etherStatsJabber
RX
There is no jabber function in Gigabit Ethernet, so this counter is undefined.
32
0b10010010 0b10010011
Counters
2-49
Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
CRS asserted and one or more collsions occurred.
Size (Bits)
11
etherStatsCollisions
TX/ RX
Since controller is Full Duplex only, this counter is undefined. Packets of length = 64 bytes, good or bad.1 Packets of length between 65-127 bytes, inclusive, good or bad.1 Packets of length between 128-255 bytes, inclusive, good or bad.1 Packets of length between 256-511 bytes, inclusive, good or bad.1 Packets of length between 512-1023 bytes, inclusive, good or bad.1 Packets of length between 1024 and Max_Packet_Length, inclusive, or bad.1 Bytes, exclusive of preamble, in good or bad packets.1
32
0b10010100 0b10010101 0b10010110 0b10010111 0b10011000 0b10011001 0b10011010 0b10011011 0b10011100 0b10011101 0b10011110 0b10011111 0b10100000 0b10100001 0b10100010 0b10100011 0b10100100 0b10100101 0b10100110 0b10100111 0b10101000 0b10101001 0b10101010 0b10101011 0b10101100 0b10101101 0b10101110 0b10101111 0b10110000 0b10110001
12
etherStatsPkts64Octets
RX
32
13
etherStatsPkts65to127Octets
RX
32
14
etherStatsPkts128to255Octets
RX
32
15
etherStatsPkts256to511Octets
RX
32
16
etherStatsPkts512to1023Octets
RX
32
17
etherStatsPkts1024to1518Octets
RX
32
18
etherStatsOctets_TX
TX
32
19
etherStatsPkts_TX
TX
All packets, good or bad.1
32
20
etherStatsBroadcastPkts_TX
TX
Broadcast packets, good only.1
32
21
etherStatsMulticastPkts_TX
TX
Multicast packets, good only.1 Packets of length = 64 bytes, good or bad.1 Packets of length between 65-127 bytes, inclusive, good or bad.1 Packets of length between 128-255, inclusive, good or bad.1 Packets of length between 256-511 bytes, inclusive, good or bad.1
32
22
etherStatsPkts64Octets_TX
TX
32
23
etherStatsPkts65to127Octets_TX
TX
32
24
etherStatsPkts128to255Octets_TX
TX
32
25
etherStatsPkts256to511Octets_TX
TX
32
2-50
Functional Description
Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
0b10110010 0b10110011
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Packets of length between 512-1023 bytes, inclusive, good or bad.1 Packets of length between 1023 and Max_Packet _Length, inclusive, good or bad.1
Size (Bits)
26
etherStatsPkts512to1023Octets_TX
TX
32
27
etherStatsPkts1024to1518Octets_ TX
TX
32
0b10110100 0b10110101
SNMP Interfaces Group MIB (RFC 1213 & 1573)
Bytes, including preamble, in good or bad packets. 0b10110110 0b10110111 0b10111000 0b10111001
28
ifInOctets
RX
32
ifInUcastPkts
RX
Unicast packets, good only. Multicast packets, good only. Equivalent to "etherStatsMulticastPkts" Broadcast packets, good only. Equivalent to "etherStatsBroadcastPkts" Broadcast and multicast packets, good only. Equivalent to "etherStatsBroadcastPkts + etherStatsMulticastPkts" Packets with receive FIFO overflow error. Equivalent to "etherStatsDropEvents" All packets, bad only. Equivalent to "etherStatsCRCAlignError + etherStatsUndersizePkts + etherStatsOversizePkts" Bytes, including preamble, in good or bad packets.
ifInMulticastPkts
RX
Use Ctr. #5
ifInBroadcastPkts
RX
Use Ctr. #4
ifInNUcastPkts
RX
Use Ctr. #4 and 5
ifInDiscards
RX
Use Ctr. #1
29
ifInErrors
RX
32
Use Ctr. #6 and 7 and 8 0b10111010 0b10111011 0b10111100 0b10111101 0b10111110 0b10111111
30
ifOutOctets
TX
32
31
ifOutUcastPkts
TX
Unicast packets, good and bad.
32
32
ifOutMulticastPkts
TX
Multicast packets, good and bad.
32
Counters
2-51
Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
0b11000000 0b11000001
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Size (Bits)
ifOutBroadcastPkts
TX
Broadcast packets, good and bad. Broadcast and multicast packets, good and bad. Equivalent to "ifOutMulticastPkts + ifOutBroadcastPkts" Packets with transmit FIFO underflow error. All Packets, bad only, exclusive of legal-length errors.
33
ifOutNUcastPkts
TX
32
Use Ctr. #32 and 33 0b11000010 0b11000011 0b11000100 0b11000101
34
ifOutDiscards
TX
32
35
ifOutErrors
TX
32
Ethernet-Like Group MIB
(RFC 1643)
Packets with alignment error only. There are no alignment errors in 8B10B Gigabit Ethernet, so this counter is undefined. Packets with CRC error only. Equivalent to "etherStatsCRCAlignErrors" Packets successfully transmitted after one and only one collision (ie: attempt value = 2). 38 dot3StatsSingleCollisionFrames TX Since controller is Full Duplex only, this counter is undefined. Packets successfully transmitted after more than one collision (ie: 2dot3StatsAlignmentErrors
RX
36
dot3StatsFCSErrors
RX
32
Use Ctr. #6
2-52
Functional Description
Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Packets that encounter a late collision, i.e. encountered collisions more than 512-bit times into transmitted packet. A late collision is counted twice: as a collision and a late collision.
Size (Bits)
42
dot3StatsLateCollisions
TX
Since controller is Full Duplex only, this counter is undefined. Packets not successfully transmitted after more than 15 collisions (ie: attempt value=16).
32
0b11010010 0b11010011
dot3StatsExcessiveCollisions
TX
Since controller is Full Duplex only, this counter is undefined. Packets with transmit FIFO underflow error. Equivalent to "ifOutDiscards" Carrier sense dropout errors, i.e. number of times that carrier sense is not asserted or deasserted during packet transmission, without a collision. This counter is only incremented once per packet, regardless of the number of dropout errors in the packet.
0b11010100 0b11010101
43
dot3StatsInternalMacTransmitErrors
TX
32
Use Ctr. #34
dot3StatsCarrierSenseErrors
TX
There is no CRS loopback in 8B10B Ethernet, so this counter is undefined. Packets of length > Max_Packet_Length with no other errors. Equivalent to "etherStatsOversizePkts" Packets with receive FIFO overflow error. Equivalent to "etherStatsDropEvents"
0b11010110 0b11010111
dot3StatsFrameTooLongs
RX
Use Ctr. #8
44
dot3StatsInternalMacReceiveErrors
RX
32
Use Ctr. #1
Ethernet MIB
(IEEE 802.3z Clause 30)
All packets, good only. Equivalent to "etherStatsPkts_TX - ifOutErrors" Packets successfully transmitted after one and only one collision (ie: attempt value = 2). Equivalent to "dot3StatsSingleCollisionFrames" Use Ctr. #19 through 35
aFramesTransmittedOK
TX
44
aSingleCollisionFrames
TX
32
Use Ctr. #38
Counters
2-53
Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Packets successfully transmitted after more than one collision (ie: 2Size (Bits)
aMultipleCollisionFrames
TX
Use Ctr. #39
aFramesReceivedOK
RX
Use Ctr. #29 and 4 and 5
aFrameCheckSequenceErrors
RX
Use Ctr. #37
44
aAlignmentErrors
RX
32
Use Ctr. #36 0b11011000 0b11011001
aOctetsTransmittedOK
TX
aFramesWithDeferredXmissions
TX
Use Ctr. #41
aLateCollisions
TX
Use Ctr. #42
aFrameAbortedDueToXSCollisions
TX
Use Ctr. #43
45
aFrameAbortedDueToIntMACXmit Error
TX
32
Use Ctr. #34
2-54
Functional Description
Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Carrier sense dropout errors, i.e. number of times that carrier sense is not asserted or deasserted during packet transmission, without a collision. This counter is only incremented once per packet, regardless of the number of dropout errors in the packet. Equivalent to "dot3StatsCarrierSenseErrors" Bytes, exclusive of preamble, in good packets only. Packets with receive FIFO overflow error. Equivalent to "etherStatsDropEvents" TX Multicast packets, good only. Equivalent to "etherStatsMulticastPkts_TX" TX Broadcast packets, good only. Equivalent to "etherStatsBroadcastPkts_TX" Packets with excessive deferral, i.e. packets waiting for transmission longer than two max packet times.
Size (Bits)
45
aCarrierSenseErrors
TX
32
Use Ctr. #44 0b11011010 0b11011011
aOctetsReceivedOK
RX
aFramesLostDueToIntMACRcvr Error
RX
Use Ctr. #1
aMulticastFrameXmittedOK
TX
Use Ctr. #21
46
aBroadcastFramesXmittedOK
TX
32
Use Ctr. #20
aFramesWithExcessiveDefferal
TX
Since controller is Full Duplex only, this counter is undefined. Multicast packets, good only. Equivalent to "etherStatsMulticastPkts" Broadcast packets, good only. Equivalent to "etherStatsBroadcastPkts" Packets of legal-length whose actual length is different from length/type field value. Packets with length/type field value > Max_Packet_Length. Packets of length > Max_Packet_Length with no other errors. Equivalent to "etherStatsOversizePkts"
0b11011100 0b11011101
aMulticastFramesReceivedOK
RX
Use Ctr. #5
47
aBroadcastFramesReceivedOK
RX
32
Use Ctr. #4
48
aInRangeLengthErrors
RX
32
0b11011110 0b11011111 0b11100000 0b11100001
aOutOfRangeLengthField
RX
49
aFrameTooLongErrors
RX
32
Use Ctr. #8
Counters
2-55
Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Number of times SQE was asserted. Equivalent to "dot3StatsSQETestError" One or more symbol errors received from a PHY during packet reception, exclusive of collision. This counter is only incremented once per packet, regardless of the number of symbol errors in that packet. Valid MAC Control packets. Equivalent to "apauseMACCtrlFramesTransmitted" Valid MAC Control packets. Equivalent to "apauseMACCtrlFramesReceived" Valid MAC Control packets with non-pause opcode. Valid MAC Control packets with pause opcode. Valid MAC Control packets with pause opcode.
Size (Bits)
49
aSQETestErrors
RX
32
Use Ctr. #40
aSymbolErrorDuringCarrier
RX
0b11100010 0b11100011
aMACControlFramesTransmitted
TX
Use Ctr. #52
50
aMACControlFramesReceived
RX
32
Use Ctr. #53 0b11100100 0b11100101 0b11100110 0b11100111 0b11101000 0b11101001
51
aUnsupportedOpcodesReceived
RX
32
52
apauseMACCtrlFramesTransmitted
TX
32
53
apauseMACCtrlFramesReceived
RX
32
1. Footnotes a. Bad RX packet = legal-length error, CRC error, receive FIFO overflow, symbol error. Where: CRC Error is bad FCS with an integral number of octets. Alignment Error is bad FCS with nonintegral number of octets. Symbol Error is an invalid codeword or a /V/. b. Bad TX packet = legal-length error, transmit FIFO underflow. c. Legal-length packet is between 64 and Max_Packet_Length in bytes. Preamble is not included in length count. d. Max_Packet_Length for the counters can be programmed to be either 1518, 1522, 1535, or unlimited bytes. 1518 is the default for both transmit and receive. e. The counter result is stored in two 16-bit registers. Thus, there are two register addresses for each counter. Of the two registers for a given counter, the register with the lower value address contains the least significant counter bits. f. The RMON specs explicitly states that packet and octet counters should only tabulate received information. This is sometimes interpreted to mean both transmitted and received information because Ethernet was originally a shared media. As such, transmit packet and octet counters are also available in counters 18-27 and can be summed with receive packet and octet counts if desired.
2-56
Functional Description
2.19.1 Counter Half Full
Each 32-bit counter has a half-full status output bit associated with it. The half-full bits are stored in "Register 112-115-Counter Half Full 1-4" Section 4.3.23. A half-full bit is set when its counter value reaches 0x80000000 (MSB bit goes from a 0 to a 1), so it is set when the counter becomes half full. The counter half-full bits latch themselves when they are set. Each bit stays latched until either the bit is read or the counter register with which the bit is associated is read. Counter half-full bits are also interrupt bits (the setting of any counter half-full bit can be programmed to cause the assertion of the interrupt pin, REGINT). When a read clears the counter half-full bit, the interrupt is also cleared. Note: REGINT stays asserted until all interrupt bits are cleared.
Each counter half-full bit can be individually programmed to assert (or not assert) the REGINT pin. Setting the appropriate mask bit associated with the counter half full "Registers 120-123-Counter Half Full Mask 1- 4" Section 4.3.24, programs the controller to mask (disable) the interrupt caused by the corresponding counter half full detect bit.
2.19.2 Counter Reset On Read
A read operation on a counter does not normally affect the counter values. However, setting the CTR_RD bit in "Register 9-Configuration 3" Section 4.3.10, programs the counter to automatically reset to zero when read. When the CTR_RD bit is set, a counter is cleared to 0 whenever any one of the two 16-bit counter registers associated with a 32-bit counter is read. An internal holding register stores the entire 32-bit counter result so that the result is correctly read as long as two successive 16-bit counter register reads are performed from the same counter. In order to read the cleared value, the read operation needs to be deasserted then reasserted (i.e., REGCSn and REGRDn). When the CTR_RD bit is cleared (default), a read does not affect the count in the counter, as long as the counter is not at maximum count. If a counter is at maximum count, its count is always reset to 0 when the counter is read.
Counters
2-57
2.19.3 Counter Rollover
Counters normally roll over to zero when they exceed their maximum count, (receive an increment when counter is at maximum count). The counters can be programmed to freeze and stop counting once they reach their maximum count. Setting the CTR_ROLL bit in "Register 9- Configuration 3" Section 4.3.10, programs the counters to freeze when they reach their maximum count.
2.19.4 Counter Maximum Packet Size
The maximum packet size used for the management counter statistics can be programmed to be one of four values. Setting the CMXPKT[1:0] bits in "Register 10-Configuration 4" Section 4.3.11, select the maximum packet size. This selection is described in the register descriptions for those registers and is also summarized in Table 2.15. The bits in Table 2.15 affect the maximum packet size for the counters only; the maximum packet size for the MAC section is described in Section 2.8, "Receive MAC". Table 2.15 Counter Maximum Packet Size Selection
Maximum Packet Size (bytes) Unlimited 1535 1522 1518
CMXPKT [1:0] 11 10 01 00
2.19.5 Counter Reset
Setting the CTRRST bit in "Register 7-Configuration 1" Section 4.3.8, resets all counters to zero. Asserting the controller reset pin, RESETn, also resets the counters to zero.
2-58
Functional Description
2.20 Loopback
To enable the diagnostic loopback mode, set the LPBK bit in "Register 10-Configuration 4" Section 4.3.11. When the loopback mode is enabled, the transmit data input to the transmit system interface and output from the 8B10B encoder is internally looped back into the receive 8B10B decoder and is available to be read from the receive system interface.
2.21 Test Modes
The TEST pin is reserved for factory test, and must be tied LOW for normal operation. Asserting the TAP pin HIGH, sets all inputs and outputs in the high-impedance state. This pin is intended for controller and board diagnostic testing.
Loopback
2-59
2-60
Functional Description
Chapter 3 Signal Descriptions
This chapter describes the 8101/8104 Gigabit Ethernet Controller signals in the following sections:
* * * * *
Section 3.1, "System Interface Signals" Section 3.2, "10-Bit PHY Interface Signals" Section 3.3, "Register Interface Signals" Section 3.4, "Micellaneous Signals" Section 3.5, "Power Supply Signals"
Figure 3.1 is a diagram of the 8101/8104 signals.
8101/8104 Gigabit Ethernet Controller
3-1
Figure 3.1
8101/8104 Interface Diagram
SCLK TXENn TXD[31:0] TXBE[3:0] TXSOF TXEOF TXWM1n TXWM2n TXDC CLR_TXDC FCNTRL TXCRCn RXENn RXOEn RXD[31:0] RXBE[3:0] RXSOF RXEOF RXWM1 RXWM2 RXDC CLR_RXDC RXABORT TBC TX[9:0]] RBC[1:0] RX[9:0] EN_CDET EWRAP LCK_REFn REGCSn REGCLK REGD[15:0] REGA[7:0] REGRDn REGWRn REGINT TCLK LINKn SD RESETn TAP TEST
10-Bit PHY Interface
System Interface
Register Interface
Miscellaneous
VCC GND[30:0]
3.3 V 5% Ground
3-2
Signal Descriptions
3.1 System Interface Signals
This section describes the 8101/8104 system interface signals. CLR_RXDC Clear RXDC Input When CLR_RXDC is asserted, the RXDC pin is cleared. Wheh CLR_RXDC is LOW, the RXDC pin is not cleared. CLR_RXDC is clocked in on the rising edge of the system clock, SCLK. This pin only clears RXDC when AutoClear mode is disabled. When AutoClear mode is enabled, this pin is ignored and RXDC is automatically cleared two clock cycles after RXEOF is asserted. CLR_TXDC Clear TXDC Input When CLR_TXDC is HIGH, the TXDC pin is cleared. When CLR_TXDC is LOW, the TXDC pin is not cleared. TXDC is clocked in on the rising edge of the system clock, SCLK. This pin only clears TXDC when AutoClear mode is disabled. When AutoClear mode is enabled, this pin is ignored and TXDC is automatically cleared two clock cycles after TXEOF is asserted. FCNTRL Flow Control Enable Input When FCNTRL is HIGH, transmitter automatically transmits a MAC control pause frame. When FCNTRL is LOW, the controller resumes normal operation. FCNTRL is clocked in on the rising edge of the system clock, SCLK. Receive FIFO Data Abort Input When RXABORT is asserted, the packet being read out on RXD[31:0] is aborted and discarded. When LOW, the packet is not aborted and discarded. RXABORT is clocked in on the rising edge of the system clock, SCLK. Receive Byte Enable Output These outputs determine which bytes of the current data on RXD[31:0] contain valid data. RXBE[3:0] is clocked out of the device on the rising edge of the system interface clock, SCLK.
RXABORT
RXBE[3:0]
System Interface Signals
3-3
RXD[31:0]
Receive Data Output This output bus contains the 32-bit received data word that is clocked out on the rising edge of the system interface clock, SCLK. Receive Packet Discard Output When HIGH, device detects that current packet being output on the system interface has an error and should be discarded. When LOW, no discard. Asserting the RXABORT pin or setting the AUTORXAB bit in "Register 9-Configuration 3" Section 4.3.10, automatically discards the packet being output. RXDC is clocked out on the rising edge of the system clock, SCLK. If AutoClear mode is not enabled, this output is latched HIGH and stays latched until cleared with the assertion of the CLR_RXDC pin. If AutoClear mode is enabled, this output is latched HIGH and automatically clears itself LOW two clock cycles after RXEOF is asserted. RXDC can also be cleared with RXABORT if programmed to do so.
RXDC
RXENn
Receive Enable Input This input must be asserted active LOW to enable the current data word to be clocked out of the receive FIFO on RXD[31:0]. RXENn is clocked in on the rising edge of the system interface clock, SCLK. Receive End Of Frame Output This output is asserted on the same clock cycle as the last word of the packet is being read out of the receive FIFO on RXD[31:0]. RXEOF is clocked out of the device on the rising edge of the system interface clock, SCLK. Receive Output Enable Input When LOW, all receive outputs are active. When HIGH, receive outputs (RXD[31:0], RXBE[3:0], RXSOF, RXEOF) are high-impedence. Receive Start Of Frame Output This output is asserted on the same clock cycle as the first word of the packet is being read out of the receive FIFO on RXD[31:0]. RXSOF is clocked out of the device on the rising edge of the system interface clock, SCLK.
RXEOF
RXOEn
RXSOF
3-4
Signal Descriptions
RXWM1
Receive FIFO Watermark 1 Output When RXWM1 is LOW, the receive FIFO data is less than or equal to the receive FIFO watermark 1 threshold. When HIGH, the receive FIFO data is greater than the watermark. RXWM1 is clocked out on the rising edge of the system clock, SCLK. Data is valid on RXD[31:0] when either RXWM1 or RXWM2 is asserted, independent of RXENn. Receive FIFO Watermark 2 Output When RXWM2 is LOW, the receive FIFO data is less than or equal to the receive FIFO watermark 2 threshold and no EOF in FIFO. When HIGH, the receive FIFO data is greater than the watermark. RXWM2 is clocked out on the rising edge of the system clock, SCLK. Data is valid on RXD[31:0] when either RXWM1 or RXWM2 is asserted, independent of RXENn. System Interface Clock Input This input clocks data in and out of the transmit and receive FIFOs on TXD[31:0] and RXD[31:0], respectively. All system interface inputs and outputs are also clocked in and out on the rising edge of SCLK, with the exception of RXOEn. SCLK clock frequency must be between 33-66 MHz. Transmit Byte Enable Input These inputs determine which bytes of the current 32-bit word on TXD[31:0] contain valid data. TXBE[3:0] is clocked into the device on the rising edge of the system interface clock, SCLK. Transmit CRC Enable Input When TXCRC is LOW, CRC is calculated and appended to the current packet being input on the system interface. When TXCRC is HIGH, CRC is not calculated. TXCRCn is clocked in on the rising edge of the system clock, SCLK, and must be asserted on the same SCLK clock cycle as TXSOF. Transmit Data Input This input bus contains the 32-bit data word that is clocked into the transmit FIFO on the rising edge of the system interface clock, SCLK.
RXWM2
SCLK
TXBE[3:0]
TXCRCn
TXD[31:0]
System Interface Signals
3-5
TXDC
Transmit Packet Discard Output When TXDC is HIGH, the controller detects that current packet being input on the system interface has an error, rest of packet ignored. When LOW, The packet is not discarded. TXDC is clocked out on thr rising edge of the system clock. If AutoClear mode is not enabled, this output is latched HIGH and stays latched until cleared with the assertion of the CLR_TXDC pin. If AutoClear mode is enabled, this output is latched HIGH and automatically clears itself LOW two clock cycles after TXEOF is asserted.
TXENn
Transmit Enable Input This input must be low to enable the current data word on TXD[31:0] to be clocked into the transmit FIFO. TXENn is clocked in on the rising edge of the system interface clock, SCLK. Transmit End Of Frame Input This input must be asserted on the same clock cycle as the last word of the packet is being clocked in on TXD[31:0]. TXEOF is clocked into the device on the rising edge of the system interface clock, SCLK. Transmit Start Of Frame Input This input must be asserted on the same clock cycle as the first word of the packet is being clocked in on TXD[31:0]. TXSOF is clocked into the device on the rising edge of the system interface clock, SCLK. Transmit FIFO Watermark 1 Output When TXWM1n is HIGH, the transmit FIFO data is less than or equal to the transmit FIFO watermark 1. When LOW, the transmit FIFO data is above the watermark. TXWM1n is clocked out on the rising edge of the system clock, SCLK. Transmit FIFO Watermark 2 Output When TXWM2n is HIGH, the transmit FIFO data is less than or equal to the transmit FIFO watermark 2. When LOW, the transmit FIFO data is above the watermark. TXWM2n is clocked out on the rising edge of the system clock, SCLK.
TXEOF
TXSOF
TXWM1n
TXWM2n
3-6
Signal Descriptions
3.2 10-Bit PHY Interface Signals
This section describes the 8101/8104 10-Bit PHY interface signals. EN_CDET Comma Detect Enable Output This output is asserted when either the receive 8B10B PCS state machine is in the loss of synchronization state or the CDET bit is set in "Register 9-Configuration 3" Section 4.3.10. This output is typically used to enable the comma detect function in an external physical layer device. Loopback Output Enable Output This output is asserted whenever the EWRAP bit is set in "Register 9-Configuration 3" Section 4.3.10. This output is typically used to enable loopback in an external physical layer device. Receiver Lock Output This output is asserted whenever the LCK_REFn bit is set in "Register 9-Configuration 3" Section 4.3.10. This output is typically used to enable the receive lock-to-reference mechanism in an external physical layer. Receive Clock Input The RBC[1:0] signals clock receive data into the controller on the clock rising edge. RBC[1:0] are 62.5 MHz clocks, 180 out of phase, that clock data into the controller on RX[9:0] at an effective rate of 125 MHz. For the device to acquire synchronization, the comma code must be input on RXD[9:0] on RBC1 rising edges. Receive Data Input These inputs contain receive data that are clocked in on the rising edges of RBC[1:0]. Transmit Clock Output This output clock transmits data out on TX[0:9] on its rising edge. TBC is a 125 MHz clock and is generated from TCLK.
EWRAP
LCK_REFn
RBC[1:0]
RX[9:0]
TBC
10-Bit PHY Interface Signals
3-7
TX[9:0]
Transmit Data Output These interface outputs transmit data on the rising edge of TBC.
3.3 Register Interface Signals
This section describes the 8101/8104 register interface signals. REGA[7:0] Register Interface Address Input These inputs provide the address for the specific internal register to be accessed, and are clocked into the device on the rising edge of REGCLK. Register Interface Clock Input This input clocks data in and out on REGD[15:0], REGA[7:0], REGRDn, and REGWRn on its rising edge. REGCLK frequency must be between 5-40 MHz. Register Interface Chip Select Input This input must be asserted to enable reading and writing data on REGD[15:0] and REGA[7:0]. This input is clocked in on the rising edge of REGCLK. Register Interface Data Bus Bidirectional This bus is a bidirectional 16-bit data path to and from the internal registers. Data is read and written from and to the internal registers on the rising edge of the register clock, REGCLK. Register Interface Interrupt Output This output is asserted when certain interrupt bits in the registers are set, and it remains latched HIGH until all interrupt bits are read and cleared. Register Interface Read Input When this input is asserted, the accessed internal register is read (data is output from the register). This input is clocked into the device on the rising edge of REGCLK. Register Interface Write Input When this input is asserted, the accessed internal register is written (data is input to the register). This input is clocked into the device on the rising edge of REGCLK.
REGCLK
REGCSn
REGD[15:0]
REGINT
REGRDn
REGWRn
3-8
Signal Descriptions
3.4 Micellaneous Signals
This section describes the 8101/8104 micellaneous signals. LINKn Receive Link Output When this signal is HGH, there is no link. When this signal is asserted, the receive link is synchronized and configured. Reserved These pins are reserved and must be left floating. Reset Input When this signal is HIGH, controller is in normal operation. When this signal is asserted, controller resets, FIFO's are cleared, counters are cleared, and register bits are set to default values. Signal Detect Input When this signal is asserted, data detected on receive 10-bit PHY is valid. When SD is LOW, data is not valid and the 8B10B PCS receiver is forced to a loss of sync state. This signal is ignored (assumed high) unless the SD_EN bit in "Register 9-Configuration 3" Section 4.3.10, is cleared. 3-state all pins Input This pin is used for testing purposes only. When asserted, all output and bidirectional pins are placed in a high-impedence state. Test Mode Input This pin is used for factory test and must be tied LOW for proper operation. Transmit Clock Input This 125 MHz input clock is used by the 8B10B PCS section and generates the 125 MHz transmit output clock, TBC, is used to output data on the 10-bit PHY interface.
RESERVED RESETn
SD
TAP
TEST
TCLK
Micellaneous Signals
3-9
3.5 Power Supply Signals
This section describes the 8101/8104 power supply signals. VCC[22:0] GND[30:0] Positive Supply. +3.3 V 5% Volts Ground 0 Volts - -
3-10
Signal Descriptions
Chapter 4 Registers
The 8101/8104 controller has 136 internal 16-bit registers. Twenty-two registers are available for setting configuration inputs and reading status outputs. The remaining 114 registers are associated with the management counters. This chapter contains the following sections:
* * *
Section 4.1, "Register Interface" Section 4.2, "Register Addresses" Section 4.3, "Register Definitions"
4.1 Register Interface
The register interface is a 16-bit bidirectional data interface that allows access to the internal registers. The register interface consists of 29 signals:
* * * * * * *
Sixteen bidirectional data I/O bits (REGD[15:0]) Eight register address inputs (REGA[7:0]) One chip select input (REGCSn) One clock input (REGCLK) The REGCLK clock frequency must be between 5-40 MHz. One read select input (REGRDn) One write select input (REGWRn) One interrupt output (REGINT)
All register accesses are done on the rising edge of the REGCLK clock. To access a register through the register interface, REGCSn must be asserted and is sampled on the rising edge of REGCLK. On that same
8101/8104 Gigabit Ethernet Controller
4-1
rising edge of REGCLK, the address of the register that is accessed is clocked in on REGA[7:0]. On that same rising edge of REGCLK, either REGRDn or REGWRn must also be asserted. These signals determine whether the register access is a read or write cycle. During a write cycle, the data to be written to a specific register is clocked in on the rising edge of the same clock that clocked in the other inputs. During a read cycle, the data is output on REGD[15:0] some delay after the rising edge of REGCLK that clocked in the input information. REGCSn can remain LOW for multiple REGCLK cycles so that many registers can be read or written during one REGCSn assertion. During read cycles, the delay from REGCLK to data valid on the REGD[15:0] pins is a function of which register is being accessed. Data read from any register, exclusive of the Counter 1-53 registers, appears on the REGD[15:0] pins in one REGCLK cycle. Data read from the Counter 1-53 registers takes at most six REGCLK cycles to be available on REGD[15:0] for the first 16 bits of the counter result, and at most three REGCLK cycles for the second 16 bits of the counter result. Refer to Chapter 6, Specifications for details of the interface timing characteristics.
4.1.1 Bit Types
The register interface is bidirectional, and there are many types of bits in the registers. The bit type definitions are summarized in Table 4.1. Write bits (W) are inputs during a write cycle and are 0 during read cycles. Read bits (R) are outputs during a read cycle and ignored and highimpedance during a write cycle. Read/Write bits (R/W) are actually write bits that can be read during a read cycle. R/WSC bits are R/W bits that are self clearing after a set period of time or after a specific event has completed. R/LL bits are read bits that latch themselves when they go to 0 and they stay latched until read. After they are read, they are set to 1. R/LH bits are the same as R/LL bits except that they latch to 1. R/LT are read bits that latch themselves whenever they make a transition or change value and they stay latched until they are read. After R/LT bits are read, they are updated to their current value. R/LLI, R/LHI, and R/LTI bits function the same as R/LL, R/LH and R/LT bits, respectively, except they also assert interrupt if programmed to do so (not masked).
4-2
Registers
Table 4.1
Register Bit Type Definition
Bit Types Definition Write Cycle Input No operation, input ignored Input Input Clears itself after operation completed Output Input ignored when bit goes to 0, bit latched, and interrupt asserted (if not masked) When bit is read, bit updated and interrupt cleared Read Cycle No operation, output not valid Output Ouput Ouput
Symbol W R R/W R/W SC R/LL R/LLI
Name Write Read Read/Write Read/Write Self Clearing
Read, Latch when 0 No operation latching Read, Latch when 0, Assert Interrupt
R/LH R/LHI
Read/write Read/write, latch HIGH with interrupt
No operation, input ignored
Output When bit goes to 1, bit latched & interrupt asserted (if not masked) When bit is read, bit updated and interrupt cleared
R/LT R/LTI
Read, Latch on Transition Read, Latch on Transition with interrupt
No operation, input ignored
Output When bit transitions, bit latched and interrupt asserted (if not masked) When bit is read, bit updated and interrupt cleared
4.1.2 Interrupt
An interrupt is triggered when certain output status bits change state. These bits are called interrupt bits and are designated as R/LLI, R/LHI, and R/LTI bits, as described in the previous section. The interrupt bits reside in "Register 11-Status 1" Section 4.3.12, and "Register 112-115- Counter Half Full 1-4" Section 4.3.23,. Interrupt bits automatically latch
Register Interface
4-3
themselves and assert the interrupt pin, REGINT. Interrupt bits stay latched until they are read. When interrupt bits are read, the interrupt pin REGINT is deasserted and the interrupt bits that caused the interrupt are updated to their current value. Each interrupt bit can be individually masked and subsequently removed as an interrupt bit. Setting the appropriate mask register bits in "Register 14-Status Mask 1" Section 4.3.13, register and "Registers 120-123- Counter Half Full Mask 1-4" Section 4.3.24, preform this function.
4.1.3 Register Structure
The Controller has 136 internal 16-bit registers. 22 registers are available for setting configuration inputs and reading status outputs. The remaining 114 registers are associated with the management counters. The location of all registers is described in Table 4.2 Register Address Table. The definition of each bit for each register is described in Section 4.3.1 through Section 4.3.25.
4.2 Register Addresses
Table 4.2 lists the register number, register address, register name, and the paragraph that describes the register. Table 4.2
Register Numbers 0 1 2 3 4 5 6 7
Register Address
Register Address (REGAD[7:0] Pins) 0b00000000 0b00000001 0b00000010 0b00000011 0b00000100 0b00000101 0b00000110 0b00000111 Paragraph Number 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8
Register Name MAC Address 1 MAC Address 2 MAC Address 3 MAC Address Filter 1 MAC Address Filter 2 MAC Address Filter 3 MAC Address Filter 4 Configuration 1
4-4
Registers
Table 4.2
Register Numbers 8 9 10 11 12-13 14 15-16 17 18 19 20 21 22 23 24 25-31 32 33-111 112-115 116-119 120-123
Register Address (Cont.)
Register Address (REGAD[7:0] Pins) 0b00001000 0b00001001 0b00001010 0b00001011 0b00001100- 0b00001101 0b00001110 0b00001111- 0b00010000 0b00010001 0b00010010 0b00010011 0b00010100 0b00010101 0b00010110 0b00010111 0b00011000 0b00011001- 0b00011111 0b00100000 0b00011001- 0b01101111 0b01110000- 0b01110011 0b01110100- 0b01110111 0b01111000- 0b01111011 Paragraph Number 4.3.9 4.3.10 4.3.11 4.3.12
Register Name Configuration 2 Configuration 3 Configuration 4 Status 1 Reserved Status Mask 1 Reserved Transmit FIFO Threshold Receive FIFO Threshold Flow Control 1 Flow Control 2 AutoNegotiation Base Page Transmit AutoNegotiation Base Page Receive AutoNegotiation Next Page Transmit AutoNegotiation Next Page Receive Reserved Device ID Reserved Counter Half Full 1-4 Reserved Counter Half Full Mask 1-4
4.3.13
4.3.14 4.3.15 4.3.16 4.3.17 4.3.18 4.3.19 4.3.20 4.3.21
4.3.22
4.3.23
4.3.24
Register Addresses
4-5
Table 4.2
Register Numbers 124-127 128-129 130-131 132-133 134-135 136-137 138-139 140-141 142-143 144-145 146-147 148-149 150-151 152-153 154-155 156-157
Register Address (Cont.)
Register Address (REGAD[7:0] Pins) 0b01111100- 0b01111111 0b10000000- 0b10000001 0b10000010- 0b10000011 0b10000100- 0b10000101 0b10000110- 0b10000111 0b10001000- 0b10001001 0b10001010- 0b10001011 0b10001100- 0b10001101 0b10001110- 0b10001111 0b10010000- 0b10010001 0b10010010- 0b10010011 0b10010100- 0b10010101 0b10010110- 0b10010111 0b10011000- 0b10011001 0b10011010- 0b10011011 0b10011100- 0b10011101 Paragraph Number
Register Name Reserved Counter 1- etherStatsDropEvents Counter 2 - etherStatsOctets Counter 3 - etherStatsPkts Counter 4 - etherStatsBroadcastPkts Counter 5 - etherStatsMulticastPkts Counter 6 - etherStatsCRCAlignErrors Counter 7 - etherStatsUndersizePkts Counter 8 - etherStatsOversizePkts Counter 9 - etherStatsFragments Counter 10 - etherStatsJabber Counter 11 - etherStatsCollisions Counter 12 - etherStatsPkts64Octets Counter 13 - etherStatsPkts65to127Octets Counter 14 - etherStatsPkts128to255Octets Counter 15 - etherStatsPkts256to511Octet
4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25
4-6
Registers
Table 4.2
Register Numbers 158-159 160-161 162-163 164-165 166-167 168-169 170-171 172-173 174-175 176-177 178-179 180-181 182-183 184-185 186-187 188-189
Register Address (Cont.)
Register Address (REGAD[7:0] Pins) 0b10011110- 0b10011111 0b10100000- 0b10100001 0b10100010- 0b10100011 0b10100100- 0b10100101 0b10100110- 0b10100111 0b10101000- 0b10101001 0b10101010- 0b10101011 0b10101100- 0b10101101 0b10101110- 0b10101111 0b10110000- 0b10110001 0b10110010- 0b10110011 0b10110100- 0b10110101 0b10110110- 0b10110111 0b10111000- 0b10111001 0b10111010- 0b10111011 0b10111100- 0b10111101 Paragraph Number 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25
Register Name Counter 16 - etherStatsPkts512to1023Octets Counter 17 - etherStatsPkts1024to1518Octets Counter 18 - etherStatsOctets_TX Counter 19 - etherStatsPkts_TX Counter 20 - etherStatsBroadcastPkts_TX Counter 21 - etherStatsMulticastPkts_TX Counter 22 - etherStatsPkts64Octets_TX Counter 23 - etherStatsPkts65to127Octets_TX Counter 24 - etherStatsPkts128to255Octets_TX Counter 25 - etherStatsPkts256to511Octets_TX Counter 26 - etherStatsPkts512to1023Octets_TX
Counter 27 - etherStatsPkts1024to1518Octets_TX 4.3.25 Counter 28 - ifInOctets Counter 29 - ifInUcastPkts Counter 30 - ifOutOctets Counter 31 - ifOutUcastPkts 4.3.25 4.3.25 4.3.25 4.3.25
Register Addresses
4-7
Table 4.2
Register Numbers 190-191 192-193 194-195 196-197 198-199 200-201 202-203 204-205 206-207 208-209 210-211 212-213 214-215 216-217 218-219 220-221
Register Address (Cont.)
Register Address (REGAD[7:0] Pins) 0b10111110- 0b10111111 0b11000000- 0b11000001 0b11000010- 0b11000011 0b11000100- 0b11000101 0b11000110- 0b11000111 0b11001000- 0b11001001 0b11001010- 0b11001011 0b11001100- 0b11001101 0b11001110- 0b11001111 0b11010000- 0b11010001 0b11010010- 0b11010011 0b11010100- 0b11010101 0b11010110- 0b11010111 0b11011000- 0b11011001 0b11011010- 0b11011011 0b11011100- 0b11011101 Paragraph Number 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25
Register Name Counter 32 - ifOutMulticastPkts Counter 33 - ifOutBroadcastPkts Counter 34 - ifOutDiscards Counter 35 - ifOutErrors Counter 36 - dot3StatsAlignmentErrors Reserved Counter 38 - dot3StatsSingleCollisionFrames Counter 39 - dot3StatsMultipleCollisionFrames Counter 40 - dot3StatsSQETestErrors Counter 41 - dot3StatsDeferredTransmissions Counter 42 - dot3StatsLateCollisions Counter 43 - dot3StatsExcessiveCollisions Counter 44 - dot3StatsCarrierSenseErrors Counter 45 - aOctetsTransmittedOK Counter 46 - aOctetsReceivedOK Counter 47 - aFramesWithExcessiveDefferal
4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25
4-8
Registers
Table 4.2
Register Numbers 222-223 224-225 226-227 228-229 230-231 232-233 234-255
Register Address (Cont.)
Register Address (REGAD[7:0] Pins) 0b11011110- 0b11011111 0b11100000- 0b11100001 0b11100010- 0b11100011 0b11100100- 0b11100101 0b11100110- 0b11100111 0b11101000- 0b11101001 0b11101010- 0b11111111 Paragraph Number 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25 4.3.25
Register Name Counter 48 - aInRangeLengthErrors Counter 49 - aOutOfRangeLengthField Counter 50 - aSymbolErrorDuringCarrier Counter 51 - aUnsupportedOpcodesReceived Counter 52 - aPauseMACCtrlFramesTransmitted Counter 53 - aPauseMACCtrlFramesReceived Reserved
4.3 Register Definitions
The following paragraphs describe the 8101/8104 internal registers.
4.3.1 Register 0-MAC Address 1
15 A[47:32] 0
Note: A[47:32]
A[47] 15-bit occurs on the REGD15 pin. MAC Address, First Word [15:0], R/W This is the fist of three words in the 48-bit MAC address. The MAC address is used to receive unicast address filtering of the DA, and serves as the SA for automatically generated MAC control pause frames.
Register Definitions
4-9
A0 (see Register 2) corresponds to the first bit transmitted or received by the MAC section (DA[0] or SA[0] in Figure 2.3).
4.3.2 Register 1-MAC Address 2
15 A[31:16] 0
Note: A[31:16]
A[31] 15-bit occurs on the REGD15 pin. MAC Address, Second Word [15:0], R/W This is the second of three words in the 48-bit MAC address. The MAC address is used to receive unicast address filtering of the DA, and serves as the SA for automatically generated MAC control pause frames. A0 (see Register 2) corresponds to the first bit transmitted or received by the MAC section (DA[0] or SA[0] in Figure 2.3.
4.3.3 Register 2-MAC Address 3
15 A[15:0] 0
Note: A[15:0]
A[15] 15-bit occurs on the REGD15 pin. MAC Address, Third Word [15:0], R/W This is the third of three words that comprise the 48-bit MAC address. The MAC address is used to receive unicast address filtering of the DA, and serves as the SA for automatically generated MAC control pause frames. A0 corresponds to the first bit transmitted or received by the MAC section (DA[0] or SA[0] in Figure 2.3).
4-10
Registers
4.3.4 Register 3-MAC Address Filter 1
15 F7[7:0] 7 F6[7:0] 0 8
Note:
F7[7] 15-bit occurs on the REGD15 pin.
F7[7:0], F6[7:0] MAC Address Filter [15:0], R/W This is the first of four words in the 64-bit MAC address filter. The MAC address filter is used to filter the destination address on multicast packets.
4.3.5 Register 4-MAC Address Filter 2
15 F5[7:0] 7 F4[7:0] 0 8
Note:
F5[7] 15-bit occurs on the REGD15 pin.
F5[7:0], F4[7:0] MAC Address Filter [15:0], R/W This is the second of four words in the 64-bit MAC address filter. The MAC address filter is used to filter the destination address on multicast packets.
Register Definitions
4-11
4.3.6 Register 5-MAC Address Filter 3
15 F3[7:0] 7 F2[7:0] 0 8
Note:
F3[7] 15-bit occurs on the REGD15 pin
F3[7:0], F2[7:0] MAC Address Filter [15:0], R/W This is the third of four words in the 64-bit MAC address filter. The MAC address filter is used to filter the destination address on multicast packets.
4.3.7 Register 6-MAC Address Filter 4
15 F1[7:0] 7 F0[7:0] 0 8
Note:
F1[7] 15-bit occurs on the REGD15 pin
F1[7:0], F0[7:0] MAC Address Filter [15:0], R/W This is the fourth of four words in the 64-bit MAC address filter. The MAC address filter is used to filter the destination address on multicast packets.
4-12
Registers
4.3.8 Register 7-Configuration 1
15 RST 7 IPG[0] 14 RXRST 6 TXPRMBL 13 TXRST 5 TXCRC 12 ANRST 4 RXPRMBL 11 CTRRST 3 RXCRC 10 APAD 2 STSWRD1 1 STSWRD0 9 IPG[2:1] 0 PEOF 8
Note: RST
RST 15-bit occurs on the REGD15 pin Reset
RST 1 0 Description Controller is reset; it self-clears in 1 s Nominal operation
15, R/WSC
RXRST
Receive Reset
RXRST 1 0 Description
14, R/WSC
Receive data path reset, self-clears when the start of the new packet is detected Normal
TXRST
Transmit Reset
TXRST 1 0 Description
13, R/WSC
Transmit data, data reset, self-clearing in 1 s Normal
ANRST
AutoNegotiation Restart
ANRST 1 0 Description
12, R/WSC
AutoNegotiation algorithm restarted, self-clearing after AutoNegotiation process starts No Reset
CTRRST
Counter Reset
CTRRST 1 0 Description
11, R/WSC
All counters reset to 0, self-clearing in 1 s No reset
Register Definitions
4-13
APAD
AutoPad Enable
APAD 1 0 Description
10, R/W
All undersize transmit packets padded to 64 bytes No autopad
IPG[2:0]
Transmit Interpacket Gap Select
IPG[2:0] 111 110 101 100 011 010 001 000 Description
[9:7], R/W
Tranmsit IPG is 96 bits (IEEE specification minimum) Transmit IPG is 122 bits Transmit IPG is 80 bits Transmit IPG is 64 bits Transmit IPG is 192 bits-(2 x IEEE specification minimum) Transmit IPG is 384 bits-(4 x IEEE specification minimum) Transmit IPG is 768 bits-(8 x IEEE specification minimum) Transmit IPG is 32 bits
TXPRMBL
Transmit Preamble Enable
TXPRMBL 1 0 Description
6, R/W
Preamble added to beginning of transmit packet Preamble not added
TXCRC
Transmit CRC Enable
TXCRC 1 0 Description
5, R/W
CRC calculated and added to end of transmit packet CRC not added
RXPRMBL
Receive Preamble Enable
RXPRMBL 1 0 Description
4, R/W
Preamble is stored in RX FIFO with rest of packet Preamble stripped off
4-14
Registers
RXCRC
Receive CRC Enable
RXCRC 1 0 Description
3, R/W
CRC is stored in RX FIFO with rest of packet CRC stripped off
STSWRD[1:0] Receive Status Word Append Select
STSWRD[1:0] 11 10 01 00 Description Reserved
[2:1], R/W
Receive status word for nondiscarded packets and discarded packets Receive status word for nondiscarded packets No receive status word
PEOF
Receive EOF Position Select
PEOF 1 0 Description Receive EOF at end of packet data
0, R/W
Receive EOF at end of receive status word
4.3.9 Register 8-Configuration 2
15 REJUCST 7 DIS_OSIZE 14 REJMCST 6 DIS_CWRD 13 REJBCST 5 DIS_RXAB 12 REJALL 4 RES = 0 11 ACPTALL 10 DIS_OVF 9 DIS_CRC 8 DIS_USIZE 0
Note: REJUCST
REJUCST 15-bit occurs on the REGD15 pin Receive Unicast Packets Reject
REJUCST Description 1 0 Receiver rejects all unicast packets Accept unicast packet if DA value in registers [0:2]
15, R/W
Register Definitions
4-15
REJMCST
Receive Multicast Packets Reject
REJMCST 1 0 Description Receiver rejects all multicast packets
14, R/W
Accept multicast packet if DA passes MAC address filter
REJBCST
Receive Broadcast Packets Reject
REJBCST 1 0 Description Receiver rejects all broadcast packets Accept broadcast packet
13, R/W
REJALL
Receive All Packet Reject
REJALL 1 0 Description Receiver rejects all packets Normal
12, R/W
ACPTALL
Receive All Packets Enable
ACPTALL 1 0 Description
11, R/W
Receiver accepts all packets regardless of address (not including MAC control frames) Normal
DIS_OVF
Discard Overflow Packet Enable
DIS_OVF 1 0 Description
10, R/W
Discard receive packet with receive FIFO overflow error No discard
DIS_CRC
Discard CRC Error Packet Enable
DIS_CRC 1 0 Description Discard receive packet with CRC error No discard
9, R/W
4-16
Registers
DIS_USIZE
Discard Undersize Packet Enable
DIS_USIZE 1 0 Description Discard receive undersize packet No discard
8, R/W
DIS_OSIZE
Discard Oversize Packet Enable
DIS_OSIZE 1 0 Description Discard receive oversize packet No discard
7, R/W
Note:
Clearing this bit to 0 allows maximum packet size to be unlimited in length. Discard Codeword Error Packet Enable
DIS_CWRD 1 0 Description Discard receive packets that contain PCS codeword error No discard
DIS_CWRD
6, R/W
DIS_RXAB
Discard RXABORT Packet Enable
DIS_RXAB 1 0 Description
5, R/W
Discard receive packets that are aborted with RXABORT No discard (i.e. RXABORT pin is disabled)
RES
Reserved [4:0], R/W Must be left at default value or written to 0 for proper operation.
4.3.10 Register 9-Configuration 3
15 RES 7 CDET 6 AN_EN 14 13 AUTOCLR 5 RMXPKT1 12 AUTORXAB 4 RMXPKT2 11 CTR_RD 3 RXAB_DEF 10 CTR_ROLL 2 9 EWRAP 1 8 LCKREF 0 SD_EN
SINTF_DIS FCNTRL_DIS
Note:
RES 15-bit occurs on the REGD15 pin
Register Definitions
4-17
RES
Reserved [15:14], R/W Must be left at default value or written to 0 for proper operation. AutoClear Mode Enable
AUTOCLR 1 0 Description TXDC and RXDC automatically cleared at next EOF TXDC and RXDC cleared by CLR_TXDC and CLR_RXDC pins, respectively
AUTOCLR
13, R/W
AUTORXAB
AutoAbort Enable
AUTORXAB 1 0 Description
12, R/W
Current packet aborted and RXDC automatically cleared at next EOF No Abort
CTR_RD
Counter Reset On Read Enable
CTR_RD 1 0 Description Counters reset to 0 when read
11, R/W
Counters not reset when read (only if count < maximum count)
CTR_ROLL
Counter Rollover Enable
CTR_ROLL 1 0 Description
10, R/W
Counters rollover to 0 after maximum count Counters stop at maximum count
EWRAP
EWRAP Pin Assert
EWRAP 1 0 Description EWRAP pin is asserted active HIGH Deassert
9, R/W
LCKREF
LCKREFn Pin Assert
LCKREF 1 0 Description LCKREFn pin is asserted Deassert
8, R/W
4-18
Registers
CDET
EN_CEDT Pin Assert
CDET 1 0 Description EN_CDET pin is asserted active HIGH
7, R/W
EN_CDET pin is controlled by receive PCS state machine
AN_EN
AutoNegotiation Enable
AN_EN 1 0 Description AutoNegotiation algorithm enabled Disabled
6, R/W
RMXPKT[1:0] Receive MAC Maximum Packet Size Select
RMXPKT[1:0] 11 10 01 00 Description Reserved 1535 Bytes 1522 Bytes 1518 Bytes
[5:4], R/W
Note: RXAB_DEF
Max packet size is unlimited if bit 7 = 0 RXABORT Pin Definition
RXAB_DEF 1 0 Description RXABORT pin and autoabort feature discards data RXABORT pin and autoabort feature discards data and status word
3, R/W
SINTF_DIS
System Interface Disable
SINTF_DIS 1 0 Description System interface disabled (see system interface section) Normal
2, R/W
Register Definitions
4-19
FCNTRL_DIS FCNTRL Pin
FCNTRL_DIS Description 1 0
1, R/W
FCNTRL pin disabled (does not cause autogenerated pause frame transmission). Enabled
SD_EN
Signal Detect Pin Enable
SD_EN 1 0 Description Enabled
0, R/W
SD pin disabled, i.e., internal SD always asserted, does not affect receive word synchronization
4.3.11 Register 10-Configuration 4
15 14 13 RES 12 LPBK 11 10 9 RES 8 7 6 5 RES 0
ENDIAN BUSSIZE
LNKDN TBC_DIS
CMXPKT1 CMXPKT0
Note: ENDIAN
ENDIAN 15-bit occurs on the REGD15 pin Endian Select
ENDIAN 1 0 Description RXD/TXD data in big endian format RXD/TXD data in little endian format
15, R/W
BUSSIZE
Bus Size Word Width
BUSSIZE 1 0 Description
14, R/W
Receive system bus word width is 16 bits Receive system bus word width is 32 bits
RES
Reserved 13, [9:8], [5:0], R/W Must be left at default value or written to 0 for proper device operation. Loopback Enable
LPBK 1 0 Description Loopback mode enabled Normal
LPBK
12, R/W
4-20
Registers
LNKDN
Link Down FIFO Flush Enable
LNKDN 1 0 Description
11, R/W
When receive link is down, data exiting the TX FIFO is discarded Normal
TBC_DIS
TX Disable
TBC_DIS 1 0 Description
10, R/W
TBC, TX [9:0] outputs disabled (high impedance) Enabled
RES
Reserved [9:8], [5:0] R/W Must be left at default value or written to 0 for proper device operation. [7:6], R/W
CMXPKT[1:0] Counter Max Packet Size Select
CMXPKT[1:0] 11 10 01 00 Description Unlimited 1535 bytes 1522 bytes 1518 bytes
4.3.12 Register 11-Status 1
15 RSYNC 14 13 12 SD 11 LINK 10 RES 8 7 6 5 4 3 2 RES 0
RES
AN_NP AN_TX_NP AN_RX_NP AN_RX_BP AN_RMTRST
Note: RSYNC
RSYNC 15-bit occurs on the REGD15 pin Receive Word Synchronization Detect
RSYNC 1 0 Description Receive 8B10B PCS has acquired word synchronization Not synchronized
15, R/LTI
RES
Reserved [14:13], [10:8], [2:0] Must be left at default value or written to 0 for proper device operation.
Register Definitions
4-21
SD
Signal Detect Pin Status
SD 1 0 Description SD input pin HIGH SD input pin LOW
12, R
LINK
Link Detect Status
LINK 1 0 Description
11, R/LTI
Link pass (receiver in sync, AutoNegotiation done) Link fail
AN_NP
AutoNegotiation Next Page Status
AN_NP 1 0 Description
7, R/LHI
One next page exchange done (both RX and TX) Not done
AN_TX_NP
AutoNegotiation TX Next Page Status
AN_TX_NP 1 0 Description Transmission of next page done Not done
6, R
AN_RX_NP
AutoNegotiation RX Next Page Status
AN_RX_NP 1 0 Description
5, R
Reception of next page done, next page valid Not done
AN_RX_BP
AutoNegotiation RX Base Page Status
AN_RX_BP 1 0 Description
4, R
Reception of base page done, base page valid Not done
AN_RMTRST AutoNegotiation Remote Restart Status
AN_RMTRST 1 0 Description
3, R/LHI
AutoNegotiation restarted because remote end sent restart codes or invalid characters Normal
4-22
Registers
4.3.13 Register 14-Status Mask 1
15 14 12 11 10 8 7 MASK_AN_NP 6 4 3 2 0
MASK_RSYNC RES = 1 MASK_LINK RES = 1
RES = 1 MASK_AN_RMTRST RES = 1
Note:
MASK_RSYNC 15-bit occurs on the REGD15 pin
MASK_RSYNC Interrupt Mask - Receive Word Synchronization Detect 15, R/W
MASK_RSYNC 1 0 Description Mask interrupt for RSYNC in Register 11 No mask
RES
Reserved [14:12], [10:8], [6:4], [2:0], R/W Must be left at default value or written to 1 for proper device operation. Interrupt Mask - Link Status Detect
MASK_LINK 1 0 Description Mask interrupt for LINK in Register 11 No mask
MASK_LINK
11, R/W
MASK_AN_NP Interrupt Mask - AutoNegotiation Next Page Status
MASK_AN_NP 1 0 Description Mask interrupt for AN_NP in Register 11 No mask
7, R/W
MASK_AN_RMTRST Interrupt Mask - AutoNegotiation Remote Restart Status 3, R/W
MASK_AN_RMTRST 1 0 Description Mask interrupt for AN_RMTRST in Register 11 No mask
Register Definitions
4-23
4.3.14 Register 17-Transmit FIFO Threshold
15 TWM1[4:0] 11 10 TWM2[4:0] 6 5 TASND[5:0] 0
Note: TWM1[4:0]
TWM1[4] 15-bit occurs on the REGD15 pin Transmit FIFO Watermark 1 Threshold
TWM1[4:0] Range Increment 11111 11110 11101 00001 00000 Description 0-1024 words (0-4096 bytes) 32 words (128 bytes) Reserved, do not use 992 words in FIFO (3968 bytes) 960 words in FIFO (3840 bytes 64 words in FIFO (256 bytes) 32 words in FIFO (128 bytes)
[15:11], R/W
.. .
TWM2[4:0]
Transmit FIFO Watermark 2 Threshold
TWM2[4:0] Range Increment 11111 11110 11101 00001 00000 Description 0-1024 words (0-4096 bytes) 32 words (128 bytes) Reserved, do not use 992 words in FIFO (3968 bytes) 960 words in FIFO (3840 bytes) 64 words in FIFO (256 bytes) 32 words in FIFO (128 bytes)
[10:6], R/W
.. .
4-24
Registers
TASND[5:0]
Transmit FIFO AutoSend Threshold
TASND[5:0] Range Increment 111111 111110 000010 000001 000000 Description 0-1024 words (0-4096 bytes) 8 words (32 bytes) Reserved do not use
[5:0], R/W
Transmit starts when 504 words in FIFO Transmit starts when 24 words in FIFO Transmit starts when 16 words in FIFO Transmit starts when 992 words in FIFO
.. .
Note 1:
An EOF written into FIFO also starts transmission of that packet regardless of the AutoSend threshold setting. The 0b000000 setting in TASND[5:0] lets the FIFO fill up before transmission starts, facilitating transmission of oversize packets.
Note 2:
4.3.15 Register 18-Receive FIFO Threshold
15 RWM1[7:0] 8 7 RWM2[7:0] 0
Note: RWM1[7:0]
RWM1[15] 15-bit occurs on REGD15 pin. Receive FIFO Watermark 1 Threshold
RWM1[7:0] Range Increment 11111111 11111110 11111110 00000001 00000000 Description 0-4096 words (0-16386 bytes) 16 words (64 bytes) Reserved, do not use 4080 words in FIFO (16320 bytes) 4064 words in FIFO (16256 bytes) 32 words in FIFO (128 bytes) 16 words in FIFO (64 bytes)
[15:8], R/W
.. .
Register Definitions 4-25
RWM2[7:0]
Receive FIFO Increment = 16 Words (64 Bytes) Watermark 2 Threshold [7:0], R/W
RWM2[7:0] Range 11111111 11111110 11111110 00000001 00000000 Description 0-4096 words (0-16386 bytes) Reserved, do not use 4080 words in FIFO (16320 bytes) 4064 words in FIFO (16256 bytes) 32 words in FIFO (128 bytes) 16 words in FIFO (64 bytes)
4.3.16 Register 19-Flow Control 1
15 MCNTRL 14 13 12 MCFLTR 11 MCENDPS 10 7 6 0
.. .
MCPASS[1:0]
MCASND[3:0]
RES = 0
Note: MCNTRL
MCNTRL 15-bit occurs on REGD15 pin MAC Control Frame Enable
MCNTRL 1 0 Description Valid receive MAC control frames cause the transmitter to pause (flow control enabled) Transmitter not paused (flow control disable)
15, R/W
MCPASS[1:0] MAC Control Frame Pass Through Enable
MCPASS[1:0] Description 11 10 01 00 Valid MAC control frame that have pause opcode are passed through to receive FIFO Valid MAC control frames that have any opcode are passed through to receive FIFO Valid MAC control frames that have nonpause opcode are passed through to receive FIFO MAC control frames are not passed through to receive FIFO
[14:13], R/W
4-26
Registers
MCFLTR
MAC Control Frame Address Filter Enable
MCFLTR 1 Description
12, R/W
Use reserved multicast address or station address as the DA to determine MAC control pause frame validity Use any address as the DA to determine MAC control pause frame validity
0
MCENDPS
MAC Control Frame End Pause Enable
MCENDPS 1 0 Description
11, R/W
When FNCTRL is deasserted, send transmit MAC control frame with pause_time = 0 Normal
MCASND[3:0] MAC Control Frame AutoSend Threshold [10:7], R/W These bits determine the receive FIFO threshold, which causes the automatic transmission of pause frames. Autogenerated pause frame transmission is also affected by the FCNTRL pin and bit 1.
MCASND[3:0] 1111 0010 0001 0000 Description 15360 bytes 2048 bytes 1024 bytes Disabled, i.e. RX FIFO data does not cause autogenerated pause frame transmission.
.. .
RES
Reserved [6:0], R/W Must be left at defaults or written to 0 for proper operation.
4.3.17 Register 20-Flow Control 2
15 P[15:0] 0
Note:
P15 15-bit occurs on REGD15 pin
Register Definitions
4-27
P[15:0]
Pause Time [15:0], R/W The contents of this register are inserted into the pause_time parameter field of all autogenerated transmit MAC control pause frames. Upon successful reception of these autogenerated pause frames, a remote device does not transmit data for a time interval equal to the decimal value of this register times 512 ns. P0 is the LSB. Any pause time value less than or equal to 0x32 is sent as 0x32.
4.3.18 Register 21-AutoNegotiation Base Page Transmit
15 NP 14 ACK 13 RF[2:1] 12 11 RES 9 8 PS_DIR 7 PS 6 HDX 5 FDX 4 RES 0
Note: NP
NP 15-bit occurs on REGD15 pin Next Page Enable
NP 1 0 Description Next page exists No next page
15, R/W
ACK
Acknowledge
ACK 1 0 Description
14, R/W
Received AutoNegotiation word recognized Not recognized
Note:
Writing this bit has no effect on device operation. The transmitted bit is controlled by internal state machine. Remote Fault
RF[2:1] 11 10 01 00 Description AutoNegotiation error Offline Link failure No error, link OK
RF[2:1]
[13:12], R/W
4-28
Registers
RES PS_DIR PS
Reserved Reserved for future IEEE use Pause Capable
PS_DIR PS 11 10 01 00 Description Capable of receive pause only Capable of transmit pause only
[11:9], R/W [8:7], R/W
Capable of transmit and receive pause Not capable
HDX
Half-Duplex Capable
HDX 1 0 Description Capable of half duplex Not capable
6, R/W
FDX
Full-Duplex Capable
FDX 1 0 Description Capable of full duplex Not capable
5, R/W
RES
Reserved Reserved for future IEEE use.
[4:0], R/W
4.3.19 Register 22-AutoNegotiation Base Page Receive
15 NP 14 ACK 13 RF[2:1] 12 11 RES 9 8 PS_DIR 7 PS 6 HDX 5 FDX 4 RES 0
Note: NP
NP 15-bit occurs on the REGD15 pin. Next Page Enable
NP 1 0 Description Next page exists No next page
15, R
Register Definitions
4-29
ACK
Acknowledge
ACK 1 0 Description
14, R
Received AutoNegotiation word recognized Not recognized
RF[2:1]
Remote Fault
RF[2:1] 11 10 01 00 Description AutoNegotiation error Offline Link failure No error, link OK
[13:12], R
RES PS_DIR, PS
Reserved Reserved for future IEEE use. Pause Capable
PS_DIR, PS 11 10 01 00 Description
[11:9], [4:0], R [8:7], R
Capable of receive pause only Capable of transmit pause only Capable of transmit and receive pause only Not capable
HDX
Half-Duplex Capable
HDX 1 0 Description Capable of half-duplex Not capable
6, R
FDX
Full-Duplex Capable
FDX 1 0 Description Capable of full-duplex Not capable
5, R
4-30
Registers
4.3.20 Register 23-AutoNegotiation Next Page Transmit
15 NP 14 ACK 13 PAGETYPE 12 ACK2 11 TOGGLE 10 MSG[10:0] 0
Note: NP
NP 15-bit occurs on REGD15 pin Next Page Enable
NP 1 0 Description Additional next page exists This is the last next page
15, R/W
ACK
Acknowledge
ACK 1 0 Description
14, R/W
Received AutoNegotiation word recognized Not recognized
Note:
Writing this bit has no effect on device operation. The transmitted bit is controlled by internal state machine. Page Type
PAGE 1 0 Description Message page Unformatted page
PAGE
13, R/W
ACK2
Acknowledge 2
ACK2 1 0 Description
12, R/W
Able to comply with the received message Not able to comply
Register Definitions
4-31
TOGGLE
Toggle Bit
TOGGLE 1 0 Description
11, R/W
Value of the toggle bit in previously transmitted AutoNegotiation word was 0 Value of the toggle bit in previously transmitted AutoNegotiation word was 1
Note:
Writing this bit has no effect on device operation. The transmitted bit is controlled by internal state machine. Message [10:0], R/W These bits carry the 11-bit message associated with this next page. Refer to IEEE 802.3z specifications for details on the format and definition of these bits.
MSG[10:0]
4.3.21 Register 24-AutoNegotiation Next Page Receive
15 NP 14 ACK 13 PAGETYPE 12 ACK2 11 TOGGLE 10 MSG[10:0] 0
Note: NP
NP 15-bit occurs on the REGD15 pin Next Page Enable
NP 1 0 Description Additional next page exists This is last next page
15, R
ACK
Acknowledge
ACK 1 0 Description
14, R
Received AutoNegotiation word recognized Not recognized
PAGETYPE
Page Type
PAGETYPE 1 0 Description Message page Unformatted page
13, R
4-32
Registers
ACK2
Acknowledge 2
ACK2 1 0 Description
12, R
Able to comply with the received message Not able to comply
TOGGLE
Toggle Bit
TOGGLE 1 0 Description
11, R
Value of the toggle bit in previous transmitted AutoNegotiation word was 0 Value of the toggle bit in previous transmitted AutoNegotiation word was 1
MSG[10:0]
Message [10:0], R These bits carry the 11-bit message associated with this next page. Refer to the IEEE 802.3z specifications for details on the format and definition of these bits.
4.3.22 Register 32-Device ID
15 PART[3:0] 12 11 HREV[3:0] 8 7 RES 4 3 SREV[3:0] 0
Note: PART[3:0]
PART[3] 15-bit occurs on the REGD15 pin. Part Number [15:12], R This field contains a 4-bit number that uniquely identifies the device. Hardware Revision Number [11:8], R This field contains a 4-bit number that identifies that a revision was made to the device and the revision did not affect any register bit definitions. Reserved Reserved for future use. [7:4], R/W
HREV[3:0]
RES SREV[3:0]
Software Revision Number [3:0], R/W This field contains a 4-bit number that identifies that a revision was made to the device and the revision did affect register bit definitions.
Register Definitions
4-33
4.3.23 Register 112-115-Counter Half Full 1-4
15 HFULL[15:0] 0
Note:
HFULL[15] 15-bit occurs on the REGD15 pin.
HFULL[15:0] Counter Half Full Detect [15:0], R/LHI These bits indicate when a counter is near overflow is half full. These four registers contain 53 counter half-full detect bits, one bit for each of the 53 counters. Bit 0 in Counter Half Full Register 0 corresponds to Counter 1 as listed in Table 4.1; bit 15 in Counter Half Full Register 0 corresponds to Counter 16; bit 4 of Counter Half Full Register 4 corresponds to Counter 53.
HFULL[15:0] 1 0 Description Counter has reached a count of 0x80000000, (half full). Count < 0x80000000
4.3.24 Registers 120-123-Counter Half Full Mask 1-4
15 MASK_HFULL[15:0] 0
Note:
MASK_HFULL[15] 15-bit occurs on the REGD15 pin
MASK_HFULL[15:0] Counter Half Full Detect Mask [15:0], R/W The MASK_HFULL[15:0] bits mask (disable) the interrupt caused by the counter half-full detect bits. These four registers contain 53 mask bits, one bit for each of the 53 half-full detect bits. Bit 0 in Counter Half Full Mask Register 0 masks the interrupt caused by the half full detect bit for Counter 1; bit 15 in Counter Half Full Mask Register 0 corresponds to Counter 16; bit 4 in Counter Half Full Mask Register 3 corresponds to Counter 53.
4-34
Registers
MASK_HFULL[15:0] Description 1 Mask (disable) the interrupt caused by the corresponding Counter Half Full Detect Bit. No mask
0
4.3.25 Registers 128-233-Counter 1-53
15 C[15:0] 0
Note: C[15:0]
C15 15-bit occurs on the REGD15 pin. Counter Result Value [15:0], R These 106 registers contain the results of the 53 32-bit management counters. Each 32-bit counter result value resides in two 16-bit registers. For the two registers associated with each counter, the register with the lower value address always contains the least-significant 16 bits of the counter result. C0 of the lower value address is the counter LSB; C15 of the higher value is the counter MSB. The definition and register address for each counter is shown in Table 2.14. The register address for each counter is also shown in Table 4.2.
Register Definitions
4-35
4-36
Registers
Chapter 5 Application Information
This Chapter provides application information for the 8101/8104 Gigabit Ethernet Controller. The chapter contains the following sections
* * * * * * * * *
Section 5.1, "Typical Ethernet Port" Section 5.2, "10-Bit PHY Interface" Section 5.3, "System Interface" Section 5.4, "Reset" Section 5.5, "Loopback" Section 5.6, "AutoNegotiation" Section 5.7, "Management Counters" Section 5.8, "TX Packet and Octet Counters" Section 5.9, "Power Supply Decoupling"
8101/8104 Gigabit Ethernet Controller
5-1
5.1 Typical Ethernet Port
A typical example of a Gigabit Ethernet switch port using the 8101/8104 controller is shown in Figure 5.1. Figure 5.1 Gigabit Ethernet Switch Port Using the 8101/8104
MAC PHY
TX DATA
32 8101/8104 Gigabit MAC + PCS IEEE 802.3 10-Bit Interface Serializer/ Deserializer IC ANSI PECL Interface Fiber Optic Transceiver Optical Fiber
RX DATA MGMT
32 16
5.2 10-Bit PHY Interface
The 10-bit PHY interface directly couples to any external physical layer device that complies with the IEEE 802.3z or the 10-bit ANSI X3.230 interface standards.
5.2.1 External Physical Layer Devices
In a typical configuration, the controller is connected to an external Serializer/Deserializer (SerDes) Integrated circuit, as shown in Figure 5.1. A list of SerDes devices whose specifications are compatible with and can directly connect to the controller is shown in Table 5.1.
5-2
Application Information
Table 5.1
Vendor Vitesse
Compatible SerDes Devices
Device No. VSC7135 HDMP-1636 HDMP-1646 CXB1589Q 52052 TQ9506
Hewlett-Packard Sony AMCC TriQuint
5.2.2 Printed Circuit Board Layout
The 10-bit PHY interface clocks data at 125 MHz. The setup and hold times on the timing signals are very short. The outputs are specified assuming a maximum load of only 10 pf. For these reasons, it is imperative that the SerDes or other physical layer device be placed as close as possible to the controller, preferably within one inch. In addition, care should be taken to eliminate any extra loading on all the 10-bit PHY interface signal lines. Also, the clock and data lines in both receive and transmit directions should be routed along the same paths so that they have similar parasitics and delays, to prevent degrading setup and hold times. Termination is not necessary if these precautions are taken.
5.3 System Interface
The system interface requires the selection of watermarks and close attention to printed circuit board layout.
5.3.1 Watermarks
There are two independent watermarks on both the transmit and receive FIFOs. The usage of these watermarks is unspecified and is left to the discretion of the system designer. Below are three examples of watermark usage based on transferring data in any of the following ways:
* * *
Complete packets Fixed block sizes Variable block sizes
System Interface
5-3
5.3.1.1 Complete Packet Watermarks To transfer data to and from the controller in completed packets, only one watermark is needed. Either transmit watermark could be chosen for this application. On the receive side, RXWM2 should be chosen because it is asserted when a complete packet is loaded into the RX FIFO. The transmit and receive watermark thresholds should preferably be set to a value equal to or larger than the maximum size packet (1518 bytes or greater). On the transmit side, the data is written into the TX FIFO in complete packet bursts when the system requires. On the receive side the data is read out of the RX FIFO beginning with the assertion of RXWM2 and ending when RXEOF is asserted. 5.3.1.2 Fixed Block Watermarks To transfer data to and from the controller in fixed block sizes (64 bytes at a time, for example), only one watermark is needed. Either transmit watermark could be chosen for this application. On the receive side, RXWM2 should be chosen because it is asserted when a complete packet is loaded into the RX FIFO. The transmit watermark threshold is set to a low value (64 bytes for example), and the receive watermark thresholds preferably are set to a value equal to or greater than the fixed cell size (64 bytes in this example). On the transmit side, the data is written into the TX FIFO in fixed block size bursts when the system requires. When the transmit watermark is deasserted, another block must be written into the TX FIFO. On the receive side, the data is read out of the RX FIFO beginning with the assertion of RXWM2 and ending when the fixed block has been read out (64 bytes in this example) or RXEOF has been asserted. 5.3.1.3 Variable Block Watermarks To transfer data to and from the controller in variable cell sizes, two watermarks are needed. The TXWM1n and RXWM1 watermark thresholds are set to some low value (64 bytes for this example) while the TXWM2n and RXWM2 watermark thresholds are set to some high value (1024 bytes for example). On the transmit side, the data is written into the TX FIFO when the system requires. If TXWM2n is asserted, the data input must be halted. If TXWM1n is deasserted, the data input must be resumed. In this way, the TX FIFO contents are kept between the high and low watermark thresholds, which potentially increses the external
5-4
Application Information
system loading efficiency. Similarly, on the receive side the data must be read out of the RX FIFO when RXWM2 is asserted. If RXWM1 is deasserted, or RXEOF is asserted, the data output must be halted. If RXWM2 is asserted the data output must be resumed. In this way, the RX FIFO contents are kept between the high and low watermarks. The transmit and receive watermarks can also be used to indicate that the FIFO is full or empty (or almost full or almost empty), if desired.
5.3.2 PCB Layout
Because the data rate of the system interface can be as high as 66 MHz, care should be taken to keep PCB trace lengths of all critical signals as short as possible, preferably less than 2 inches in length. If this guideline is followed termination is not necessary.
5.4 Reset
While the device is being reset, it transmits valid 10B symbols out of the 10-bit PHY interface on TXD[0:9] and TBC. If the device is reset with the RESETn pin for a long period of time, these 10B symbols may be mistakenly decoded as valid packet information and fill up the memory in a remote device. The reset procedure outlined in Table 5.2 avoids this situation and is recommended for use when the RESETn pin is asserted for long periods of time. When the reset bit is used for device reset the above situation is avoided because the reset bit is self-clearing in 1 s.
Reset
5-5
Table 5.2
Step 1 2
Reset Procedure
Result Stop transmission of data from the 10-bit PHY interface to SerDes. Insures that the remote device receiver detects that the link has been broken so it will not decode 10B data as valid. Start the reset period. Allow enough time for all circuits in controller to be reset. Stop the reset period. Turns on 10-bit PHY interface and returns controller to normal operation.
Action Set the TBC_DIC bit Wait for more than 20 s
3 4 5 6
Assert RESETn Wait more than 10 s. Deassert RESETn Clear the TBC_DIC bit
5.5 Loopback
The controller has a loopback mode, but most external SerDes devices connected to the controller 10-bit PHY interface also have a loopback mode. Sometimes it is desirable to use the SerDes loopback mode instead of the controller loopback mode because the SerDes loopback mode tests a larger and/or different section of the system circuitry. When the SerDes loopback mode is used, it is recommended that the procedure outlined in Table 5.3 be followed.
5-6
Application Information
Table 5.3
STEP 1 2 3
SerDes Loopback Procedure
Result Ignore all receive data until the loopback mode is ready for operation. Enable the external SerDes loopback mode. Ignore the signal detect output from optical transceiver because the receive optical data may be invalid. Stop transmission of data out of 10-bit PHY interface which causes the SerDes and controller to lose sync so that they properly resync to the new data stream. Allow time for the SerDes and controller receivers to lose sync. Turn on the transmitter so that the SerDes and controller receivers can gain sync. Allow time for the SerDes and controller receivers to gain sync. Stop ignoring receive data and turn on the receive MAC.
Action Set the REJALL bit in Register 8 Set the EWRAP bit in Register 9 Clear the SD_EN bit in Register 9 Set the TBC_DIS bit in Register 10
4
5 6 7 8 9 10
Wait more than 200 s Clear the TBC_DIS bit in Register 10 Wait more than 200 s Clear the REJALL bit in Register 8 Do loopback tests Clear the EWRAP bit, and set the SD_EN bit in Register 9 (if SD pin is used) Set the ANRST bit in Register 7
Turn off the SerDes loopback mode and enable the signal detect function (if used).
11
Restarts AutoNegotiation. Controller is ready for normal operation when AutoNegotation is completed.
5.6 AutoNegotiation
AutoNegotiation is a handshake operation between the controller and the external device (see Section 2.15, "AutoNegotiation"). If the external device is capable of AutoNegotiation, the procedures described in Section 5.6.1, "AutoNegotiation at Power Up" should be followed. If the external device is not capable of AutoNegotiation, refer to Section 5.6.2, "Negotiating with a Non-AutoNegotiation Capable Device".
AutoNegotiation
5-7
5.6.1 AutoNegotiation at Power Up
When the device is powered up the AutoNegotiation algorithm must handshake with the remote device to configure itself for a common mode of operation. To insure smooth and proper AutoNegotiation operation at power up it is recommended that the procedure outlined in Table 5.4 be followed. Table 5.4
STEP 1
AutoNegotiation Power Up Procedure
Result Waits for valid data from the optical transceiver. Resets the device. Sets up the capabilities for AutoNegotiation. Sets up the device for the desired operation. Restarts AutoNegotiation. Wait for AutoNegotiation to complete. Determine if AutoNegotiation done and link pass. If link pass, device ready for operation. If link fail, retry again seven more times. If no link pass after seven times, disable ANEG and try manual link pass. Disable AutoNegotiation. Clears all internal AutoNegotiation circuitry. Wait for manual link pass. If manual link pass, then device ready for operation. If link fail, then redo procedure until link pass is achieved.
Action Wait for the SD pin to go HIGH (If SD is not used, go to the next step.) Set RST bit in Register 7 Set bits [15:0] in Register 21 Set the remaining register bits as needed. Set ANRST bit in Register 7 Wait > 50 s Read LINK bit in register 11 twice. If 0, then done. If 1, repeat #5-7 (up to seven times).
2 3 4 5 6 7
8 9 10 11
Clear AN_EN bit in Register 9 Clear ANRST bit in Register 7 Wait > 100 s Read LINK bit in Register 11 twice. If 0, go to first step. If 1, done.
5-8
Application Information
5.6.2 Negotiating with a Non-AutoNegotiation Capable Device
When the controller has AutoNegotiation enabled and the remote device to which it is connected has the AutoNegotiation disabled (or does not have AutoNegotiation capability at all), the controller stays in the link fail state and continually restarts AutoNegotiation because it cannot complete a negotiation sequence successfully. Conversely, the remote device goes to the link pass state because it sees the AutoNegotiation words transmitted to it as valid idle symbols. For proper operation between two devices, the controller and the remote device must both be either set with AutoNegotiation enabled or set with AutoNegotiation disabled.
5.7 Management Counters
The controller management counters provide the necessary statistics to completely support the following IETF and IEEE specifications:
* * * *
IETF RFC 1757: IETF RFC 1213 and 1573 IETF RFC 1643: IEEE 802.3/Cl. 30:
RMON Statistics Group SNMP Interfaces Group Ethernet-Like MIB Ethernet MIB
A complete list of the counters along with their definitions was already defined in Table 2.14. A map of the actual MIB objects from the IETF and IEEE specifications to the specific controller counters is shown below in Table 5.5-Table 5.8.
Management Counters
5-9
Table 5.5
MIB Objects vs. Counter Location For RMON Statistics Group MIB (RFC 1757)
Counter Location Register Address (Low/High) 0b10000000 0b10000001 0b10000010 0b10000011 0b10000100 0b10000101 0b10000110 0b10000111 0b10001000 0b10001001 0b10001010 0b10001011 0b10001100 0b10001101 0b10001110 0b10001111 0b10010000 0b10010001 0b10010010 0b10010011 0b10010100 0b10010101 0b10010110 0b10010111 0b10011000 0b10011001 0b10011010 0b10011011
MIB Objects etherStatsDropEvents etherStatsOctets etherStatsPkts etherStatsBroadcastPkts etherStatsMulticastPkts etherStatsCRCAlignErrors etherStatsUndersizePkts etherStatsOversizePkts etherStatsFragments etherStatsJabber etherStatsCollisions etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets
Counter 1 2 3 4 5 6 7 8 9 10 11 12 13 14
5-10
Application Information
Table 5.5
MIB Objects vs. Counter Location For RMON Statistics Group MIB (RFC 1757) (Cont.)
Counter Location Register Address (Low/High) 0b10011100 0b10011101 0b10011110 0b10011111 0b10100000 0b10100001
MIB Objects etherStatsPkts256to511Octets etherStatsPkts512to1023Octets etherStatsPkts1024to1518Octets
Counter 15 16 17
Table 5.6
MIB Objects vs. Counter Location For SNMP Interface Group MIB (RFC 1213 and 1573)
Counter Location Counter # 28 29 5 4 5 and 4 Register Address (Low/High) 0b10110110 0b10110111 0b10111000 0b10111001 0b10001000 0b10001001 0b10000110 0b10000111 0b10001000 0b10001001 and 0b10000110 0b10000111 0b10000000 0b10000001
MIB Objects ifInOctets ifInUcastPkts ifInMulticastPkts ifInBroadcastPkts ifInNUcastPkts
ifInDiscards
1
Management Counters
5-11
Table 5.6
MIB Objects vs. Counter Location For SNMP Interface Group MIB (RFC 1213 and 1573) (Cont.)
Counter Location Counter # 6 and 7 and 8 Register Address (Low/High) 0b10001010 0b10001011 and 0b10001100 0b10001101 and 0b10001110 0b10001111 0b10111010 0b10111011 0b10111100 0b10111101 0b10111110 0b10111111 0b11000000 0b11000001 0b10111110 0b10111111 and 0b11000000 0b11000001 0b11000010 0b11000011 0b11000100 0b11000101
MIB Objects ifInErrors
ifOutOctets ifOutUcastPkts ifOutMulticastPkts ifOutBroadcastPkts ifOutNUcastPkts
30 31 32 33 32 and 33
ifOutDiscards ifOutErrors
34 35
5-12
Application Information
Table 5.7
MIB Objects vs. Counter Location For Ethernet-Like Group MIB (RFC 1643)
Counter Location Counter # 36 6 38 39 40 41 42 43 34 44 8 1 Register Address (Low/High) 0b11000110 0b11000111 0b10001010 0b10001011 0b11001010 0b11001011 0b11001100 0b11001101 0b11001110 0b11001111 0b11010000 0b11010001 0b11010010 0b11010011 0b11010100 0b11010101 0b11000010 0b11000011 0b11010110 0b11010111 0b10001110 0b10001111 0b10000000 0b10000001
MIB Objects dot3StatsAlignmentErrors dot3StatsFCSErrors dot3StatsSingleCollisionFrames dot3StatsMultipleCollisionFrames dot3StatsSQETestErrors dot3StatsDeferredTransmissions dot3StatsLateCollisions dot3StatsExcessiveCollisions dot3StatsInternalMacTransmitErrors dot3StatsCarrierSenseErrors dot3StatsFrameTooLongs dot3StatsInternalMacReceiveErrors
Management Counters
5-13
Table 5.8
MIB Objects vs. Counter Location For Ethernet MIB (IEEE 802.3z, Clause 30)
Counter Location Counter # 19 through 35 Register Address (Low/High) 0b10100100 0b10100101 through 0b11000100 0b11000101 0b11001010 0b11001011 0b11001100 0b11001101 0b10111000 0b10111001 and 0b10000110 0b10000111 and 0b10001000 0b10001001 0b10001010 0b10001011 0b11000110 0b11000111 0b11011000 0b11011001 0b11010000 0b11010001 0b11010010 0b11010011 0b11010100 0b11010101 0b11000010 0b11000011 0b11010110 0b11010111
MIB Objects aFramesTransmittedOK
aSingleCollisionFrames aMultipleCollisionFrames aFramesReceivedOK
38 39 29 and 4 and 5
aFrameCheckSequenceErrors aAlignmentErrors aOctetsTransmittedOK aFramesWithDeferredXmissions aLateCollisions aFrameAbortedDueToXSCollisions aFrameAbortedDueToIntMACXmitError aCarrierSenseErrors
6 36 45 41 42 43 34 44
5-14
Application Information
Table 5.8
MIB Objects vs. Counter Location For Ethernet MIB (IEEE 802.3z, Clause 30) (Cont.)
Counter Location Counter # 46 1 21 20 47 5 4 48 49 8 40 50 52 53 Register Address (Low/High) 0b11011010 0b11011011 0b10000000 0b10000001 0b10101000 0b10101001 0b10100110 0b10100111 0b11011100 0b11011101 0b10001000 0b10001001 0b10000110 0b10000111 0b11011110 0b11011111 0b11100000 0b11100001 0b10001110 0b10001111 0b11001110 0b11001111 0b11100010 0b11100011 0b11100110 0b11100111 0b11101000 0b11101001
MIB Objects aOctetsReceivedOK aFramesLostDueToIntMACRcvrError aMulticastFrameXmittedOK aBroadcastFramesXmittedOK aFramesWithExcessiveDefferal aMulticastFramesReceivedOK aBroadcastFramesReceivedOK aInRangeLengthErrors aOutOfRangeLengthField aFrameTooLongErrors aSQETestErrors aSymbolErrorDuringCarrier aMACControlFramesTransmitted aMACControlFramesReceived
Management Counters
5-15
Table 5.8
MIB Objects vs. Counter Location For Ethernet MIB (IEEE 802.3z, Clause 30) (Cont.)
Counter Location Counter # 51 52 53 Register Address (Low/High) 0b11100100 0b11100101 0b11100110 0b11100111 0b11101000 0b11101001
MIB Objects aUnsupportedOpcodesReceived aPauseMACCtrlFramesTransmitted aPauseMACCtrlFramesReceived
5.8 TX Packet and Octet Counters
The controller counter set includes packet and octet counters for the transmit and receive packets. The RMON specifications state that packet and octet counters should only tabulate received information. This is sometimes interpreted to mean both transmitted and received information, because Ethernet was originally a shared media protocol. As such, the tables above only point to receive packet and octet counters, but the transmit packet and octet counters are also available in counters 17 through 26 and can be summed with the receive packet and octet counts if desired.
5.9 Power Supply Decoupling
There are 23 VCCs (VCC[22:0]) and 31 GNDs (GND[30:0]) on the controller. All GNDs should also be connected to a large ground plane. If the GNDs vary in potential by even a small amount, noise and latch up can result. The GNDs should be kept to within 50 mV of each other. Some of the VCC pins on the controller go to the internal core logic, and the remaining VCCs go to the I/O buffers. The core and I/O VCCs should be isolated from each other to minimize jitter on the 10-bit PHY interface. It is recommended that all of the I/O VCCs be directly connected to a large VCC plane. It is also recommended that the core VCCs (pins 70,
5-16
Application Information
97, 135, 147, 193) be isolated from the I/O VCCs with a 2-ohm resistor between the VCC plane and the device core VCC pins, as shown in Figure 5.2. Figure 5.2 Decoupling Recommendations
3.3 V VCC Plane Ferrite Bead 2 Ferrite Bead Analog Digital VCC VCC [4] SerDes GND
VCC [1] [5] Other Devices GND [1]
I/O VCC [3]
Core VCC [1] [2]
[2]
8101/8104 Controller GND
GND Plane
Notes:: [1] It is recommended that a 0.1/0.001 F pair of capacitors for every four VCCs less than 0.5 inches from the device VCC/GND pins, evenly distributed around all four sides of the devices. [2] Same as Note [1] except every two VCCs. [3] Core VCC pins are 70, 97, 135, 147, and 193. All remaining VCC pins are I/O VCCs. [4] These are generic recommendations for SerDes. Follow any recommendations fromthe specific SerDes manufacturer. [5] This is a generic recommendation for other digital devices. Follow any recommendations from the spevific device manufacturers.
The 2 ohm resistor will reduce the amount of noise coupling from the I/O VCCs to the core VCCs. A resistor is recommended over a ferrite bead because the inductance of a ferrite bead can induce noise spikes at the device pins. Decoupling capacitors should then be placed between the device VCC pins and GND plane, as shown in Figure 5.2 and described as follows. The external SerDes device that is typically connected to the 10-bit PHY interface can also be very sensitive to noise from the VCC plane. Recommendations from the manufacturer of the SerDes device used should be followed. Generically, it has been found from practice that the SerDes should be isolated from all devices on the PCB with a ferrite bead between the VCC plane and all of the SerDes VCC pins, as shown in Figure 5.2. In addition, it has been found from practice that the analog
Power Supply Decoupling
5-17
and digital VCC pins on the SerDes device should be isolated from each other with a ferrite bead placed between the analog SerDes VCC pins and the digital SerDes VCC pins, as shown in Figure 5.2. Decoupling capacitors should then be placed between the SerDes device VCC pins and GND plane, as shown in Figure 5.2 and described as follows. For the controller and other digital devices there should be a pair of 0.1 f and 0.001 f decoupling capacitors connected between VCC and GND for every four sets of VCC/GND pins placed as close as possible to the device pins, preferably within 0.5" and evenly distributed around all four sides of the devices. For the external SerDes device, there should be a pair of 0.1/0.001 f capacitors for every two sets of VCC/GND pins. The 0.1 f and 0.001 f capacitors reduce the LOW and HIGH frequency noise, respectively, on the VCC at the device. The PCB layout and power supply decoupling discussed above should provide sufficient decoupling to achieve the following when measured at the device:
* * *
The resultant AC noise voltage measured across each VCC/GND set should be less than 100 mVpp. All VCCs should be within 50 mVpp of each other. All GNDs should be within 50 mVpp of each other.
5-18
Application Information
Chapter 6 Specifications
This Chapter describes the specifications of the 8101/8104 Gigabit Ethernet Controller and consists of the following Sections:
* * * * * *
Section 6.1, "Absolute Maximum Ratings" Section 6.2, "DC Electrical Characteristics" Section 6.3, "AC Electrical Characteristics" Section 6.4, "8101 208-pin PQFP Pinout and Pin Listing" Section 6.5, "8104 208-Pin BGA Pinout and Pin Listing" Section 6.6, "Package Mechanical Dimensions"
6.1 Absolute Maximum Ratings
Absolute maximum ratings are limits, which when exceeded may cause permanent damage to the device or affect device reliability. All voltages are specified with respect to GND, unless otherwise specified. VCC supply voltage All inputs and outputs Package power dissipation Storage temperature Temperature under bias Lead temperature (soldering, 10 sec) Body temperature (soldering, 30 sec) -0.3 V to 4.0 V -0.3 V to 5.5 V 2.2 Watt @ 70 C -65 to +150 C -10 to +85 C 260 C 220 C
8101/8104 Gigabit Ethernet Controller
6-1
6.2 DC Electrical Characteristics
Table 6.1 lists and describes the DC electrical characteristics of the 8101/8104. Unless otherwise noted, all test conditions are as follows:
* * * *
Table 6.1
TA = 0 to +70 C VCC = 3.3 V 5% SCLK = 66 MHz 0.01% TCLK = 125 MHz 0.01%
DC Electrical Characteristics
Limit
Symbol VIL VIH IIL IIH VOL
Parameter Input LOW voltage Input HIGH voltage Input LOW current Input HIGH current Output LOW voltage
Min - 2 - - GND GND
Typ - - - - - - - - - -
Max 0.8 5.5 -1 1 0.4 1 VCC VCC 5 300
Unit Volt Volt A A Volt Volt Volt Volt pF mA
Conditions
VIN = GND VIN = VCC IOL = -4 mA All except LINKn IOL = -20 mA LINKn IOL = 4 mA All except LINKn IOL = 20 mA LINKn
VOH
Output HIGH voltage
2.4 VCC - 1.0
CIN ICC
Input capacitance VCC supply current
- -
No output load
6-2
Specifications
6.3 AC Electrical Characteristics
The following tables list and describe the the AC electrical characteristics of the 8101/8104. Unless otherwise noted, all test conditions are as follows:
* * * * * *
TA = 0 to +70 C VCC = 3.3 V 5% SCLK = 66 MHz 0.01% TCLK = 125 MHz 0.01% Input conditions: All Inputs: tr, tf 4 ns, 0.8 V to 2.0 V Output loading TBC, TX[0:9]: 10 pF LINK: 50 pF All other digital outputs: 30 pF
*
Measurement points: Data active to 3-state: 200 mV change Data 3-state to active: 200 mV change All inputs and outputs: 1.5 Volts
AC Electrical Characteristics
6-3
Table 6.2
Input Clock Timing Characteristics
Limit
Symbol t1 t2 t3 t4 t5 t6 t7 t8
Parameter SCLK cycle time SCLK duty cycle TCLK period TCLK HIGH time TCLK LOW time TCLK to TBC delay REGCLK cycle time REGCLK duty cycle
Min 1/33 40 7.9992 3.6 3.6 0 1/5 40
Typ
Max 1/66 60
Unit 1 MHz % ns ns ns ns 1 MHz %
Conditions
8
8.0008 4.4 4.4 8 1/40 60
Note: Figure 6.1
Refer to Figure 6.1 for timing diagram. Input Clock Timing
t1
SCLK t2 t3 TCLK t6 TBC t7 REGCLK t8 t8 t4 t5 t2
System Interface
10-Bit PHY Interface
Register Interface
6-4
Specifications
Table 6.3
Transmit System Interface Timing Characteristics
Limit
Symbol t11 t12
Parameter TXENn setup time TXENn hold time
Min 5 0 1 SCLK cycle
Typ
Max
Unit ns ns
Conditions
t13
TXENn deassert time TXD, TXBE, TXSOFn, TXEOF, and TXCRC setup time TXD, TXBE, TXSOFn, TXEOF, and TXCRC hold time TXWMn delay time TXWMn rise/fall time
ns
t14 t15
5 0
ns ns
t16 t17
0
8 4
ns ns
Note:
Refer to Figure 6.2 for timing diagram.
AC Electrical Characteristics
6-5
Figure 6.2
SCLK
Transmit System Interface Timing
6-6 AC Electrical Characteristics
t16 TXWMn[2:1] t11 TX_ENn t15 t14 TXD[31:0] t15 t14 TXBE[3:0] t14 TXSOF t15
t16
t12
[1]
t13
t14 TXEOF t14 TXCRCn t15
t15
Note: [1] Back-to-back packet transmission allowed without TXENn deassertion.
Table 6.4
Receive System Interface Timing Characteristics
Limit
Symbol t31 t32
Parameter RXENn setup time RXENn hold time
Min 5 1 3 SCLK cycles
Typ
Max
Unit ns ns
Conditions
t33
RXENn deassert time RXD, RXBE, RXSOF, RXEOF, and RXWM delay time RXD, RXBE, RXSOF, RXEOF, and RXWM rise/fall time RXABORT setup time RXABORT hold time
ns
t34
0
8
ns
t35 t41 t42
4 5 0 1 SCLK cycles + 8 ns
ns ns ns
t43
RXABORT assert to RXWM deassert delay RXOEn deassert to data High-Z delay RXOEn assert to data active delay
0
ns
t46
0
15
ns
t47
0
15
ns
Note:
Refer to Figure 6.3-Figure 6.5 for timing diagrams.
AC Electrical Characteristics
6-7
Figure 6.3
SCLK
Receive System Interface Timing
6-8 AC Electrical Characteristics
t34 RXWM1
t34
t34 RXWM2 t31 RX_ENn t33 t34 RXD[31:0]
First Word Last Word Status Word First Word
t32
t34 RXBE[3:0]
1111 1111 1111 1111 1111 1111 1111 00011111 1111 1111 1111 1111
t34 RXSOF
t34
t34 RXEOF
t34
Figure 6.4
SCLK
Receive System Interface RXABORT Timing
t43 RXWM[2:1]
RX_ENn t41 RXABORT t42
RXD[31:0]
First Word
Aborted Packet Status Word
RXBE[3:0]
1111
1111 11 11
1111
1111
1111
RXSOF
RXEOF
Figure 6.5
RXOEn
Receive System Interface RXOEn Timing
t46 RXD[31:0] RXBE[3:0] RXSOF RXEOF
High-Z
t47
AC Electrical Characteristics
6-9
Table 6.5
System Interface RXDC/TXDC Timing Characteristics
Limit
Symbol Parameter t51 t52 TXDC/RXDC assert delay time TXDC/RXDC deassert delay time
Min 0 0
Typ
Max 8 2 SCLK cycle + 8 ns 3 SCLK cycle + 8 ns
Unit ns ns
Conditions
AutoClear mode off
0
ns
AutoClear mode on
t53 t54
CLR_TXDC/RXDC setup time CLR_TXDC/RXDC hold time TXDC/RXDC rise and fall time
5 0 4
ns ns ns
Note: Figure 6.6
SCLK
Refer to Figure 6.6 for timing diagram.
System Interface RXDC/TXDC Timing
TXENn RXENn t51 TXDC RXDC t53 CLR_TXDC CLR_RXDC t54
Autoclear Mode Off
t52
TXEOF
Autoclear Mode Off
RXEOF
6-10
Specifications
Table 6.6
Transmit 10-Bit PHY Interface Timing Characteristics
Limit
Symbol t61 t62 t63
Parameter TBC period TBC HIGH time TBC LOW time TX[0:9] data valid before TBC rising edge TX[0:9] data valid after TBC rising edge TBC, TX[0:9] rise and fall time
Min 7.992 3.2 3.2
Typ 8
Max 8.008 4.8 4.8
Unit ns ns ns
Conditions
t64
2.0
ns
Assumes TBC duty cycle = 40-60% Assumes TBC duty cycle = 40-60%
t65
1.0
ns
t66
0.7
2.4
ns
Note: Figure 6.7
Refer to Figure 6.7 for timing diagram.
Transmit 10-Bit PHY Interface Timing
t61 t66 t66
TBC t64 TX[0:9] t65 t62 t63 t66
AC Electrical Characteristics
6-11
Table 6.7
Receive 10-Bit PHY Interface Timing Characteristics
Limit
Symbol Parameter
t71 t72
Min 62.4937 6.4 6.4
Typ 62.5
Max 62.5063 9.6 128 9.6 128 8.5
Unit MHz ns ns ns ns ns ns ns
Conditions
RBC frequency RBC HIGH time
During synchronization
t73
RBC LOW time
6.4 6.4
During synchronization
t
74
RBC skew RX[0:9] setup time RX[0:9] hold time RBC, RX[0:9] rise and fall time
7.5 2.5 1.5 0.7
t75 t76 t77
2.4
ns
Note: Figure 6.8
Refer to Figure 6.8 for timing diagram.
Receive 10-Bit PHY Interface Timing
t71 t77 t77
RBC1 t72 t74 RBC0 t76 t75 RX[0:9] t75 t76 t72 t73 t77 t73 t71 t77 t77
6-12
Specifications
Table 6.8
Register Interface Timing Characteristics
Limit
Symbol t81
Parameter REGCSn, REGWRn, REGRDn, REGA, REGD setup time REGCSn, REGWRn, REGRDn, REGA, REGD hold time REGCLK to REGD active delay
Min 10
Typ
Max
Unit ns
Conditions
t82
1
ns
t83
10
ns
Read cycle. All registers except Counter Registers 1-53 Read cycle. Counter Registers 1-53, first 16 bits of counter result Read cycle. Counter Registers 1-53, second 16 bits of counter result
6 REGCLK cycles + 10 ns 3 REGCLK cycles + 10 ns t84 t85 t86 t87 REGCLK to REGD 3-state delay REGCLK to REGINT assert delay REGCLK to REGINT deassert delay Deassertion time between reads 0 0 0 4 REGCLK 10 20 20
ns
ns
ns ns ns
Note:
Refer to Figure 6.9 and Figure 6.10 for timing diagrams.
AC Electrical Characteristics
6-13
Figure 6.9
Register Interface Timing (Excluding Counter Read Cycle)
t7
REGCLK t82 t81 REGCSn t82 t81 REGWRn t82 t81 REGRDn t81 REGA{7:0] t82 t81 REGD[15:0]
High-Z Data In High-Z
t8
t8
t82
t83
Data Out
t84
High-Z
t85 REGINT
Write Cycle REGD[15:0] Is Input
t86
Read Cycle REGD[15:0] is Output
6-14
Specifications
Figure 6.10 Register Interface Timing, Counter Read Cycle (of the Same Counter)
1 REGCLK t81 REGCSn t82 2 6 1 3
REGWRn t81 REGRDn t81 REGAD[15:0] t84 REGD[15:0]
High-Z 1st Counter Address
t82
t84
2nd Counter Address
t83 t84
Not Valid
1st 16 Bits of Counter Result
t83
Not Valid
t84
2nd 16 Bits of Counter Result
High-Z
AC Electrical Characteristics
6-15
Figure 6.11 Register Interface Timing, Counter Read Cycle (Between Different Counters)
t87 REGCLK t81 REGCSn t82 t81 t82
REGWRn t81 REGRDn t81 REGAD[15:0]
Counter Address A
t82
t81
t82
t82
t81
Counter Address B
t82
t84 REGD[15:0]
High-Z 16 Bits of Not Valid Counter Results
t84
Hi-Z
t84
Not Valid 16 Bits of Counter Results
t84
High-Z
t83 Note: No burst reading,
t83
6-16
Specifications
6.4 8101 208-pin PQFP Pinout and Pin Listing
Figure 6.12 8101 208-Pin PQFP Pinout
VCC RXEOF RXSOF RXBE3 RXBE2 RXBE1 RXBE0 GND RXD0 RXD1 RXD2 RXD3 GND RXD4 RXD5 VCC VCC RXD6 RXD7 GND RXD8 RXD9 RXD10 RXD11 GND RXD12 RXD13 VCC RXD14 RXD15 GND RXD16 RXD17 RXD18 RXD19 GND RXD20 RXD21 VCC RXD22 RXD23 GND RXD24 RXD25 RXD26 RXD27 GND RXD28 RXD29 VCC RXD30 RXD31 RXENn RXOEn GND VCC VCC VCC RESERVED VCC VCC TAP VCC TEST SD GND RX0 RX1 RX2 RX3 RX4 GND RX5 RX6 RX7 RX8 RX9 RBC0 GND RBC1 LCK_REFn VCC EN_CDET TBC GND EWRAP TX9 GND TX8 TX7 GND TX6 TX5 GND TX4 VCC TX3 GND TX2 TX1 GND TX0 GND TCLK
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
VCC LINKn REGA0 REGA1 REGA2 REGA3 GND REGA4 REGA5 REGA6 REGA7 REGINT REGWRn REGRDn GND REGCLK REGD15 VCC REGD14 REGD13 REGD12 GND REGD11 REGD10 REGD9 REGD8 GND REGD7 VCC REGD6 REGD5 REGD4 GND REGD3 REGD2 REGD1 REGD0 GND GND REGCSn RESERVED RESETn FCNTRL TXD31 VCC TXD30 TXD29 TXD28 TXD27 TXD26 TXD25 TXD24
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
8101 208 PQFP Top View
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
RXWM1 RXWM2 RXDC CLR_RXDC RXABORT VCC GND SCLK VCC VCC TXENn TXSOF TXEOF GND TXBE0 TXBE1 TXBE2 TXBE3 GND TXWM1n TXWM2n VCC TXDC CLR_TXDC TXCRCn TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 GND TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 VCC TXD15 TXD16 GND TXD17 TXD18 TXD19 TXD20 TXD21 TXD22 TXD23
8101 208-pin PQFP Pinout and Pin Listing
6-17
Table 6.9
Signal CLR_RXDC CLR_TXDC EN_CDET EWRAP FCNTRL GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LCK_REFn LINKn RBC0 RBC1 REGA0 REGA1
8101 208-Pin PQFP Pin List (AlphabeticalListing)
Pin Signal 153 133 31 34 95 3 14 20 27 33 36 39 42 46 49 51 59 67 74 79 85 90 91 112 123 138 143 150 162 167 173 178 184 189 196 201 29 54 26 28 55 56 REGA2 REGA3 REGA4 REGA5 REGA6 REGA7 REGCLK REGCSn REGD0 REGD1 REGD2 REGD3 REGD4 REGD5 REGD6 REGD7 REGD8 REGD9 REGD10 REGD11 REGD12 REGD13 REGD14 REGD15 REGINT REGRDn REGWRn RESERVED RESERVED RESETn RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RXABORT RXBE0 Pin 57 58 60 61 62 63 68 92 89 88 87 86 84 83 82 80 78 77 76 75 73 72 71 69 64 66 65 7 93 94 15 16 17 18 19 21 22 23 24 25 152 202 Signal RXBE1 RXBE2 RXBE3 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 RXD16 RXD17 RXD18 RXD19 RXD20 RXD21 RXD22 RXD23 RXD24 RXD25 RXD26 RXD27 RXD28 RXD29 RXD30 RXD31 RXDC RXENn RXEOF RXOEn RXSOF RXWM1 RXWM2 Pin 203 204 205 200 199 198 197 195 194 191 190 188 187 186 185 183 182 180 179 177 176 175 174 172 171 169 168 166 165 164 163 161 160 158 157 154 1 207 2 206 156 155 Signal SCLK SD TAP TBC TCLK TEST TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 TXBE0 TXBE1 TXBE2 TXBE3 TXCRCn TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TXD16 TXD17 TXD18 TXD19 TXD20 Pin Signal 149 13 10 32 52 12 50 48 47 45 43 41 40 38 37 35 142 141 140 139 132 131 130 129 128 127 126 125 124 122 121 120 119 118 117 116 114 113 111 110 109 108 TXD21 TXD22 TXD23 TXD24 TXD25 TXD26 TXD27 TXD28 TXD29 TXD30 TXD31 TXDC TXENn TXEOF TXSOF TXWM1n TXWM2n VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin 106 107 105 104 103 102 101 100 99 98 96 134 145 144 146 137 136 4 5 6 8 9 11 30 44 53 70 81 97 115 135 147 148 151 159 170 181 193 192 208
6-18
Specifications
6-19 8104 208-Pin BGA Pinout and Pin Listing
6.5 8104 208-Pin BGA Pinout and Pin Listing
Figure 6.13 8104 208-Pin BGA Pinout
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
VCC
B1 B2
RXEOF
B3
RXBE3
B4
RXD0
B5
RXD4
B6
VCC
B7
GND
B8
RXD11
B9
RXD16
B10
RXD20
B11
RXD21
B12
GND
B13
RXD27
B14
RXD29
B15
RXD30
B16
RXD31
RXOEn
C1 C2
RXENn
C3
RXSOF
C4
RXBE2
C5
RXD2
C6
VCC
C7
RXD8
C8
RXD10
C9
RXD15
C10
RXD19
C11
RXD22
C12
RXD25
C13
RXD28
C14
VCC
RXWM1
C15
RXWM2
C16
GND
D1 D2
VCC
D3
VCC
D4
RXBE1
D5
RXD3
D6
RXD6
D7
RXD7
D8
RXD12
D9
RXD14
D10
RXD18
D11
RXD23
D12
RXD26
D13
GND
RX-ABORT
D14
CLR_RXDC
D15 D16
RXDC
RESERVED
E1 E2
VCC
E3
VCC
E4
RXBE0
RXD1
RXD5
RXD9
RXD13
VCC
RXD17
VCC
RXD24
E13
VCC
E14
VCC
E15
VCC
E16
VCC
TAP
F1 F2
VCC
F3
VCC
F4
TEST
F13
GND
F14
TXEOF
F15
TXENn
F16
TXSOF
SD
G1 G2
RX0
G3
RX1
G4
RX2
G7 G8 G9 G10 G13
TXBE3
G14
TXBE2
G15
TXBE0
G16
TXBE1
RX4
H1 H2
RX3
H3
RX5
H4
RX6
H7
GND
H8
GND
H9
GND
H10
GND
H13
TXDC
H14
VCC
TXWM2n
H15
TXWM1n
H16
RX8
J1 J2
RX7
J3
RX9
J4
RBC0
J7
GND
J8
GND
J9
GND
J10
GND
J13
TXD1
J14
TXD0
TXCRCn
J15
CLR_TXDC
J16
GND
K1 K2
RBC1
LCK_REFn
K3 K4
VCC
K7
GND
K8
GND
K9
GND
K10
GND
K13
TXD2
K14
TXD3
K15
TXD5
K16
TXD4
TBC
L1 L2
ENC_DET
L3
EWRAP
L4
TX9
GND
GND
GND
GND
L13
TXD6
L14
TXD7
L15
GND
L16
TXD8
TX7
M1 M2
TX8
M3
GND
M4
TX6
M13
TXD9
TXD10
M14 M15
TXD11
M16
TXD12
GND
N1 N2
TX5
N3
TX4
N4
VCC
N5 N6 N7 N8 N9 N10 N11 N12 N13
TXD13
N14
TXD14
N15
TXD15
N16
VCC
TX3
P1 P2
TX2
P3
GND
P4
GND
REGWRn
P5 P6
REGD15
P7
REGD12
P8
REGD8
P9
GND
REGD5
P10
REGD1
P11
RESERVED
P12 P13
VCC
P14
TXD17
P15
TXD18
P16
TXD16
TX1
R1 R2
TCLK
R3
REGA3
R4
REGA5
R5
REGINT
R6
REGCLK
R7
REGD13
R8
REGD9
R9
REGD6
REGD4
R10
REGD0
R11
RESETn
R12 R13
TXD30
R14
TXD19
R15
TXD21
R16
TXD20
TX0
T1 T2
VCC
T3
REGA2
T4
REGA4
T5
REGA6
T6
REGRDn
T7
VCC
T8
REGD11
T9
VCC
REGD2
T10 T11
GND
T12
TXD31
T13
TXD28
T14
TXD27
T15
TXD23
T16
TXD22
LINKn
REGA0
REGA1
GND
REGA7
GND
REGD14
REGD10
REGD7
REGD3
REGCSn
FCNTRL
TXD29
TXD26
TXD25
TXD24
Table 6.10
Signal CLR_RXDC CLR_TXDC EN_CDET EWRAP FCNTRL GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LCK_REFn LINKn RBC0 RBC1 REGA0 REGA1
8104 208-Pin BGA Pin List (AlphabeticalListing)
Pin Signal C15 H16 K02 K03 T12 A07 A12 C01 C13 E13 G07 G08 G09 H07 H08 H09 H10 J01 J07 J08 J10 K07 K08 K09 K10 K15 L03 M01 N03 N04 N09 R11 T04 T06 G10 J09 J03 T01 H04 J02 T02 T03 REGA2 REGA3 REGA4 REGA5 REGA6 REGA7 REGCLK REGCSn REGD0 REGD1 REGD2 REGD3 REGD4 REGD5 REGD6 REGD7 REGD8 REGD9 REGD10 REGD11 REGD12 REGD13 REGD14 REGD15 REGINT REGRDn REGWRn RESERVED RESERVED RESETn RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RXABORT RXBE0 Pin R03 P03 R04 P04 R05 T05 P06 T11 P11 N11 R10 T10 P10 N10 P09 T09 N08 P08 T08 R08 N07 P07 T07 N06 P05 R06 N05 D01 N12 P12 F02 F03 F04 G02 G01 G03 G04 H02 H01 H03 C14 D04 Signal RXBE1 RXBE2 RXBE3 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 RXD16 RXD17 RXD18 RXD19 RXD20 RXD21 RXD22 RXD23 RXD24 RXD25 RXD26 RXD27 RXD28 RXD29 RXD30 RXD31 RXDC RXENn RXEOF RXOEn RXSOF RXWM1 RXWM2 Pin C04 B04 A03 A04 D05 B05 C05 A05 D06 C06 C07 B07 D07 B08 A08 C08 D08 C09 B09 A09 D10 C10 B10 A10 A11 B11 C11 D12 B12 C12 A13 B13 A14 A15 A16 C16 B02 A02 B01 B03 B15 B16 Signal SCLK SD TAP TBC TCLK TEST TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 TXBE0 TXBE1 TXBE2 TXBE3 TXCRCn TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TXD16 TXD17 TXD18 TXD19 TXD20 Pin Signal D15 F01 E01 K01 P02 E04 R01 P01 N02 N01 M03 M02 L04 L01 L02 K04 F15 F16 F14 F13 H15 H14 H13 J13 J14 J16 J15 K13 K14 K16 L13 L14 L15 L16 M13 M14 M15 N16 N14 N15 P14 P16 TXD21 TXD22 TXD23 TXD24 TXD25 TXD26 TXD27 TXD28 TXD29 TXD30 TXD31 TXDC TXENn TXEOF TXSOF TXWM1n TXWM2n VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin P15 R16 R15 T16 T15 T14 R14 R13 T13 P13 R12 G13 E15 E14 E16 G16 G15 A01 A06 B06 B14 C02 C03 D02 D03 D09 D11 D13 D14 D16 E02 E03 G14 J04 M04 M16 N13 R02 R07 R09
6-20
Specifications
6.6 Package Mechanical Dimensions
The 8101 Gigabit Ethernet Controller is available in the 208-pin Plastic Quad Flat Pack (PQFP) as shown in Figure 6.14. and the 8104 Ball Grid Array Package as shown in Figure 6.15. Figure 6.14 208-Pin PQFP Mechanical Drawing
30. 60 0.30 28. 00 0.20 0.15 0. 0 - 0. 05 1
30. 60 0.30
28. 00 0.20
0.10 MAX
#208
See Detail A
#1 0. 20 0.10
1. 25 0. 50 4.10 Max.
0. 25 min. 3.40 0. 20
Detail A 1. All Dimensions are in (millimeters) 0. 50 0. 20
0 - 8
Package Mechanical Dimensions
6-21
Figure 6.15 208 mini-BGA (HG) Mechanical Drawing
Important:
This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code HG
6-22
Specifications
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4940 Pearl East Circle Suite 201 Boulder, CO 80301
Tel: 972.244.5000
Houston
500 North Central Expressway Suite 440 Plano, TX 75074
Fax: 972.244.5001
Tel: 81.3.5463.7821
Osaka
Rivage-Shinagawa Bldg. 14F 4-1-8 Kounan Minato-ku, Tokyo 108-0075
Fax: 81.3.5463.7820
Fax: 303.541.0641
Tel: 781.685.3800 Fax: 781.685.3801 Minnesota Minneapolis
20405 State Highway 249 Suite 450 Houston, TX 77070
4420 Arrowswest Drive Colorado Springs, CO 80907
Tel: 281.379.7800 Fax: 281.379.7818
Tel: 719.533.7000 Fax: 719.533.7020
Tel: 612.921.8300
8300 Norman Center Drive Suite 730 Minneapolis, MN 55437
Tel: 81.6.947.5281
Crystal Tower 14F 1-2-27 Shiromi Chuo-ku, Osaka 540-6014
Fax: 81.6.947.5287
Fax: 612.921.8399
Sales Offices and Design Resource Centers (Continued)
Korea Seoul LSI Logic Corporation of Korea Ltd
10th Fl., Haesung 1 Bldg. 942, Daechi-dong, Kangnam-ku, Seoul, 135-283
Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd
World Trade Center Eindhoven Building `Rijder' Bogert 26 5612 LZ Eindhoven
Tel: 31.40.265.3580 Fax: 31.40.296.2109 Singapore Singapore LSI Logic Pte Ltd
7 Temasek Boulevard #28-02 Suntec Tower One Singapore 038987
Tel: 65.334.9061 Fax: 65.334.4749 Sweden Stockholm LSI Logic AB
Tel: 46.8.444.15.00
Finlandsgatan 14 164 74 Kista
Fax: 46.8.750.66.47 Taiwan Taipei LSI Logic Asia, Inc. Taiwan Branch
10/F 156 Min Sheng E. Road Section 3 Taipei, Taiwan R.O.C.
Tel: 886.2.2718.7828 Fax: 886.2.2718.8869 United Kingdom Bracknell LSI Logic Europe Ltd
Tel: 44.1344.426544 Sales Offices with
Greenwood House London Road Bracknell, Berkshire RG12 2UB
Fax: 44.1344.481039
Design Resource Centers
International Distributors
Australia New South Wales Reptechnic Pty Ltd
Hong Kong Hong Kong AVT Industrial Ltd
Unit 608 Tower 1 Cheung Sha Wan Plaza 833 Cheung Sha Wan Road Kowloon, Hong Kong
Yokohama-City Innotech
2-15-10 Shin Yokohama Kohoku-ku Yokohama-City, 222-8580
United Kingdom Maidenhead Azzurri Technology Ltd
16 Grove Park Business Estate Waltham Road White Waltham Maidenhead, Berkshire SL6 3LW
Tel: 612.9953.9844
Belgium Acal nv/sa
Lozenberg 4 1932 Zaventem
3/36 Bydown Street Neutral Bay, NSW 2089
Fax: 612.9953.9683
Tel: 81.45.474.9037 Fax: 81.45.474.9065 Macnica Corporation
Hakusan High-Tech Park 1-22-2 Hadusan, Midori-Ku, Yokohama-City, 226-8505
Tel: 852.2428.0008 Fax: 852.2401.2105 Serial System (HK) Ltd
2301 Nanyang Plaza 57 Hung To Road, Kwun Tong Kowloon, Hong Kong
Tel: 44.1628.826826 Fax: 44.1628.829730 Milton Keynes Ingram Micro (UK) Ltd
Garamonde Drive Wymbush Milton Keynes Buckinghamshire MK8 8DF
Tel: 32.2.7205983 Fax: 32.2.7251014 China Beijing LSI Logic International Services Inc.
Beijing Representative Office Room 708 Canway Building 66 Nan Li Shi Lu Xicheng District Beijing 100045, China
Tel: 81.45.939.6140 Fax: 81.45.939.6141 The Netherlands Eindhoven Acal Nederland b.v.
Beatrix de Rijkweg 8 5657 EG Eindhoven
Tel: 852.2995.7538 Fax: 852.2950.0386 India Bangalore Spike Technologies India Private Ltd
951, Vijayalakshmi Complex, 2nd Floor, 24th Main, J P Nagar II Phase, Bangalore, India 560078
Tel: 44.1908.260422 Swindon EBV Elektronik
12 Interface Business Park Bincknoll Lane Wootton Bassett, Swindon, Wiltshire SN4 8SY
Tel: 31.40.2.502602 Fax: 31.40.2.510255 Switzerland Brugg LSI Logic Sulzer AG
Mattenstrasse 6a CH 2555 Brugg
Tel: 86.10.6804.2534 to 38 Fax: 86.10.6804.2521 France Rungis Cedex Azzurri Technology France
22 Rue Saarinen Sillic 274 94578 Rungis Cedex
Tel: 91.80.664.5530
Israel Tel Aviv Eastronics Ltd
11 Rozanis Street P.O. Box 39300 Tel Aviv 61392
Tel: 44.1793.849933 Fax: 44.1793.859555
Fax: 91.80.664.9748
Tel: 41.32.3743232 Fax: 41.32.3743233 Taiwan Taipei Avnet-Mercuries Corporation, Ltd
14F, No. 145, Sec. 2, Chien Kuo N. Road Taipei, Taiwan, R.O.C.
Sales Offices with
Design Resource Centers
Tel: 33.1.41806310 Fax: 33.1.41730340 Germany Haar EBV Elektronik
Hans-Pinsel Str. 4 D-85540 Haar
Tel: 972.3.6458777 Fax: 972.3.6458666 Japan Tokyo Daito Electron
Sogo Kojimachi No.3 Bldg 1-6 Kojimachi Chiyoda-ku, Tokyo 102-8730
Tel: 886.2.2516.7303 Fax: 886.2.2505.7391 Lumax International Corporation, Ltd
7th Fl., 52, Sec. 3 Nan-Kang Road Taipei, Taiwan, R.O.C.
Tel: 49.89.4600980 Fax: 49.89.46009840 Munich Avnet Emg GmbH
Stahlgruberring 12 81829 Munich
Tel: 81.3.3264.0326 Fax: 81.3.3261.3984 Global Electronics Corporation
Nichibei Time24 Bldg. 35 Tansu-cho Shinjuku-ku, Tokyo 162-0833
Tel: 886.2.2788.3656 Fax: 886.2.2788.3568 Prospect Technology Corporation, Ltd
4Fl., No. 34, Chu Luen Street Taipei, Taiwan, R.O.C.
Tel: 49.89.45110102 Fax: 49.89.42.27.75 Wuennenberg-Haaren Peacock AG
Graf-Zepplin-Str 14 D-33181 Wuennenberg-Haaren
Tel: 81.3.3260.1411 Fax: 81.3.3260.7100 Technical Center Tel: 81.471.43.8200 Marubeni Solutions
1-26-20 Higashi Shibuya-ku, Tokyo 150-0001
Tel: 886.2.2721.9533 Fax: 886.2.2773.3756 Wintech Microeletronics Co., Ltd
7F., No. 34, Sec. 3, Pateh Road Taipei, Taiwan, R.O.C.
Tel: 49.2957.79.1692 Fax: 49.2957.79.9341
Tel: 81.3.5778.8662 Fax: 81.3.5778.8669 Shinki Electronics
Myuru Daikanyama 3F 3-7-3 Ebisu Minami Shibuya-ku, Tokyo 150-0022
Tel: 886.2.2579.5858 Fax: 886.2.2570.3123
Tel: 81.3.3760.3110 Fax: 81.3.3760.3101