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8-Bit SAA-XC866
8-Bit Single-Chip Microcontroller
Data Sheet
V1.5 2010-09
Microcontrollers
Edition 2010-09 Published by Infineon Technologies AG 81726 Munich, Germany
(c) 2010 Infineon Technologies AG All Rights Reserved.
Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
8-Bit SAA-XC866
8-Bit Single-Chip Microcontroller
Data Sheet
V1.5 2010-09
Microcontrollers
SAA-XC866
SAA-XC866 Data Sheet Revision History: 2010-09 Previous Version: V1.4 2010-08 Page All Subjects (major changes since last revision) Changes from V1.4 2010-08 to V1.5 2010-09
V1.5
3.3 V device variant is added to the data sheet. Parameters specific to the variant are also added.
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
Data Sheet
V1.5, 2010-09
SAA-XC866
Table of Contents 1 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.2.4 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.4.3 3.5 3.6 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.10 3.11 3.11.1 3.11.2 3.12 3.13 3.13.1 3.14 3.15 3.16
Page
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAA-XC866 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Programming Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
15 15 16 19 21 21 23 27 28 40 42 43 44 44 49 51 52 55 56 58 58 59 61 63 65 66 69 70 73 73 74 74 76 78 79
Data Sheet
V1.5, 2010-09
SAA-XC866
3.17 3.18 3.18.1 3.18.2 3.19 3.19.1 3.20 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.2.3.1 4.2.4 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 5 5.1 5.2 5.3
Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80 82 83 84 85 86 87
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters (PG-TSSOP-38) . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 108 109 110
Data Sheet
3
V1.5, 2010-09
8-Bit Single-Chip Microcontroller XC800 Family
SAA-XC866
1
Summary of Features
* High-performance XC800 Core - compatible with standard 8051 processor - two clocks per machine cycle architecture (for memory access without wait state) - two data pointers * On-chip memory - 8 Kbytes of Boot ROM - 256 bytes of RAM - 512 bytes of XRAM - 4/8/16 Kbytes of Flash; or 8/16 Kbytes of ROM, with additional 4 Kbytes of Flash (includes memory protection strategy) * I/O port supply at 3.3 V/5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (further features are on next page)
4K/ 8K/16K Bytes Flash or 8K/16K Bytes ROM 1)
On-Chip Debug Support
UART
SSC
Port 0
6-bit Digital I/O
Boot ROM 8K Bytes XC800 Core XRAM 512 Bytes
Capture/Compare Unit 16-bit
Port 1
5-bit Digital I/O
Compare Unit 16-bit
Port 2
8-bit Digital/Analog Input
RAM 256 Bytes
Timer 0 16-bit
Timer 1 16-bit
Timer 2 16-bit
Watchdog Timer
ADC 10-bit 8-channel
Port 3
8-bit Digital I/O
1) All ROM devices include 4K bytes Flash
Figure 1
SAA-XC866 Functional Units
Data Sheet
4
V1.5, 2010-09
SAA-XC866
Summary of Features Features (continued): * Reset generation - Power-On reset - Hardware reset - Brownout reset for core logic supply - Watchdog timer reset - Power-Down Wake-up reset * On-chip OSC and PLL for clock generation - PLL loss-of-lock detection * Power saving modes - slow-down mode - idle mode - power-down mode with wake-up capability via RXD or EXINT0 - clock gating control to each peripheral * Programmable 16-bit Watchdog Timer (WDT) * Four ports - 19 pins as digital I/O - 8 pins as digital/analog input * 8-channel, 10-bit ADC * Three 16-bit timers - Timer 0 and Timer 1 (T0 and T1) - Timer 2 * Capture/compare unit for PWM signal generation (CCU6) * Full-duplex serial interface (UART) * Synchronous serial channel (SSC) * On-chip debug support - 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) - 64 bytes of monitor RAM * PG-TSSOP-38 pin package * Temperature range TA: - SAA (-40 to 140 C)
Data Sheet
5
V1.5, 2010-09
SAA-XC866
Summary of Features SAA-XC866 Variant Devices The SAA-XC866 product family features devices with different configurations and program memory sizes, offering cost-effective solution for different application requirements. The list of SAA-XC866 devices and their differences are summarized in Table 1. Table 1 Device Type Flash1) Device Summary Device Name Power Supply (V) 5.0 5.0 5.0 P-Flash Size (Kbytes) 12 12 4 4 - - 12 - - - - D-Flash Size (Kbytes) 4 4 4 4 4 4 4 4 4 4 4 ROM Size (Kbytes) - - - - - - - 16 16 8 8 LIN BSL Support Yes No Yes No Yes No Yes Yes No Yes No
SAA-XC866L-4FRA 5.0 SAA-XC866-4FRA SAA-XC866-2FRA SAA-XC866-1FRA SAA-XC866L-2FRA 5.0 SAA-XC866L-1FRA 5.0 SAA-XC866L-4FRA 3.3
ROM
SAA-XC866L-4RRA 5.0 SAA-XC866-4RRA SAA-XC866-2RRA 5.0 5.0 SAA-XC866L-2RRA 5.0
1)
The flash memory (P-Flash and D-Flash) can be used for code or data.
Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies: * The derivative itself, i.e. its function set, the temperature range, and the supply voltage * the package and the type of delivery For the available ordering codes for the SAA-XC866, please refer to your responsible sales representative or your local distributor. As this document refers to all the derivatives, some descriptions may not apply to a specific product. For simplicity all versions are referred to by the term SAA-XC866 throughout this document.
Data Sheet
6
V1.5, 2010-09
SAA-XC866
General Device Information
2
2.1
General Device Information
Block Diagram
XC866 Internal Bus 8-Kbyte Boot ROM1) XC800 Core 256-byte RAM + 64-byte monitor RAM
Port 0
P0.0 - P0.5
Port 1
T0 & T1
UART
TMS MBC RESET VDDP VSSP VDDC VSSC
P1.0 - P1.1 P1.5-P1.7
CCU6
Port 2
512-byte XRAM 4/8/16-Kbyte Flash or 8/16-Kbyte ROM 2) Clock Generator 10 MHz On-chip OSC PLL WDT SSC Timer 2
P2.0 - P2.7
ADC
XTAL1 XTAL2
VAREF VAGND
Port 3
OCDS
P3.0 - P3.7
1) Includes 1-Kbyte monitor ROM 2) Includes additional 4-Kbyte Flash
Figure 2
SAA-XC866 Block Diagram
Data Sheet
7
V1.5, 2010-09
SAA-XC866
General Device Information
2.2
Logic Symbol
VDDP VSSP
VAREF Port 0 6-Bit VAGND Port 1 5-Bit RESET MBC TMS XTAL1 XTAL2 Port 3 8-Bit XC866 Port 2 8-Bit
VDDC
VSSC
Figure 3
SAA-XC866 Logic Symbol
Data Sheet
8
V1.5, 2010-09
SAA-XC866
General Device Information
2.3
Pin Configuration
MBC P0.3/SCLK_1/COUT63_1 P0.4/MTSR_1/CC62_1 P0.5/MRST_1/EXINT0_0/COUT62_1 XTAL2 XTAL1 VSSC VDDC P1.6/CCPOS1_1/T12HR_0/EXINT6 P1.7/CCPOS2_1/T13HR_0 TMS P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT/RXDO_1 P0.2/CTRAP_2/TDO_0/TXD_1 P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1 P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0 P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1 P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2 VDDP VSSP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 XC866
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
RESET P3.5/COUT62_0 P3.4/CC62_0 P3.3/COUT61_0 P3.2/CCPOS2_2/CC61_0 P3.1/CCPOS0_2/CC61_2/COUT60_0 P3.0/CCPOS1_2/CC60_0 P3.7/EXINT4/COUT63_0 P3.6/CTRAP_0 P1.5/CCPOS0_1/EXINT5/EXF2_0/RXDO_0 P1.1/EXINT3/TDO_1/TXD_0 P1.0/RXD_0/T2EX P2.7/AN7 VAREF VAGND P2.6/AN6 P2.5/AN5 P2.4/AN4 P2.3/AN3
Figure 4
SAA-XC866 Pin Configuration, PG-TSSOP-38 Package (top view)
Data Sheet
9
V1.5, 2010-09
SAA-XC866
General Device Information
2.4
Table 2
Pin Definitions and Functions
Pin Definitions and Functions
Symbol Pin Type Reset Function Number State P0 I/O Port 0 Port 0 is a 6-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC. Hi-Z TCK_0 T12HR_1 CC61_1 CLKOUT RXDO_1 P0.1 14 Hi-Z TDI_0 T13HR_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input Input/Output of Capture/Compare channel 1 Clock Output UART Transmit Data Output
P0.0
12
JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input RXD_1 UART Receive Data Input COUT61_1 Output of Capture/Compare channel 1 EXF2_1 Timer 2 External Flag Output CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/ Clock Output
P0.2
13
PU
CTRAP_2 TDO_0 TXD_1
P0.3
2
Hi-Z
SCK_1 SSC Clock Input/Output COUT63_1 Output of Capture/Compare channel 3 MTSR_1 CC62_1 SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/Compare channel 2
P0.4
3
Hi-Z
P0.5
4
Hi-Z
MRST_1
SSC Master Receive Input/ Slave Transmit Output EXINT0_0 External Interrupt Input 0 COUT62_1 Output of Capture/Compare channel 2
Data Sheet
10
V1.5, 2010-09
SAA-XC866
General Device Information Table 2 Pin Definitions and Functions (cont'd)
Symbol Pin Type Reset Function Number State P1 I/O Port 1 Port 1 is a 5-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC. PU PU RXD_0 T2EX EXINT3 TDO_1 TXD_0 CCPOS0_1 EXINT5 EXF2_0 RXDO_0 UART Receive Data Input Timer 2 External Trigger Input External Interrupt Input 3 JTAG Serial Data Output UART Transmit Data Output/ Clock Output CCU6 Hall Input 0 External Interrupt Input 5 TImer 2 External Flag Output UART Transmit Data Output
P1.0 P1.1
27 28
P1.5
29
PU
P1.6
9
PU
CCPOS1_1 CCU6 Hall Input 1 T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6 External Interrupt Input 6 CCPOS2_1 CCU6 Hall Input 2 T13HR_0 CCU6 Timer 13 Hardware Run Input P1.5 and P1.6 can be used as a software chip select output for the SSC.
P1.7
10
PU
Data Sheet
11
V1.5, 2010-09
SAA-XC866
General Device Information Table 2 Pin Definitions and Functions (cont'd)
Symbol Pin Type Reset Function Number State P2 I Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC. Hi-Z CCPOS0_0 CCU6 Hall Input 0 EXINT1 External Interrupt Input 1 T12HR_2 CCU6 Timer 12 Hardware Run Input TCK_1 JTAG Clock Input CC61_3 Input of Capture/Compare channel 1 AN0 Analog Input 0 CCPOS1_0 CCU6 Hall Input 1 EXINT2 External Interrupt Input 2 T13HR_2 CCU6 Timer 13 Hardware Run Input TDI_1 JTAG Serial Data Input CC62_3 Input of Capture/Compare channel 2 AN1 Analog Input 1 CCPOS2_0 CTRAP_1 CC60_3 AN2 AN3 AN4 AN5 AN6 AN7 CCU6 Hall Input 2 CCU6 Trap Input Input of Capture/Compare channel 0 Analog Input 2 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7
P2.0
15
P2.1
16
Hi-Z
P2.2
17
Hi-Z
P2.3 P2.4 P2.5 P2.6 P2.7
20 21 22 23 26
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Data Sheet
12
V1.5, 2010-09
SAA-XC866
General Device Information Table 2 Pin Definitions and Functions (cont'd)
Symbol Pin Type Reset Function Number State P3 I Port 3 Port 3 is a bidirectional general purpose I/O port. It can be used as alternate functions for the CCU6. Hi-Z CCPOS1_2 CCU6 Hall Input 1 CC60_0 Input/Output of Capture/Compare channel 0 CCPOS0_2 CCU6 Hall Input 0 CC61_2 Input/Output of Capture/Compare channel 1 COUT60_0 Output of Capture/Compare channel 0 CCPOS2_2 CCU6 Hall Input 2 CC61_0 Input/Output of Capture/Compare channel 1 COUT61_0 Output of Capture/Compare channel 1 CC62_0 Input/Output of Capture/Compare channel 2
P3.0
32
P3.1
33
Hi-Z
P3.2
34
Hi-Z
P3.3 P3.4 P3.5 P3.6 P3.7
35 36 37 30 31
Hi-Z Hi-Z Hi-Z PD Hi-Z
COUT62_0 Output of Capture/Compare channel 2 CTRAP_0 CCU6 Trap Input EXINT4 External Interrupt Input 4 COUT63_0 Output of Capture/Compare channel 3
Data Sheet
13
V1.5, 2010-09
SAA-XC866
General Device Information Table 2 Pin Definitions and Functions (cont'd)
Symbol Pin Type Reset Function Number State
VDDP VSSP VDDC VSSC VAREF VAGND
XTAL1 XTAL2 TMS RESET MBC
1)
18 19 8 7 25 24 6 5 11 38 1
- - - - - - I O I I I
- - - - - - Hi-Z Hi-Z PD PU PU
I/O Port Supply (3.3 V/5.0 V) Also used by EVR and analog modules. I/O Port Ground Core Supply Monitor (2.5 V) Core Supply Ground ADC Reference Voltage ADC Reference Ground External Oscillator Input (NC if not needed) External Oscillator Output (NC if not needed) Test Mode Select Reset Input Monitor & BootStrap Loader Control
1)
An external pull-up device in the range of 4.7 k to 100 k is required to enter user mode. Alternatively MBC can be tied to high if alternate functions (for debugging) of the pin are not utilized.
Data Sheet
14
V1.5, 2010-09
SAA-XC866
Functional Description
3
3.1
Functional Description
Processor Architecture
The SAA-XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the SAA-XC866 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The SAA-XC866 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and SFRs. Figure 5 shows the CPU functional blocks.
Internal Data Memory Core SFRs External Data Memory 16-bit Registers & Memory Interface Program Memory Opcode & Immediate Registers Multiplier / Divider ALU Register Interface External SFRs
Opcode Decoder
Timer 0 / Timer 1
fCCLK Memory Wait Reset
State Machine & Power Saving
UART
Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt
Interrupt Controller
Figure 5
Data Sheet
CPU Block Diagram
15 V1.5, 2010-09
SAA-XC866
Functional Description
3.2
* * * * *
Memory Organization
The SAA-XC866 CPU operates in the following five address spaces: 8 Kbytes of Boot ROM program memory 256 bytes of internal RAM data memory 512 bytes of XRAM memory a 128-byte Special Function Register area 4/8/16 Kbytes of Flash program memory (Flash devices); or 8/16 Kbytes of ROM program memory, with additional 4 Kbytes of Flash (ROM devices)
Data Sheet
16
V1.5, 2010-09
SAA-XC866
Functional Description Figure 6 illustrates the memory address spaces of the SAA-XC866-4FR devices.
FFFF H FFFF H
XRAM 512 bytes
F200H F000H
XRAM 512 bytes
F200H F000H
E000H
Boot ROM 8 Kbytes
C000H
B000H
D-Flash Bank 4 Kbytes 1)
A000H
3000H
Indirect Address
Direct Address
FFH
P-Flash Bank 2 4 Kbytes2)
2000H
Internal RAM
Special Function Registers
80H
P-Flash Bank 1 4 Kbytes2)
1000H 7FH
P-Flash Bank 0 4 Kbytes 1)
0000H 0000H 00H
Internal RAM
Program Space External Data Space Internal Data Space 1) For SAA -XC866-1FR device, physically one 4KByte D-Flash bank is mapped to both address range 0000H - 0FFFH and A000H AFFFH, and the shaded banks are not available. 2) For SAA -XC866-2FR device, the shaded banks are not available.
Figure 6
Memory Map of SAA-XC866 Flash Devices
Data Sheet
17
V1.5, 2010-09
SAA-XC866
Functional Description Figure 7 illustrates the memory address spaces of the SAA-XC866-4RR device.
FFFF H
XRAM 512 Bytes
F200H F000H E000H
XRAM 512 Bytes
F200H F000H
Boot ROM 8 KBytes
C000H B000H Flash (4K-X bytes)
Total 4 KBytes
2)
User ROM (X bytes)
A000H
3000H
Indirect Address
Direct Address
FF H
User ROM 4 KBytes1)
2000H
Internal RAM
Special Function Registers
80H
User ROM 8 KBytes
7FH
Internal RAM
0000H 0000H 00H
Code Space
External Data Space
Internal Data Space
1) For SAA - XC866-2RR device, the shaded area is not available and Flash is 4 Kbytes. 2) For SAA - XC866-4RR device: ROM = (12+X) KBytes, Flash = (4-X) Kbytes.
Memory Map User Mode
Figure 7
Memory Map of SAA-XC866 ROM Devices
Data Sheet
18
V1.5, 2010-09
SAA-XC866
Functional Description
3.2.1
Memory Protection Strategy
The SAA-XC866 memory protection strategy includes: * Read-out protection: The Flash Memory can be enabled for read-out protection and ROM memory is always protected. * Program and erase protection: The Flash memory in all devices can be enabled for program and erase protection. Flash memory protection is available in two modes: * Mode 0: Only the P-Flash is protected; the D-Flash is unprotected * Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 3. Table 3 Mode Activation Selection Flash Protection Modes 0 MSB of password = 0 1 MSB of password = 1 Read instructions in the P-Flash or D-Flash Not possible Read instructions in the P-Flash or D-Flash Not possible Not possible
Program a valid password via BSL mode 6
P-Flash contents Read instructions in the can be read by P-Flash P-Flash program Not possible and erase D-Flash contents Read instructions in any program can be read by memory D-Flash program Possible D-Flash erase Possible, on the condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. A password match triggers an automatic erase of the read-protected Flash contents, see Table 4 and Table 5, and the programmed password is erased. The Flash protection is then disabled upon the next reset. For XC866-2FR and XC866-4FR devices: The selection of protection type is summarized in Table 4.
Data Sheet
19
V1.5, 2010-09
SAA-XC866
Functional Description Table 4 PASSWORD 1XXXXXXXB 0XXXXXXXB Flash Protection Type for XC866-2FR and XC866-4FR devices Type of Protection Flash Protection Mode 1 Flash Protection Mode 0 Flash Banks to Erase when Unprotected All Banks P-Flash Bank
For XC866-1FR device and ROM devices: The selection of protection type is summarized in Table 5. Table 5 PASSWORD Flash Protection Type for XC866-1FR device and ROM devices Type of Protection (Applicable to the whole Flash) Sectors to Erase when Unprotected Comments
1XXXXXXXB 00001XXXB 00010XXXB 00011XXXB 00100XXXB 00101XXXB 00110XXXB 00111XXXB 01000XXXB 01001XXXB 01010XXXB Others
Read/Program/Erase All Sectors Erase Erase Erase Erase Erase Erase Erase Erase Erase Erase Erase Sector 0 Sector 0 and 1 Sector 0 to 2 Sector 0 to 3 Sector 0 to 4 Sector 0 to 5 Sector 0 to 6 Sector 0 to 7 Sector 0 to 8 All Sectors None
Compatible to Protection mode 1
Although no protection scheme can be considered infallible, the SAA-XC866 memory protection strategy provides a very high level of protection for a general purpose microcontroller.
Data Sheet
20
V1.5, 2010-09
SAA-XC866
Functional Description
3.2.2
Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include: * Mapping * Paging
3.2.2.1
Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 8. SYSCON0 System Control Register 0
7 6 5 0 r 4 3 2 1 rw
Reset Value: 00H
1 0 r 0 RMAP rw
Field RMAP
Bits 0
Type Description rw Special Function Register Map Control 0 The access to the standard SFR area is enabled. 1 The access to the mapped SFR area is enabled. Reserved Returns the last value if read; should be written with 1. Reserved Returns 0 if read; should be written with 0.
1
2
rw
0
1,[7:3]
r
Data Sheet
21
V1.5, 2010-09
SAA-XC866
Functional Description Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of SYSCON0 should not be modified. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software.
Standard Area (RMAP = 0) FFH Module 1 SFRs
SYSCON0.RMAP
rw
Module 2 SFRs
Module n SFRs
......
SFR Data (to/from CPU)
80H Mapped Area (RMAP = 1) FFH Module (n+1) SFRs
Module (n+2) SFRs
Module m SFRs
......
80H Direct Internal Data Memory Address
Figure 8
Address Extension by Mapping
Data Sheet
22
V1.5, 2010-09
SAA-XC866
Functional Description
3.2.2.2
Address Extension by Paging
Address extension is further performed at the module level by paging. With the address extension by mapping, the SAA-XC866 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 9.
SFR Address (from CPU) MOD_PAGE.PAGE
rw
PAGE 0 SFR0 SFR1
......
SFRx
PAGE 1 SFR0 SFR Data (to/from CPU) SFR1
......
SFRy
......
PAGE q SFR0 SFR1
......
SFRz
Module
Figure 9
Data Sheet
Address Extension by Paging
23 V1.5, 2010-09
SAA-XC866
Functional Description In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and finally, the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can: * Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or * Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred)
ST3 ST2 ST1 ST0 STNR value update from CPU PAGE
Figure 10
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The SAA-XC866 supports local address extension for: * * * * Parallel Ports Analog-to-Digital Converter (ADC) Capture/Compare Unit 6 (CCU6) System Control Registers
Data Sheet
24
V1.5, 2010-09
SAA-XC866
Functional Description The page register has the following definition: MOD_PAGE Page Register for module MOD
7 OP w 6 5 STNR w 4 3 0 r 2
Reset Value: 00H
1 PAGE rw 0
Field PAGE
Bits [2:0]
Type Description rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected.
STNR
[5:4]
w
Data Sheet
25
V1.5, 2010-09
SAA-XC866
Functional Description Field OP Bits [7:6] Type Description w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. Reserved Returns 0 if read; should be written with 0.
0
3
r
Data Sheet
26
V1.5, 2010-09
SAA-XC866
Functional Description
3.2.3
Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. Note that access is opened for maximum 32 CCLKs if the "close access" password is not written. If "open access" password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD. PASSWD Password Register
7 6 5 PASS w 4 3 2 PROTECT _S rh
Reset Value: 07H
1 MODE rw 0
Field MODE
Bits [1:0]
Type Description rw Bit Protection Scheme Control bits 00 Scheme Disabled 11 Scheme Enabled (default) Others: Scheme Enabled These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. Bit Protection Signal Status bit This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected bits. Password bits The Bit Protection Scheme only recognizes three patterns. 11000B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits.
PROTECT_S
2
rh
PASS
[7:3]
w
Data Sheet
27
V1.5, 2010-09
SAA-XC866
Functional Description
3.2.4
SAA-XC866 Register Overview
The SFRs of the SAA-XC866 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Table 6 to Table 14, with the addresses of the bitaddressable SFRs appearing in bold typeface. The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 6
Addr
CPU Register Overview
Bit
Reset: 07H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r EA rw 0 r 0 r 0 r SM0 rw SM1 rw DPL7 DPL6 rw rw DPH7 DPH6 rw rw SMOD rw TF1 TR1 rwh rw GATE1 0 rw r
Register Name
7
6
5
4
SP rw
3
2
1
0
RMAP = 0 or 1 SP 81H Stack Pointer Register 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 98H 99H A2H
DPL Reset: 00H Data Pointer Register Low DPH Reset: 00H Data Pointer Register High PCON Power Control Register TCON Timer Control Register TMOD Timer Mode Register TL0 Timer 0 Register Low TL1 Timer 1 Register Low TH0 Timer 0 Register High TH1 Timer 1 Register High Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H
SCON Reset: 00H Serial Channel Control Register SBUF Reset: 00H Serial Data Buffer Register EO Reset: 00H Extended Operation Register IEN0 Reset: 00H Interrupt Enable Register 0 IP Reset: 00H Interrupt Priority Register IPH Reset: 00H Interrupt Priority Register High PSW Reset: 00H Program Status Word Register ACC Accumulator Register Reset: 00H
DPL5 DPL4 DPL3 DPL2 rw rw rw rw DPH5 DPH4 DPH3 DPH2 rw rw rw rw 0 GF1 GF0 r rw rw TF0 TR0 IE1 IT1 rwh rw rwh rw T1M GATE0 0 rw rw r VAL rwh VAL rwh VAL rwh VAL rwh SM2 REN TB8 RB8 rw rw rw rwh VAL rwh TRAP_ 0 EN rw r ET2 rw PT2 rw PT2H rw ES rw PS rw PSH rw ET1 rw PT1 rw PT1H rw EX1 rw PX1 rw PX1H rw OV rwh ACC2 rw EX2 rw
DPL1 DPL0 rw rw DPH1 DPH0 rw rw 0 IDLE r rw IE0 IT0 rwh rw T0M rw
TI rwh
RI rwh
DPSEL 0 rw ET0 rw PT0 rw PT0H rw F1 rwh ACC1 rw ESSC rw EX0 rw PX0 rw PX0H rw P rh ACC0 rw EADC rw
A8H B8H B9H D0H E0H E8H
Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type
IEN1 Reset: 00H Interrupt Enable Register 1
CY AC F0 RS1 RS0 rw rwh rwh rw rw ACC7 ACC6 ACC5 ACC4 ACC3 rw rw rw rw rw ECCIP ECCIP ECCIP ECCIP EXM 3 2 1 0 rw rw rw rw rw
Data Sheet
28
V1.5, 2010-09
SAA-XC866
Functional Description Table 6
Addr
F0H F8H B B Register
CPU Register Overview (cont'd)
Bit
Reset: 00H Bit Field Type Bit Field Type Bit Field Type
Register Name
7
6
5
4
3
2
B2 rw PX2
1
B1 rw PSSC
0
B0 rw PADC
IP1 Reset: 00H Interrupt Priority Register 1 IPH1 Reset: 00H Interrupt Priority Register 1 High
F9H
B7 B6 B5 B4 B3 rw rw rw rw rw PCCIP PCCIP PCCIP PCCIP PXM 3 2 1 0 rw rw rw rw rw PCCIP PCCIP PCCIP PCCIP PXMH 3H 2H 1H 0H rw rw rw rw rw
rw rw rw PX2H PSSCH PADC H rw rw rw
The system control SFRs can be accessed in the standard memory area (RMAP = 0). Table 7
Addr
System Control Register Overview
Bit
Bit Field Type Bit Field Type Bit Field Type Bit Field Type OP w 0 STNR w
Register Name
7
6
5
4
0 r
3
2
1
0
RMAP rw
RMAP = 0 or 1 SYSCON0 Reset: 00H 8FH System Control Register 0 RMAP = 0 SCU_PAGE Reset: 00H BFH Page Register for System Control RMAP = 0, Page 0 MODPISEL Reset: 00H B3H Peripheral Input Select Register B4H IRCON0 Reset: 00H Interrupt Request Register 0 IRCON1 Reset: 00H Interrupt Request Register 1 EXICON0 Reset: 00H External Interrupt Control Register 0 EXICON1 Reset: 00H External Interrupt Control Register 1 NMICON NMI Control Register NMISR NMI Status Register Reset: 00H
0 r
PAGE rwh
B5H
Bit Field Type
B7H BAH BBH
Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type
JTAG JTAG 0 EXINT URRIS TDIS TCKS 0IS r rw rw r rw rw 0 EXINT EXINT EXINT EXINT EXINT EXINT EXINT 6 5 4 3 2 1 0 r rwh rwh rwh rwh rwh rwh rwh 0 ADCS ADCS RIR TIR EIR RC1 RC0 r rwh rwh rwh rwh rwh EXINT3 EXINT2 EXINT1 EXINT0 rw rw rw rw 0 EXINT6 EXINT5 EXINT4 r rw rw rw 0 NMI NMI NMI NMI NMI NMI NMI ECC VDDP VDD OCDS FLASH PLL WDT r rw rw rw rw rw rw rw 0 FNMI ECC r rwh BGSEL rw FNMI VDDP rwh 0 r FNMI FNMI FNMI FNMI VDD OCDS FLASH PLL rwh rwh rwh rwh BREN BRPRE rw rw FNMI WDT rwh R rw
BCH
Reset: 00H
BDH BEH E9H
BCON Reset: 00H Baud Rate Control Register BG Reset: 00H Baud Rate Timer/Reload Register FDCON Reset: 00H Fractional Divider Control Register FDSTEP Reset: 00H Fractional Divider Reload Register FDRES Reset: 00H Fractional Divider Result Register
BGS rw
BR_VALUE rw SYNEN ERRSY EOFSY BRK N N rw rwh rwh rwh STEP rw RESULT rh
NDOV rwh
FDM rw
FDEN rw
EAH EBH
Bit Field Type Bit Field Type
RMAP = 0, Page 1
Data Sheet
29
V1.5, 2010-09
SAA-XC866
Functional Description Table 7
Addr
B3H B4H
System Control Register Overview (cont'd)
Bit
Reset: 01H Bit Field Type Bit Field Type Bit Field Type 0 r
Register Name
ID Identity Register
7
6
5
4
3
2
1
VERID r WS rw SSC _DIS
0
PMCON0 Reset: 00H Power Mode Control Register 0 PMCON1 Reset: 00H Power Mode Control Register 1 OSC_CON OSC Control Register PLL_CON PLL Control Register CMCON Clock Control Register PASSWD Password Register Reset: 08H
B5H
PRODID r WDT WKRS WK RST SEL rwh rwh rw 0 r 0 r NDIV rw OSC PD rw
SD rw T2_DIS rw XPD rw VCO BYP rw
PD rwh CCU _DIS
ADC _DIS
B6H
Bit Field Type Bit Field Type
B7H
Reset: 20H
rw rw rw OSC ORD OSCR SS RES rw rwh rh OSC RESLD LOCK DISC rw rwh CLKREL rh
BAH
Reset: 00H
Bit Field Type Bit Field Type
VCO SEL rw
0 r PASS
BBH
Reset: 07H
BCH BDH BEH
FEAL Reset: 00H Flash Error Address Register Low FEAH Reset: 00H Flash Error Address Register High COCON Reset: 00H Clock Output Control Register MISC_CON Reset: 00H Miscellaneous Control Register
Bit Field Type Bit Field Type Bit Field Type 0 r
rw PROTE MODE CT_S w rh rw ECCERRADDR[7:0] rh ECCERRADDR[15:8] rh TLEN COUT COREL S rw rw rw 0 r ADDRH rw DFLAS HEN rwh
E9H
Bit Field Type
RMAP = 0, Page 3 B3H XADDRH Reset: F0H Bit Field On-Chip XRAM Address Higher Order Type
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Table 8
Addr
WDT Register Overview
Bit
Bit Field Type
Register Name
7
0 r
6
5
WINB EN rw
4
WDT PR rh
3
0
2
WDT EN rw
1
WDT RS rwh
0
WDT IN rw
RMAP = 1 WDTCON Reset: 00H BBH Watchdog Timer Control Register BCH BDH WDTREL Reset: 00H Watchdog Timer Reload Register WDTWINB Reset: 00H Watchdog Window-Boundary Count Register WDTL Reset: 00H Watchdog Timer Register Low WDTH Reset: 00H Watchdog Timer Register High
Bit Field Type Bit Field Type Bit Field Type Bit Field Type
r WDTREL rw WDTWINB rw WDT[7:0] rh WDT[15:8] rh
BEH BFH
Data Sheet
30
V1.5, 2010-09
SAA-XC866
Functional Description The Port SFRs can be accessed in the standard memory area (RMAP = 0). Table 9
Addr
Port Register Overview
Bit
Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type P7 rwh P7 rw P7 rwh P7 rw P7 rwh P7 rw 0 r 0 r P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw 0 r 0 r P7 rw P7 rw P7 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw
Register Name
7
OP w 0 r 0 r
6
5
STNR w P5 rwh P5 rw P5 rwh P5 rw P5 rwh P5 rw P5 rwh P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw
4
3
0 r P3 rwh P3 rw 0 r 0 r P3 rwh P3 rw P3 rwh P3 rw P3 rw P3 rw 0 r 0 r P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw 0 r 0 r P3 rw
2
1
PAGE rwh
0
RMAP = 0 PORT_PAGE Reset: 00H B2H Page Register for PORT RMAP = 0, Page 0 80H 86H 90H 91H A0H A1H B0H B1H P0_DATA P0 Data Register P0_DIR P0 Direction Register P1_DATA P1 Data Register P1_DIR P1 Direction Register P2_DATA P2 Data Register P2_DIR P2 Direction Register P3_DATA P3 Data Register P3_DIR P3 Direction Register Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H
P4 rwh P4 rw
P2 rwh P2 rw
P6 rwh P6 rw P6 rwh P6 rw P6 rwh P6 rw
P1 rwh P1 rw P1 rwh P1 rw P1 rwh P1 rw P1 rwh P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw
P0 rwh P0 rw P0 rwh P0 rw P0 rwh P0 rw P0 rwh P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw
P4 rwh P4 rw P4 rwh P4 rw P4 rw P4 rw
P2 rwh P2 rw P2 rwh P2 rw P2 rw P2 rw
RMAP = 0, Page 1 P0_PUDSEL Reset: FFH 80H P0 Pull-Up/Pull-Down Select Register 86H 90H 91H A0H A1H B0H B1H
Bit Field Type P0_PUDEN Reset: C4H Bit Field P0 Pull-Up/Pull-Down Enable Register Type P1_PUDSEL Reset: FFH Bit Field P1 Pull-Up/Pull-Down Select Register Type P1_PUDEN Reset: FFH Bit Field P1 Pull-Up/Pull-Down Enable Register Type P2_PUDSEL Reset: FFH Bit Field P2 Pull-Up/Pull-Down Select Register Type P2_PUDEN Reset: 00H Bit Field P2 Pull-Up/Pull-Down Enable Register Type P3_PUDSEL Reset: BFH Bit Field P3 Pull-Up/Pull-Down Select Register Type P3_PUDEN Reset: 40H Bit Field P3 Pull-Up/Pull-Down Enable Register Type P0_ALTSEL0 Reset: 00H P0 Alternate Select 0 Register P0_ALTSEL1 Reset: 00H P0 Alternate Select 1 Register P1_ALTSEL0 Reset: 00H P1 Alternate Select 0 Register P1_ALTSEL1 Reset: 00H P1 Alternate Select 1 Register P3_ALTSEL0 Reset: 00H P3 Alternate Select 0 Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type
P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw
P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw
RMAP = 0, Page 2 80H 86H 90H 91H B0H
P4 rw
P2 rw
Data Sheet
31
V1.5, 2010-09
SAA-XC866
Functional Description Table 9
Addr
B1H
Port Register Overview (cont'd)
Bit
Bit Field Type Bit Field Type Bit Field Type Bit Field Type P7 rw P7 rw
Register Name
P3_ALTSEL1 Reset: 00H P3 Alternate Select 1 Register
7
P7 rw 0 r
6
P6 rw
5
P5 rw P5 rw P5 rw P5 rw
4
P4 rw P4 rw
3
P3 rw P3 rw 0 r P3 rw
2
P2 rw P2 rw
1
P1 rw P1 rw P1 rw P1 rw
0
P0 rw P0 rw P0 rw P0 rw
RMAP = 0, Page 3 P0_OD Reset: 00H 80H P0 Open Drain Control Register 90H B0H P1_OD Reset: 00H P1 Open Drain Control Register P3_OD Reset: 00H P3 Open Drain Control Register
P6 rw P6 rw
P4 rw
P2 rw
The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Table 10
Addr
ADC Register Overview
Bit
Reset: 00H Bit Field Type Bit Field Type Bit Field Type
Register Name
7
OP w ANON rw 0
6
5
STNR w
4
3
0 r
2
1
PAGE rwh 0 r
0
RMAP = 0 ADC_PAGE D1H Page Register for ADC RMAP = 0, Page 0 CAH ADC_GLOBCTR Global Control Register CBH ADC_GLOBSTR Global Status Register
Reset: 30H Reset: 00H
DW rw
CTC rw CHNR
CCH CDH CEH CFH
ADC_PRAR Reset: 00H Priority and Arbitration Register ADC_LCBR Reset: B7H Limit Check Boundary Register ADC_INPCR0 Input Class Register 0 Reset: 00H
Bit Field Type Bit Field Type Bit Field Type Bit Field Type
r ASEN1 ASEN0 0 rw rw r BOUND1 rw
ADC_ETRCR Reset: 00H External Trigger Control Register
SYNEN SYNEN 1 0 rw rw 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw
SAM BUSY PLE rh r rh rh ARBM CSM1 PRIO1 CSM0 PRIO0 rw rw rw rw rw BOUND0 rw STC rw ETRSEL1 ETRSEL0 rw 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw
0
RMAP = 0, Page 1 ADC_CHCTR0 Reset: 00H CAH Channel Control Register 0 CBH CCH CDH CEH CFH D2H D3H ADC_CHCTR1 Reset: 00H Channel Control Register 1 ADC_CHCTR2 Reset: 00H Channel Control Register 2 ADC_CHCTR3 Reset: 00H Channel Control Register 3 ADC_CHCTR4 Reset: 00H Channel Control Register 4 ADC_CHCTR5 Reset: 00H Channel Control Register 5 ADC_CHCTR6 Reset: 00H Channel Control Register 6 ADC_CHCTR7 Reset: 00H Channel Control Register 7
Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type
RMAP = 0, Page 2
Data Sheet
32
V1.5, 2010-09
SAA-XC866
Functional Description Table 10
Addr
CAH CBH CCH CDH CEH CFH D2H D3H
ADC Register Overview (cont'd)
Bit
Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Reset: 00H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type VFCTR WFR rw rw 0 r 0 r 0 r 0 r 0 r RESULT[2:0] rh RESULT[2:0] rh RESULT[2:0] rh RESULT[2:0] rh RESULT[1:0] rh 0 r
Register Name
ADC_RESR0L Result Register 0 Low ADC_RESR0H Result Register 0 High ADC_RESR1L Result Register 1 Low ADC_RESR1H Result Register 1 High ADC_RESR2L Result Register 2 Low ADC_RESR2H Result Register 2 High ADC_RESR3L Result Register 3 Low ADC_RESR3H Result Register 3 High
7
6
5
0 r
4
3
2
1
CHNR rh
0
RESULT[1:0] rh
RESULT[1:0] rh
0 r
RESULT[1:0] rh
0 r
VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[10:3] rh VF DRC rh rh RESULT[10:3] rh VF DRC rh rh RESULT[10:3] rh VF DRC rh rh RESULT[10:3] rh IEN rw IEN rw IEN rw IEN rw VFC3 w 0 r 0 r 0 r 0 r VFC2 w
CHNR rh
CHNR rh
CHNR rh
RMAP = 0, Page 3 ADC_RESRA0L Reset: 00H CAH Result Register 0, View A Low CBH CCH CDH CEH CFH D2H D3H ADC_RESRA0H Reset: 00H Result Register 0, View A High ADC_RESRA1L Reset: 00H Result Register 1, View A Low ADC_RESRA1H Reset: 00H Result Register 1, View A High ADC_RESRA2L Reset: 00H Result Register 2, View A Low ADC_RESRA2H Reset: 00H Result Register 2, View A High ADC_RESRA3L Reset: 00H Result Register 3, View A Low ADC_RESRA3H Reset: 00H Result Register 3, View A High
CHNR rh
CHNR rh
CHNR rh
CHNR rh
RMAP = 0, Page 4 ADC_RCR0 Reset: 00H CAH Result Control Register 0 CBH ADC_RCR1 Reset: 00H Result Control Register 1 ADC_RCR2 Reset: 00H Result Control Register 2 ADC_RCR3 Reset: 00H Result Control Register 3 ADC_VFCR Reset: 00H Valid Flag Clear Register
DRCT R rw DRCT R rw DRCT R rw DRCT R rw VFC0 w
Bit Field Type Bit Field Type Bit Field Type Bit Field Type
VFCTR WFR rw rw
CCH
VFCTR WFR rw rw VFCTR WFR rw rw
CDH
CEH
VFC1 w
RMAP = 0, Page 5
Data Sheet
33
V1.5, 2010-09
SAA-XC866
Functional Description Table 10
Addr
CAH
ADC Register Overview (cont'd)
Bit
Bit Field Type Bit Field Type
Register Name
ADC_CHINFR Reset: 00H Channel Interrupt Flag Register ADC_CHINCR Reset: 00H Channel Interrupt Clear Register ADC_CHINSR Reset: 00H Channel Interrupt Set Register ADC_CHINPR Reset: 00H Channel Interrupt Node Pointer Register ADC_EVINFR Reset: 00H Event Interrupt Flag Register ADC_EVINCR Reset: 00H Event Interrupt Clear Flag Register ADC_EVINSR Reset: 00H Event Interrupt Set Flag Register ADC_EVINPR Reset: 00H Event Interrupt Node Pointer Register
7
6
5
4
3
2
1
0
CBH
CCH
Bit Field Type Bit Field Type Bit Field Type Bit Field Type
CDH
CHINF CHINF CHINF CHINF CHINF 7 6 5 4 3 rh rh rh rh rh CHINC CHINC CHINC CHINC CHINC 7 6 5 4 3 w w w w w CHINS CHINS CHINS CHINS CHINS 7 6 5 4 3 w w w w w CHINP CHINP CHINP CHINP CHINP 7 6 5 4 3 rw rw rw rw rw EVINF EVINF EVINF EVINF 7 6 5 4 rh rh rh rh EVINC EVINC EVINC EVINC 7 6 5 4 w w w w EVINS EVINS EVINS EVINS 7 6 5 4 w w w w EVINP EVINP EVINP EVINP 7 6 5 4 rw rw rw rw CH7 rwh CHP7 rwh Rsv r CEV w Rsv r EXTR rh EXTR rh EXTR w CH6 rwh CHP6 rwh LDEV w TREV w 0 r ENSI rh ENSI rh ENSI w CH5 rwh CHP5 CH4 rwh CHP4 0 r 0 r 0 r 0 r
CHINF CHINF CHINF 2 1 0 rh rh rh CHINC CHINC CHINC 2 1 0 w w w CHINS CHINS CHINS 2 1 0 w w w CHINP CHINP CHINP 2 1 0 rw rw rw EVINF EVINF 1 0 rh rh EVINC EVINC 1 0 w w EVINS EVINS 1 0 w w EVINP EVINP 1 0 rw rw 0 r 0
CEH
CFH
D2H
Bit Field Type
D3H
Bit Field Type
RMAP = 0, Page 6 CAH ADC_CRCR1 Reset: 00H Bit Field Conversion Request Control Register 1 Type ADC_CRPR1 Reset: 00H Bit Field CBH Conversion Request Pending Register 1 Type CCH ADC_CRMR1 Reset: 00H Conversion Request Mode Register 1 ADC_QMR0 Reset: 00H Queue Mode Register 0 ADC_QSR0 Reset: 20H Queue Status Register 0 ADC_Q0R0 Queue 0 Register 0 Reset: 00H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type
CDH CEH CFH D2H D2H
ADC_QBUR0 Reset: 00H Queue Backup Register 0 ADC_QINR0 Queue Input Register 0 Reset: 00H
rwh rwh r CLR SCAN ENSI ENTR ENGT PND w rw rw rw rw FLUSH CLRV TRMD ENTR ENGT w w rw rw rw EMPTY EV 0 rh rh r RF V 0 REQCHNR rh rh r rh RF V 0 REQCHNR rh rh r rh RF 0 REQCHNR w r w
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Table 11
Addr
C0H
Timer 2 Register Overview
Bit
Bit Field Type
Register Name
T2_T2CON Reset: 00H Timer 2 Control Register
7
TF2 rwh
6
EXF2 rwh
5
0 r
4
3
EXEN2 rw
2
TR2 rwh
1
0 r
0
CP/ RL2 rw
Data Sheet
34
V1.5, 2010-09
SAA-XC866
Functional Description Table 11
C1H
Timer 2 Register Overview (cont'd)
Reset: 00H Bit Field Type T2 T2 EDGE PREN REGS RHEN SEL rw rw rw rw RC2[7:0] rwh RC2[15:8] rwh THL2[7:0] rwh THL2[15:8] rwh T2PRE rw DCEN rw
T2_T2MOD Timer 2 Mode Register
C2H C3H C4H C5H
Bit Field Type T2_RC2H Reset: 00H Bit Field Timer 2 Reload/Capture Register High Type T2_T2L Reset: 00H Bit Field Timer 2 Register Low Type T2_T2H Reset: 00H Bit Field Timer 2 Register High Type
T2_RC2L Reset: 00H Timer 2 Reload/Capture Register Low
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 12
Addr
CCU6 Register Overview
Bit
Bit Field Type
Register Name
7
OP w
6
5
STNR w
4
3
0 r
2
1
PAGE rwh
0
RMAP = 0 CCU6_PAGE Reset: 00H A3H Page Register for CCU6
RMAP = 0, Page 0 CCU6_CC63SRL Reset: 00H Bit Field 9AH Capture/Compare Shadow Register for Channel CC63 Low Type CCU6_CC63SRH Reset: 00H Bit Field 9BH Capture/Compare Shadow Register for Channel CC63 High Type 9CH CCU6_TCTR4L Reset: 00H Timer Control Register 4 Low CCU6_TCTR4H Reset: 00H Timer Control Register 4 High CCU6_MCMOUTSL Reset: 00H Multi-Channel Mode Output Shadow Register Low CCU6_MCMOUTSH Reset: 00H Multi-Channel Mode Output Shadow Register High CCU6_ISRL Reset: 00H Capture/Compare Interrupt Status Reset Register Low CCU6_ISRH Reset: 00H Capture/Compare Interrupt Status Reset Register High CCU6_CMPMODIFL Reset: 00H Compare State Modification Register Low CCU6_CMPMODIFH Reset: 00H Compare State Modification Register High Bit Field Type Bit Field Type 9EH Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field T12 STD w T13 STD w STRM CM w STRHP w T12 STR w T13 STR w 0 r 0 r 0 r
CC63SL rw CC63SH rw DTRES T12 RES w w T13 RES w MCMPS rw CURHS rw EXPHS rw RCC60 R w RT13 CM w MCC60 S w MCC60 R w T12RS T12RR w w T13RS T13RR w w
9DH
0 r
9FH
A4H
A5H
A6H
A7H
FAH
Type CCU6_CC60SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC60 Low Type
RT12P RT12O RCC62 RCC62 RCC61 RCC61 RCC60 M M F R F R F w w w w w w w RSTR RIDLE RWHE RCHE 0 RTRPF RT13 PM w w w w r w w 0 MCC63 0 MCC62 MCC61 S S S r w r w w 0 MCC63 0 MCC62 MCC61 R R R w w r w r CC60SL rwh
Data Sheet
35
V1.5, 2010-09
SAA-XC866
Functional Description Table 12
Addr
FBH
CCU6 Register Overview (cont'd)
Bit 7 6 5 4 3 2 1 0
CC60SH rwh CC61SL rwh CC61SH rwh CC62SL rwh CC62SH rwh CC63VL rh CC63VH rh T12PVL rwh T12PVH rwh T13PVL rwh T13PVH rwh DTM rw 0 r CTM rw 0 r DTR2 rh CDIR rh DTR1 rh STE12 rh STE13 rh DTR0 rh 0 DTE2 rw DTE1 rw T12CLK rw T13CLK rw DTE0 rw
Register Name
FCH
CCU6_CC60SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC60 High Type CCU6_CC61SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC61 Low Type CCU6_CC61SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC61 High Type CCU6_CC62SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC62 Low Type
FDH
FEH
CCU6_CC62SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC62 High Type RMAP = 0, Page 1 CCU6_CC63RL Reset: 00H Bit Field 9AH Capture/Compare Register for Channel CC63 Low Type CCU6_CC63RH Reset: 00H Bit Field 9BH Capture/Compare Register for Channel CC63 High Type FFH 9CH 9DH 9EH 9FH A4H CCU6_T12PRL Reset: 00H Timer T12 Period Register Low CCU6_T12PRH Reset: 00H Timer T12 Period Register High CCU6_T13PRL Reset: 00H Timer T13 Period Register Low CCU6_T13PRH Reset: 00H Timer T13 Period Register High CCU6_T12DTCL Reset: 00H Dead-Time Control Register for Timer T12 Low CCU6_T12DTCH Reset: 00H Dead-Time Control Register for Timer T12 High CCU6_TCTR0L Reset: 00H Timer Control Register 0 Low CCU6_TCTR0H Reset: 00H Timer Control Register 0 High Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field
A5H
A6H
A7H
FAH
Type CCU6_CC60RL Reset: 00H Bit Field Capture/Compare Register for Channel CC60 Low Type CCU6_CC60RH Reset: 00H Bit Field Capture/Compare Register for Channel CC60 High Type CCU6_CC61RL Reset: 00H Bit Field Capture/Compare Register for Channel CC61 Low Type
r T12 PRE rh rw T13R T13 PRE rw rh CC60VL T12R rh CC60VH rh CC61VL rh
FBH
FCH
Data Sheet
36
V1.5, 2010-09
SAA-XC866
Functional Description Table 12
Addr
FDH
CCU6 Register Overview (cont'd)
Bit 7 6 5 4 3 2 1 0
CC61VH rh CC62VL rh CC62VH rh MSEL61 rw DBYP HSYNC MSEL60 rw MSEL62
Register Name
FEH
CCU6_CC61RH Reset: 00H Bit Field Capture/Compare Register for Channel CC61 High Type CCU6_CC62RL Reset: 00H Bit Field Capture/Compare Register for Channel CC62 Low Type CCU6_CC62RH Reset: 00H Bit Field Capture/Compare Register for Channel CC62 High Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field
FFH
RMAP = 0, Page 2 CCU6_T12MSELL Reset: 00H 9AH T12 Capture/Compare Mode Select Register Low 9BH CCU6_T12MSELH Reset: 00H T12 Capture/Compare Mode Select Register High CCU6_IENL Reset: 00H Capture/Compare Interrupt Enable Register Low CCU6_IENH Reset: 00H Capture/Compare Interrupt Enable Register High CCU6_INPL Reset: 40H Capture/Compare Interrupt Node Pointer Register Low CCU6_INPH Reset: 39H Capture/Compare Interrupt Node Pointer Register High
9CH
9DH
9EH
rw rw rw ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC PM OM 62F 62R 61F 61R 60F 60R rw rw rw rw rw rw rw rw ENSTR EN EN EN 0 EN ENT13 ENT13 IDLE WHE CHE TRPF PM CM rw rw rw rw r rw rw rw INPCHE INPCC62 INPCC61 INPCC60 rw 0 rw INPT13 rw INPT12 rw INPERR
9FH
A4H
Type CCU6_ISSL Reset: 00H Bit Field Capture/Compare Interrupt Status Set Register Low Type CCU6_ISSH Reset: 00H Bit Field Capture/Compare Interrupt Status Set Register High Type CCU6_PSLR Reset: 00H Bit Field Passive State Level Register Type CCU6_MCMCTR Reset: 00H Multi-Channel Mode Control Register CCU6_TCTR2L Reset: 00H Timer Control Register 2 Low CCU6_TCTR2H Reset: 00H Timer Control Register 2 High CCU6_MODCTRL Reset: 00H Modulation Control Register Low CCU6_MODCTRH Reset: 00H Modulation Control Register High CCU6_TRPCTRL Reset: 00H Trap Control Register Low Bit Field Type Bit Field Type
A5H
A6H A7H FAH
FBH FCH
Bit Field Type Bit Field Type Bit Field Type Bit Field Type
r rw rw rw ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60 M M F R F R F R w w w w w w w w SSTR SIDLE SWHE SCHE SWHC STRPF ST13 ST13 PM CM w w w w w w w w PSL63 0 PSL rwh r rwh 0 SWSYN 0 SWSEL r rw r rw 0 T13TED T13TEC T13 T12 SSC SSC rw rw r rw rw 0 T13RSEL T12RSEL r rw rw MC MEN rw ECT13 O rw 0 r 0 r 0 r T12MODEN rw T13MODEN rw TRPM2 TRPM1 TRPM0 rw rw rw
FDH
FEH
Data Sheet
37
V1.5, 2010-09
SAA-XC866
Functional Description Table 12
Addr
FFH
CCU6 Register Overview (cont'd)
Bit
Bit Field Type
Register Name
CCU6_TRPCTRH Reset: 00H Trap Control Register High
7
6
5
4
3
rw
2
1
0
TRPPE TRPEN N 13 rw rw 0 r 0 R rh CURH
TRPEN
RMAP = 0, Page 3 CCU6_MCMOUTL Reset: 00H 9AH Multi-Channel Mode Output Register Low 9BH CCU6_MCMOUTH Reset: 00H Multi-Channel Mode Output Register High CCU6_ISL Reset: 00H Capture/Compare Interrupt Status Register Low CCU6_ISH Reset: 00H Capture/Compare Interrupt Status Register High CCU6_PISEL0L Reset: 00H Port Input Select Register 0 Low CCU6_PISEL0H Reset: 00H Port Input Select Register 0 High CCU6_PISEL2 Reset: 00H Port Input Select Register 2 CCU6_T12L Reset: 00H Timer T12 Counter Register Low CCU6_T12H Reset: 00H Timer T12 Counter Register High CCU6_T13L Reset: 00H Timer T13 Counter Register Low CCU6_T13H Reset: 00H Timer T13 Counter Register High CCU6_CMPSTATL Reset: 00H Compare State Register Low CCU6_CMPSTATH Reset: 00H Compare State Register High
Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type
MCMP rh EXPH
9CH
9DH
rh r rh T12PM T12OM ICC62F ICC62 ICC61F ICC61 ICC60F ICC60 R R R rh rh rh rh rh rh rh rh STR IDLE WHE CHE TRPS TRPF T13PM T13CM rh rh ISTRP rw IST12HR rw rh rh ISCC62 rw ISPOS2 rw 0 r rh rh ISCC61 rw ISPOS1 rw rh rh ISCC60 rw ISPOS0 rw IST13HR rw
9EH 9FH
A4H FAH FBH FCH FDH FEH
Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r CC63 ST rh
T12CVL rwh T12CVH rwh T13CVL rwh T13CVH rwh CCPO CCPO CCPO S2 S1 S0 rh rh rh CC62 PS rwh COUT 61PS rwh
CC62 ST rh CC61 PS rwh
CC61 ST rh COUT 60PS rwh
CC60 ST rh CC60 PS rwh
FFH
Bit Field Type
T13IM COUT COUT 63PS 62PS rwh rwh rwh
The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 13
Addr
SSC Register Overview
Bit
Bit Field Type Bit Field Type Bit Field Type
Register Name
7
6
5
0 r PH rw 0 r
4
3
2
CIS rw
1
SIS rw BM rw BC rh
0
MIS rw
RMAP = 0 SSC_PISEL Reset: 00H A9H Port Input Select Register AAH SSC_CONL Control Register Low Programming Mode Operating Mode Reset: 00H
LB rw
PO rw
HB rw
Data Sheet
38
V1.5, 2010-09
SAA-XC866
Functional Description Table 13
ABH
SSC Register Overview
Reset: 00H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type EN rw EN rw MS rw MS rw 0 r 0 r AREN BEN PEN rw PE rwh REN rw RE rwh TEN rw TE rwh rw rw BSY BE rh rwh TB_VALUE rw RB_VALUE rh BR_VALUE[7:0] rw BR_VALUE[15:8] rw
SSC_CONH Control Register High Programming Mode Operating Mode
ACH ADH AEH AFH
SSC_TBL Reset: 00H Transmitter Buffer Register Low SSC_RBL Reset: 00H Receiver Buffer Register Low SSC_BRL Reset: 00H Baudrate Timer Reload Register Low SSC_BRH Reset: 00H Baudrate Timer Reload Register High
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). Table 14
Addr
OCDS Register Overview
Bit
Bit Field Type
Register Name
7
6
5
4
3
2
1
0
RMAP = 1 MMCR2 Reset: 0UH E9H Monitor Mode Control Register 2 F1H MMCR Reset: 00H Monitor Mode Control Register MMSR Reset: 00H Monitor Mode Status Register MMBPCR Reset: 00H BreakPoints Control Register
Bit Field Type Bit Field Type
F2H
F3H
Bit Field Type
EXBC_ EXBC MBCO MBCO MMEP P N_P N _P w rw w rwh w MEXIT MEXIT MSTEP MSTEP MRAM _P _P S_P w rwh w rw w MBCA MBCIN EXBF SWBF HWB3 M F rw rh rwh rwh rwh SWBC HWB3C HWB2C rw rw 0 r rw
MMEP MMOD JENA E rwh rh rh MRAM TRF RRF S rwh rh rh HWB2 HWB1 HWB0 F F F rwh rwh rwh HWB1 HWB0C C
F4H
F5H
MMICR Reset: 00H Bit Field Monitor Mode Interrupt Control Register Type MMDR Reset: 00H Bit Field Monitor Mode Data Register Receive Type Transmit Bit Field Type
DVECT DRETR rwh rwh
rw rw MMUIE MMUIE RRIE_ RRIE _P P w rw w rw MMRR rh MMTR w BPSEL _P w HWBPxx rw
F6H
HWBPSR Reset: 00H Bit Field Hardware Breakpoints Select Register Type HWBPDR Reset: 00H Hardware Breakpoints Data Register Bit Field Type
0 r
BPSEL rw
F7H
Data Sheet
39
V1.5, 2010-09
SAA-XC866
Functional Description
3.3
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The sectorization of the Flash memory allows each sector to be erased independently. Features * * * * * * * * * * * * * In-System Programming (ISP) via UART In-Application Programming (IAP) Error Correction Code (ECC) for dynamic correction of single-bit errors Background program and erase operations for CPU load minimization Support for aborting erase operation Minimum program width1) of 32-byte for D-Flash and 32-byte for P-Flash 1-sector minimum erase width 1-byte read access Flash is delivered in erased state (read all zeros) Operating supply voltage: 2.5 V 7.5 % Read access time: 3 x tCCLK = 112.5 ns2) Program time: 209440 / fSYS = 2.6 ms3) Erase time: 8175360 / fSYS = 102 ms3)
1)
P-Flash: 32-byte wordline can only be programmed once, i.e., one gate disturb allowed. D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed.
2) 3)
fsys = 80 MHz 7.5% (fCCLK = 26.7 MHz 7.5 %) is the maximum frequency range for Flash read access. fsys = 80 MHz 7.5% is the only frequency range for Flash programming and erasing. fsysmin is used for
obtaining the worst case timing.
Data Sheet
40
V1.5, 2010-09
SAA-XC866
Functional Description Table 15 shows the Flash data retention and endurance targets. Table 15 Retention Flash Data Retention and Endurance Endurance1) TA=- 40 to 125 C Program Flash 20 years 20 years 20 years Data Flash 20 years 5 years 2 years 2 years
1)
Size TA= 125 to 140 C
Remarks
1,000 cycles 1,000 cycles 1,000 cycles
up to 16 Kbytes2) up to 8 Kbytes2) up to 4 Kbytes2)
for 16-Kbyte Variant for 8-Kbyte Variant for 4-Kbyte Variant 1 Kbytes 256 bytes 128 bytes 32 bytes
1,000 cycles3) 10,000 cycles3) 70,000 cycles3) 100,000 cycles3)
4 Kbytes 1 Kbyte 512 bytes 128 bytes
One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance data specified in Table 15 is valid only if the following conditions are fulfilled: - the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles. - the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles. - the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles. If no Flash is used for data, the Program Flash size can be up to the maximum Flash size available in the device variant. Having more Data Flash will mean less Flash is available for Program Flash. For TA=125 to 140C, refers to programming of second 8 bytes (bytes 8 to 15) per WL
2)
3)
Data Sheet
41
V1.5, 2010-09
SAA-XC866
Functional Description
3.3.1
Flash Bank Sectorization
The SAA-XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of embedded Flash memory. These Flash memory sizes are made up of two or four 4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash (P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization shown in Figure 11. Both types can be used for code and data storage. The label "Data" neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage. It is used to distinguish the different Flash bank sectorizations.
Sector 2: 128-byte Sector 1: 128-byte
Sector 9: Sector 8: Sector 7: Sector 6:
128-byte 128-byte 128-byte 128-byte
Sector 5: 256-byte Sector 4: 256-byte Sector 3: 512-byte Sector 0: 3.75-Kbyte Sector 2: 512-byte Sector 1: 1-Kbyte
Sector 0: 1-Kbyte P-Flash D-Flash
Figure 11
Flash Bank Sectorization
The internal structure of each Flash bank represents a sector architecture for flexible erase capability. The minimum erase width is always a complete sector, and sectors can be erased separately or in parallel. Contrary to standard EPROMs, erased Flash memory cells contain 0s. The D-Flash bank is divided into more physical sectors for extended erasing and reprogramming capability; even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements.
Data Sheet
42
V1.5, 2010-09
SAA-XC866
Functional Description
3.3.2
Flash Programming Width
For the P-Flash banks, a programmed wordline (WL) must be erased before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL. For the D-Flash bank, the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to program the same WL, for example, with 16 bytes of data in two times (see Figure 12).
32 bytes (1 WL) 0000 ..... 0000 H 0000 ..... 0000 H
Program 1
16 bytes 0000 ..... 0000 H
16 bytes 1111 ..... 1111 H
0000 ..... 0000 H
1111 ..... 1111 H
Program 2
1111 ..... 0000 H
0000 ..... 0000 H
1111 ..... 0000 H
1111 ..... 1111 H
Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0.
Flash memory cells
32-byte write buffers
Figure 12
D-Flash Programming
Note: When programming a D-Flash WL the second time, the previously programmed Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain its original contents and to prevent "over-programming".
Data Sheet
43
V1.5, 2010-09
SAA-XC866
Functional Description
3.4
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC866 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and determining the interrupt source.
3.4.1
Interrupt Source
Figure 13 to Figure 17 give a general overview of the interrupt sources and illustrates the request and control flags.
WDT Overflow
FNMIWDT NMIISR.0 NMIWDT NMICON.0
PLL Loss of Lock
FNMIPLL NMIISR.1 NMIPLL NMICON.1
Flash Operation Complete
FNMIFLASH NMIISR.2 NMIFLASH >=1 Non Maskable Interrupt
VDD Pre-Warning
FNMIVDD NMIISR.4 NMIVDD NMICON.4
0073
H
VDDP Pre-Warning
FNMIVDDP NMIISR.5 NMIVDDP NMICON.5
Flash ECC Error
FNMIECC NMIISR.6 NMIECC NMICON.6
Figure 13
Non-Maskable Interrupt Request Sources
Data Sheet
44
V1.5, 2010-09
SAA-XC866
Functional Description
Highest
Timer 0 Overflow
TF0 TCON.5 ET0 IEN0.1 000B H IP.1/ IPH.1
Lowest Priority Level
Timer 1 Overflow
TF1 TCON.7 ET1 IEN0.3 001B H IP.3/ IPH.3
UART Receive UART Transmit
RI SCON.0 TI SCON.1 >=1 ES IEN0.4 0023 H IP.4/ IPH.4
P o l l i n g S e q u e n c e
EXINT0
IE0 TCON.1 IT0 TCON.0 EX0 IEN0.0 0003 H IP.0/ IPH.0
EINT0
IRCON0.0
EXINT0 EXICON0.0/1
EXINT1
IE1 TCON.3 IT1 TCON.2 EX1 IEN0.2 0013 H IP.2/ IPH.2
EINT1
IRCON0.1
EXINT1 EXICON0.2/3
EA IEN0.7
Bit-addressable Request flag is cleared by hardware
Figure 14
Interrupt Request Sources (Part 1)
Data Sheet
45
V1.5, 2010-09
SAA-XC866
Functional Description
Timer 2 Overflow
TF2
T2_T2CON.7
Highest
T2EX
EXF2
EXEN2 T2_T2CON.6 EDGES EL T2MOD.5 T2_T2CON.3
ET2 IEN0.5 >=1
002B
Lowest Priority Level
H IP.5/ IPH.5
Normal Divider Overflow
NDOV FDCON.2
End of Synch Byte Synch Byte Error
EOFSYN
FDCON.4
>=1
FDCON.6 SYNEN FDCON.6
ERRSYN
FDCON.5
EINT2
EXINT2 IRCON0.2
EX2 IEN1.2
0043
H IP1.2/ IPH1.2
P o l l i n g S e q u e n c e
EXINT2 EXICON0.4/5
EINT3
EXINT3 IRCON0.3
EXINT3 EXICON0.6/7
EINT4
EXINT4 IRCON0.4
EXM
EXINT4 EXICON1.0/1
004B
H
>=1
IEN1.3
IP1.3/ IPH1.3
EINT5
EXINT5 IRCON0.5
EXINT5 EXICON1.2/3
EA
EINT6
EXINT6 IRCON0.6
IEN0.7
Bit-addressable Request flag is cleared by hardware
EXINT6 EXICON1.4/5
Bit-addressable Request flag is cleared by hardware
Figure 15
Interrupt Request Sources (Part 2)
Data Sheet
46
V1.5, 2010-09
SAA-XC866
Functional Description
Highest
ADC Service Request 0 ADC Service Request 1 ADCSRC0
IRCON1.3
>=1 EADC IEN1.0 0033 H IP1.0/ IPH1.0
ADCSRC1
IRCON1.4
Lowest Priority Level
SSC Error
EIR
IRCON1.0
SSC Transmit
TIR
IRCON1.1
>=1 ESSC IEN1.1 003B H IP1.1/ IPH1.1
SSC Receive
RIR
IRCON1.2
CCU6 Node 0
CCU6SR0
IRCON3.0
P o l l i n g S e q u e n c e
ECCIP0 IEN1.4
0053
H
IP1.4/ IPH1.4
CCU6 Node 1
CCU6SR1
IRCON3.4
ECCIP1 IEN1.5
005B
H
IP1.5/ IPH1.5
CCU6 Node 2
CCU6SR2
IRCON4.0
ECCIP2 IEN1.6
0063
H
IP1.6/ IPH1.6
CCU6 Node 3
CCU6SR3
IRCON4.4
ECCIP3 IEN1.7
006B
H
IP1.7/ IPH1.7
EA IEN0.7 Bit-addressable Request flag is cleared by hardware
Figure 16
Interrupt Request Sources (Part 3)
Data Sheet
47
V1.5, 2010-09
SAA-XC866
Functional Description
ICC60R CC60 ISL.0 ICC60F ISL.1 ICC61R CC61 ISL.2 ICC61F ISL.3 ICC62R CC62 ISL.4 ICC62F ISL.5 T12 One match T12 Period match T13 Compare match T13 Period match T12OM ISL.6 T12PM ISL.7 T13CM ISH.0 T13PM ISH.1 CTRAP TRPF ISH.2 Wrong Hall Event Correct Hall Event Multi-Channel Shadow Transfer WHE ISH.5 CHE ISH.4 STR ISH.7 ENSTR IENH.7 INPL.7 INPL.6 ENCHE IENH.4 >=1 ENWHE IENH.5 INPH.1 INPH.0 ENTRPF IENH.2 >=1 ENT13PM IENH.1 INPH.5 INPH.4 ENT13CM IENH.0 >=1 ENT12PM IENL.7 INPH.3 INPH.2 ENT12OM IENL.6 >=1 ENCC62F IENL.5 INPL.5 INPL.4 ENCC62R IENL.4 >=1 ENCC61F IENL.3 INPL.3 INPL.2 ENCC61R IENL.2 >=1 ENCC60F IENL.1 INPL.1 INPL.0 ENCC60R IENL.0 >=1
CCU6 Interrupt node 0 CCU6 Interrupt node 1 CCU6 Interrupt node 2 CCU6 Interrupt node 3
Figure 17
Interrupt Request Sources (Part 4)
Data Sheet
48
V1.5, 2010-09
SAA-XC866
Functional Description
3.4.2
Interrupt Source and Vector
Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the SAA-XC866 interrupt sources to the interrupt vector addresses and the corresponding interrupt source enable bits are summarized in Table 16. Table 16 Interrupt Source NMI Interrupt Vector Addresses Vector Address 0073H Assignment for SAAXC866 Watchdog Timer NMI PLL NMI Flash NMI VDDC Prewarning NMI VDDP Prewarning NMI Flash ECC NMI XINTR0 XINTR1 XINTR2 XINTR3 XINTR4 XINTR5 0003H 000BH 0013H 001BH 0023H 002BH External Interrupt 0 Timer 0 External Interrupt 1 Timer 1 UART T2 Fractional Divider (Normal Divider Overflow) LIN Enable Bit NMIWDT NMIPLL NMIFLASH NMIVDD NMIVDDP NMIECC EX0 ET0 EX1 ET1 ES ET2 IEN0 SFR NMICON
Data Sheet
49
V1.5, 2010-09
SAA-XC866
Functional Description Table 16 XINTR6 XINTR7 XINTR8 XINTR9 Interrupt Vector Addresses (cont'd) 0033H 003BH 0043H 004BH ADC SSC External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 XINTR10 XINTR11 XINTR12 XINTR13 0053H 005BH 0063H 006BH CCU6 INP0 CCU6 INP1 CCU6 INP2 CCU6 INP3 ECCIP0 ECCIP1 ECCIP2 ECCIP3 EADC ESSC EX2 EXM IEN1
Data Sheet
50
V1.5, 2010-09
SAA-XC866
Functional Description
3.4.3
Interrupt Priority
Each interrupt source, except for NMI, can be individually programmed to one of the four possible priority levels. The NMI has the highest priority and supersedes all other interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are available to program the priority level of each non-NMI interrupt vector. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot be interrupted by any other interrupt source. If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within each priority level, there is a second priority structure determined by the polling sequence shown in Table 17. Table 17 Source Non-Maskable Interrupt (NMI) External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt UART Interrupt ADC Interrupt SSC Interrupt External Interrupt 2 External Interrupt [6:3] CCU6 Interrupt Node Pointer 0 CCU6 Interrupt Node Pointer 1 CCU6 Interrupt Node Pointer 2 CCU6 Interrupt Node Pointer 3 Priority Structure within Interrupt Level Level (highest) 1 2 3 4 5 7 8 9 10 11 12 13 14
Timer 2,Fractional Divider, LIN Interrupts 6
Data Sheet
51
V1.5, 2010-09
SAA-XC866
Functional Description
3.5
Parallel Ports
The SAA-XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Port P2 is an input-only port, providing general purpose input functions, alternate input functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital Converter (ADC). Bidirectional Port Features: * * * * * Configurable pin direction Configurable pull-up/pull-down devices Configurable open drain mode Transfer of data through digital inputs and outputs (general purpose I/O) Alternate input/output for on-chip peripherals
Input Port Features: * * * * * Configurable input driver Configurable pull-up/pull-down devices Receive of data through digital input (general purpose input) Alternate input for on-chip peripherals Analog input for ADC module
Data Sheet
52
V1.5, 2010-09
SAA-XC866
Functional Description
Internal Bus
Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_OD Open Drain Control Register
Px_DIR Direction Register
Px_ALTSEL0 Alternate Select Register 0
VDDP
Px_ALTSEL1 Alternate Select Register 1
AltDataOut 3 AltDataOut 2 AltDataOut1
11 10 01 00
enable
Pull Up Device
enable
Output Driver
Pin
Px_Data Data Register
Out In
enable
Input Driver
AltDataIn
Schmitt Trigger
enable
Pull Down Device
Pad
Figure 18
General Structure of Bidirectional Port
Data Sheet
53
V1.5, 2010-09
SAA-XC866
Functional Description
Internal Bus
Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register
VDDP
enable enable Input Driver
Pull Up Device Pin
Px_DATA Data Register
In
Schmitt Trigger
AltDataIn AnalogIn
enable
Pull Down Device
Pad
Figure 19
General Structure of Input Port
Data Sheet
54
V1.5, 2010-09
SAA-XC866
Functional Description
3.6
Power Supply System with Embedded Voltage Regulator
The SAA-XC866 microcontroller requires two different levels of power supply: * 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports * 2.5 V for the core, memory, on-chip oscillator, and peripherals Figure 20 shows the SAA-XC866 power supply system. A power supply of 3.3 V or 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regulator and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption.
CPU & Memory
On-chip OSC
Peripheral logic ADC
V D D C (2.5V)
FLASH PLL
GPIO Ports (P0-P3)
EVR
XTAL1& XTAL2
VD D P VSSP
Figure 20 SAA-XC866 Power Supply System
EVR Features: * * * * * Input voltage (VDDP): 3.3 V/5.0 V Output voltage (VDDC): 2.5 V 7.5% Low power voltage regulator provided in power-down mode VDDC and VDDP prewarning detection VDDC brownout detection
Data Sheet
55
V1.5, 2010-09
SAA-XC866
Functional Description
3.7
Reset Control
The SAA-XC866 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the SAA-XC866 is first powered up, the status of certain pins (see Table 19) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device. In order to power up the system properly, the external reset pin RESET must be asserted until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches 0.4 V, but not before VDDC reaches 0.9* VDDC. A typical application example is shown in Figure 21. VDDP capacitor value is 300 nF. VDDC capacitor value is 220 nF. The capacitor connected to RESET pin is 100 nF. Typically, the time taken for VDDC to reach 0.9*VDDC is less than 50 s once VDDP reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less than 500 s, the RESET pin should be held low for 500 s typically. See Figure 22.
3.3/5V e.g. 300nF 220nF
VSSP typ. 100nF RESET
VDDP
VDDC
VSSC
EVR 30k XC866
Figure 21 Reset Circuitry
Data Sheet
56
V1.5, 2010-09
SAA-XC866
Functional Description
Voltage 5V 2.5V 2.3V 0.9*VDDC VDDP
VDDC
Time Voltage 5V RESET with capacitor
< 0.4V 0V typ. < 50 u s
Time
Figure 22
VDDP, VDDC and VRESET during Power-on Reset
The second type of reset in SAA-XC866 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. To ensure the recognition of the hardware reset, pin RESET must be held low for at least 100 ns. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode.
Data Sheet
57
V1.5, 2010-09
SAA-XC866
Functional Description
3.7.1
Module Reset Behavior
Table 18 shows how the functions of the SAA-XC866 are affected by the various reset types. A " " means that this function is reset to its default state. Table 18 Module/ Function CPU Core Peripherals On-Chip Static RAM Oscillator, PLL Port Pins EVR The voltage Not affected regulator is switched on Disabled Disabled Not affected, Not affected, Not affected, Affected, un- Affected, unreliable reliable reliable reliable reliable Not affected Effect of Reset on Device Functions Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset
FLASH NMI
3.7.2
Booting Scheme
When the SAA-XC866 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectively select the different boot options. Table 19 shows the available boot options in the SAA-XC866. Table 19 MBC 1 0 0 1
1) 2)
SAA-XC866 Boot Selection P0.0 x x 0 0 Type of Mode User Mode; on-chip OSC/PLL non-bypassed BSL Mode; on-chip OSC/PLL non-bypassed OCDS Mode1); on-chip OSC/PLL nonbypassed Standalone User (JTAG) Mode2); on-chip OSC/PLL non-bypassed (normal) PC Start Value 0000H 0000H 0000H 0000H
TMS 0 0 1 1
The OCDS mode is not accessible if Flash is protected. Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Data Sheet
58
V1.5, 2010-09
SAA-XC866
Functional Description
3.8
Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the SAA-XC866. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state. Features: * * * * * Phase-Locked Loop (PLL) for multiplying clock source by different factors PLL Base Mode Prescaler Mode PLL Mode Power-down mode support
The CGU consists of an oscillator circuit and a PLL.In the SAA-XC866, the oscillator can be from either of these two sources: the on-chip oscillator (10 MHz) or the external oscillator (4 MHz to 12 MHz). The term "oscillator" is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down.
osc fail detect lock detect
1 0 fsys
OSCR
LOCK
OSC
fosc
P:1
fp fn
PLL core
fvco
K:1
N:1
OSCDISC
NDIV
VCOBYP
Figure 23
Data Sheet
CGU Block Diagram
59 V1.5, 2010-09
SAA-XC866
Functional Description The clock system provides three ways to generate the system clock: PLL Base Mode The system clock is derived from the VCO base (free running) frequency clock divided by the K factor. 1 f SYS = f VCObase x --K Prescaler Mode (VCO Bypass Operation) In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors. 1 f SYS = f OSC x ------------PxK PLL Mode The system clock is derived from the oscillator clock, multiplied by the N factor, and divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for this PLL mode. The PLL mode is used during normal system operation. N f SYS = f OSC x ------------PxK Table 20 shows the settings of bits OSCDISC and VCOBYP for different clock mode selection. Table 20 OSCDISC 0 0 1 1 Clock Mode Selection VCOBYP 0 1 0 1 Clock Working Modes PLL Mode Prescaler Mode PLL Base Mode PLL Base Mode
Note: When oscillator clock is disconnected from PLL, the clock mode is PLL Base mode regardless of the setting of VCOBYP bit. System Frequency Selection For the SAA-XC866, the values of P and K are fixed to "1" and "2", respectively. In order to obtain the required system frequency, fsys, the value of N can be selected by bit NDIV for different oscillator inputs. Table 21 provides examples on how fsys = 80 MHz can be obtained for the different oscillator sources.
Data Sheet 60 V1.5, 2010-09
SAA-XC866
Functional Description
Table 21 Oscillator On-chip External
System frequency (fsys = 80 MHz) fosc 10 MHz 10 MHz 8 MHz 5 MHz N 16 16 20 32 P 1 1 1 1 K 2 2 2 2 fsys 80 MHz 80 MHz 80 MHz 80 MHz
Table 22 shows the VCO range for the SAA-XC866. Table 22 fVCOmin 150 100 VCO Range fVCOmax 200 150 fVCOFREEmin 20 10 fVCOFREEmax 80 80 Unit MHz MHz
3.8.1
Recommended External Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitry must be connected to both pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz to 12 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1 and CX2 values shown in Figure 24 can be used as starting points for the negative resistance evaluation and for non-productive systems. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative resistance method. Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The oscillator can also be used in combination with a ceramic resonator. The final circuitry must also be verified by the resonator vendor. Figure 24 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode.
Data Sheet
61
V1.5, 2010-09
SAA-XC866
Functional Description
XTAL1 4 - 12 MHz XC866 Oscillator
fO SC
Ex ternal Cloc k Signal
XTAL1 XC866 Oscillator XTAL2
fO SC
RQ
RX2
XTAL2
CX1
CX2 VSS
1)
Fundamental Mode Cry s tal
VSS
RX2 0 0 0 0
Clock_EXOSC
1)
Cry s tal Frequenc y C X1 , C X2 4 MHz 8 MHz 10 MHz 12 MHz 33 18 15 12 pF pF pF pF
1) Note that these are evaluation start values!
Figure 24
External Oscillator Circuitries
Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier.
Data Sheet
62
V1.5, 2010-09
SAA-XC866
Functional Description
3.8.2
Clock Management
The CGU generates all clock signals required within the microcontroller from a single clock, fsys. During normal system operation, the typical frequencies of the different modules are as follow: * * * * CPU clock: CCLK, SCLK = 26.7 MHz CCU6 clock: FCLK = 26.7 MHz Other peripherals: PCLK = 26.7 MHz Flash Interface clock: CCLK3 = 80 MHz and CCLK = 26.7 MHz
In addition, different clock frequency can output to pin CLKOUT(P0.0). The clock output frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the resulting output frequency has 50% duty cycle. Figure 25 shows the clock distribution of the SAA-XC866.
CLKREL
FCLK fosc
CCU6 Peripherals
OSC
PLL
fsys /3
PCLK SCLK CCLK CORE
N,P,K
CCLK3
FLASH Interface
COREL COUTS TLEN Toggle Latch CLKOUT
Figure 25
Clock Generation from fsys
Data Sheet
63
V1.5, 2010-09
SAA-XC866
Functional Description For power saving purposes, the clocks may be disabled or slowed down according to Table 23. Table 23 System frequency (fsys = 80 MHz) Power Saving Mode Idle Slow-down Action Clock to the CPU is disabled. Clocks to the CPU and all the peripherals, including CCU6, are divided by a common programmable factor defined by bit field CMCON.CLKREL. Oscillator and PLL are switched off.
Power-down
Data Sheet
64
V1.5, 2010-09
SAA-XC866
Functional Description
3.9
Power Saving Modes
The power saving modes of the SAA-XC866 provide flexible power consumption through a combination of techniques, including: * * * * Stopping the CPU clock Stopping the clocks of individual system components Reducing clock speed of some peripheral components Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see Figure 26) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are: * Idle mode * Slow-down mode * Power-down mode
any interrupt & SD=0 set IDLE bit
ACTIVE
EXINT0/RXD pin & SD=0 set PD bit
IDLE
set SD bit
clear SD bit
POWER-DOWN
set IDLE bit any interrupt & SD=1 SLOW-DOWN
set PD bit EXINT0/RXD pin & SD=1
Figure 26
Transition between Power Saving Modes
Data Sheet
65
V1.5, 2010-09
SAA-XC866
Functional Description
3.10
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an SAA-XC866 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the SAA-XC866 will be aborted in a user-specified time period. In debug mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging. Features: * * * * * 16-bit Watchdog Timer Programmable reload value for upper 8 bits of timer Programmable window boundary Selectable input frequency of fPCLK/2 or fPCLK/128 Time-out detection with NMI generation and reset prewarning activation (after which a system reset will be performed)
The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access. Figure 27 shows the block diagram of the WDT unit.
WDT Control
WDTREL
1:2 MUX f PCLK 1:128
Clear
WDT Low Byte WDT High Byte
Overflow/Time-out Control & Window-boundary control WDTIN
ENWDT Logic ENWDT_P WDTWINB
WDTTO WDTRST
Figure 27
WDT Block Diagram
Data Sheet
66
V1.5, 2010-09
SAA-XC866
Functional Description If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is entered. The prewarning period lasts for 30H count, after which the system is reset (assert WDTRST). The WDT has a "programmable window boundary" which disallows any refresh during the WDT's count-up. A refresh during this window boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. After being serviced, the WDT continues counting up from the value ( * 28). The time period for an overflow of the WDT is programmable in two ways: * the input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128 * the reload value WDTREL for the high byte of WDT can be programmed in register WDTREL The period, PWDT, between servicing the WDT and the next overflow can be determined by the following formula:
( 1 + WDTIN x 6 ) x ( 2 16 - WDTREL x 2 8 ) P WDT = 2 ----------------------------------------------------------------------------------------------------f PCLK
If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 28. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not be smaller than WDTREL.
Count FFFF H
WDTWINB
WDTREL
time No refresh allowed Refresh allowed
Figure 28
Data Sheet
WDT Timing Diagram
67 V1.5, 2010-09
SAA-XC866
Functional Description Table 24 lists the possible watchdog time range that can be achieved for different module clock frequencies. Some numbers are rounded to 3 significant digits. Table 24 Reload value in WDTREL Watchdog Time Ranges Prescaler for fPCLK 2 (WDTIN = 0) 26.7 MHz FFH 7FH 00H 19.2 s 2.48 ms 4.92 ms 128 (WDTIN = 1) 26.7 MHz 1.23 ms 159 ms 315 ms
Data Sheet
68
V1.5, 2010-09
SAA-XC866
Functional Description
3.11
Universal Asynchronous Receiver/Transmitter
The Universal Asynchronous Receiver/Transmitter (UART) provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. Features: * Full-duplex asynchronous modes - 8-bit or 9-bit data frames, LSB first - fixed or variable baud rate * Receive buffered * Multiprocessor communication * Interrupt generation on the completion of a data transmission or reception The UART can operate in four asynchronous modes as shown in Table 25. Data is transmitted on TXD and received on RXD. Table 25 UART Modes Baud Rate fPCLK/2 Variable fPCLK/32 or fPCLK/64 Variable
Operating Mode Mode 0: 8-bit shift register Mode 1: 8-bit shift UART Mode 2: 9-bit shift UART Mode 3: 9-bit shift UART
There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock and can be configured to either fPCLK/32 or fPCLK/64. The variable baud rate is set by either the underflow rate on the dedicated baud-rate generator, or by the overflow rate on Timer 1.
Data Sheet
69
V1.5, 2010-09
SAA-XC866
Functional Description
3.11.1
Baud-Rate Generator
The baud-rate generator is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud rates based on its input clock fPCLK, see Figure 29.
Fractional Divider
FDSTEP 1 FDM 1 0 FDEN&FDM
8-Bit Reload Value
Adder
fDIV
00 01 0 1
FDEN
FDRES
0 11 fMOD (overflow) 10
8-Bit Baud Rate Timer
fBR
R fPCLK
Prescaler
fDIV
clk 11 10 01 `0' 00 NDOV
Figure 29
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate generation, the fractional divider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel. Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12. The baud rate (fBR) value is dependent on the following parameters: * Input clock fPCLK * Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON * Fractional divider (STEP/256) defined by register FDSTEP (to be considered only if fractional divider is enabled and operating in fractional divider mode)
Data Sheet 70 V1.5, 2010-09
SAA-XC866
Functional Description * 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG The following formulas calculate the final baud rate without and with the fractional divider respectively:
f PCLK BRPRE baud rate = ---------------------------------------------------------------------------------- where 2 x ( BR_VALUE + 1 ) > 1 BRPRE 16 x 2 x ( BR_VALUE + 1 )
f PCLK - STEP baud rate = ---------------------------------------------------------------------------------- x -------------BRPRE 256 16 x 2 x ( BR_VALUE + 1 )
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module clock of 26.7 MHz, the maximum achievable baud rate is 0.83 MBaud. Standard LIN protocol can support a maximum baud rate of 20kHz, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for greater accuracy. Table 26 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors. The fractional divider is disabled and a module clock of 26.7 MHz is used. Table 26 Baud rate 19.2 kBaud 9600 Baud 4800 Baud 2400 Baud Typical Baud rates for UART with Fractional Divider disabled Prescaling Factor (2BRPRE) 1 (BRPRE=000B) 1 (BRPRE=000B) 2 (BRPRE=001B) 4 (BRPRE=010B) Reload Value (BR_VALUE + 1) 87 (57H) 174 (AEH) 174 (AEH) 174 (AEH) Deviation Error -0.22 % -0.22 % -0.22 % -0.22 %
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 27 lists the resulting deviation errors from generating a baud rate of 115.2 kHz, using different module clock frequencies. The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet 71 V1.5, 2010-09
SAA-XC866
Functional Description Table 27 fPCLK 26.67 MHz 13.33 MHz 6.67 MHz Deviation Error for UART with Fractional Divider enabled STEP Prescaling Factor Reload Value (BR_VALUE + 1) (2BRPRE) 1 1 1 10 (AH) 7 (7H) 3 (3H) 177 (B1H) 248 (F8H) 212 (D4H) Deviation Error +0.03 % +0.11 % -0.16 %
Data Sheet
72
V1.5, 2010-09
SAA-XC866
Functional Description
3.11.2
Baud Rate Generation using Timer 1
In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows: [3.1] 2 x f PCLK Mode 1, 3 baud rate = ---------------------------------------------------32 x 2 x ( 256 - TH1 )
SMOD
3.12
Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 29). Once the fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At each timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP. The output frequency in normal divider mode is derived as follows: [3.2] f MOD 1 = f DIV x ----------------------------256 - STEP
Data Sheet
73
V1.5, 2010-09
SAA-XC866
Functional Description
3.13
LIN Protocol
The UART can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception. LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An attractive feature of LIN is self-synchronization of the slave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame. The structure of a LIN frame is shown in Figure 30. The frame consists of the: * * * * header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field response time data bytes (according to UART protocol) checksum
Frame slot Frame Interframe space
Header
Response space
Response
Synch
Protected identifier
Data 1
Data 2
Data N
Checksum
Figure 30
Structure of LIN Frame
3.13.1
LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by each frame. The information needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame. The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
Data Sheet 74 V1.5, 2010-09
SAA-XC866
Functional Description The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of frame. For this purpose, every frame starts with a sequence consisting of a break field followed by a synch byte field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field. Upon entering LIN communication, a connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps: STEP 1: Initialize interface for reception and timer for baud rate measurement STEP 2: Wait for an incoming LIN frame from host STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame.
Data Sheet
75
V1.5, 2010-09
SAA-XC866
Functional Description
3.14
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces. Features: * Master and slave mode operation - Full-duplex or half-duplex operation * Transmit and receive buffered * Flexible data format - Programmable number of data bits: 2 to 8 bits - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock * Variable baud rate * Compatible with Serial Peripheral Interface (SPI) * Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error)
Data Sheet
76
V1.5, 2010-09
SAA-XC866
Functional Description Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. Figure 31 shows the block diagram of the SSC.
PCLK
Baud-rate Generator
Clock Control Shift Clock RIR SSC Control Block Register CON TIR EIR
SS_CLK MS_CLK
Receive Int. Request Transmit Int. Request Error Int. Request
Status
Control TXD(Master) RXD(Slave) Pin Control
16-Bit Shift Register
TXD(Slave) RXD(Master)
Transmit Buffer Register TB
Receive Buffer Register RB
Internal Bus
Figure 31
SSC Block Diagram
Data Sheet
77
V1.5, 2010-09
SAA-XC866
Functional Description
3.15
Timer 0 and Timer 1
Timers 0 and 1 are count-up timers which are incremented every machine cycle, or in terms of the input clock, every 2 PCLK cycles. They are fully compatible and can be configured in four different operating modes for use in a variety of applications, see Table 28. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 28 Mode 0 Timer 0 and Timer 1 Modes Operation 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 8-bit timer with auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow. Timer 0 operates as two 8-bit timers The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled.
1
2
3
Data Sheet
78
V1.5, 2010-09
SAA-XC866
Functional Description
3.16
Timer 2
Timer 2 is a 16-bit general purpose timer (THL2) that has two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is disabled, Timer 2 counts with an input clock of PCLK/12. Timer 2 continues counting as long as it is enabled. Table 29 Mode Timer 2 Modes Description
Auto-reload Up/Down Count Disabled * Count up only * Start counting from 16-bit reload value, overflow at FFFFH * Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well * Programmble reload value in register RC2 * Interrupt is generated with reload event Up/Down Count Enabled * Count up or down, direction determined by level at input pin T2EX * No interrupt is generated * Count up - Start counting from 16-bit reload value, overflow at FFFFH - Reload event triggered by overflow condition - Programmble reload value in register RC2 * Count down - Start counting from FFFFH, underflow at value defined in register RC2 - Reload event triggered by underflow condition - Reload value fixed at FFFFH Channel capture * * * * * * * Count up only Start counting from 0000H, overflow at FFFFH Reload event triggered by overflow condition Reload value fixed at 0000H Capture event triggered by falling/rising edge at pin T2EX Captured timer value stored in register RC2 Interrupt is generated with reload or capture event
Data Sheet
79
V1.5, 2010-09
SAA-XC866
Functional Description
3.17
Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and multi-phase machines. The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only. The multi-channel control unit generates output patterns, which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. Timer T12 Features: * Three capture/compare channels, each channel can be used either as a capture or as a compare channel * Supports generation of a three-phase PWM (six outputs, individual signals for highside and lowside switches) * 16-bit resolution, maximum count frequency = peripheral clock frequency * Dead-time control for each channel to avoid short-circuits in the power stage * Concurrent update of the required T12/13 registers * Generation of center-aligned and edge-aligned PWM * Supports single-shot mode * Supports many interrupt request sources * Hysteresis-like control mode Timer T13 Features: * * * * * One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock frequency Can be synchronized to T12 Interrupt generation at period-match and compare-match Supports single-shot mode
Additional Features: * * * * * * * Implements block commutation for Brushless DC-drives Position detection via Hall-sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage
Data Sheet
80
V1.5, 2010-09
SAA-XC866
Functional Description The block diagram of the CCU6 module is shown in Figure 32.
module kernel
compare
address decoder T12 clock control
channel 0 channel 1 channel 2
start capture
1
1
deadtime control
multichannel control
trap control
1 output select output select 3
T13 interrupt control
channel 3
compare 1
3
2
2
2
trap input 1
input / output control
CCPOS0
CCPOS1
CCPOS2
COUT63
COUT60
COUT61
COUT62
Hall input
compare
compare
compare
port control
CCU6_block_diagram
Figure 32
CCU6 Block Diagram
Data Sheet
81
V1.5, 2010-09
CTRAP
T12HR
T13HR
CC60
CC61
CC62
SAA-XC866
Functional Description
3.18
Analog-to-Digital Converter
The SAA-XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2. Features: * Successive approximation * 8-bit or 10-bit resolution (TUE of 1 LSB and 2 LSB, respectively) * Eight analog channels * Four independent result registers * Result data protection for slow CPU access (wait-for-read mode) * Single conversion mode * Autoscan functionality * Limit checking for conversion results * Data reduction filter (accumulation of up to 2 conversion results) * Two independent conversion request sources with programmable priority * Selectable conversion request trigger * Flexible interrupt generation with configurable service nodes * Programmable sample time * Programmable clock divider * Cancel/restart feature for running conversions * Integrated sample and hold circuitry * Compensation of offset errors * Low power modes
Data Sheet
82
V1.5, 2010-09
SAA-XC866
Functional Description
3.18.1
ADC Clocking Scheme
A common module clock fADC generates the various clock signals used by the analog and digital parts of the ADC module: * fADCA is input clock for the analog part. * fADCI is internal clock for the analog part (defines the time base for conversion length and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components. * fADCD is input clock for the digital part. The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz. Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required.
fADC = fPCLK
fADCD
arbiter
registers
interrupts
digital part
fADCA
CTC
/ 32 f ADCI /4 MUX /3 /2
clock prescaler
analog components
analog part 1 fADCI
Condition: f ADCI 10 MHz, where t ADCI =
Figure 33
ADC Clocking Scheme
Data Sheet
83
V1.5, 2010-09
SAA-XC866
Functional Description For module clock fADC = 26.7 MHz, the analog clock fADCI frequency can be selected as shown in Table 30. Table 30 26.7 MHz fADCI Frequency Selection CTC 00B 01B 10B 11B (default) Prescaling Ratio /2 /3 /4 / 32 Analog Clock fADCI 13.3 MHz (N.A) 8.9 MHz 6.7 MHz 833.3 kHz Module Clock fADC
As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00B when fADC is 26.7 MHz. During slow-down mode where fADC may be reduced to 13.3 MHz, 6.7 MHz etc., CTC can be set to 00B as long as the divided analog clock fADCI does not exceed 10 MHz. However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode.
3.18.2
* * * *
ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases: Synchronization phase (tSYN) Sample phase (tS) Conversion phase Write result phase (tWR)
conversion start trigger Sample Phase fADCI BUSY Bit SAMPLE Bit tSYN tS tCONV Write Result Phase tWR Conversion Phase Source interrupt Channel interrupt Result interrupt
Figure 34
ADC Conversion Timing
Data Sheet
84
V1.5, 2010-09
SAA-XC866
Functional Description
3.19
On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: * * * * use the built-in debug functionality of the XC800 Core add a minimum of hardware overhead provide support for most of the operations by a Monitor Program use standard interfaces to communicate with the Host (a Debugger)
Features: * * * * * Set breakpoints on instruction address and within a specified address range Set breakpoints on internal RAM address Support unlimited software breakpoints in Flash/RAM code region Process external breaks Step through the program code
The OCDS functional blocks are shown in Figure 35. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control signals and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is accessed through the JTAG1), which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application. The dedicated MBC pin is used for external configuration and debugging control. Note: All the debug functionality described here can normally be used only after SAAXC866 has been started in OCDS mode.
1)
The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet
85
V1.5, 2010-09
SAA-XC866
Functional Description
JTAG Module
Primary Debug Interface TMS TCK TDI TDO TCK TDI TDO Control Reset Monitor & Bootstrap loader Control line MBC
Memory Control Unit
User Program Memory Boot/ Monitor ROM
JTAG
Monitor Mode Control
WDT Suspend System Control Unit Reset Clock
User Internal RAM
Monitor RAM
- parts of OCDS
Reset Clock Debug PROG PROG Memory Interface & IRAM Data Control Addresses
XC800
OCDS_XC800-Block_Diagram-UM-v0.2
Figure 35
OCDS Block Diagram
3.19.1
JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID register contents for the SAA-XC866 devices are given in Table 31. Table 31 Device Type Flash JTAG ID Summary Device Name SAA-XC866L-4FRA SAA-XC866-4FRA SAA-XC866L-2FRA SAA-XC866-2FRA SAA-XC866L-1FRA SAA-XC866-1FRA JTAG ID 1010 0083H 100F 5083H 1010 2083H 1010 1083H 1013 8083H 1013 8083H
Data Sheet
86
V1.5, 2010-09
SAA-XC866
Functional Description Table 31 ROM JTAG ID Summary SAA-XC866L-4RRA SAA-XC866-4RRA SAA-XC866L-2RRA SAA-XC866-2RRA 1013 9083H 1013 9083H 1013 9083H 1013 9083H
3.20
Identification Register
The SAA-XC866 identity register is located at Page 1 of address B3H. ID Identity Register
7 6 5 PRODID r 4 3 2
Reset Value: 0000 0010B
1 VERID r 0
Field VERID PRODID
Bits [2:0] [7:3]
Type Description r r Version ID 010B Product ID 00000B
Data Sheet
87
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4
Electrical Parameters
Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the SAA-XC866.
4.1
General Parameters
The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 and Section 4.3.
4.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the SAAXC866 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the "Symbol" column: * CC These parameters indicate Controller Characteristics, which are distinctive features of the SAA-XC866 and must be regarded for a system design. * SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the SAA-XC866 is designed in.
Data Sheet
88
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.1.2
Absolute Maximum Rating
Maximum ratings are the extreme limits to which the SAA-XC866 can be subjected to without permanent damage. Table 32 Parameter Ambient temperature Absolute Maximum Rating Parameters Symbol -40 -65 -40 -0.5 -0.5 -0.5 Limit Values min. max. 140 150 150 6 3.25 C C C V V V under bias
1)
Unit Notes
TA Storage temperature TST Junction temperature TJ Voltage on power supply pin with VDDP respect to VSS Voltage on core supply pin with VDDC respect to VSS Voltage on any pin with respect VIN to VSS
Input current on any pin during overload condition
under bias1)
1)
1)
VDDP +
0.5 or max. 6
Whichever is lower1)
1)
IIN
-10 -
10 50
mA mA
Absolute sum of all input currents |IIN| during overload condition
1)
1)
Not subjected to production test, verified by design/characterization.
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pin with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
89
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.1.3
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation of the SAA-XC866. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 33 Parameter Digital power supply voltage Digital power supply voltage Digital ground voltage Digital core supply voltage System Clock
1)
Operating Condition Parameters Symbol Limit Values min. max. 5.5 3.6 0 2.3 74 -40 2.7 86 140 4.5 3.0 Unit Notes/ Conditions V V V V MHz C SAA-XC866... 5V Device 3.3V Device
Frequency1)
Ambient temperature
VDDP VDDP VSS VDDC fSYS TA
fSYS is the PLL output clock. During normal operating mode, CPU clock is fSYS / 3. Please refer to Figure 25 for detailed description.
Data Sheet
90
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.2 4.2.1
Table 34 Parameter
DC Parameters Input/Output Characteristics
Input/Output Characteristics (Operating Conditions apply) Symbol Limit Values min. max. 1.0 0.4 V V V V V Unit Test Conditions
VDDP = 5V Range
Output low voltage Output high voltage
VOL CC VOH CC
- - 1.0
VDDP - - VDDP - -
0.4
IOL = 15 mA IOL = 5 mA IOH = -15 mA IOH = -5 mA
CMOS Mode
Input low voltage on VILP SR port pins (all except P0.0 & P0.1) Input low voltage on P0.0 & P0.1 Input low voltage on RESET pin Input low voltage on TMS pin
-
0.3 x
VDDP
-0.2 - - 0.7 x 0.3 x V V V V CMOS Mode CMOS Mode CMOS Mode CMOS Mode
VILP0 SR VILR SR VILT SR
VDDP
0.3 x
VDDP
0.3 x
VDDP
-
Input high voltage on VIHP SR port pins (all except P0.0 & P0.1) Input high voltage on P0.0 & P0.1 Input high voltage on RESET pin Input high voltage on TMS pin Input Hysteresis1) on Port Pins Input Hysteresis1) on XTAL1
VDDP
0.7 x
VIHP0 SR VIHR SR VIHT SR HYS CC HYSXCC
VDDP
-
V V V V V
CMOS Mode CMOS Mode CMOS Mode CMOS Mode
VDDP
0.7 x
VDDP
0.75 x -
VDDP
0.08 x -
VDDP
0.07 x -
VDDC
Data Sheet
91
V1.5, 2010-09
SAA-XC866
Electrical Parameters Table 34 Parameter Input low voltage at XTAL1 Input high voltage at XTAL1 Pull-up current Pull-down current Input leakage current2) Input current at XTAL1 Input/Output Characteristics (Operating Conditions apply) Symbol Limit Values min. max. 0.3 x V V A A A A A A mA mA V mA
3)
Unit Test Conditions
VILX SR VIHX SR IPU IPD
SR SR
VSS 0.5 0.7 x
VDDC VDDC
+ 0.5 -10 - 10 - 2 10 5 25 0.3 15
VDDC
- -150 - 150 -2 -10
IOZ1 CC IILX
CC
TA 140C
VIH,min VIL,max VIL,max VIH,min 0 < VIN < VDDP,
Overload current on any IOV pin Absolute sum of overload currents Voltage on any pin during VDDP power off |IOV|
SR -5 - SR SR - SR -
3)
VPO
4)
Maximum current per IM pin (excluding VDDP and VSS)
Maximum current for all |IM| - pins (excluding VDDP SR and VSS) Maximum current into
60
mA
IMVDDP
SR
- -
80 80
mA mA
3)
VDDP
Maximum current out of IMVSS
3)
VSS
SR
Data Sheet
92
V1.5, 2010-09
SAA-XC866
Electrical Parameters Table 34 Parameter Input/Output Characteristics (Operating Conditions apply) Symbol Limit Values min. max. 1.0 0.4 V V V V V Unit Test Conditions
VDDP = 3.3V Range
Output low voltage Output high voltage
VOL CC VOH CC
- - 1.0
VDDP - - VDDP - -
0.4
IOL = 8 mA IOL = 2.5 mA IOH = -8 mA IOH = -2.5 mA
CMOS Mode
Input low voltage on VILP SR port pins (all except P0.0 & P0.1) Input low voltage on P0.0 & P0.1 Input low voltage on RESET pin Input low voltage on TMS pin
-
0.3 x
VDDP
-0.2 - - 0.7 x 0.3 x V V V V CMOS Mode CMOS Mode CMOS Mode CMOS Mode
VILP0 SR VILR SR VILT SR
VDDP
0.3 x
VDDP
0.3 x
VDDP
-
Input high voltage on VIHP SR port pins (all except P0.0 & P0.1) Input high voltage on P0.0 & P0.1 Input high voltage on RESET pin Input high voltage on TMS pin Input Hysteresis1) on Port Pins Input Hysteresis1) on XTAL1 Input low voltage at XTAL1 Input high voltage at XTAL1
VDDP
0.7 x
VIHP0 SR VIHR SR VIHT SR HYS CC HYSXCC VILX SR VIHX SR
VDDP
-
V V V V V V V
CMOS Mode CMOS Mode CMOS Mode CMOS Mode
VDDP
0.7 x
VDDP
0.75 x -
VDDP
0.03 x -
VDDP
0.07 x -
VDDC VSS - 0.3 x 0.5 VDDC 0.7 x VDDC VDDC + 0.5
93
Data Sheet
V1.5, 2010-09
SAA-XC866
Electrical Parameters Table 34 Parameter Pull-up current Pull-down current Input leakage current2) Input current at XTAL1 Input/Output Characteristics (Operating Conditions apply) Symbol Limit Values min. max. -5 - 5 - 2 10 5 25 0.3 15 A A A A A A mA mA V mA
3)
Unit Test Conditions
IPU IPD
SR SR
- -50 - 50 -2 - 10
IOZ1 CC IILX
CC
TA 140C
VIH,min VIL,max VIL,max VIH,min 0 < VIN < VDDP,
Overload current on any IOV pin Absolute sum of overload currents Voltage on any pin during VDDP power off |IOV|
SR -5 - SR SR - SR -
3)
VPO
4)
Maximum current per IM pin (excluding VDDP and VSS)
Maximum current for all |IM| - pins (excluding VDDP SR and VSS) Maximum current into
60
mA
IMVDDP
SR
- -
80 80
mA mA
VDDP
Maximum current out of IMVSS
VSS
1)
SR
Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and RESET pin have internal pull devices and are not included in the input leakage current characteristic. Not subjected to production test, verified by design/characterization. Not subjected to production test, verified by design/characterization. However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off.
2)
3) 4)
Data Sheet
94
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.2.2
Supply Threshold Characteristics
5.0V VDDPPW VDDP
2.5V VDDC VDDCPOR
VDDCPW VDDCBO VDDCRDR VDDCBOPD
Figure 36 Table 35 Parameters
Supply Threshold Parameters Supply Threshold Parameters (Operating Conditions apply) Symbol min. VDDCPW VDDCBO CC 2.2 CC 2.0 Limit Values typ. 2.3 2.1 1.0 1.5 4.0 1.5 max. 2.4 2.2 1.1 1.7 4.65 1.7 V V V V V V Unit
VDDC prewarning voltage1) VDDC brownout voltage in active mode1) RAM data retention voltage VDDC brownout voltage in power-down mode2) VDDP prewarning voltage3) Power-on reset
1) 2) 3)
VDDCRDR CC 0.9 VDDCBOPD CC 1.3 VDDPPW CC 3.3
voltage2)4)
VDDCPOR CC 1.3
Detection is disabled in power-down mode. Detection is enabled in both active and power-down mode. Detection is enabled for external power supply of 5.0V Detection must be disabled for external power supply of 3.3V. The reset of EVR is extended by 300 s typically after the VDDC reaches the power-on reset voltage.
4)
Data Sheet
95
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.2.3
ADC Characteristics
The values in the table below are given for an analog power supply between 4.5 V to 5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case, the analog parameters may show a reduced performance. All ground pins (VSS) must be externally connected to one single star point in the system. The voltage difference between the ground pins must not exceed 200mV. Table 36
Parameter
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Symbol min. Limit Values typ . max. Unit Test Conditions/ Remarks
1)
Analog reference voltage Analog reference ground Analog input voltage range ADC clocks
VAREF
VAGND VDDP SR + 1 VSS
VDDP V + 0.05 VAREF V -1 VAREF V 40 10 MHz MHz
VSS VAGND SR - 0.05
1)
VAIN SR VAGND - fADC fADCI - - 20 -
module clock1) internal analog clock1) See Figure 33
1)
Sample time Conversion time Total unadjusted error Differential Nonlinearity Integral Nonlinearity Offset Gain Overload current coupling factor for analog inputs
tS tC
CC (2 + INPCR0.STC) x tADCI CC See Section 4.2.3.1 - - 1 1 1 1 - - 1 2 - - - - 1.0 x 10-4 1.5 x 10-3
96
s s LSB LSB LSB LSB LSB LSB - -
1)
TUE CC - - |EADNL| - CC |EAINL| - CC |EAOFF| - CC |EAGAIN| - CC KOVA CC - -
8-bit conversion.2) 10-bit conversion.2) 10-bit conversion1) 10-bit conversion1) 10-bit conversion1) 10-bit conversion1)
IOV > 01)3) IOV < 01)3)
Data Sheet
V1.5, 2010-09
SAA-XC866
Electrical Parameters Table 36
Parameter
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Symbol min. Limit Values typ . max. Unit Test Conditions/ Remarks
Overload current coupling factor for digital I/O pins Switched capacitance at the reference voltage input Switched capacitance at the analog voltage inputs
KOVD CC - - CAREFSW - CC
- - 10
5.0 x 10-3 1.0 x 10-2 20
- - pF
IOV > 01)3) IOV < 01)3)
1)4)
- CAINSW CC
5
7
pF
1)5)
Input resistance of RAREFCC - the reference input Input resistance of RAIN CC - the selected analog channel
1) 2) 3)
1 1
2 1.5
k k
1)
1)
Not subject to production test, verified by design/characterization. TUE is tested at VAREF = 5.0 V, VAGND = 0 V , VDDP = 5.0 V. An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error current adds to the respective pin's leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ1| + (|IOV| x KOV). The additional error current may distort the input voltage on analog inputs. This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage. The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2.
4)
5)
Data Sheet
97
V1.5, 2010-09
SAA-XC866
Electrical Parameters
Analog Input Circuitry
REXT
ANx
RAIN, On
VAIN
CEXT
C AINSW
VAGNDx
Reference Voltage Input Circuitry
VAREFx
R AREF, On
VAREF
C AREFSW
VAGNDx
Figure 37
ADC Input Circuits
4.2.3.1
ADC Conversion Timing
Conversion time, tC = tADC x ( 1 + r x (3 + n + STC) ) , where r = CTC + 2 for CTC = 00B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC), n = 8 or 10 (for 8-bit and 10-bit conversion respectively), tADC = 1 / fADC
Data Sheet
98
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.2.4
Table 37 Parameter
Power Supply Current
Power Supply Current Parameters (Operating Conditions apply) Symbol Limit Values typ.1) max.2) 24.5 19.7 8.2 8 mA mA mA mA
3) 4) 5)
Unit Test Condition
Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled
1) 2) 3)
IDDP IDDP IDDP IDDP
22.6 17.2 7.2 7.1
6)
The typical IDDP values are periodically measured at TA = + 25 C and VDDP = 5.0 V. The maximum IDDP values are measured under worst case conditions (TA = + 140 C and VDDP = 5.5 V). IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010B), RESET = VDDP. IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 26.7 MHz, RESET = VDDP. IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 833 KHz by setting CLKREL in CMCON to 0101B, RESET = VDDP. IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 833 KHz by setting CLKREL in CMCON to 0101B, RESET = VDDP.
4)
5)
6)
Data Sheet
99
V1.5, 2010-09
SAA-XC866
Electrical Parameters Table 38 Parameter Power-Down Mode3)
1) 2) 3) 4)
Power Down Current (Operating Conditions apply) Symbol Limit Values typ.1) max.2) 10 30 A A TA = + 25 C.4) TA = + 85 C.4)5) 1 Unit Test Condition
IPDP
The typical IPDP values are measured at VDDP = 5.0 V. The maximum IPDP values are measured at VDDP = 5.5 V. IPDP (power-down mode) has a maximum value of 400 A at TA = + 140 C. IPDP (power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. Not subject to production test, verified by design/characterization.
5)
Data Sheet
100
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.3 4.3.1
AC Parameters Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 38, Figure 39 and Figure 40.
VDDP 90% 90%
VSS
10% tR tF
10%
Figure 38
Rise/Fall Time Parameters
VDDP VDDE / 2 VSS Test Points VDDE / 2
Figure 39
Testing Waveform, Output Delay
VLoad + 0.1 V VLoad - 0.1 V
Timing Reference Points
VOH - 0.1 V VOL - 0.1 V
Figure 40
Testing Waveform, Output High Impedance
Data Sheet
101
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.3.2
Table 39 Parameter
Output Rise/Fall Times
Output Rise/Fall Times Parameters (Operating Conditions apply) Symbol Limit Values min. max. Unit Test Conditions
VDDP = 5V Range
Rise/fall times 1) 2) tR, tF tR, tF - - 10 10 ns ns 20 pF. 3) 20 pF. 4)
VDDP = 3.3V Range
Rise/fall times 1) 2)
1) 2) 3) 4)
Rise/Fall time measurements are taken with 10% - 90% of the pad supply. Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF. Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF.
V DDP 90% 90%
VSS
10%
10%
tR
tF
Figure 41
Rise/Fall Times Parameters
Data Sheet
102
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.3.3
Table 40 Parameter
Power-on Reset and PLL Timing
Power-On Reset and PLL Timing (Operating Conditions apply) Symbol Limit Values min. typ. max. - 500 - - V ns s s
1) 1)
Unit Test Conditions
Pad operating voltage On-Chip Oscillator start-up time RESET hold time
VPAD CC 2.3 - tOSCST
CC
- - 160 500
Flash initialization time tFINIT CC -
1)
tRST SR -
VDDP rise time
1) 1)3)
(10% - 90%) 500s1)2)
PLL lock-in in time
1) 2) 3)
tLOCK CC -
-
- -
200 0.7
s ns
PLL accumulated jitter DP
Not all parameters are 100% tested, but are verified by design/characterization and test correlation. RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V). PLL lock at 80 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 40 and P = 1.
VDDP
VPAD
VDDC tOSCST OSC
PLL
PLL unlock tLOCK
PLL lock
Flash State tRST RESET Pads
1) 2)
Reset
Initialization tFINIT
Ready to Read
3) 1)Pad state undefined 2)ENPS control 3)As Programmed
I)until EVR is stable
II)until PLL is locked
III) until Flash go IV) CPU reset is released; Boot to Ready-to-Read ROM software begin execution
Figure 42
Data Sheet
Power-on Reset Timing
103 V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.3.4
Table 41 Parameter
On-Chip Oscillator Characteristics
On-chip Oscillator Characteristics (Operating Conditions apply) Symbol Limit Values min. typ. max. Unit Test Conditions
Nominal frequency
fNOM CC 9.75 10 -
10.25 MHz under nominal conditions1) 6.0 % with respect to fNOM, over lifetime and temperature (125C to 140C), for one device after trimming with respect to fNOM, over lifetime and temperature (-10C to 125C), for one device after trimming with respect to fNOM, over lifetime and temperature (-40C to -10C), for one device after trimming within one LIN message (<10 ms .... 100 ms)
Long term frequency fLT CC 0 deviation
-5.0
-
5.0
%
-6.0
-
0
%
Short term frequency fST CC -1.0 deviation
1)
-
1.0
%
Nominal condition: VDDC = 2.5 V, TA = + 25C.
Data Sheet
104
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.3.5
Table 42 Parameter
JTAG Timing
TCK Clock Timing (Operating Conditions apply; CL = 50 pF) Symbol Limits min max - - - 4 4 ns ns ns ns ns 50 20 20 - - Unit
TCK clock period1) TCK high time1) time1) TCK low time1) TCK clock rise
1)
TCK clock fall time1)
tTCK SR t1 SR t2 SR t3 SR t4 SR
Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
0.5 V DDP
0.9 V DDP 0.1 V DDP
TCK
t1 t TCK
Figure 43 TCK Clock Timing
t2
t4
t3
Data Sheet
105
V1.5, 2010-09
SAA-XC866
Electrical Parameters Table 43 Parameter TMS setup to TCK1) TMS hold to TDI hold to TCK1) TDI setup to TCK1) TCK1) TDO valid output from TCK1) TDO high impedance to valid output from TCK1) TDO valid output to high impedance from
1)
JTAG Timing (Operating Conditions apply; CL = 50 pF) Symbol Limits min max - - - - 23 26 18 ns ns ns ns ns ns ns Unit
TCK1)
t1 t2 t1 t2 t3 t4 t5
SR 8.0 SR 5.0 SR 11.0 SR 6.0 CC - CC - CC -
Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
TCK
t2
t1
TMS
t2
t1
TDI
t4 t3 t5
TDO
Figure 44
JTAG Timing
Data Sheet
106
V1.5, 2010-09
SAA-XC866
Electrical Parameters
4.3.6
Table 44 Parameter
SSC Master Mode Timing
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) Symbol min. Limit Values max. - 8 - - ns ns ns ns Unit
SCLK clock period1) MTSR delay from MRST hold from
1) 2)
SCLK1)
MRST setup to SCLK1) SCLK1)
t0 t1 t2 t3
CC 2*TSSC 2) CC 0 SR 22 SR 0
Not all parameters are 100% tested, but are verified by design/characterization and test correlation. TSSCmin = TCPU = 1/fCPU. When fCPU = 26.7MHz, t0 = 74.9ns. TCPU is the CPU clock period.
t0
SCLK1)
t1
MTSR1)
t1
t2
MRST1)
t3
Data valid
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_Tmg1
Figure 45
SSC Master Mode Timing
Data Sheet
107
V1.5, 2010-09
SAA-XC866
Package and Reliability
5
5.1
Table 45 Parameter
Package and Reliability
Package Parameters (PG-TSSOP-38)
Thermal Characteristics of the Package Symbol Limit Values Min. Max. 15.7 39.2 K/W - K/W - - - Unit Notes
Table 45 provides the thermal characteristics of the package.
Thermal resistance junction case1)2) Thermal resistance junction lead1)2)
1)
RTJC RTJL
CC CC
The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA) are to be combined with the thermal resistances between the junction and the case (RTJC), the junction and the lead (RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ=TA + RTJA x PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
2)
Data Sheet
108
V1.5, 2010-09
SAA-XC866
Package and Reliability
5.2
Package Outline
Figure 46
PG-TSSOP-38-4 Package Outline
Data Sheet
109
V1.5, 2010-09
SAA-XC866
Package and Reliability
5.3
Quality Declaration
Table 46 shows the characteristics of the quality parameters in the SAA-XC866. Table 46 Parameter Operation Lifetime when the device is used at the four stated TA1)2) Quality Parameters Symbol Limit Values Min. Typ. - - - - - - 106 - Max. 1500 2000 10000 1500 18000 hours hours hours hours hours TA= 140C TA= 125C TA= 85C TA= -40C TA= 108C TA= 27C for 15000 hours Conforming to EIA/JESD22A114-B Conforming to EIA/JESD22A114-B Conforming to JESD22-C101-C - - - - Operation Lifetime when the device is used at the two stated TA1)2) Weighted Average Temperature2)3) Unit Notes
tOP
tOP2
- -
130000 hours - 2000 C V
TWA
- -
ESD susceptibility VHBM according to Human Body Model (HBM) for all pins (except VDDC)2) ESD susceptibility VHBMC according to Human Body Model (HBM) for VDDC2) ESD susceptibility according to Charged Device Model (CDM) pins2)
1) 2) 3)
-
-
600
V
VCDM
-
-
750
V
This lifetime refers only to the time when the device is powered-on. Not all parameters are 100% tested, but are verified by design/characterization and test correlation. This parameter is derived based on the Arrhenius model.
Data Sheet
110
V1.5, 2010-09
www.infineon.com
Published by Infineon Technologies AG

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