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IPD09N03LA IPS09N03LA
IPF09N03LA IPU09N03LA
OptiMOS(R)2 Power-Transistor
Features * Ideal for high-frequency dc/dc converters * Qualified according to JEDEC for target application * N-channel, logic level * Excellent gate charge x R DS(on) product (FOM) * Superior thermal resistance * 175 C operating temperature
1)
Product Summary V DS R DS(on),max (SMD version) ID 25 8.6 50 V m A
Type
IPD09N03LA
IPF09N03LA
IPS09N03LA
IPU09N03LA
Package Ordering Code Marking
P-TO252-3-11 Q67042-S4154 09N03LA
P-TO252-3-23 Q67042-S4199 09N03LA
P-TO251-3-11 Q67042-S 09N03LA
P-TO251-3-21 Q67042-S4155 09N03LA
Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 C2) T C=100 C Pulsed drain current Avalanche energy, single pulse Reverse diode dv /dt Gate source voltage4) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 C T C=25 C3) I D=45 A, R GS=25 I D=50 A, V DS=20 V, di /dt =200 A/s, T j,max=175 C Value 50 45 350 75 6 20 63 -55 ... 175 55/175/56 mJ kV/s V W C Unit A
Rev. 1.5
page 1
2004-03-22
IPD09N03LA IPS09N03LA
Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area5) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=20 A V DS=25 V, V GS=0 V, T j=25 C V DS=25 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=30 A V GS=4.5 V, I D=30 A, SMD version V GS=10 V, I D=30 A V GS=10 V, I D=30 A, SMD version Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=30 A 25 1.2 1.6 0.1 Values typ.
IPF09N03LA IPU09N03LA
Unit max.
2.4 75 50
K/W
2 1
V
A
23
10 10 12 11.8 7.4 7.2 1 46
100 100 15 14.8 8.8 8.6 S nA m
1) 2)
J-STD20 and JESD22 Current is limited by bondwire; with an R thJC=2.4 K/W the chip is able to carry 67 A. See figure 3 T j,max=150 C and duty cycle D <0.25 for V GS<-5 V
3) 4) 5)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air.
Rev. 1.5
page 2
2004-03-22
IPD09N03LA IPS09N03LA
Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics6) Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total Gate plateau voltage Gate charge total, sync. FET Output charge Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 C V GS=0 V, I F=50 A, T j=25 C V R=15 V, I F=I S, di F/dt =400 A/s 0.97 Q gs Q g(th) Q gd Q sw Qg V plateau Q g(sync) Q oss V DS=0.1 V, V GS=0 to 5 V V DD=15 V, V GS=0 V V DD=15 V, I D=25 A, V GS=0 to 5 V 4.3 2.0 2.8 5.2 10 3.5 8.7 10 C iss C oss Crss t d(on) tr t d(off) tf V DD=15 V, V GS=10 V, I D=25 A, R G=2.7 V GS=0 V, V DS=15 V, f =1 MHz 1235 474 61 7.0 5.6 20 3.4 Values typ.
IPF09N03LA IPU09N03LA
Unit max.
1642 630 92 10 8.4 30 5.1
pF
ns
5.7 2.6 4.3 7.3 13 12 14
nC
V nC
50 350 1.2
A
V
Reverse recovery charge
Q rr
-
-
10
nC
6)
See figure 16 for gate charge parameter definition
Rev. 1.5
page 3
2004-03-22
IPD09N03LA IPS09N03LA
1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V
IPF09N03LA IPU09N03LA
70
60
60
50
50 40
P tot [W]
40
I D [A]
0 50 100 150 200
30
30
20 20 10
10
0
0 0 50 100 150 200
T C [C]
T C [C]
3 Safe operation area I D=f(V DS); T C=25 C; D =0 parameter: t p
1000
4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T
10
1 s limited by on-state resistance
100
10 s
0.5
1
Z thJC [K/W]
0.2 0.1 0.05
I D [A]
100 s DC
10
1 ms
0.1
0.02 0.01
10 ms single pulse
1 0.1 1 10 100
0.01
0
0
0
0
0
0
1
10-6
10-5
10-4
10-3
10-2
10-1
100
V DS [V]
t p [s]
Rev. 1.5
page 4
2004-03-22
IPD09N03LA IPS09N03LA
5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS
60
10 V 4.5 V 4.1 V
IPF09N03LA IPU09N03LA
6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS
28
3.2 V 3.5 V 3.8 V 4.1 V
50
24
20 40
R DS(on) [m]
3.8 V
16
4.5 V
I D [A]
30
3.5 V
12
20 8
3.2 V 10 V
10
3V 2.8 V
4
0 0 1 2 3
0 0 20 40 60
V DS [V]
I D [A]
7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j
100
8 Typ. forward transconductance g fs=f(I D); T j=25 C
60
80
50
40 60
g fs [S]
40 20
175 C 25 C
I D [A]
30
20
10
0 0 1 2 3 4 5
0 0 10 20 30 40 50 60
V GS [V]
I D [A]
Rev. 1.5
page 5
2004-03-22
IPD09N03LA IPS09N03LA
9 Drain-source on-state resistance R DS(on)=f(T j); I D=30 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS parameter: I D
16 14 2 12
200 A
IPF09N03LA IPU09N03LA
2.5
R DS(on) [m]
10 8 6 4
98 %
V GS(th) [V]
1.5
20 A
typ
1
0.5 2 0 -60 -20 20 60 100 140 180
0 -60 -20 20 60 100 140 180
T j [C]
T j [C]
11 Typ. Capacitances C =f(V DS); V GS=0 V; f =1 MHz
12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j
104
10000
1000
25 C
Ciss
103
1000
100
Coss 175 C, 98% 175 C 25 C, 98%
C [pF]
102
I F [A]
100
Crss
10
101
10
1 10 20 30 0.0 0.5 1.0 1.5 2.0
0
V DS [V]
V SD [V]
Rev. 1.5
page 6
2004-03-22
IPD09N03LA IPS09N03LA
13 Avalanche characteristics I AS=f(t AV); R GS=25 parameter: T j(start)
100
IPF09N03LA IPU09N03LA
14 Typ. gate charge V GS=f(Q gate); I D=25 A pulsed parameter: V DD
12
10
150 C 100 C 25 C 5V
15 V
8
20 V
10
V GS [V]
1 10 100 1000
I AV [A]
6
4
2
1
0 0 5 10 15 20
t AV [s]
Q gate [nC]
15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA
16 Gate charge waveforms
29
V GS
28 27 26
Qg
V BR(DSS) [V]
25 24 23 22 21 20 -60 -20 20 60 100 140 180
V g s(th)
Q g (th) Q gs
Q sw Q gd
Q gate
T j [C]
Rev. 1.5
page 7
2004-03-22
IPD09N03LA IPS09N03LA
Package Outline P-TO252-3-11: Outline
IPF09N03LA IPU09N03LA
Footprint:
Packaging:
Dimensions in mm Rev. 1.5 page 8 2004-03-22
IPD09N03LA IPS09N03LA
Package Outline P-TO252-3-23: Outline
IPF09N03LA IPU09N03LA
Footprint:
Dimensions in mm Rev. 1.5 page 9 2004-03-22
IPD09N03LA IPS09N03LA
Package Outline P-TO251-3-11: Outline
IPF09N03LA IPU09N03LA
P-TO251-3-21: Outline
Dimensions in inch [mm] Rev. 1.5 page 10 2004-03-22
IPD09N03LA IPS09N03LA
Published by Infineon Technologies AG Bereich Kommunikation St.-Martin-Strae 53 D-81541 Munchen (c) Infineon Technologies AG 1999 All Rights Reserved.
IPF09N03LA IPU09N03LA
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide (see address list). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies office. Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.5
page 11
2004-03-22

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