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L6585D
Combo IC for PFC and ballast control
Features

Pre-heating and ignition phases independently programmable Ignition voltage control Transition mode PFC with over-current protection Programmable and precise End-of-life protection compliant with all ballast configurations Auto-adjusting half-bridge over-current control Automatic re-lamp 3% oscillator precision 1.2s dead time PFC over-voltage protection and feedback disconnection Under voltage lock-out SO-20

Applications
Electronic ballast
Block diagram
COMP MULT PFCS Vcc
2.5V + _
E/A
INV
1V
ZCD
OL
S 0.7V
PFG STARTER
Q
R
LATCH OVP PFSTOP DIS EOL CONTROL
Vcc
PFSTOP
WINDOW COMPARATOR & REF.
CTR
OL OVP 3.4V DIS 2V 0.8V 2V
EOLR
0.8V
RELAMP
EOLP
December 2006
+
MULTIPLIER and THD OPTIMIZER
LEB
1.7V 17V
BOOT
UV DETECTION SYNCHRONOUS BOOTSTRAP DIODE
_
CHOKE SAT.
PWM COMP.
HVG DRIVER
HSD OUT
+
_
DEAD TIME
DRIVING LOGIC
LEVEL SHIFTER LVG DRIVER
Vcc
LSD GND
1.5V
HB STOP
LOGIC
HBCS
1.9V
TIMING MANAGEMENT 4.6 1.5
0.9V Vcc
CCO
RF
OSC
EOI
Tch
Rev 3
1/25
www.st.com 25
Contents
L6585D
Contents
1 2 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 5.1.2 5.1.3 Pre-heating (time interval A Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ignition (time interval B Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Run mode (time interval C Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 7 8 9 10 11 12
End of life - window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Half-bridge current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Re-lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25
L6585D
Device description
1
Device description
Designed in High-voltage BCD Off-line technology, the L6585D embeds a PFC controller, a half-bridge controller, the relevant drivers and the logic necessary to build an electronic ballast. The advanced and precise logic circuitry, combined with the programmability of the End-ofLife windows comparator threshold, makes the L6585D compliant with either "lamp-toground" or "block capacitor-to ground" configurations. Another outstanding feature is the possibility of controlling and limiting the lamp voltage during the ignition phase. The pre-heating and ignition durations are independently settable as well as the half-bridge switching frequencies for each operating phases (pre-heating, ignition and normal mode). Other features (half-bridge over-current with frequency increase, PFC over-voltage) allow building a reliable and flexible solution with a reduced part count. The PFC section achieves current mode control operating in Transition Mode; the highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. The PFC output voltage is controlled by means of a voltage-mode error amplifier and a precise internal voltage reference. The driver of the PFC is able to provide 300mA (source) and 600mA (sink) and the drivers of the half-bridge provide 290mA source and 480mA sink.
Figure 1.
Typical system block diagram
LPFC
HV BUS R5 CBULK R7
R1 R8 Charge pump CBOOT
CTR Vcc 7 17 20 BOOT 19 18 16
R2 AC MAINS
PFG
R4
ZCD 11 13
R6
CCOMP
INV 10 COMP 9
HSD OUT LSD HBCS
CIN
PFCS MULT 12 8 15 GND OSC 1 2 RF
L6585D
3 EOI Tch 4 5 EOLP 6
LB
14 EOL-R
LAMP
CRES
R3
RSNSPF COSC
RPRE RRUN CIGN
RD
CD
RP
RSNSHB
CBLOCK
3/25
Pin settings
L6585D
2
2.1
Pin settings
Connection
Figure 2. Pin sonnection (Top view)
OSC RF EOI TCH EOLP EOL-R CTR MULT COMP INV
BOOT HSD OUT VCC LSD GND HBCS PFG PFCS ZCD
4/25
L6585D
Pin settings
2.2
Functions
Table 1. Pin functions
Function An external capacitor to GND fixes the half-bridge switching frequency with a 3% precision. Voltage reference able to source up to 240A; the current sunk from this pin fixes the switching frequency of the half-bridge for each operating state. A resistor (RRUN) connected to ground sets the half-bridge operating frequency combined with the capacitor connected to the pin OSC. A resistor connected to EOI (RPRE) - in parallel with RRUN - sets the maximum half-bridge switching frequency during pre-heating. Connected to ground by a capacitor that, combined with RPRE, determines the ignition duration Pre-heating: low impedance to set high switching frequency Ignition and run mode: high impedance with controlled current sink in case of HBCS threshold triggering. Pin for setting the pre-heating time and the protection intervention. Connect a RC parallel network (RD and CD) to ground Pre-heating: the CD is charged by an internal current generator. When the pin voltage reaches 4.63V the generator is disabled and the capacitor discharges because of RD; once the voltage drops below 1.52V, the preheating finishes, the ignition phase starts and the RDCD is discharged to ground. Run mode: according to the kind of fault (either over-current or EOL) the internal generator charges the RC parallel network and appropriate actions are taken to stop the application. During proper behavior of the IC, this pin is low impedance. Pin num. Name 1 OSC
2
RF
3
EOI
4
Tch
5
Pin to program the EOL comparator. EOLP It is possible to select both the EOL sensing method and the window comparator amplitude by connecting a resistor (REOLP) to ground. Input for the window comparator and re-lamp function. It can be used to detect the lamp ageing for either "lamp to ground" and "block capacitor to ground" configurations. According to the EOLP pin setting, it is possible to program: - the window amplitude (VW) EOL-R - the center of the window (VSET) either fixed or in tracking with the PFC output bus. This function is blanked during the ignition phase. In case of either lamp disconnection or removal, a second threshold (VSL-UP) crossing latches the IC and drives the chip in "ready-mode" so that when the voltage at EOL-R pin is brought below VSL-DOWN (re-lamp) a new preheating/ignition sequence is repeated. Input pin for: - PFC over-voltage detection: the PFC driver is stopped until the voltage returns in the proper operating range - Feedback disconnection detection - reference for End-of-life in case tracking reference; - shut-down: forcing the pin to a voltage lower than 0.75V, the IC shuts down in unlatched condition. Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the PFC current loop.
6
7
CTR
8
MULT
5/25
Pin settings Table 1. Pin functions (continued)
Function
L6585D
Pin num. Name 9
Output of the error amplifier. A compensation network is placed between this pin COMP and INV to achieve stability of the PFC voltage control loop and ensure high power factor and low THD. INV Inverting input of the error amplifier. The information on the output voltage of the PFC pre-regulator is fed into the pin through a resistor divider. Input for the feedback disconnection comparator Boost inductor's demagnetization sensing input for PFC transition-mode operation. A negative-going edge triggers PFC MOSFET turn-on. During start-up or when the voltage is not high enough to arm the internal comparator (e.g. AC Mains peak), the PFC driver is triggered by means of an internal starter. Input to the PFC PWM comparator. The current flowing in the PFC mosfet is sensed by a resistor; the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine the PFC MOSFET' s turn-off. A second comparison level detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, shuts down and latches the IC reducing its consumption to the start-up. An internal LEB prevents undesired function triggering. PFC gate driver output. The totem pole output stage is able to drive power MOSFET'S with a peak current of 300mA source and 600mA sink.
10
11
ZCD
12
PFCS
13
PFG
14
2-levels half-bridge current monitor for current control. The current flowing in the HB mosfet is sensed by a resistor; the resulting voltage is applied to this pin. Low threshold (active during run mode): in case of thresholds crossing, the IC reacts with self-adjusting frequency increase in order to limit the half-bridge HBCS (lamp) current. High threshold: - ignition: in case of thresholds crossing during the frequency shift, the IC reacts with self-adjusting frequency increase in order to limit the lamp voltage and preventing operation below resonance. - run mode: in case of thresholds crossing because of current spikes (due e. g. to capacitive mode / cross-conduction), the L6585D latches to avoid MOSFETs damaging, GND LSD VCC OUT HSD Ground. Current return for both the signal part of the IC and the gate driver. Low side driver output: the output stage can deliver 290mA source and 480mA sink (typ. values). Supply Voltage of both the signal part of the IC and the gate driver. Clamped with a Zener inside. High Side Driver Floating Reference. This pin must be connected close to the source of the high side power MOS. High side driver output: the output stage can deliver 290mA source and 480mA (typ. values).
15 16 17 18 19
20
Bootstrapped Supply Voltage. Between this pin and VCC, the bootstrap capacitor must be connected. BOOT A patented integrated circuitry replaces the external bootstrap diode, by means of a high voltage DMOS, synchronously driven with the low side power MOSFET.
6/25
L6585D
Electrical data
3
3.1
Electrical data
Maximum ratings
Table 2.
Symbol VBOOT VOUT dVOUT /dt VCC
Absolute maximum ratings
Pin 20 18 18 17 1, 3, 4, 8, 10, 12 2, 5 6 7 14 9, 11 ZCD clamp (IZCD < 4mA) Current capability Current capability Maximum operating frequency Power dissipation @TA = 70C Parameter Floating supply voltage Floating ground voltage Floating ground max. slew rate IC Supply voltage (ICC = 20mA) Analog input and outputs
(1)
Value -1 to 618 -3 to VBOOT - 18 50 Self-limited -0.3 to 5 -0.3 to 2.7 Vcc -0.3 to 7 -5 to 5 Self-limited 240 100 250 0.83
Unit V V V/ns V V V
V
IRF IEOLP FOSC(MAX) PTOT
2 5
A A KHz W
1. The device has an internal Clamping Zener between GND and the VCC pin, it must not be supplied by a Low Impedance Voltage Source.
Note:
ESD immunity for pins 18, 19 and 20 is guaranteed up to 900V (Human Body Model)
3.2
Thermal data
Table 3.
Symbol RthJA TJ TSTG
Thermal data
Description Max. thermal resistance junction to ambient Junction operating temperature range Storage temperature Value 120 -40 to 150 -55 to 150 Unit C/W C C
7/25
Electrical characteristics
L6585D
4
Electrical characteristics
VCC = 15V, TA = 25C, CL = 1nF, COSC = 470pF, RRUN = 47K, unless otherwise specified
Table 4.
Symbol
Electrical characteristics
Pin Parameter Test condition Min Typ Max Unit
Supply voltage Vcc VCC(on) VCC(OFF) VZ Supply current IST-UP ICC Iq VCC VCC VCC Start-up current Operating supply current Residual current IC latched Before turn-on @ 13V 250 7 350 350 A mA A VCC VCC VCC VCC Operating range Turn-on threshold Turn-off threshold Zener Voltage After turn-on
(1) (1)
11 13.6 9.6 16.2 14.3 10.3 17.2
16 15 11 17.7
V V V V
Icc = 20mA
PFC section - multiplier input IMULT VMULT
VCS VMULT
MULT MULT MULT MULT
Input bias current Linear operation range Output max. slope Gain
VMULT = 0 VCOMP = 3V VMULT = 0 to 1V, VCOMP = Upper clamp VMULT = 1V, VCOMP= 3V 0 to 3 0.75 0.52
-1
A V V/V 1/V
KM
PFC section - error amplifier VINV INV INV IINV Gv GB ICOMP INV INV INV COMP Voltage feedback input threshold Line regulation Input bias current Voltage gain Gain-bandwidth product Source current Sink current VCOMP COMP Upper clamp voltage Lower clamp voltage VDIS INV COMP Open loop detection threshold Static OVP threshold Open loop
(2) (2)
2.45 VCC = 10.3V to 16V 60
2.5
2.55 50 -1
V mV A dB MHz mA mA V V V
80 1 -2.6 4 4.2 2.25 1.2
VCOMP = 4V, VINV = 2.4 V VCOMP = 4V, VINV = 2.6 V ISOURCE = 0.5 mA ISINK = 0.5 mA CTR > 3.4 2.1
2.25
2.4
V
8/25
L6585D Table 4.
Symbol CTR pin DIS CTR Disable threshold Hysteresys Dynamic PFC overvoltage Hysteresys Available range as tracking reference CTR Lower threshold (falling) Hysteresys Higher threshold (rising) Hysteresys PFC section - current sense comparator ICS tLEB VCSdis td(H-L) VCSclamp PFCS PFCS PFCS PFCS PFCS Input bias current Leading edge blanking IC disable level Delay to output Current sense reference clamp VCOMP = Upper clamp VCS = 0
(2)
Electrical characteristics Electrical characteristics (continued)
Pin Parameter Test condition Min Typ Max Unit
Falling edge
0.75 120
V mV V mV V
PFOV
CTR
Rising edge
3.4 140 1.7 0.12 3.4 0.14
V
-1 100 1.65 200 1.75 120 1.0 1.08 1.16 300 1.85
A ns V ns V
PFC section - zero current detector VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk ZCD ZCD ZCD ZCD ZCD ZCD ZCD Upper clamp voltage Lower clamp voltage Arming voltage (positive-going edge) Triggering voltage (negative-going edge) Input bias current Source current capability Sink current capability IZCD = 2.5 mA IZCD = -2.5 mA
(2)
5 -0.3 0 1.4 0.7 1 -4 4 0.3
V V V V A mA mA
(2)
VZCD = 1 to 4.5 V
PFC section - gate driver PFG tf tr ISINK ISOURCE PFG PFG PFG PFG PFG Output high/low Fall time Rise time Peak sink current Peak source current Pull-down resistor 475 200 ISINK = 10mA ISOURCE = 10mA 14.5 40 90 600 300 10 90 140 0.2 V V ns ns mA mA k
9/25
Electrical characteristics Table 4.
Symbol
L6585D
Electrical characteristics (continued)
Pin Parameter Test condition Min Typ Max Unit
Half bridge section - Timing & oscillator ICH VCHP VCHN TCH TCH TCH TCH RTCH REOI TCH EOI EOI Charge current Charge threshold (positive going-edge) Discharge threshold (negative going edge) Leakage current Internal impedance Open state current EOI impedance
(1) (1)
34 4.63 1.52 0.1 150 200 0.15 125 42 85 140 200 265 1.83 1.92 240
(1) (1) (3) (3) (3)
A V V A A
1.5V < VTCH < 4.63V, falling Run mode VEOI = 2V During pre-heating Tspike = 700ns
IEOI
EOI
EOI current generator during ignition and run mode
Tspike = 800ns Tspike = 900ns Tspike = 1s Tspike = 3s
(1) (1) (3) (3)
A
VEOI VREF IRF
EOI RF RF OSC OSC
EOI threshold Reference voltage Max current capability Rising threshold Falling threshold Output duty cycle Dead time Half-bridge oscillation frequency (run mode) Half-bridge oscillation frequency (pre heating)
1.9 2
1.98 2.08
V V A
3.7 0.9 48 0.96 58.4 50 1.2 60.2 118 52 1.44 62 121.5
V V % s KHz KHz
D TDEAD fRUN fPRE
OSC OSC OSC OSC
RPRE=50K
114.4
Half bridge section - End Of Life FUNCTION and re-lamp comparator EOLP EOLP EOL-R Current capability Reference voltage Operating range EOLP=xxx 220K = REOLP = 270K or 22K = REOLP = 27K REOLP > 620K or 75K = REOLP = 91K 220K = REOLP = 270K or 75K = REOLP = 91K REOLP > 620K or 22K = REOLP = 27K 100 1.92 0.95 2 2.08 4.15 A V V
tracking with CTR V 2.5 220 720 mV mV
VS
EOL-R
Window comparator reference
VW
Half window amplitude
10/25
L6585D Table 4.
Symbol
Electrical characteristics Electrical characteristics (continued)
Pin EOL-R
EOL-R
Parameter Sink/source capability Relamp comparator hysteresys
Test condition
Min
Typ 2.5 4.63 160
Max
Unit A V mV
Half bridge section - Half-bridge current sense HBCSH HBCSL HBCS HBCS HBCS Latched threshold Frequency increase threshold VEOI < 1.9V (ignition) VEOI > 1.9V (run mode) Run mode 1.53 0.85 1.53 1.6 0.91 1.6 1.66 0.97 1.66 V V V
Half bridge section - Low side gate driver LSD LSD LSD LSD TRISE TFALL LSD LSD LSD Output low voltage Output high voltage Peak source current Peak sink current Rise time Fall time Pull-down resistor ; ISINK = 10mA ISOURCE = 10mA 14.5 200 400 290 480 120 80 45 0.3 V V mA mA ns ns K
Half bridge section - High side gate driver (voltages referred to OUT) HSD HSD HSD HSD TRISE TFALL HSD HSD HSD Output low voltage Output high voltage Peak source current Peak sink current Rise time Fall time HSD-OUT pull-down ISINK = 10mA ISOURCE = 10mA VBOOT - 0.5 200 400 290 480 120 80 50 VOUT + 0.3 V V mA mA ns ns K
High-side floating gate-drive supply BOOT OUT Leakage current Leakage current Synchronous bootstrap diode on-resistance
1. Parameter in tracking 2. Specification over the -40C to 125C junction temperature range are ensured by design, characterization and statistical correlation 3. A pulse train has been sent to the HBCS pin with f=6KHz; the pulse duration is the one indicated in the notes as "TON"
VBOOT = 600V (2) VOUT = 600V VLSD = HIGH
(2)
5 5 250
A A
11/25
Application information
L6585D
5
5.1
5.1.1
Application information
Start-up sequence
Pre-heating (time interval A Figure 4)
After IC turn-on, unless a lamp absence is detected, the oscillator starts switching at a frequency (fPRE) set by values of COSC and RRUN and RPRE Figure 3: Equation 1
1.41 f PRE = ----------------------------------------------------------------C OSC ( R RUN | | R PRE )
The pre-heating time is: Equation 2
CD 4.63 T PRE = 4.63 -------- + R D C D ln ---------1.52 I CH
where CD and RD are shown in Figure 3 and ICH is typically 34 A. Figure 3. Oscillator, pre-heating and ignition circuitry
IMAX VREF
RF
RRUN CIGN RD RPRE
EOI Tch
CD COSC
LOGIC OSC
12/25
L6585D
Application information
5.1.2
Ignition (time interval B Figure 4)
When the voltage at pin TCH drops down to 1.52V (typ.), the pin EOI is driven in high impedance state and CIGN is exponentially charged according to the time constant given by CIGN*RPRE that defines the ignition time and the frequency shift starts. The ignition time is the time necessary to EOI voltage to reach 1.9V, so, by means of simple calculation: Equation 3
T IGN = 3 C IGN R PRE
During this phase, the half-bridge current control can limit the maximum voltage applied to the lamp by forcing small frequency increases whenever the half-bridge sense resistor voltage exceeds the HBCSH threshold (see the "Half-Bridge current control" paragraph). Figure 4, centre and right, shows the L6585D behavior as the lamp gets older; if it doesn't ignite for a time longer than the pre-heating one (counted by a cycle charge/discharge of the TCH pin), the IC is stopped, enters low consumption and waits for either a re-lamp or an UVLO.
13/25
Application information
L6585D
5.1.3
Run mode (time interval C Figure 4)
As the voltage at EOI exceeds 1.9V and the lamp has ignited, the L6585D enters Run mode and remains in this condition unless one of the protections (all enabled in this mode) is trigged. The switching frequency reaches the FRUN value set by RRUN and COSC: Equation 4
1.4 f RUN = ------------------------------------R RUN C OSC
Figure 4.
Oscillator, pre-heating and ignition sequence
VZ
VCC(on)
VCC(on)
VCC(on)
VCC
VCC(off)
VCC
VCC(off)
VCC
VCC(off)
4.63V
= RD x CD
1.5V
4.63V
4.63V
Tch
Tch
1.5V
Tch
1.5V
EOI
2V 1.9V
EOI
2V 1.9V
EOI
2V 1.9V
fPRE
fPRE
fPRE
fHB
fRUN
fHB
fRUN
fHB
fRUN
VHBCS
VHBCS
VHBCS
VLAMP
VLAMP
VLAMP
A
B
C
A
B
C
A
B
C
14/25
L6585D
End of life - window comparator
6
End of life - window comparator
To detect the ageing of the lamp with particular attention to the effect appearing as asymmetric rectification, a programmable window comparator has been introduced (centered around "VSET" with amplitude "VW") that triggers when the EOL-R voltage is higher than VSET+ VW/2 or lower than VREF - VW/2. By means of the resistor connected to the EOLP pin, it is possible to select: 1. the sensing mode: - - 2. fixed reference: the centre of the window comparator (VREF) is fixed at 2.5V by an internal reference; tracking reference: the centre of the window comparator is the voltage at pin CTR (that is a signal proportional to the PFC output voltage).
the half-window amplitude (VW/2): 200mV or 750mV.
Figure 5.
End-of-life detection circuitry and waveforms
RP2
R P1 CBOOT
HV BUS CBOOT
HV BUS
CTR
INTERNAL FIXED REF.
BOOT HSD
CTR
BOOT HSD
INTERNAL FIXED REF.
WINDOW COMPARATOR
AMPLITUDE
INPUT
OUT
W INDOW COMPARATOR
AMPLITUDE
INPUT
OUT
C BLOCK
LSD V LAMP EOLR VK R E1
LSD EOLP EOLR VK R FL or RFH
V LAMP EOLP R E1
R E2
C BLOCK
R FL or RFH
V Z2
V Z1
RE2
HVBUS (100Hz or 120Hz)
PFC OUT
V CB
PFC OUT/2
V LAMP
V REF + W/2 + VZ1 + V R2
CTR
VK
V REF - W/2 - VZ1 - V R2
V SET + W/2
V REF + W/2 V REF
V EOLR
V SET - W/2
V REF - W/2
V EOLR
15/25
End of life - window comparator
L6585D
The four possible configurations are summarized in the following table, together with the value of resistance to be connected to the EOLP pin in order to obtain the desired setting: Table 5. Configuration of the EOLP pin
Symbol RFH RTL RFL RTL Reference Fixed 2.5V Tracking with CTR Fixed 2.5V Tracking with CTR Half-window amplitude 750mV 200mV 200mV 750mV
EOLP resistor REOLP > 620K 220K = REOLP = 270K 75K = REOLP = 91K 22K = REOLP = 27K
Tracking reference: this setting is suitable for the block capacitor to ground configuration (Figure 5, left). In this case the window comparator centre is set by the CTR voltage that is internally transferred to the EOL structure. The effect of rectification appears as shifting of the DC voltage component across the block capacitor, which, under normal conditions, equals one half of the PFC output voltage. A signal proportional to the DC block capacitor voltage is sent to the EOL-R pin by means of a resistive divider (RE1 and RE2); the dividers RE1 and RE2 and RP1 and RP2 must be designed to set the EOL-R voltage equal to CTR under nominal condition.
Fixed reference: this setting is suitable for the lamp to ground configuration (Figure 5, right). The effect of rectification appears as shifting of the DC lamp voltage. A resistive divider (RE1 and RE2) senses the voltage across the lamp under normal condition, that is an AC signal with zero average value whereas in case of asymmetric rectification the DC value can shift either in positive or negative direction. Two Zener diodes can be connected back-to-back between the EOL-R pin and the centre of the resistive divider. The Zener voltages should differ by an amount as close as possible to the double of the internal reference to have a symmetrical detection, as it can easily obtained from the following equations:

VUP = VREF + W/2 + VZ1 + VR2 VDOWN = VREF - W/2 - VZ2 - VR1
where VUP and VDOWN are the VK values (equal in absolute value) that trigger the window comparator. To avoid an immediate intervention of the EOL protection, a filtering is introduced; as long as the fault condition persists, the Tch internal generator charges the CD up to 4.63V and then it opens. If this fault condition is still present when the Tch voltage decreases down to 1.5V, then the half bridge is stopped, otherwise (if the fault disappears) the counting is stopped and reset.
16/25
L6585D
Half-bridge current control
7
Half-bridge current control
The information about the lamp current can be obtained by reading the voltage across a sense resistor placed in series to the source of the half-bridge low side MOS. This circuitry is enabled at the end of the pre-heating phase and it enriches the L6585D with two features:
Controlled lamp voltage/current during ignition (Figure 4): by properly setting the sense resistor (such that the VHBCS level is crossed in correspondence of a lamp voltage higher than the ignition voltage) it is possible to limit the maximum lamp voltage during ignition. In case of this occurrence, then the L6585D would react with a small frequency increase that allows limiting the lamp voltage (V+IGN). This also prevents the risk of crossing the resonance frequency of the LBALLAST-CRES circuit. If the lamp ignites before TCH reaches 1.52V (Figure 4 left) that is EOI has exceeded 1.9V, then: - - - EOI internal switch opens and its voltage moves asymptotically to 2V The switching frequency reaches the operating one; When TCH reaches 1.52, it will be discharged
If instead that the lamp hasn't ignited after a time equal to the pre-heat time (Figure 4 right) the oscillator stops, the chip enters low consumption mode and this condition is latched until the mains supply voltage is removed or a re-lamp is detected.
Over-current protection during run mode: if the HBCSL threshold is crossed, the TCH internal generator is turned on as well as the one at pin EOI causing a frequency increase: this implements a current control structure.
During run mode another protection is active: a second comparator (HBCSH) on the pin HBCS detects anomalous current flow through the sense resistor such as the spikes generated by the capacitive mode; the crossing of this second threshold latches the IC.
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CTR
L6585D
8
CTR
This is a multi-function pin, connected to a resistive divider to the PFC output bus:
PFC over-voltage: in case of PFC output overshoot (e.g. at start-up) that causes a threshold crossing, the PFC section stops switching until the pin voltage falls below 3.26V (typ.); this is helpful because the bandwidth of the PFC error amplifier is narrow so the control loop is not fast enough to properly reacts Feedback disconnection: The OVP function above described (together with the static one embedded in the PFC error amplifier) is able to handle "normal" over-voltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. In case of over-voltage generated when the upper resistor of the feedback output divider fails open, the control loop can no longer read the information on the output voltage and will force the PFC pre-regulator to work at maximum ON time; if this occurs (i.e. the pin INV falls below 1.2V, typ.) and the CTR detects an OVP, the gate drivers activity is immediately stopped, the device enters low consumption and the condition is latched as long as the IC supply voltage is above the UVLO threshold; Reference for EOL in case of tracking reading. Disable: by forcing the pin below 0.75V an immediate unlatched shut-down is activated; it can be also used as re-lamp in fact after the pin voltage is above 0.8V a preheating/ignition sequence is repeated.

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L6585D
Re-lamp
9
Re-lamp
A second comparator has been introduced on the pin EOL-R; a voltage higher than the internal threshold is read as lamp absence so the chip suddenly stops switching, enters idle mode (low consumption) and is ready for a new pre-heating/ignition sequence as soon as a new lamp is inserted. In this idle mode the consumption of the chip is reduced so that the current flowing through the resistors (connected to the high voltage bus for the start-up) is enough to keep the VCC voltage above the UVLO threshold. After a re-lamp cycle (that is the EOL-R voltage is brought above 4.63V and then released below), a new pre-heating/ignition sequence starts.
Table 6.
IC configuration
Pre-heating TCH cycle(1); It depends on RD and CD Ignition Run mode
Time duration
EOI charge from 0 to 1.9V (typ.); Until a fault appears or It depends on RD and the AC Mains is removed CD
Half-bridge switching frequency
1.41 f PRE = ----------------------------------------------------------------C OSC ( R RUN | | R PRE )
The frequency shifts from fPRE to fRUN with exponential trend
1.4 f RUN = ------------------------------------R RUN C OSC
RELAMP comparator CTR: PFC overvoltage CTR: disable function
ENABLED ENABLED ENABLED
ENABLED ENABLED ENABLED ENABLED - low threshold disabled - high threshold FSW increase DISABLED ENABLED
ENABLED ENABLED ENABLED ENABLED - low threshold FSW increase latch - high threshold ENABLED ENABLED
Half-bridge current sense
DISABLED
EOL: window comparator PFC choke saturation
DISABLED ENABLED
1. TCH cycle: charge of the TCH voltage up to 4.63V and discharge down to 1.53V following the RDCD time constant
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Re-lamp Table 7. Fault conditions
Condition At turn-on: EOL-R voltage higher than 4.63V Run mode: EOL-R voltage higher than 4.63V EOL-R voltage outside the limits of window comparator IC behavior - The TCH charge doesn't start (no ignition) - Drivers stopped - IC low consumption (Vcc clamped) - All drivers stopped - IC low consumption (Vcc clamped) - TCH cycle (1) (reset if the fault disappears) - drivers stopped at the end of TCH cycle - IC low consumption (VCC clamped) - TCH cycle (1) with lamp voltage control - In case of HBCS at the end of the TCH cycle, drivers stopped - IC low consumption (Vcc clamped) - TCH cycle (1) with lamp voltage control (frequency increase) - In case of HBCS at the end of the TCH cycle, drivers stopped - IC low consumption (Vcc clamped) - Drivers stopped - IC low consumption (Vcc clamped) - Drivers stopped - IC low consumption (Vcc clamped) - Drivers stopped - IC low consumption (Vcc clamped)
L6585D
Fault
Action required
Lamp absence (re-lamp comparator)
Lamp replacement (EOL-R below 4.63V)
End of life
Re-lamp cycle (2)
Ignition: HBCS threshold Half-bridge current sense
Re-lamp cycle (2)
Run mode: HBCSL threshold Run mode: HBCSH threshold CTR voltage lower than 0.8V PFCS voltage higher than 1.6V
Re-lamp cycle (2)
Re-lamp cycle (2) When the CTR voltage returns above 0.8V, the IC driver restart with a pre-heating sequence Re-lamp cycle (2)(3) When the CTR voltage returns below 4.63V, the PFC driver restart Re-lamp cycle (2)(3)
Shut-down
Choke saturation
Over-voltage of PFC CTR voltage higher than - PFC driver stopped output 4.63V PFC open loop (feedback disconnection)
1.
CTR voltage higher than - Drivers stopped 4.63V AND INV voltage - IC low consumption (Vcc clamped) lower than xxx
TCH cycle: charge of the TCH voltage up to 4.63V and discharge down to 1.52V following the RDCD time constant;
2. Re-lamp cycle: the voltage at EOL-R pin must be first pulled above 4.63V and then released below it; this typically happens in case of lamp replacement; 3. This fault can't actually be solved replacing the lamp so a lamp replacement is not effective/safe to restart the ballast.
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L6585D
Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
L6585D
Table 8.
SO-20 mechanical data
Dimensions mm. inch Max. 2.65 0.1 0.2 2.45 0.35 0.23 0.5 45 (typ.) 12.60 10.00 1.27 11.43 7.40 0.50 7.60 1.27 0.75 8 (max.) 0.291 0.020 13.00 10.65 0.496 0.393 0.050 0.450 0.300 0.050 0.029 0.512 0.419 0.49 0.32 0.014 0.009 0.020 0.004 Min. Typ. Max. 0.104 0.008 0.096 0.019 0.012
Ref. Min. A a1 a2 b b1 C c1 D E e e3 F L M S Typ.
Figure 6.
Package dimensions
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L6585D
Order codes
11
Order codes
Table 9. Order codes
Part Number L6585D L6585DTR Package SO-20 SO-20 Shipment Tube Tape and Reel
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Revision history
L6585D
12
Revision history
Table 10.
Date 12-Jan-2006 25-Oct-2006 21-Dec-2006
Revision history
Revision 1 2 3 Initial release Final datasheet Updated fRUN value on Table 4: Electrical characteristics on page 8 Changes
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L6585D
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