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Advance Product Information
October 21, 2004
2W Q-Band High Power Amplifier
Key Features
* * * * * * *
TGA4046-EPU
Typical Frequency Range: 41 - 46 GHz Typical 33dBm Psat, 32dBm P1dB 17 dB Nominal Gain 16 dB Nominal Return Loss Bias: 6 V, 2 A 0.15 um 3MI pHEMT Technology Chip Dimensions 3.45 x 4.39 x 0.10 mm (0.136 x 0.173 x 0.004 in)
Primary Applications
* Sat - Com
Product Description
The TriQuint TGA4046-EPU is a compact High Power Amplifier MMIC for Q-band applications. The part is designed using TriQuint's 0.15um gate power pHEMT process. The TGA4046-EPU nominally provides 33dBm of Saturated Output Power, and 32dBm Output Power at 1dB gain compression from 41 - 46GHz. The MMIC also provides 17dB Gain and 16dB Return Loss. The part is ideally suited for markets such as Satellite Communications both commercial and military. The TGA4046-EPU is 100% DC and RF tested on-wafer to ensure performance compliance.
35 34 33 32 31 30 29 28 27 26 25
Measured Fixtured Data
Bias Conditions: Vd = 6 V, Id = 2 A
20 15 10 5 0 -5 -10 -15 -20 -25 -30 40 41 42
GAIN
S-Parameter (dB)
IRL
ORL
43
44
45
46
47
48
Frequency (GHz)
Psat P1dB
Power (dBm)
40
41
42
43
44
45
46
47
48
Frequency (GHz)
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
1
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com
Advance Product Information
October 21, 2004
TGA4046-EPU
TABLE I MAXIMUM RATINGS 1/ SYMBOL
Vd Vg Id Ig PIN PD TCH TM TSTG 1/ 2/ 3/ 4/ Drain Voltage Gate Voltage Range Drain Current Gate Current Input Continuous Wave Power Power Dissipation Operating Channel Temperature Mounting Temperature (30 Seconds) Storage Temperature
PARAMETER
VALUE
7V -2 TO 0 V 3A 112 mA 29 dBm 16 W 150 C 320 0C -65 to 150 0C
0
NOTES
2/
2/ 3/ 3/
2/ 4/ 5/ 6/
These ratings represent the maximum operable values for this device. Combinations of supply voltage, supply current, input power, and output power shall not exceed PD. Total current for the entire MMIC. When operated at this bias condition with a base plate temperature of 700C, the median life is 1E+6 hrs.
5/
Junction operating temperature will directly affect the device median time to failure (MTTF). For maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels. These ratings apply to each individual FET.
6/
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
2
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com
Advance Product Information
October 21, 2004
TGA4046-EPU
TABLE III ELECTRICAL CHARACTERISTICS (Ta = 25 0C Nominal)
PARAMETER
Frequency Range Drain Voltage, Vd Drain Current, Id Gate Voltage, Vg Small Signal Gain, S21 Input Return Loss, S11 Output Return Loss, S22 Output Power @ 1dB Gain Compression, P1dB Saturated Power, Psat
TYPICAL
41 - 46 6.0 2 -0.6 17 18 20 32 33
UNITS
GHz V A V dB dB dB dBm dBm
TABLE IV THERMAL INFORMATION
PARAMETER TEST CONDITIONS Vd = 6 V Id = 2 A Pdiss = 12 W TCH O ( C) 129 RTJC (qC/W) 4.9 TM (HRS) 6.4E+6
RJC Thermal Resistance (channel to Case)
Note: Assumes eutectic attach using 1.5 mil 80/20 AuSn mounted to a 20 mil CuMo o Carrier at 70 C baseplate temperature. Worst case condition with no RF applied, 100% of DC power is dissipated.
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
3
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com
Advance Product Information
October 21, 2004
Preliminary Measured Data
22 20 18 16 14 Gain (dB) 12 10 8 6 4 2 0 35 36 37 38 39 40 41 42 43 44 45
Bias Conditions: Vd = 6 V, Id = 2 A
TGA4046-EPU
46
47
48
Frequency (GHz)
0 -2 -4 -6 -8 Return Loss (dB) -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Frequency (GHz)
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
4
ORL IRL
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com
Advance Product Information
October 21, 2004
Preliminary Measured Data
Bias Conditions: Vd = 6 V, Id = 2 A
TGA4046-EPU
35 34 33 32 Power (dBm) 31 30 29 28 27 26 25 40 41 42 43 44 Frequency (GHz) 45 46 47 48
Psat
P1dB
36 34 32 30 Pout (dBm) & Gain (dB) 28 26 24 22 20 18 16 14 12 10 0 2 4 6 8 10 12 14 16 18 20 22 Pin (dBm)
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
5
@ 45 GHz
Pout
Gain
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com
Advance Product Information
October 21, 2004
TGA4046-EPU
Mechanical Drawing
0.443 (0.017) 4.386 (0.173) 0.868 (0.034) 2.062 (0.081) 3.300 3.349 (0.130) (0.130)
2
3
4
5
4.281 (0.169)
6
2.771 2.575 (0.101) 2.390
1.997 1.811 (0.071) 1.626
1
0.095 (0.004) 0 0
10
0.443 (0.017)
9
0.868 (0.034)
8
7
3.446 3.300 (0.130) (0.136)
0.105 (0.004)
2.062 (0.081)
Units: millimeters (inches) Thickness: 0.100 (0.004) Chip edge to bond pad dimensions are shown to center of bond pad Chip size tolerance: +/- 0.051 (0.002) GND is back side of MMIC Bond pad #1: Bond pad #2, #4, #8, #10: Bond pad #3, #9: Bond pad #5, #7: Bond pad #6: (RF In) (Vg) (Vd) (Vd) (RF Out) 0.114 x 0.200 0.100 x 0.100 0.150 x 0.100 0.200 x 0.120 0.105 x 0.200 (0.004 x 0.008) (0.004 x 0.004) (0.006 x 0.004) (0.008 x 0.005) (0.004 x 0.008)
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should be observed during handling, assembly and test.
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
6
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com
Advance Product Information
October 21, 2004
TGA4046-EPU
Recommended Chip Assembly Diagram
Vg
Vd
Top
Top
100pF 100pF
100pF 100pF
.01uF
RF OUT RF IN
100pF 100pF
100pF 100pF
.01uF
Vg Bottom
Vd Bottom
The TFNs at both RF in and RF out are flare TFNs with dimensions of 0.01 x 0.03 in on 0.01 in thick Alumina substrate.
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should be observed during handling, assembly and test.
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
7
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com
Advance Product Information
October 21, 2004
TGA4046-EPU
Recommended Test Setup Diagram
R=20 : C=15uF C=33uF
Gate Voltage Gate JT1 for Top JL1 for Bottom Drain JT2 for Top JL2 for Bottom
Drain Voltage
Biasing setup procedures
(1) Recommend use conductive thermal grease underneath carrier for proper operation. Also use cooling fan to improve heat dissipation. (2) Before applying bias, set gate supply voltage to -1.5V and current limit to 4mA on each half of the amplifier, then apply the bias to gate. (3) Set drain supply voltage to 1V and current limit to 1.6A on each half of the amplifier, then apply the bias to drain. (4) Slowly increase the gate supply voltage and check the drain current, if drain current slowly increases, then increase drain supply voltage slowly to 6V. (5) Slowly adjust gate supply voltage to obtain a drain current of 1A quiescent on each half of the amplifier.
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
8
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com
Advance Product Information
October 21, 2004
TGA4046-EPU Assembly Process Notes
Reflow process assembly notes: * * * * * Use AuSn (80/20) solder with limited exposure to temperatures at or above 300 C (30 seconds max). An alloy station or conveyor furnace with reducing atmosphere should be used. No fluxes should be utilized. Coefficient of thermal expansion matching is critical for long-term reliability. Devices must be stored in a dry nitrogen atmosphere.
0
Component placement and adhesive attachment assembly notes: * * * * * * * Vacuum pencils and/or vacuum collets are the preferred method of pick up. Air bridges must be avoided during placement. The force impact is critical during auto placement. Organic attachment can be used in low-power applications. Curing should be done in a convection oven; proper exhaust is a safety concern. Microwave or radiant curing should not be used because of differential heating. Coefficient of thermal expansion matching is critical.
Interconnect process assembly notes: * * * * Thermosonic ball bonding is the preferred interconnect technique. Force, time, and ultrasonics are critical parameters. Aluminum wire should not be used. 0 Maximum stage temperature is 200 C.
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should be observed during handling, assembly and test.
Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice
9
TriQuint Semiconductor Texas: Phone (972)994-8465 Fax (972)994-8504 Email: Info-mmw@tqs.com Web: www.triquint.com

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